WO2013143033A1 - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- WO2013143033A1 WO2013143033A1 PCT/CN2012/000465 CN2012000465W WO2013143033A1 WO 2013143033 A1 WO2013143033 A1 WO 2013143033A1 CN 2012000465 W CN2012000465 W CN 2012000465W WO 2013143033 A1 WO2013143033 A1 WO 2013143033A1
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- Prior art keywords
- semiconductor device
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- layer
- shallow trench
- hard mask
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 238000002955 isolation Methods 0.000 claims abstract description 21
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 15
- 239000010410 layer Substances 0.000 description 64
- 239000000463 material Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000005388 borosilicate glass Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- -1 LPCVD Chemical compound 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Definitions
- STI shallow trench isolation
- the shallow trench isolation of the insulating padding such as silicon oxide, cuts off parasitic electrical connections that may be formed between the NMOS and PMOS, improving device reliability.
- LOCOS local field oxygen process
- STI occupies a shorter channel width and a smaller isolation spacing, so it does not erode the active region and avoids the LOCOS bird's beak effect.
- the isolation structure formed by the STI is mostly located below the surface of the substrate, thereby facilitating planarization of the entire device surface.
- the liner layer comprises at least a first liner layer of oxide and a second liner layer of nitride.
- the step of forming a shallow trench in the substrate specifically includes: forming a hard mask layer on the substrate; lithography/etching the hard mask layer to form a hard mask layer pattern, having an opening exposing the substrate;
- the mask layer pattern is a mask, and the exposed substrate in the opening is etched to form a shallow trench having a bottom surface lower than the upper surface of the substrate.
- the hard mask layer comprises at least a first hard mask layer of an oxide and a second hard mask layer of nitride.
- the semiconductor device structure is formed in the active region surrounded by the shallow trench isolation.
- the stress accumulated in the STI formation process is released by adding a softer stress releasing layer between the substrate and the STI.
- the substrate leakage current of the device is reduced, which improves the reliability of the device.
- Figures 1 to 4 are schematic cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with the present invention. detailed description
- a hard mask layer 2 is formed on a substrate 1
- a hard mask layer 2 is photolithographically/etched, and a shallow trench is formed in the substrate 1, and a liner layer 3 is deposited in the shallow trench.
- a substrate 1 is provided.
- Substrate 1 is reasonably selected according to the needs of the device, and may include single crystal silicon (Si), silicon on insulator (SOI), single crystal germanium (Ge), germanium on insulator (GeOI), strained silicon (strained Si), germanium silicon (SiGe). ) or compound semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as graphene, SiC, carbon nanotubes and many more.
- the substrate 1 is bulk silicon (e.g., a Si wafer) or SOI.
- a hard mask layer 2 is deposited on the substrate 1, and is photolithographically/etched to form a hard mask layer pattern having openings, the openings exposing portions of the substrate 1.
- the hard mask layer may be a single layer or a plurality of layers.
- the hard mask layer includes at least a first hard mask layer 2A of an oxide such as silicon oxide.
- the surface of the substrate to be etched is deposited on the substrate 1, and is photolithographically/etched to form a hard mask layer pattern having openings, the openings exposing portions of the substrate 1.
- the hard mask layer may be a single layer or a plurality of layers.
- the hard mask layer includes at least a first hard mask layer 2A of an oxide such as silicon oxide.
- a photoresist (not shown) is spin-coated and exposed to develop a photoresist pattern, and the photoresist pattern is used as a mask by dry etching such as plasma etching, anisotropically in the hard mask layer 2A/2B.
- the hard mask layer opening 2C is formed by etching until the substrate 1 is exposed. At this time, the surface of the substrate 1 is not over-etched due to the laminated structure of the hard mask, and the surface defect density is not increased.
- the opening 2C is in two parts in a cross-sectional view, the opening 2C is actually surrounded by the active area of the device, that is, in a top view (not shown), an annular structure, such as a rectangular ring frame.
- the substrate 1 is anisotropically etched by dry etching.
- the substrate 1 is Si, it can also be etched using TMAH, an anisotropically good wet etching solution.
- an opening 1 C is also formed in the substrate 1 to constitute a shallow trench having the same width W as the opening 2C.
- the depth of the opening 1 C of the substrate 1 (from the upper surface of the substrate 1 to the bottom surface of the opening 1C) H is smaller than the thickness of the substrate 1, for example, less than or equal to 2/3 of the thickness of the substrate 1, depending on the specific device insulation characteristics. Need to be reasonably selected.
- the width W of the openings 1C, 2C is smaller than the depth H, for example, W is only 1/5 to 1/3 of H.
- a stress relief layer 4 is formed on the inner surface of the shallow trench.
- the stress relief layer 4 is deposited on the bottom and side surfaces of the shallow trench (opening 1C) and the side surface of the opening 2C by a conventional deposition method such as LPCVD, PECVD, HDPCVD, or ALD.
- the stress relieving layer 4 selects a softer material, that is, its viscosity is lowered at a low temperature of, for example, 600 ° C, thereby releasing stress by flow, thereby preventing strained STI from being generated in adjacent substrate regions. The necessary stress.
- the stress relief layer 4 in the shallow trench is filled with an insulating material to form shallow trench isolation (STI) 5.
- the STI5 is formed by filling a shallow trench with an insulating material of conventional deposited silicon oxide such as LPCVD, PECVD, HDPCVD, or ALD.
- the insulating material is treated by a planarization method such as CMP until the hard mask layer 2A/2B is exposed. Subsequently, annealing at a temperature of more than 600 ° C causes the stress relief layer 4 to be heated and rheological, thereby releasing the stress accumulated during the deposition of STI 5 .
- the hard mask layer 2A/2B is removed to form a semiconductor device structure in the active region surrounded by the STI 5.
- wet etching or dry etching removes the hard mask layer 2A/2B, deposits and etches on the surface of the active region of the substrate 1 surrounded by the STI 5 to form a pad oxide layer (eg, silicon oxide, not shown), a gate stack of a gate insulating layer 6 (for example, a high-k material), a gate conductive layer 7 (for example, doped polysilicon, a metal, a metal alloy, a metal nitride), and a gate stack as a mask for source and drain for the first time
- the ion implantation forms a lightly doped source/drain extension region 8A, a gate spacer 9 of a silicon nitride material is formed on the second epitaxial layer 3 on both sides of the gate stack, and a source and drain is performed by using the gate spacer 9 as a mask.
- the second ion implantation forms a heavily doped source and drain region 8B, and the second epitaxial layer 3 portion between the source and drain regions 8A/8B constitutes a channel region 8C, and a silicide self-alignment process is formed on the source and drain regions 8B.
- a metal silicide (not shown) is formed to reduce a source-drain resistance, and an interlayer dielectric layer (not shown) of a low-k material such as silicon oxide is formed over the entire device, and a direct metal silicide is formed by etching in the interlayer dielectric layer. Contact holes and filled with metal form contact plugs (not shown).
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
提供一种半导体器件及其制造方法。该半导体器件包括衬底(1)、衬底(1)中的浅沟槽隔离(5),衬底(1)与浅沟槽隔离(5)之间还包括应力释放层(4)。通过在衬底(1)与浅沟槽隔离(5)之间增加材质较软的应力释放层(4),将浅沟槽隔离(5)形成过程中积累的应力释放出来,减小了器件的衬底泄漏电流,提高了器件的可靠性。
Description
半导体器件及其制造方法 优先权要求
本申请要求了 2012年 3月 29日提交的、 申请号为 201210088445.0、 发明名称为 "半导体器件及其制造方法" 的中国专利申请的优先权, 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及一种半导体器件及其制造方法, 特别是涉及一种能有 效从 STI释放应力的半导体器件及其制造方法。
背景技术
在传统的体硅 CMOS中,阱区与衬底之间形成 pn结,而 MOSFET 的源漏区与衬底之间也形成 pn结, 这些寄生的可控硅结构在一定条件 下可能引起电源到地之间极大的泄漏电流, 产生闩锁效应。 特别是在 0.25 μ m的逻辑电路工艺节点以下,这种寄生的闩锁效应极大阻碍了半 导体器件性能的进一步提高。
有效的防止闩锁效应的一种方法是采用浅沟槽隔离 (STI ) 技术。 绝缘的填充有例如氧化硅的浅沟槽隔离切断了 NMOS、 PMOS之间可 能形成的寄生电连接, 提高了器件可靠性。 此外, 与局部场氧工艺 ( LOCOS ) 相比, STI 占用沟道宽度较短、 具有较小的隔离间距, 因 此不会侵蚀有源区从而避免了 LOCOS的鸟嘴效应。 此外, STI形成的 隔离结构大部分位于衬底表面下方, 因此利于整个器件表面的平坦化。
然而, 现有的 STI在形成过程中会积累应力, 这些积累的应力给 衬底带来例如错位的缺陷, 而这些缺陷在器件工作时将作为电子 -空穴 对的再复合中心, 从而增大了器件的衬底泄漏电流。
因此, 需要将 STI形成过程中积累的应力释放出来, 以避免上述问 题。
发明内容
由上所述, 本发明的目的在于提供一种能有效从 STI释放应力的半 导体器件及其制造方法。
为此, 本发明提供了一种半导体器件, 包括衬底、 衬底中的浅沟 槽隔离, 其特征在于: 衬底与浅沟槽隔离之间还包括应力释放层。
其中, 应力释放层包括 BSG、 BPSG。 其中, 应力释放层的厚度为 10 ~ 15亂
其中, 应力释放层与衬底之间还包括衬垫层。 其中, 衬垫层至少 包括氧化物的第一衬垫层和氮化物的第二衬垫层。
其中, 在浅沟槽隔离包围的有源区内形成半导体器件结构。
本发明还提供了一种半导体器件制造方法, 包括以下步骤: 在衬 底中形成浅沟槽; 在浅沟槽中形成应力释放层; 在浅沟槽中填充绝缘 材料, 形成浅沟槽隔离; 退火, 使得应力释放层流变以释放应力。
其中, 应力释放层包括 BSG、 BPSG。 其中, 应力释放层的厚度 为 10 ~ 15nm。
其中, 形成浅沟槽之后、 形成应力释放层之前, 还包括在浅沟槽 中形成衬垫层。 其中, 衬垫层至少包括氧化物的第一衬垫层和氮化物 的第二衬垫层。
其中, 在大于 600°C温度下退火。
其中, 在衬底中形成浅沟槽的步骤具体包括: 在衬底上形成硬掩 膜层; 光刻 /刻蚀硬掩膜层形成硬掩膜层图形, 具有暴露衬底的开口; 以硬掩膜层图形为掩膜, 刻蚀开口中暴露的衬底, 形成底面低于衬底 上表面的浅沟槽。 其中, 硬掩膜层至少包括氧化物的第一硬掩膜层和 氮化物的第二硬掩膜层。
其中, 在退后之后, 还包括在浅沟槽隔离包围的有源区内形成半 导体器件结构。
依照本发明的半导体器件及其制造方法, 通过在衬底与 STI之间增 加材质较软的应力释放层, 将 STI形成过程中积累的应力释放出来, 减
小了器件的衬底泄漏电流, 提高了器件的可靠性。 附图说明
以下参照附图来详细说明本发明的技术方案, 其中:
图 1至图 4为依照本发明的半导体器件制造方法各步骤的剖面示意 图。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果, 公开了能有效从 STI释放应力的半导体器件及其 制造方法。 需要指出的是, 类似的附图标记表示类似的结构, 本申请 中所用的术语 "第一,, 、 "第二" 、 "上" 、 "下" 等等可用于修饰 各种器件结构或制造工序。 这些修饰除非特别说明并非暗示所修饰器 件结构或制造工序的空间、 次序或层级关系。
以下将参照图 1至图 4的剖面示意图来详细说明依照本发明的器件 的制造方法各步骤。
参照图 1 , 在衬底 1 上形成硬掩膜层 2, 光刻 /刻蚀硬掩膜层 2以 及衬底 1形成浅沟槽, 在浅沟槽中沉积衬垫层 3。
提供衬底 1。衬底 1依照器件用途需要而合理选择,可包括单晶体 硅( Si )、 绝缘体上硅( SOI )、 单晶体锗( Ge )、 绝缘体上锗( GeOI )、 应变硅 (Strained Si ) 、 锗硅 (SiGe ) , 或是化合物半导体材料, 例如 氮化镓 (GaN ) 、 砷化镓 (GaAs ) 、 磷化铟(InP)、 锑化铟 ( InSb ) , 以及碳基半导体例如石墨烯、 SiC、碳纳管等等。优选地, 为了与 CMOS 工艺兼容而应用于数字逻辑集成电路, 衬底 1为体硅(例如为 Si晶片 ) 或 SOI。
在衬底 1上沉积硬掩膜层 2, 并光刻 /刻蚀形成具有开口的硬掩膜 层图形, 开口暴露部分的衬底 1。 硬掩膜层可以是单层也可以是多层, 优选地, 硬掩膜层至少包括氧化物(例如氧化硅 )的第一硬掩膜层 2A,
以及氮化物 (例如氮化硅) 或氮氧化物 (例如氮氧化硅) 的第二硬掩 膜层 2B, 这种硬掩膜叠层能够良好控制刻蚀图形的精度、 并且良好保 护所覆盖的将要被刻蚀的衬底表面。 旋涂光刻胶 (未示出) 并曝光显 影形成光刻胶图形, 以光刻胶图形为掩膜采用等离子刻蚀等干法刻蚀, 各向异性地在硬掩膜层 2A/2B中刻蚀形成了硬掩膜层开口 2C, 直至暴 露衬底 1。 此时由于硬掩膜的叠层结构, 衬底 1的表面并未被过刻蚀, 未增大表面缺陷密度。 虽然开口 2C在剖视图中为两个部分, 但是实际 上开口 2C是环绕器件有源区的, 也即在顶视图 (未示出) 中是环形结 构, 例如矩形环框。
以硬掩膜层图形为掩膜, 刻蚀开口中暴露的部分衬底 1, 直至衬底
1表面以下的一定深度 H。 优选地, 采用干法刻蚀各向异性地刻蚀衬底 1。 当衬底 1为 Si时, 也可以采用 TMAH这种各向异性较好的湿法腐 蚀液来刻蚀。如图 1所示,衬底 1 中也形成了开口 1 C从而构成浅沟槽, 与开口 2C具有相同的宽度 W。 衬底 1的开口 1 C的深度(从衬底 1上 表面至开口 1C的底表面) H小于衬底 1的厚度, 例如小于等于衬底 1 厚度的 2/3, 其依照具体的器件绝缘特性需要而合理选定。 开口 1C、 2C (浅沟槽) 的宽度 W小于其深度 H, 例如 W仅为 H的 1/5 ~ 1/3。
优选地, 采用 LPCVD、 PECVD、 HDPCVD、 ALD等常规沉积方 法在浅沟槽中沉积衬垫层 3 ,用于消除衬底浅沟槽表面的缺陷。优选地, 衬垫层 3包括层叠结构,至少包括氧化物的第一衬垫层 3A以及氮化物 的第二衬垫层 3B。 衬垫层 3A/3B的总厚度例如为 10 ~ 20nm。 当良好 控制了刻蚀工艺参数以避免带来过多的衬底缺陷时, 衬垫层 3 也可省 略。
参照图 2 , 在浅沟槽内表面形成应力释放层 4。 采用 LPCVD、 PECVD、 HDPCVD、 ALD 等常规沉积方法在浅沟槽 (开口 1C ) 的底 面和侧表面、 以及开口 2C的侧表面上沉积应力释放层 4。 应力释放层 4选择较软的材质, 也即在例如 600°C的低温下其粘性就降低, 从而通 过流动来释放应力, 从而防止应变的 STI 在相邻的衬底区域中产生不
必要的应力。 合适的应力释放层 4 的材盾包括硼硅玻璃 (BSG ) 、 硼 磷硅玻璃 (BPSG ) 等, 其厚度优选地为 10 ~ 15nm, 在足够释放应力 的同时又不至于降低 STI的绝缘性能。
参照图 3, 在浅沟槽中的应力释放层 4上填充绝缘材料, 形成浅沟 槽隔离 (STI ) 5。 采用 LPCVD、 PECVD、 HDPCVD、 ALD等常规沉 积氧化硅的绝缘材料来填充浅沟槽形成 STI5。通过例如 CMP等平坦化 方法处理绝缘材料, 直至暴露硬掩膜层 2A/2B。 随后, 在大于 600°C的 温度下退火, 使得应力释放层 4受热而流变, 从而释放了沉积 STI5过 程中积累的应力。
参照图 4, 去除硬掩膜层 2A/2B , 在 STI5包围的有源区内形成半 导体器件结构。例如湿法腐蚀或干法刻蚀移除硬掩膜层 2A/2B,在 STI5 包围的衬底 1 有源区表面上沉积并刻蚀形成包括垫氧化层 (例如氧化 硅, 未示出) 、 栅极绝缘层 6 (例如高 k材料) 、 栅极导电层 7 (例如 掺杂多晶硅、 金属、 金属合金、 金属氮化物) 的栅极堆叠, 以栅极堆 叠为掩膜进行源漏第一次离子注入形成轻掺杂的源漏扩展区 8A, 在栅 极堆叠两侧的第二外延层 3上形成氮化硅材质的栅极侧墙 9, 以栅极侧 墙 9为掩膜进行源漏第二次离子注入形成重掺杂的源漏区 8B, 源漏区 8A/8B之间的第二外延层 3部分构成沟道区 8C, 在源漏区 8B上进行 硅化物自对准工艺形成金属硅化物 (未示出) 以降低源漏电阻, 在整 个器件上形成氧化硅等低 k 材质的层间介质层 (未示出 ) , 在层间介 质层中刻蚀形成直达金属硅化物的接触孔并填充金属形成接触塞 (未 示出) 。
最终形成的半导体器件如图 4所示, 包括衬底、 衬底中的浅沟槽隔 离、 浅沟槽围绕的有源区以及有源区内形成的半导体器件结构, 其中, 衬底与浅沟槽隔离之间还包括应力释放层。 优选地, 应力释放层与村 底之间还包括村垫层。 其余各个部件的材质和形成方法已在前文中详 述, 在此不再赘述。
依照本发明的半导体器件及其制造方法, 通过在衬底与 STI之间增
加材质较软的应力释放层, 将 STI形成过程中积累的应力释放出来, 减 小了器件的衬底泄漏电流, 提高了器件的可靠性。
尽管已参照一个或多个示例性实施例说明本发明, 本领域技术人 员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和 等价方式。 此外, 由所公开的教导可做出许多可能适于特定情形或材 料的修改而不脱离本发明范围。 因此, 本发明的目的不在于限定在作 为用于实现本发明的最佳实施方式而公开的特定实施例, 而所公开的 器件结构及其制造方法将包括落入本发明范围内的所有实施例。
Claims
1. 一种半导体器件, 包括衬底、 衬底中的浅沟槽隔离, 其特征在 于: 衬底与浅沟槽隔离之间还包括应力释放层。
2. 如权利要求 1的半导体器件,其中,应力释放层包括 BSG、 BPSG。
3. 如权利要求 1的半导体器件, 其中, 应力释放层的厚度为 10 ~ 15nm。
4. 如权利要求 1的半导体器件, 其中, 应力释放层与衬底之间还 包括衬垫层。
5. 如权利要求 4的半导体器件, 其中, 衬垫层至少包括氧化物的 第一衬垫层和氮化物的第二衬垫层。
6. 如权利要求 1的半导体器件, 其中, 在浅沟槽隔离包围的有源 区内形成半导体器件结构。
7. 一种半导体器件制造方法, 包括以下步骤:
在衬底中形成浅沟槽;
在浅沟槽中形成应力释放层;
在浅沟槽中填充绝缘材料, 形成浅沟槽隔离;
退火, 使得应力释放层流变以释放应力。
8. 如权利要求 7的半导体器件制造方法, 其中, 应力释放层包括 BSG、 BPSG。
9. 如权利要求 7的半导体器件制造方法, 其中, 应力释放层的厚 度为 10 ~ 15亂
10. 如权利要求 7的半导体器件制造方法, 其中, 形成浅沟槽之后、 形成应力释放层之前, 还包括在浅沟槽中形成村垫层。
1 1. 如权利要求 10的半导体器件制造方法, 其中, 衬垫层至少包 括氧化物的第一衬垫层和氮化物的第二衬垫层。
12. 如权利要求 7的半导体器件制造方法, 其中, 在大于 600 °C温 度下退火。
13. 如权利要求 7的半导体器件制造方法, 其中, 在衬底中形成浅 沟槽的步骤具体包括:
在衬底上形成硬掩膜层;
光刻 /刻蚀硬掩膜层形成硬掩膜层图形, 具有暴露衬底的开口; 以硬掩膜层图形为掩膜, 刻蚀开口中暴露的衬底, 形成底面低于 衬底上表面的浅沟槽。
14. 如权利要求 13的半导体器件制造方法, 其中, 硬掩膜层至少 包括氧化物的第一硬掩膜层和氮化物的第二硬掩膜层。
15. 如权利要求 7的半导体器件制造方法, 其中, 在退后之后, 还 包括在浅沟槽隔离包围的有源区内形成半导体器件结构。
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