WO2013140713A1 - Image display device drive method, image display device, and image display system - Google Patents
Image display device drive method, image display device, and image display system Download PDFInfo
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- WO2013140713A1 WO2013140713A1 PCT/JP2013/000862 JP2013000862W WO2013140713A1 WO 2013140713 A1 WO2013140713 A1 WO 2013140713A1 JP 2013000862 W JP2013000862 W JP 2013000862W WO 2013140713 A1 WO2013140713 A1 WO 2013140713A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/033—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor
- G06F3/037—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor using the raster scan of a cathode-ray tube [CRT] for detecting the position of the member, e.g. light pens cooperating with CRT monitors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0416—Control or interface arrangements specially adapted for digitisers
- G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/042—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/292—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for reset discharge, priming discharge or erase discharge occurring in a phase other than addressing
- G09G3/2927—Details of initialising
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/292—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for reset discharge, priming discharge or erase discharge occurring in a phase other than addressing
- G09G3/2922—Details of erasing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
Definitions
- the present invention relates to a driving method of an image display apparatus that displays an image in an image display area by combining binary control of light emission and non-light emission in a plurality of light emitting elements constituting a pixel, an image display apparatus, and an image using a light pen.
- the present invention relates to an image display system capable of handwritten input of characters and drawings on a display device.
- a plasma display panel (hereinafter abbreviated as “panel”) is a typical image display device that displays an image in an image display area by combining binary control of light emission and non-light emission in each of a plurality of light emitting elements constituting a pixel. There is).
- a large number of discharge cells which are light-emitting elements constituting pixels, are formed between a front substrate and a rear substrate that are arranged to face each other.
- the front substrate a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate.
- the back substrate has a plurality of parallel data electrodes formed on a glass substrate on the back side.
- Each discharge cell is coated with one of red (R), green (G), and blue (B) phosphors, and a discharge gas is enclosed therein.
- R red
- G green
- B blue
- an ultraviolet ray is generated by causing a gas discharge, and the phosphor is excited to emit light by the ultraviolet ray.
- a subfield method is generally used as a method of displaying an image in an image display area of a panel by combining binary control of light emission and non-light emission in a light emitting element.
- each discharge cell In the subfield method, one field is divided into a plurality of subfields having different emission luminances.
- each discharge cell light emission / non-light emission of each subfield is controlled by a combination according to the gradation value to be displayed.
- each discharge cell emits light with brightness corresponding to the gradation value to be displayed, and a color image composed of various combinations of gradation values is displayed in the image display area of the panel.
- Some of such image display apparatuses have a function of allowing handwriting input of characters and drawings on a panel using a pointing device called “light pen”.
- position coordinates In order to realize a handwriting input function using a light pen, a technique for detecting the position of the light pen in an image display area is disclosed.
- position coordinates the coordinates representing the position of the light pen in the image display area.
- an abscissa detection subfield for displaying an abscissa detection pattern is provided in one field. Then, the light emission of this abscissa detection subfield is detected by the light pen, and the position (abscissa) of the light pen is detected based on the timing at which the light emission is detected.
- a position detection period for generating a light signal for detecting position coordinates is provided in one field only when detecting the position coordinates of the light pen. Then, this light signal is detected by the light pen, and the position coordinates of the light pen are detected based on the timing at which the light signal is detected.
- An image display device includes an image display unit having a plurality of scan electrodes, sustain electrodes, and a plurality of data electrodes, and a drive circuit configured to form one field by a plurality of subfields and drive the image display unit. .
- the drive circuit generates a field having an image display subfield, a y-coordinate detection subfield, and an x-coordinate detection subfield, and the y-coordinate detection subfield or the x-coordinate detection subfield is set in the field. It happens last.
- the drive circuit applies an upward ramp waveform voltage that rises to the first voltage after alternately applying a sustain pulse to the scan electrode and the sustain electrode, to the scan electrode.
- the driving circuit scans an up-slope waveform voltage and a down-slope waveform voltage that rise to a second voltage higher than the first voltage in the y-coordinate detection subfield or the x-coordinate detection subfield generated at the end of the field.
- An erasing period to be applied to the electrode is provided.
- An image display system includes the above-described image display device, a light pen, a coordinate calculation circuit, and a drawing circuit.
- the light pen has a light receiving element, and receives light emission generated in the image display unit in the y coordinate detection subfield and light emission generated in the image display unit in the x coordinate detection subfield, and outputs a light reception signal.
- the coordinate calculation circuit based on the light reception signal, coordinates indicating the position of light emission received by the light pen in the light emission generated in the image display unit in the y coordinate detection subfield, and light emission generated in the image display unit in the x coordinate detection subfield.
- the coordinates representing the light emission position received by the light pen are calculated.
- the drawing circuit creates a drawing signal for displaying an image based on the coordinates calculated by the coordinate calculation circuit on the image display unit. Then, the image display device displays an image based on the drawing signal on the image display unit.
- FIG. 1 is an exploded perspective view showing an example of the structure of a panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 2 is a diagram showing an example of the electrode arrangement of the panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 3 is a diagram schematically showing an example of a drive voltage waveform applied to each electrode of the panel in the subfields SF1 to SF3 of the image display subfield in the embodiment of the present invention.
- FIG. 4 is a diagram schematically showing an example of a drive voltage waveform applied to each electrode of the panel in the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx in the embodiment of the present invention.
- FIG. 5 is a diagram schematically showing an example of a circuit block and a plasma display system constituting the plasma display device in the embodiment of the present invention.
- FIG. 6 is a circuit diagram schematically showing a configuration example of the scan electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 7 is a circuit diagram schematically showing a configuration example of the sustain electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 8 is a circuit diagram schematically showing a configuration example of the data electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 5 is a diagram schematically showing an example of a circuit block and a plasma display system constituting the plasma display device in the embodiment of the present invention.
- FIG. 6 is a circuit diagram schematically showing a configuration example of the scan electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 7 is a circuit diagram schematically showing
- FIG. 9 is a diagram schematically showing an example of the operation when detecting the position coordinates of the light pen in the plasma display system according to the embodiment of the present invention.
- FIG. 10 is a diagram schematically showing an example of a drive voltage waveform when detecting the position coordinates of the light pen in the plasma display system according to the embodiment of the present invention.
- FIG. 11 is a diagram schematically showing an example of an operation when performing handwriting input with a light pen in the plasma display system according to the embodiment of the present invention.
- FIG. 1 is an exploded perspective view showing an example of the structure of a panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
- a plurality of display electrode pairs 14 each including a scanning electrode 12 and a sustaining electrode 13 are formed on a glass front substrate 11.
- a dielectric layer 15 is formed so as to cover the display electrode pair 14, and a protective layer 16 is formed on the dielectric layer 15.
- the front substrate 11 serves as an image display surface on which an image is displayed.
- a plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is further formed thereon.
- the phosphor layer 25R that emits red (R), the phosphor layer 25G that emits green (G), and the phosphor layer that emits blue (B) are formed on the side surfaces of the barrier ribs 24 and the surface of the dielectric layer 23. 25B is provided.
- the phosphor layer 25R, the phosphor layer 25G, and the phosphor layer 25B are collectively referred to as a phosphor layer 25.
- the front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 intersect each other with a minute space therebetween, and a discharge space is provided in the gap between the front substrate 11 and the rear substrate 21.
- the outer peripheral part is sealed with sealing materials, such as glass frit.
- sealing materials such as glass frit.
- a mixed gas of neon and xenon is sealed in the discharge space as a discharge gas.
- the discharge space is partitioned into a plurality of sections by the barrier ribs 24, and discharge cells, which are light-emitting elements constituting the pixels, are formed at the intersections between the display electrode pairs 14 and the data electrodes 22.
- discharge is generated in these discharge cells, and the phosphor layer 25 emits light (discharge cells are turned on), thereby displaying a color image on the panel 10.
- one pixel is composed of three consecutive discharge cells arranged in the direction in which the display electrode pair 14 extends.
- the three discharge cells are a discharge cell having a phosphor layer 25R and emitting red (R) light (hereinafter referred to as “red discharge cell” or “red pixel”), and a phosphor layer 25G.
- Discharge cells hereinafter referred to as “green discharge cells” or “green pixels”) having a green color (G)
- green pixels having a phosphor layer 25B.
- the structure of the panel 10 is not limited to the above-described structure, and may be, for example, provided with a stripe-shaped partition wall.
- FIG. 2 is a diagram showing an example of the electrode arrangement of the panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
- n scan electrodes SC1 to SCn scan electrode 12 in FIG. 1
- n sustain electrodes SU1 to SUn sustain electrode 13 in FIG. 1 extended in the first direction
- the m data electrodes D1 to Dm data electrode 22 in FIG. 1 extended in the second direction intersecting the first direction are arranged.
- the first direction is referred to as a row direction (or horizontal direction or line direction), and the second direction is referred to as a column direction (or vertical direction).
- m discharge cells are formed on one pair of display electrodes 14 and m / 3 pixels are formed.
- the discharge cell having the data electrode Dp + 1 is coated with a green phosphor as the phosphor layer 25G, and this discharge cell becomes a green discharge cell.
- a blue phosphor is applied as a phosphor layer 25B to the discharge cell having the data electrode Dp + 2, and this discharge cell becomes a blue discharge cell.
- a red discharge cell, a green discharge cell, and a blue discharge cell adjacent to each other constitute a set to constitute one pixel.
- one field includes a plurality of image display subfields for displaying an image on the panel 10, a timing detection subfield SFo, a y coordinate detection subfield SFy, and an x coordinate detection subfield SFx.
- the image display subfield is also simply referred to as a subfield.
- Each image display subfield has an initialization period, an address period, and a sustain period.
- initialization discharge is generated in each discharge cell, and wall charges necessary for the subsequent address operation are formed in the discharge cell.
- priming particles charged particles that assist the generation of discharge
- address period an address discharge is generated in the discharge cells that should emit light.
- sustain pulses are alternately applied to the scan electrodes and the sustain electrodes, and a sustain discharge is generated in the discharge cells that have generated the address discharge.
- the initialization operation in the initialization period includes “forced initialization operation” and “selective initialization operation”, and generated drive voltage waveforms are different from each other.
- forced initializing operation an initializing discharge is forcibly generated in the discharge cells regardless of the presence or absence of discharge in the immediately preceding subfield.
- selective initializing operation initializing discharge is selectively generated only in the discharge cells that have generated address discharge in the address period of the immediately preceding subfield.
- the first subfield (for example, subfield SF1) is set as a subfield (forced initialization subfield) for performing a forced initialization operation, and other subfields are included.
- a field for example, a subfield after subfield SF2
- selective initialization subfield for performing a selective initialization operation.
- a luminance weight is set for each subfield.
- one field has eight subfields (subfields SF1 to SF8), and each subfield has a luminance of (1, 34, 21, 13, 8, 5, 3, 2).
- An example of setting a weight is given.
- the position of the light pen in the image display area is represented by the x coordinate and the y coordinate.
- the x-coordinate detection subfield SFx and the y-coordinate detection subfield SFy are subfields for detecting the x-coordinate and y-coordinate of the position (position coordinate) of the light pen in the image display area.
- the light pen is provided in the plasma display system, and is used by a user to input characters and drawings on the panel by handwriting. Details of the light pen will be described later.
- wireless communication is performed between the light pen and the plasma display device.
- the light pen calculates the position coordinates of the light pen inside the light pen, and transmits data of the calculated position coordinates from the light pen to the plasma display device by wireless communication.
- the timing detection subfield SFo of the present embodiment is for enabling the light pen itself to generate a signal (coordinate reference signal) serving as a reference for detecting position coordinates with high accuracy.
- a plurality of image display subfields for example, subfields SF1 to SF8
- a timing detection subfield SFo for example, a y coordinate detection subfield SFy
- an x coordinate detection subfield SFx are arranged in this order.
- An example in which each subfield occurs will be described, but the generation order of each subfield is not limited to this order.
- the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx are not necessarily provided in each field.
- the timing detection subfield SFo, the y-coordinate detection subfield SFy, and the x-coordinate detection subfield SFx may be generated at a rate of once per a plurality of fields in accordance with the video signal, the usage state of the plasma display device, and the like. .
- FIG. 3 schematically shows an example of a drive voltage waveform applied to each electrode of panel 10 in subfields SF1 to SF3 of the image display subfield in the embodiment of the present invention.
- FIG. 3 shows sustain electrodes SU1 to SUn, scan electrode SC1 that performs the address operation first in the address period, scan electrode SCn that performs the address operation last in the address period (for example, scan electrode SC1080), and data electrode D1 to data electrode.
- the drive voltage waveform applied to each of Dm (for example, data electrode D5760) is shown.
- Scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected based on image data (data indicating light emission / non-light emission for each subfield) from among the electrodes.
- each subfield after subfield SF3 generates a drive voltage waveform substantially similar to that of subfield SF2, except for the number of sustain pulses.
- the subfield SF1 which is a forced initialization subfield
- the initialization period Pia1 of the subfield SF1 is divided into four periods of a first period Pi1, a second period Pi2, a third period Pi3, and a fourth period Pi4, and each period will be described.
- the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn, and the voltage 0 (V) is applied to the data electrodes D1 to Dm.
- a high impedance state is set later.
- a scan waveform SC1 to SCn is applied with voltage Vi1 after voltage 0 (V) is applied, and a ramp waveform voltage (hereinafter referred to as “upward ramp waveform voltage”) that gradually rises from voltage Vi1 to voltage Vi2. Apply.
- the voltage Vi1 is set to a voltage lower than the discharge start voltage for the sustain electrodes SU1 to SUn, and the voltage Vi2 is set to a voltage exceeding the discharge start voltage for the sustain electrodes SU1 to SUn.
- negative wall voltage is accumulated on scan electrodes SC1 to SCn
- positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn.
- priming particles that assist the generation of the subsequent discharge are generated in the discharge cell.
- the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.
- the data electrodes D1 to Dm are in a high impedance state after the voltage 0 (V) is applied, as the voltage applied to the scan electrodes SC1 to SCn rises, the voltage of the data electrodes D1 to Dm also increases. It gradually rises from 0 (V) in the positive direction.
- the protective layer 16 is formed of a material mainly composed of magnesium oxide (MgO) having a large secondary electron emission coefficient and excellent durability in order to lower the discharge start voltage in the discharge cell.
- the phosphor layer 25 has a smaller secondary electron emission coefficient than the protective layer 16.
- discharge between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, which are relatively likely to generate discharge is first generated, and scan electrodes SC1 to SCn and data electrodes are generated using priming particles generated by the discharge.
- the initialization discharge can be generated stably.
- the voltage of scan electrodes SC1 to SCn is once lowered to voltage Vi3 lower than voltage Vi2, and then lowered to voltage 0 (V).
- the voltage Vi3 is set to a voltage lower than the voltage Vi2 and lower than the discharge start voltage with respect to the sustain electrodes SU1 to SUn. Although an example in which the voltage Vi3 is about 200 (V) is shown in this embodiment, the voltage Vi3 may be a voltage that does not cause discharge in the discharge cells. Further, the voltage may be sharply decreased from the voltage Vi2 to the voltage 0 (V).
- the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn.
- the sustain electrodes SU1 to SUn may be in a high impedance state after the voltage Ve is applied.
- the voltage Ve may be kept applied to the sustain electrodes SU1 to SUn.
- the scan electrodes SC1 to SCn have a ramp waveform voltage that gradually falls from a voltage that is less than the discharge start voltage (eg, voltage 0 (V)) to a negative voltage Vi4 (hereinafter also simply referred to as “down ramp waveform voltage”). Is applied. Voltage Vi4 is set to a voltage exceeding the discharge start voltage with respect to sustain electrodes SU1 to SUn.
- the voltage applied to the scan electrodes SC1 to SCn is set to voltage 0 (V).
- the voltage 0 (V) is applied to the scan electrodes SC1 to SCn while the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn and the data electrodes D1 to Dm.
- An upward ramp waveform voltage that gradually rises to Vr is applied.
- the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn. To do.
- the sustain electrodes SU1 to SUn may be in a high impedance state after the voltage Ve is applied.
- the voltage Ve may be applied to the sustain electrodes SU1 to SUn.
- the downward ramp waveform voltage that gently falls from the voltage 0 (V) to the negative voltage Vi4 is applied to the scan electrodes SC1 to SCn.
- the voltage applied to the scan electrodes SC1 to SCn is set to the voltage Vc.
- the above-mentioned drive voltage waveform generated in the initialization period Pia1 is a forced initialization waveform (first forced initialization waveform).
- first forced initialization waveform By this forced initializing operation, the wall voltage of each discharge cell in which the initializing discharge has occurred can be made substantially uniform.
- the forced initializing operation is described as an initializing operation for forcibly generating an initializing discharge in all the discharge cells in the image display area of the panel. It is not limited to.
- an operation for applying a forced initialization waveform only to a part of the discharge cells in the image display area of the panel is also a forced initialization operation, and a subfield for performing the forced initialization operation is forcibly initialized.
- Subfield For example, in the odd-field subfield SF1, the forced initializing waveform is applied only to the odd-numbered scan electrodes SC (2N-1) (N is an integer of 1 or more), and the other scan electrodes SC (2N) are described later. A selective initialization waveform is applied.
- a forced initialization waveform is applied only to the even-numbered scan electrode SC (2N), and a selective initialization waveform is applied to the other scan electrode SC (2N-1).
- the scan electrodes SC1 to SCn to which the forced initialization waveform is applied may be changed for each field. The same applies to all subfields that perform the forced initialization operation in the following description.
- voltage 0 (V) is applied to data electrodes D1 to Dm
- voltage Ve is applied to sustain electrodes SU1 to SUn
- voltage Vc is applied to scan electrodes SC1 to SCn.
- a negative scan pulse having a negative voltage Va is applied to the scan electrode SC1 in the first row.
- a positive address pulse of a positive voltage Vd is applied to the data electrode Dk of the discharge cell that should emit light in the first row of the data electrodes D1 to Dm.
- the time from the end of the initialization period Pia1 to the generation of the first address pulse in the address period Pw1 (the first scan pulse is applied after the voltage Vc is applied to the scan electrode SC1).
- Tw0, and the time for applying the scan pulse to each of the scan electrodes SC1 to SCn (the width of the scan pulse, and the width of the write pulse applied to the data electrode Dk is substantially equal to this) Tw1
- the period Tw0 is about 50 ⁇ sec, for example, and Tw1 is about 1 ⁇ sec, for example.
- the voltages of the scan pulse and the address pulse are adjusted so that the address discharge is weaker than the sustain discharge. Therefore, the light emission due to the address discharge has lower luminance than the light emission due to the sustain discharge. This is to prevent light emission due to the address discharge from hindering display of an image on the panel 10.
- a scan pulse of voltage Va is applied to scan electrode SC2 in the second row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light in the second row.
- address discharge occurs in the discharge cells in the second row to which the scan pulse and address pulse are simultaneously applied. Address discharge does not occur in the discharge cells to which no address pulse is applied. Thus, the address operation in the discharge cells in the second row is performed.
- the order in which the scan pulses are applied to the scan electrodes SC1 to SCn is not limited to the order described above.
- the order in which the scan pulses are applied to the scan electrodes SC1 to SCn may be arbitrarily set according to the specifications of the image display device.
- voltage 0 (V) is applied to the data electrodes D1 to Dm. Then, a sustain pulse of positive voltage Vs is applied to scan electrodes SC1 to SCn, and voltage 0 (V) is applied to sustain electrodes SU1 to SUn.
- a sustain discharge is generated between the scan electrode SCi and the sustain electrode SUi in the discharge cell that has generated the address discharge in the immediately preceding address period Pw1.
- the phosphor layer 25 of the discharge cell emits light due to the ultraviolet rays generated by the sustain discharge.
- a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is also accumulated on the data electrode Dk.
- the sustain discharge does not occur in the discharge cells in which the address discharge has not occurred in the immediately preceding address period Pw1, and the wall voltage at the end of the initialization period Pia1 is maintained.
- the number of sustain pulses obtained by multiplying the brightness weight by a predetermined brightness multiple is alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn.
- the discharge cells that have generated the address discharge in the immediately preceding address period Pw1 generate the sustain discharge the number of times corresponding to the luminance weight, and emit light with the luminance corresponding to the luminance weight.
- voltage 0 (V) is applied to sustain electrodes SU1 to SUn and data electrodes D1 to Dm, and applied to scan electrodes SC1 to SCn.
- An upward ramp waveform voltage that gradually rises from the voltage 0 (V) to the positive voltage Vr that is the first voltage is applied.
- this upward ramp waveform voltage is referred to as a “first ramp waveform voltage”.
- the negative wall voltage is accumulated on the sustain electrode SUi and the positive wall voltage is accumulated on the scan electrode SCi, so that the discharge start voltage of those discharge cells is exceeded.
- the voltage Vr is set as the voltage.
- a weak discharge is generated between sustain electrode SUi and scan electrode SCi of the discharge cell in which the sustain discharge is generated while applying the first ramp waveform voltage to scan electrodes SC1 to SCn. It occurs continuously.
- the wall voltage on the scan electrode SCi and the wall voltage on the sustain electrode SUi are weakened while leaving the positive wall voltage on the data electrode Dk, and unnecessary wall charges in the discharge cell are erased.
- the voltage Vr as the first voltage is preferably a voltage value approximate to the voltage Vs, and in this embodiment, the voltage Vr is set to a voltage value equal to the voltage Vs.
- the selective initialization subfield will be described by taking the subfield SF2 as an example.
- the same drive voltage waveform as that in the initialization period Pib2 of the subfield SF2 is applied to each electrode to perform the selective initialization operation. .
- the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn.
- a downward ramp waveform voltage that drops from a voltage that is lower than the discharge start voltage (for example, voltage 0 (V)) to a negative voltage Vi4 is applied to scan electrodes SC1 to SCn.
- the downward ramp waveform voltage has substantially the same waveform shape as the downward ramp waveform voltage generated in the second period Pi2 and the fourth period Pi4 of the initialization period Pia1.
- This initialization discharge weakens the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi.
- the positive wall voltage accumulated on the data electrode Dk by the last sustain discharge is adjusted to a wall voltage suitable for the address operation by discharging an excessive portion.
- the initialization discharge does not occur, and the wall voltage at the end of the initialization period Pia1 of the subfield SF1 is maintained.
- the voltage applied to the scan electrodes SC1 to SCn is set to the voltage Vc.
- the initializing discharge is performed on the discharge cell that has performed the address operation in the address period Pw1 of the immediately preceding subfield SF1 (that is, the discharge cell that has performed the sustain operation in the sustain period Ps1).
- Select initialization operation that generates Thereby, the wall voltage in the discharge cell is adjusted to a wall voltage suitable for the address operation in the subsequent address period Pw2. Further, priming particles that assist the generation of the address discharge are generated in the discharge cell.
- the above-mentioned drive voltage waveform generated in the initialization period Pib2 is a selective initialization waveform.
- the voltage Vi4 and the voltage Ve are set to voltage values that satisfy the above-described operation according to the characteristics of the panel 10, the specifications of the plasma display device 100, and the like.
- the drive voltage waveforms similar to those in the address period Pw1 and the sustain period Ps1 in the subfield SF1 are applied to the respective electrodes, except for the number of sustain pulses generated, and thus the description thereof is omitted.
- each subfield after subfield SF3 the drive voltage waveform similar to that in subfield SF2 is applied to each electrode except for the number of sustain pulses, and the description thereof is omitted.
- the subfield for performing the forced initialization operation is the subfield SF1, but the present invention is not limited to this configuration.
- the subfield in which the forced initialization operation is performed may be a subfield after subfield SF2.
- the present invention is not limited to this configuration.
- the number of times of performing the forced initialization operation may be once in a plurality of fields.
- the coordinate detection subfield is a generic name for the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx.
- FIG. 4 schematically shows an example of a drive voltage waveform applied to each electrode of panel 10 in timing detection subfield SFo, y coordinate detection subfield SFy, and x coordinate detection subfield SFx in the embodiment of the present invention. It is.
- FIG. 4 shows drive voltages applied to sustain electrodes SU1 to SUn, scan electrodes SC1 to SCn, and data electrodes D1 to Dm in timing detection subfield SFo, y coordinate detection subfield SFy, and x coordinate detection subfield SFx. Waveform is shown.
- FIG. 4 also shows a part of the sustain period Ps8 of the subfield SF8 immediately before the timing detection subfield SFo and a part of the subfield SF1.
- the timing detection subfield SFo has an initialization period Pico, an address period Pwo, and a timing detection period Po.
- the initialization period Pico a forced initialization operation is performed.
- a driving voltage waveform different from that in the initialization period Pia1 of the subfield SF1 of the image display subfield is applied to each electrode.
- the initialization period Pico is divided into two periods of a sixth period Pi6 and a seventh period Pi7, and each period will be described.
- the same drive voltage waveform as that in the first period Pi1 of the initialization period Pia1 is applied to each electrode.
- the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn, and the data electrodes D1 to Dm are set to the high impedance state after the voltage 0 (V) is applied.
- a voltage Vi1 is applied to scan electrodes SC1 to SCn after voltage 0 (V) is applied, and an upward ramp waveform voltage that gradually rises from voltage Vi1 to voltage Vi2 is applied.
- Voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to sustain electrodes SU1 to SUn.
- Voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrodes SU1 to SUn.
- the upslope waveform voltage has substantially the same waveform shape as the upslope waveform voltage generated in the first period Pi1 of the initialization period Pia1.
- negative wall voltage is accumulated on scan electrodes SC1 to SCn
- positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Furthermore, priming particles that assist the generation of the subsequent address discharge are generated in the discharge cell.
- the voltage applied to scan electrodes SC1 to SCn reaches voltage Vi2
- the voltage of scan electrodes SC1 to SCn is once lowered to voltage Vi3 lower than voltage Vi2, and then lowered to voltage 0 (V).
- the present invention is not limited to this configuration.
- the voltage may be sharply decreased from voltage Vi2 to voltage 0 (V).
- the same drive voltage waveform as that in the initialization period Pib2 of the subfield SF2 is applied to each electrode.
- the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn.
- a downward ramp waveform voltage that falls from a voltage (for example, voltage 0 (V)) that is lower than the discharge start voltage to a negative voltage Vi4 is applied to scan electrodes SC1 to SCn.
- This downward ramp waveform voltage has substantially the same waveform shape as the downward ramp waveform voltage generated in the initialization period Pib2.
- This initialization discharge weakens the wall voltage on scan electrodes SC1 to SCn and the wall voltage on sustain electrodes SU1 to SUn, and the positive wall voltage accumulated on data electrodes D1 to Dm has an excessive portion. It is discharged and adjusted to a wall voltage suitable for the subsequent address operation.
- the voltage applied to the scan electrodes SC1 to SCn is set to the voltage Vc.
- the above-mentioned drive voltage waveform generated in the initialization period Pico is a forced initialization waveform (second forced initialization waveform).
- initialization discharge is forcibly generated in all the discharge cells in the image display area of panel 10.
- the wall voltage of each discharge cell can be made substantially uniform by this forced initialization operation.
- the wall voltage in each discharge cell is adjusted to a wall voltage suitable for the address operation in the subsequent address period Pwo, and priming particles that assist the generation of the address discharge are generated in the discharge cell.
- the voltage 0 (V) is applied to the data electrodes D1 to Dm
- the voltage Ve is applied to the sustain electrodes SU1 to SUn
- the voltage Vc is applied to the scan electrodes SC1 to SCn.
- an address pulse of the voltage Vd is applied to the data electrodes D1 to Dm and a scan pulse of the voltage Va is applied to the scan electrodes SC1 to SCn to generate an address discharge in each discharge cell.
- the scan pulse is sequentially applied to each of the electrodes from the scan electrode SC1 to the scan electrode SCn while applying the write pulse to all the data electrodes D1 to Dm. It is also possible to apply a scan pulse to all the scan electrodes SC1 to SCn at a time and generate an address discharge in all the discharge cells in the image display area of the panel 10 at the same time.
- the voltage 0 (V) is applied to the data electrodes D1 to Dm. Further, voltage Vc is applied to scan electrodes SC1 to SCn, and then voltage 0 (V) is applied. Further, the voltage applied to sustain electrodes SU1 to SUn is changed from voltage Ve to voltage 0 (V). In the present embodiment, this state is maintained from time to0 to time To0. Therefore, during this period, after the last address discharge occurs in the discharge cells, a state in which no discharge occurs is maintained. Time to0 is the time when the scan pulse for generating the last address discharge is applied to scan electrode SCn.
- the time To0 is set to a time longer than any of the time To1, the time To2, and the time To3 described later.
- the time To0 is about 50 ⁇ sec, for example.
- the panel 10 is caused to emit a plurality of times of light emission (light emission for timing detection) as a reference when calculating the position coordinates of the light pen. That is, light emission for timing detection is emitted to all the discharge cells in the image display area of the panel 10 at a predetermined time interval (in this embodiment, for example, time To1, time To2, and time To3 in this embodiment).
- the timing detection discharge to be generated is generated a plurality of times (in this embodiment, for example, four times).
- timing detection pulse V1 of voltage Vso is applied to scan electrodes SC1 to SCn.
- first timing detection discharge is generated in all the discharge cells in the image display area of the panel 10, and the entire image display surface of the panel 10 emits light (first timing detection light emission).
- timing detection discharge is a stronger discharge than the address discharge, similarly to the sustain discharge.
- timing detection pulse V3 of voltage Vso is applied to scan electrodes SC1 to SCn.
- the third timing detection discharge is generated in all the discharge cells in the image display region of the panel 10, and the entire image display surface of the panel 10 emits light (third timing detection light emission).
- a predetermined time interval in the present embodiment, for example, time To1, time To2, and time To3 in this embodiment
- time To1, time To2, and time To3 in this embodiment is multiple times (in this embodiment, for example, 4 Timing detection discharge is generated, and the entire image display surface of the panel 10 is caused to emit light a plurality of times (for example, four times) at predetermined time intervals (for example, time To1, time To2, and time To3).
- the light pen receives this light emission and creates a coordinate reference signal (a signal that becomes a reference when calculating the position coordinates (x coordinate, y coordinate) of the light pen).
- the entire surface of the image display surface of the panel 10 shines at the same timing, so that the light pen is at the same timing no matter where the tip of the light pen is in the image display area of the panel 10. This light emission can be received.
- the time To1 is about 40 ⁇ sec
- the time To2 is about 20 ⁇ sec
- the time To3 is about 30 ⁇ sec.
- the present invention is not limited to the numerical values described above for the times To0 to To3, and each time may be set appropriately according to the specifications of the plasma display system.
- the light pen generates a coordinate reference signal when it detects a plurality of times (for example, four times) of light emission occurring at a predetermined time interval (for example, time To1, time To2, and time To3).
- the scan electrodes SC1 to SCn gradually increase from the voltage 0 (V) to the first voltage (voltage Vr) while the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn and the data electrodes D1 to Dm.
- a ramp waveform voltage of 1 is applied.
- the voltage applied to the scan electrodes SC1 to SCn is lowered to the voltage 0 (V).
- the voltage Vso is set to a voltage equal to the voltage Vs.
- the voltage Vso is about 205 (V).
- the voltage Vso may be a voltage different from the voltage Vs.
- the voltage Vso may be any voltage that generates timing detection discharge.
- a y-coordinate detection subfield SFy and an x-coordinate detection subfield SFx are generated.
- the y coordinate detection subfield SFy has an initialization period Piby, a y coordinate detection period Py, and an erase period Peby.
- timing detection discharges are generated in all the discharge cells in the image display area of the panel 10, and therefore in the initialization period Piby A weak initializing discharge is generated in all discharge cells.
- the wall voltage of all the discharge cells in the image display area of the panel 10 is adjusted to the wall voltage suitable for the y coordinate detection pattern display operation in the subsequent y coordinate detection period Py.
- priming particles that assist the generation of discharge in the y-coordinate detection period Py are generated in the discharge cell.
- the voltage Ve is applied to the sustain electrodes SU1 to SUn, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the scan electrodes SC1 to SCn are applied. A voltage Vc is applied. Then, this state is maintained during the period Ty0.
- This period Ty0 is longer than the above-described period Tw0, and is set to about 700 ⁇ sec, for example.
- y coordinate detection voltage Vdy is a voltage higher than the voltage 0 (V)
- the voltage Vay of the y coordinate detection pulse is a negative voltage lower than the voltage Vc.
- the pulse width of the y coordinate detection pulse is shown as Ty1.
- the data electrodes D1 to Dm and the scan electrodes The voltage difference at the intersection with SC1 exceeds the discharge start voltage, and discharge occurs between data electrodes D1 to Dm and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1.
- This discharge is as strong as the address discharge and is weaker than the sustain discharge.
- discharge occurs in all the discharge cells constituting the first row, and these discharge cells emit light all at once.
- the 5760 discharge cells (1920 pixels) constituting the first row emit light all at once. And this light emission becomes light emission for y coordinate detection.
- discharge cell row an aggregate of discharge cells constituting one row
- pixel row an aggregate of pixels constituting one row
- the discharge cell row and the pixel row are substantially the same, and in the above operation, the first pixel row (first discharge cell row) emits light all at once.
- a positive wall voltage is accumulated on scan electrode SC1
- a negative wall voltage is accumulated on sustain electrode SU1
- a negative wall voltage is also formed on data electrodes D1 to Dm. Is accumulated.
- a y coordinate detection pulse of the voltage Vay is applied to the scan electrode SC2 in the second row.
- light emission for y coordinate detection occurs in the second pixel row (second discharge cell row).
- one horizontal line that emits light corresponds to the upper end portion (pixels in the first row) of the image display area of the panel 10.
- a pattern (y-coordinate detection pattern) that sequentially moves one line at a time from the lower line to the lower end (nth pixel line) is displayed. That is, the y-coordinate detection pattern is a pattern in which each pixel row from the first row to the n-th row of the image display area sequentially emits light for each row.
- each pixel row from the first row to the n-th row of the image display region emits light sequentially for each row, so that the tip of the light pen is the image display region of the panel 10
- the timing at which the light pen receives this light emission varies depending on where the light pen is.
- the y coordinate of the position (x coordinate, y coordinate) of the light pen in the image display area is detected by detecting the light reception timing when the light emission is received by the light pen.
- the period during which the y-coordinate detection pattern is displayed on the panel 10 is very short. Therefore, the possibility that the y-coordinate detection pattern is recognized by the user is low, and even if it is recognized by the user, it is only a slight change in luminance.
- the time for applying the y-coordinate detection pulse to each of the scan electrodes SC1 to SCn is Ty1.
- the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn, and the data electrodes D1 to Dm are set to the high impedance state after the voltage 0 (V) is applied.
- the upward ramp waveform voltage that gently rises from the voltage 0 (V) to the first voltage (voltage Vr) is applied to the scan electrodes SC1 to SCn.
- the voltages of scan electrodes SC1 to SCn are once lowered to voltage 0 (V).
- a voltage Vi1 lower than the voltage Vr is applied to the scan electrodes SC1 to SCn, and an upward ramp waveform voltage that gradually rises from the voltage Vi1 to a second voltage (voltage Vi2) higher than the first voltage is applied.
- Voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrodes SU1 to SUn.
- the wall voltage of all the discharge cells in the image display area of panel 10 is adjusted to the wall voltage suitable for the initialization operation in the subsequent x coordinate detection subfield SFx. Furthermore, priming particles that assist the generation of discharge in the x-coordinate detection subfield SFx are generated in the discharge cell.
- FIG. 4 shows an example in which the rising ramp waveform voltage that rises in two steps from the voltage 0 (V) to the positive voltage Vi2 is applied to the scan electrodes SC1 to SCn.
- the start voltage of the second rising ramp voltage is equal to or lower than the maximum voltage of the first rising ramp voltage. It is desirable to set it to a value.
- the upward ramp waveform voltage is not limited to a configuration that is generated in two steps, and the upward ramp waveform voltage is continuous from voltage 0 (V) to voltage Vi2. It may be a waveform shape that rises.
- this upward ramp waveform voltage is referred to as a “second ramp waveform voltage”. Therefore, the second up-ramp waveform voltage shown in FIG. 4 has a waveform shape that rises in two steps from voltage 0 (V) to voltage Vi2, but rises continuously from voltage 0 (V) to voltage Vi2. A waveform having a waveform shape is also included in the second ramp waveform voltage.
- the voltage applied to the scan electrodes SC1 to SCn is once lowered to the voltage Vi3 lower than the voltage Vi2, and then set to the voltage 0 (V).
- the present invention is not limited to this configuration.
- the voltage may be sharply decreased from voltage Vi2 to voltage 0 (V).
- the subsequent x-coordinate detection subfield SFx has an initialization period Pidx, an x-coordinate detection period Px, and an erase period Pedx.
- a drive voltage waveform similar to that in the initialization period Piby of the y coordinate detection subfield SFy is applied to each electrode, and a selective initialization operation similar to that in the initialization period Piby is performed.
- a downward ramp waveform voltage having a larger amplitude than that of the downward ramp waveform voltage generated in the initialization period Piby is applied to the scan electrodes SC to SCn.
- the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the voltage Ve is applied to the sustain electrodes SU1 to SUn. Then, a downward ramp waveform voltage that falls from a voltage (for example, voltage 0 (V)) that is lower than the discharge start voltage to a negative voltage Va is applied to scan electrodes SC1 to SCn.
- a voltage for example, voltage 0 (V)
- the negative voltage Va has a lower voltage value than the negative voltage Vi4. That is, the absolute value of the voltage Va is larger than the absolute value of the voltage Vi4.
- the voltage Va is about ⁇ 200 (V), for example, and the voltage Vi4 is about ⁇ 175 (V), for example.
- the discharge and erasure discharge for detecting the y-coordinate occur in all the discharge cells in the image display area of the panel 10, and therefore, in the initialization period Pidx
- a weak initializing discharge is generated in all the discharge cells.
- the wall voltage of all the discharge cells in the image display area of the panel 10 is adjusted to the wall voltage suitable for the x coordinate detection pattern display operation in the subsequent x coordinate detection period Px.
- priming particles that assist the generation of discharge in the x-coordinate detection period Px are generated in the discharge cell.
- the arrival potential of the downward ramp waveform voltage generated in the initialization period Pidx of the x-coordinate detection subfield SFx is set to the voltage Va lower than the voltage Vi4 (larger absolute value), and the data electrodes D1 to The positive wall voltage remaining on Dm is applied to the data electrodes D1 to D1 at the end of the initialization periods Pia1, Pib2 to Pib8 of the subfields SF1 to SF8 of the image display subfield (or at the end of the initialization periods Pico and Piby). It is adjusted to a value lower than the positive wall voltage remaining on Dm.
- the voltage 0 (V) is applied to the data electrodes D1 to Dm
- the voltage Ve is applied to the sustain electrodes SU1 to SUn
- the scan electrodes SC1 to SCn are applied.
- a voltage Vc is applied to SCn. Then, this state is maintained during the period Tx0.
- This period Tx0 is set to be longer than the period Tw0 described above.
- the period Tx0 is desirably set between 200 ⁇ sec and 1 msec, and is set to about 700 ⁇ sec in the present embodiment, for example.
- the negative x-coordinate detection voltage Vax is applied to the scan electrodes SC1 to SCn, and the voltage applied to the scan electrodes SC1 to SCn reaches the x-coordinate detection voltage Vax.
- a positive x coordinate detection pulse of voltage Vdx is applied to data electrodes D1 to D3 in the first to third columns.
- the voltage Vdx of the x coordinate detection pulse is higher than the voltage 0 (V), and the x coordinate detection voltage Vax is a negative voltage lower than the voltage Vc.
- the pulse width of the x-coordinate detection pulse is shown as Tx1
- the drive voltage waveform applied to scan electrodes SC1 to SCn is a drive voltage waveform in which the voltage drops relatively slowly from voltage Vc to voltage Vax. As shown.
- the data electrodes D1 to D3 correspond to a red discharge cell, a green discharge cell, and a blue discharge cell constituting one pixel, and the pixel is a pixel arranged at the left end of the image display area, for example. It is.
- the data electrodes D1 to D3 and the scan electrodes SC1 to SC1 In the discharge cell at the intersection of the data electrodes D1 to D3 to which the x coordinate detection pulse of the voltage Vdx is applied and the scan electrodes SC1 to SCn to which the x coordinate detection voltage Vax is applied, the data electrodes D1 to D3 and the scan electrodes SC1 to SC1 The voltage difference at the intersection with SCn exceeds the discharge start voltage, and discharge occurs between data electrodes D1 to D3 and scan electrodes SC1 to SCn and between sustain electrodes SU1 to SUn and scan electrodes SC1 to SCn. .
- This discharge is the same as or weaker than the address discharge, and is weaker than the sustain discharge.
- discharge occurs in all the pixels constituting the first column, and these pixels emit light all at once.
- the 1080 pixels (3 columns ⁇ 1080 discharge cells) constituting the first column emit light all at once. And this light emission becomes light emission for x coordinate detection.
- discharge cell column an assembly of discharge cells constituting one column
- pixel column an assembly of discharge cells (pixel column) composed of three adjacent discharge cell columns
- the first pixel column that is, the first, second, and third discharge cell columns
- the x coordinate detection pulse of the voltage Vdx is applied to the data electrodes D4 to D6 in the fourth column to the sixth column.
- light emission for x coordinate detection occurs in the second pixel column (fourth, fifth, and sixth discharge cell columns).
- Similar operations are performed adjacent to each other in the order of data electrodes D7 to D9, data electrodes D10 to D12,..., Data electrodes Dm-2 to Dm, with the x coordinate detection voltage Vax being applied to scan electrodes SC1 to SCn.
- Each of the three data electrodes 22 is sequentially performed until reaching the m-th discharge cell, and light emission for x coordinate detection is performed on each pixel column from the third column to the last column (for example, 1920 column). Generate sequentially.
- the x coordinate detection pattern is a pattern in which each pixel column from the first column to the last column in the image display area sequentially emits light for each column.
- the x-coordinate detection pattern is a pattern in which three discharge cell columns adjacent to each other sequentially emit light by three columns from the left end (first column) to the right end (m column) of the image display area. is there.
- each pixel column from the first column to the last column in the image display region sequentially emits light for each column, so that the tip of the light pen is the image display region of the panel 10.
- the timing at which the light pen receives this light emission varies depending on where the light pen is.
- the x coordinate of the position (x coordinate, y coordinate) of the light pen in the image display area is detected.
- the period during which the x-coordinate detection pattern is displayed on the panel 10 is very short. Therefore, the possibility that the x coordinate detection pattern is recognized by the user is low, and even if it is recognized by the user, it is only a slight change in luminance.
- the time for applying the x-coordinate detection pulse to each of the data electrodes D1 to Dm is Tx1.
- the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn, and the data electrodes D1 to Dm are set to the high impedance state after the voltage 0 (V) is applied.
- the second ramp waveform voltage is applied to the scan electrodes SC1 to SCn in the same manner as the erase period Peby of the y coordinate detection subfield SFy. That is, when an upward ramp waveform voltage that gradually rises from the voltage 0 (V) to the first voltage (voltage Vr) is applied and the upward ramp waveform voltage reaches the voltage Vr, the voltages of the scan electrodes SC1 to SCn are temporarily set to voltages. Reduce to 0 (V). Next, a voltage Vi1 lower than the voltage Vr is applied to the scan electrodes SC1 to SCn, and an upward ramp waveform voltage that gradually rises from the voltage Vi1 to a second voltage (voltage Vi2) higher than the first voltage is applied. . Voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrodes SU1 to SUn.
- the voltage applied to the scan electrodes SC1 to SCn is once lowered to the voltage Vi3 lower than the voltage Vi2, and then set to the voltage 0 (V).
- the present invention is not limited to this configuration.
- the voltage may be sharply decreased from voltage Vi2 to voltage 0 (V).
- a voltage 0 (V) is applied to the data electrodes D1 to Dm, and a voltage Vs higher than the voltage Ve is applied to the sustain electrodes SU1 to SUn.
- a downward ramp waveform voltage that drops from a voltage (for example, voltage 0 (V)) that is lower than the discharge start voltage to a negative voltage Vi4 is applied to scan electrodes SC1 to SCn.
- this downward ramp waveform voltage is referred to as a “third ramp waveform voltage”.
- This third ramp waveform voltage is applied to scan electrodes SC1 to SCn, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm. In this case, a weak erasing discharge is generated.
- the wall voltage on scan electrodes SC1 to SCn and the wall voltage on sustain electrodes SU1 to SUn are weakened, and the positive wall voltage accumulated on data electrodes D1 to Dm is also weakened.
- the wall voltage of all the discharge cells in the image display area of panel 10 is adjusted to the wall voltage suitable for the initialization operation in subfield SF1 of the subsequent image display subfield. Furthermore, priming particles that assist the generation of the subsequent initializing discharge are generated in the discharge cell.
- FIG. 4 shows this dormant state as a dormant period BLK.
- the scan electrodes SC1 to SCn are supplied with the first voltage (voltage) from the voltage 0 (V).
- the second ramp waveform voltage rising to the second voltage (voltage Vi2) higher than Vr) is applied for the following reason.
- the erase operation is performed after the sustain discharge, which is a relatively strong discharge, is completed.
- the timing detection period Po of the timing detection subfield SFo similarly to the sustain discharge, the erase operation is performed after the timing detection discharge, which is a relatively strong discharge, is completed. Therefore, in these subfields, the wall charge sufficient to generate an erasing discharge is sufficient for the erasing operation even in the first erasing lamp that rises from the voltage 0 (V) to the first voltage (voltage Vr). Accumulated in the discharge cell immediately before.
- the erase operation is performed after the discharge for y-coordinate detection and the discharge for x-coordinate detection, which are weaker discharges than the sustain discharge, are completed. .
- the wall charges stored in the discharge cells immediately before these erasing operations are less than the wall charges stored in the discharge cells after the sustain operation is completed, and the first charge (voltage Vr) is reached.
- the first erase lamp that only rises there is a possibility that the erase discharge does not occur stably.
- the first voltage (voltage Vr) is used.
- the erase operation is performed using the second ramp waveform voltage that rises to a higher second voltage (voltage Vi2).
- the third voltage that drops from the voltage 0 (V) to the negative voltage Vi4 is applied to the scan electrodes SC1 to SCn following the second ramp waveform voltage.
- the ramp waveform voltage is applied for the following reason.
- the rest period BLK from the end of the x coordinate detection subfield SFx to the start of the subfield SF1 of the next field is a period in which a rest state in which no discharge occurs is maintained.
- the length of the pause period BLK is also changed because the number of sustain pulses generated is changed according to the image signal.
- the third ramp waveform voltage that drops to the voltage Vi4 is applied to the scan electrodes SC1 to SCn to further generate the erase discharge.
- the erasing operation is performed with the first ramp waveform voltage at the end of the sustain periods Ps1 to Ps8 and at the end of the timing detection period Po.
- the above is the outline of the drive voltage waveforms of the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx.
- FIG. 4 shows an example in which the x coordinate detection subfield SFx is generated after the y coordinate detection subfield SFy.
- the y coordinate detection subfield SFy is generated after the x coordinate detection subfield SFx.
- the drive voltage waveform generated during the erasing period Pedx of the x-coordinate detection subfield SFx shown in FIG. 4 is generated during the erasing period Peby of the y-coordinate detection subfield SFy, and the y-coordinate detection shown in FIG. It is assumed that the drive voltage waveform generated in the erase period Peby of the subfield SFy is generated in the erase period Pedx of the x coordinate detection subfield SFx.
- voltage Vc ⁇ 50 (V)
- voltage Vr 205 (V)
- voltage Ve 155 (V )
- the voltage Va, the voltage Vay, and the voltage Vax are set to be equal to each other, and the voltage Vd, the voltage Vdy, and the voltage Vdx are set to be equal to each other. Different voltages may be used.
- an upward ramp waveform voltage voltage Vi2 generated in the initialization period Pia1 of the subfield SF1 an upward ramp waveform voltage voltage Vi2 generated in the initialization period Pico of the timing detection subfield SFo
- the voltage Vi2 of the second ramp waveform voltage generated in the erase period Peby of the y-coordinate detection subfield SFy and the erase period Pedx of the x-coordinate detection subfield SFx is set to be equal to each other, but the voltages Vi2 are different from each other. It may be set.
- an upward ramp waveform voltage generated in the initialization period Pia1 of the subfield SF1, the initialization period Pico of the timing detection subfield SFo, the erase period Peby of the y coordinate detection subfield SFy, and the erase period Pedx of the x coordinate detection subfield SFx is about 1.5 (V / ⁇ sec).
- the gradient of the falling ramp waveform voltage generated in the initialization period Pidx of the detection subfield SFx is about ⁇ 2.5 (V / ⁇ sec).
- the gradient of the first ramp waveform voltage generated at the end of each sustain period Ps1 to Ps8 of the image display subfield (subfields SF1 to SF8) and at the end of the timing detection period Po of the timing detection subfield SFo is about 10 ( V / ⁇ sec).
- the specific numerical values such as the voltage value and the gradient described above are merely examples, and the present invention is not limited to the numerical values described above for each voltage value and the gradient.
- Each voltage value, gradient, and the like are preferably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.
- the reason why the timing detection subfield SFo is provided in one field and each drive voltage waveform of the timing detection subfield SFo is generated with the waveform shape shown in FIG. 4 is as follows.
- the light pen itself can generate a coordinate reference signal (a signal indicating the generation timing of the y-coordinate detection period Py and the x-coordinate detection period Px), and the timing detection subfield in one field.
- SFo is provided.
- the light pen detects light emission generated at a specific time interval on the panel 10 by timing detection discharge, and generates a coordinate reference signal. Based on this coordinate reference signal, the light pen calculates the position coordinates of the light pen itself.
- each drive voltage waveform of the timing detection subfield SFo is generated with the waveform shape shown in FIG. 4, and the time To0 is set to the time To1.
- the time To0 is set to a time longer than any of the time To1, the time To2, and the time To3. This is due to the following reasons.
- the light receiving element of the light pen also detects light emission generated by address discharge. Therefore, depending on the set value of time To0, the light pen may misrecognize the light emission generated by the address discharge in the address period Pwo of the timing detection subfield SFo as the light emission by the timing detection discharge.
- the time To0 is set to a time longer than the time To1, no matter where the light pen is in the image display area, the time from the time when the light pen detects light emission due to the write discharge to the time to1 The interval is longer than time To1. Thereby, it is possible to prevent the light pen from erroneously recognizing light emission due to the address discharge generated in the address period Pwo of the timing detection subfield SFo as light emission due to the timing detection discharge. If the time To0 is set to a time longer than any of the time To1, the time To2, and the time To3, the erroneous recognition can be prevented with higher accuracy, and the write in the image display area can be prevented. It becomes possible to detect the position (position coordinates) of the pen more accurately.
- the image display device detects the position (positional coordinates) of the light pen in the image display area while displaying an image corresponding to the image signal on the panel 10 by the above-described operation. Discharge can be generated stably, and the position coordinates of the light pen can be calculated with high accuracy.
- FIG. 5 is a diagram schematically showing an example of a circuit block and a plasma display system 30 constituting the plasma display device 100 according to the embodiment of the present invention.
- the plasma display system 30 shown in the present embodiment includes a plasma display device 100 and a light pen 50 as components.
- the plasma display device 100 includes a panel 10 and a driving circuit that drives the panel 10 with a plurality of subfields in one field.
- the drive circuit supplies power necessary for the image signal processing circuit 31, the data electrode drive circuit 32, the scan electrode drive circuit 33, the sustain electrode drive circuit 34, the timing generation circuit 35, the drawing circuit 44, the reception circuit 46, and each circuit block.
- a power supply circuit (not shown) for supplying is provided.
- the image signal processing circuit 31 receives an image signal, a drawing signal output from the drawing circuit 44, and a timing signal supplied from the timing generation circuit 35.
- the image signal processing circuit 31 combines the image signal and the drawing signal in order to display an image obtained by combining the image signal and the drawing signal on the panel 10, and applies red, green to each discharge cell based on the combined signal.
- Blue gradation values (gradation values expressed by one field) are set.
- the image signal processing circuit 31 uses the red, green, and blue gradation values set for each discharge cell as image data indicating lighting / non-lighting for each subfield (light emission / non-light emission is “1” of the digital signal).
- Data corresponding to “0”) and output the image data (red image data, green image data, and blue image data).
- the timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal.
- the generated timing signal is supplied to each circuit block (data electrode drive circuit 32, scan electrode drive circuit 33, sustain electrode drive circuit 34, image signal processing circuit 31, etc.).
- the data electrode driving circuit 32 Based on the image data output from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35, the data electrode driving circuit 32 performs the writing periods Pw1 to Pw1 of the subfields SF1 to SF8 which are image display subfields.
- the writing pulse of the voltage Vd is used
- the y coordinate detection period Py of the y coordinate detection subfield SFy the y coordinate detection voltage Vdy is used
- the x coordinate detection subfield SFx the x coordinate detection period.
- an x-coordinate detection pulse of voltage Vdx is applied to each data electrode D1 to Dm.
- Sustain electrode drive circuit 34 includes a sustain pulse generation circuit and a circuit (not shown in FIG. 5) for generating voltage Ve, and generates each drive voltage waveform based on the timing signal supplied from timing generation circuit 35.
- the voltage is applied to each of the sustain electrodes SU1 to SUn.
- the sustain pulse of the voltage Vs is used in the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8, which are image display subfields.
- the voltage Vso (equal to the voltage Vs in the present embodiment).
- timing detection pulses V2 and V4 the voltage Vs in the erasing period Pedx of the x-coordinate detection subfield SFx, the initialization periods Pia1, Pib2 to Pib8 and the writing periods of the subfields SF1 to SF8 which are image display subfields.
- Pw1 to Pw8 timing detection subfield SFo initialization period Pico and writing period Pwo, y coordinate detection subfield SFy initialization period Piby and y coordinate detection period Py, and x coordinate detection subfield SFx initialization period Pidx x coordinate detection period
- a voltage Ve at x it is applied to sustain electrodes SU1 ⁇ SUn.
- Scan electrode drive circuit 33 includes a ramp waveform voltage generation circuit, a sustain pulse generation circuit, and a scan pulse generation circuit (not shown in FIG. 5), and each drive voltage waveform is based on a timing signal supplied from timing generation circuit 35. Is applied to each of scan electrodes SC1 to SCn.
- the ramp waveform voltage generating circuit based on the timing signal, initializes the initialization periods Pia1, Pib2 to Pib8 and the sustain periods Pw1 to Pw8 of the subfields SF1 to SF8, which are image display subfields, and the initialization period of the timing detection subfield SFo.
- the ramp waveform voltage is applied to the scan electrodes SC1 to SCn.
- the sustain pulse generating circuit Based on the timing signal, the sustain pulse generating circuit generates sustain pulses in the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8 that are image display subfields, and the voltage Vso (this implementation) in the timing detection period Po of the timing detection subfield SFo.
- timing detection pulses V1 and V3 equal to the voltage Vs) are applied to the scan electrodes SC1 to SCn.
- the scan pulse generation circuit includes a plurality of scan electrode driving ICs (scan ICs), and based on the timing signal, the writing periods Pw1 to Pw8 of the subfields SF1 to SF8 that are image display subfields and the timing detection subfield Sfo
- scanning pulses of the voltage Vc and the voltage Va are used, in the y coordinate detection period Py of the y coordinate detection subfield SFy, the y coordinate detection pulse of the voltage Vc and voltage Vay is used, and the x coordinate detection period of the x coordinate detection subfield SFx.
- voltage Vc and x-coordinate detection voltage Vax are applied to scan electrodes SC1 to SCn.
- the light pen 50 is used when the user inputs characters, drawings and the like in the image display area of the panel 10 by handwriting.
- the light pen 50 is formed in a rod shape and includes a light receiving element 52, a timing detection circuit 54, a coordinate calculation circuit 56, and a transmission circuit 58.
- the light pen 50 has a contact switch.
- the contact switch is provided at the tip of the light pen 50 and detects the contact when the light pen 50 contacts the front substrate 11 of the panel 10 (the image display surface of the panel 10).
- the light receiving element 52 receives light emitted from the image display surface of the panel 10 and converts it into an electric signal (light receiving signal). Then, the light reception signal is output to the timing detection circuit 54 and the coordinate calculation circuit 56.
- the position coordinates (x, y) of the light pen 50 are positions where the light receiving element 52 receives light emitted from the image display surface.
- the timing detection circuit 54, the coordinate calculation circuit 56, and the transmission circuit 58 have a period during which the contact switch detects contact (for example, a period during which the manual switch is turned on in a non-contact type light pen without a contact switch). The following operations are performed.
- the timing detection circuit 54 detects light emission for timing detection (light emission generated by the timing detection discharge) generated in the timing detection period Po of the timing detection subfield SFo based on the light reception signal. Specifically, the timing detection circuit 54 measures a time interval of a plurality of (for example, five times) emission using a timer (not shown in FIG. 5) included in the timing detection circuit 54. Then, whether or not the time interval matches a predetermined time interval (for example, time To0, time To1, time To2, time To3) is determined by a plurality of threshold values (set in the timing detection circuit 54). For example, the determination is made by comparing the measured time interval with a threshold value corresponding to time To0, time To1, time To2, and time To3.
- a predetermined time interval for example, time To0, time To1, time To2, and time To3.
- the timing detection circuit 54 generates a coordinate reference signal based on one of the continuous plural times (for example, five times) of light emission.
- the coordinate reference signal is generated based on the light emission generated at the time to1 in the timing detection period Po of the timing detection subfield SFo.
- the time to1 is the time when the first timing detection pulse V1 is applied to the scan electrodes SC1 to SCn in the timing detection period Po of the timing detection subfield SFo.
- the coordinate reference signal is not shown in FIG. 4, but is, for example, a signal having rising edges at time ty0 and time tx0.
- Time ty0 is a time at which a y-coordinate detection pulse is applied to scan electrode SC1 in the first row in y-coordinate detection period Py of y-coordinate detection subfield SFy.
- Time tx0 is a time at which an x-coordinate detection pulse is applied to the data electrodes D1 to D3 corresponding to the first pixel column in the x-coordinate detection period Px of the x-coordinate detection subfield SFx.
- the timing detection circuit 54 outputs the coordinate reference signal to the coordinate calculation circuit 56.
- the coordinate reference signal may be generated on the basis of the time to2 at which the second timing detection pulse V2 is generated, or the time to3 at which the third timing detection pulse V3 is generated or the fourth timing detection pulse V4. You may generate
- the coordinate reference signal is not limited to a signal having rising edges at time ty0 and time tx0.
- the coordinate reference signal may be any signal that can be used as a reference for specifying the time when the light receiving element 52 receives light emission by the y coordinate detection pattern and light emission by the x coordinate detection pattern.
- the coordinate calculation circuit 56 includes a counter that measures the length of time and an arithmetic circuit that performs an operation on the output of the counter (not shown in FIG. 5).
- the coordinate calculation circuit 56 selectively extracts a signal indicating the light emission of the y coordinate detection pattern and a signal indicating the light emission of the x coordinate detection pattern from the light reception signal, and writes the light in the image display area.
- the position (x coordinate, y coordinate) of the pen 50 is calculated.
- the coordinate calculation circuit 56 counts the time (time Tyy) from time ty0 to the time (time tyy) from which light is first received by the light receiving element 52 after time ty0 based on the coordinate reference signal. Measure with Then, the time Tyy is divided by the time Ty1 (pulse width of the y coordinate detection pulse) in the arithmetic circuit. In this way, the y coordinate of the position of the light pen 50 in the image display area is calculated.
- the coordinate calculation circuit 56 measures, based on the coordinate reference signal, a time (time Txx) from time tx0 to time (time txx) when light is first received by the light receiving element 52 after time tx0. To do. Then, the time Txx is divided by the time Tx1 (pulse width of the x coordinate detection pulse) in the arithmetic circuit. In this way, the x coordinate of the position of the light pen 50 in the image display area is calculated.
- the time tyy is the time when the light receiving element 52 of the light pen 50 receives light emitted from the panel 10 by the y coordinate detection pattern
- the time txx is the time when the light receiving element 52 of the light pen 50 receives the panel 10 by the x coordinate detection pattern. It is the time when the light emission generated in
- the coordinate calculation circuit 56 outputs the position coordinates (x, y) of the light pen 50 calculated in this way to the transmission circuit 58.
- the transmission circuit 58 has a transmission circuit that encodes an electric signal and converts the encoded signal into a radio signal such as infrared rays and transmits the signal (not shown in FIG. 5). Then, a signal representing the position (coordinates (x, y)) of the light pen 50 calculated by the coordinate calculation circuit 56 is encoded, converted into a wireless signal, and wirelessly transmitted to the reception circuit 46 of the plasma display device 100.
- the light pen 50 is configured to perform the above-described operation even during a period in which the contact switch does not detect contact (in a non-contact type light pen without a contact switch, for example, a period in which the manual switch is turned off). May be.
- the reception circuit 46 includes a conversion circuit that receives a wireless signal wirelessly transmitted from the transmission circuit 58 of the light pen 50, decodes the received signal, and converts it into an electrical signal (not shown in FIG. 5).
- the wireless signal wirelessly transmitted from the transmission circuit 58 is converted into a signal representing the position (x coordinate, y coordinate) of the light pen 50 and output to the drawing circuit 44.
- the drawing circuit 44 includes an image memory 47 (referred to as memory in FIG. 5).
- the drawing circuit 44 generates a drawing signal for indicating the locus of the light pen 50 in the image display area of the panel 10 based on the signal received by the receiving circuit 46 (x coordinate and y coordinate calculated by the coordinate calculation circuit 56). To do.
- the drawing signal is a signal for displaying on the panel 10 an image or the like handwritten by the user, and is substantially the same as the image signal.
- the drawing signal is stored in the image memory 47.
- a drawing signal obtained by adding the current position coordinates of the light pen 50 to the past locus of the light pen 50 is accumulated in the image memory 47.
- the drawing circuit 44 outputs the drawing signal accumulated in the image memory 47 to the image signal processing circuit 31.
- the image signal processing circuit 31 synthesizes the drawing signal output from the drawing circuit 44 and the image signal, converts the image signal into image data, and outputs the image data to a subsequent circuit. In this way, the graphic input handwritten by the light pen 50 is combined with the image based on the image signal and displayed on the panel 10.
- the light pen 50 may be provided with a switch for switching between the “drawing” mode and the “erasing” mode.
- the trace of the light pen 50 shown on the panel 10 is traced with the light pen 50 again, so that the drawing signal stored in the image memory 47 can be partially or totally.
- the light pen may be configured in this way.
- the light pen 50 is configured so that the light receiving element 52 converts the received light emission into a light reception signal and outputs it to a subsequent circuit only when the tip of the light pen 50 is in contact with the image display surface of the panel 10. It may be.
- FIG. 6 is a circuit diagram schematically showing a configuration example of the scan electrode driving circuit 33 of the plasma display device 100 according to the embodiment of the present invention.
- the scan electrode drive circuit 33 includes a sustain pulse generation circuit 55, a ramp waveform voltage generation circuit 60, and a scan pulse generation circuit 70. Each circuit block operates based on the timing signal supplied from the timing generation circuit 35, but details of the timing signal path are omitted in FIG. Hereinafter, the voltage input to the scan pulse generation circuit 70 is referred to as “reference potential A”.
- Sustain pulse generation circuit 55 has power recovery circuit 51, switching element Q55, switching element Q56, and switching element Q59.
- the power recovery circuit 51 includes a power recovery capacitor C10, a switching element Q11, a switching element Q12, a backflow prevention diode Di11, a diode Di12, a resonance inductor L11, and an inductor L12.
- the power recovery circuit 51 recovers the power stored in the panel 10 from the panel 10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L12, and stores it in the capacitor C10. Then, the recovered power is supplied to the panel 10 again from the capacitor C10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L11, and reused as power when driving the scan electrodes SC1 to SCn.
- Switching element Q55 clamps scan electrodes SC1 to SCn to voltage Vs
- switching element Q56 clamps scan electrodes SC1 to SCn to voltage 0 (V).
- the switching element Q59 is a separation switch, and prevents a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 33.
- the scan pulse generation circuit 70 sequentially applies scan pulses to the scan electrodes SC1 to SCn at the timings shown in FIGS. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 55 as it is during the sustain period. That is, the reference potential A is output to scan electrodes SC1 to SCn.
- a voltage Vc and an x-coordinate detection voltage Vax are generated and applied to the scan electrodes SC1 to SCn.
- the ramp waveform voltage generation circuit 60 includes a Miller integration circuit 61, a Miller integration circuit 62, and a Miller integration circuit 63, and generates the ramp waveform voltage shown in FIGS.
- Up-slope waveform voltage (initialization period Pia1 of subfield SF1, which is an image display subfield, initialization period Pico of timing detection subfield SFo, erase period Peby of y coordinate detection subfield SFy, and x coordinate detection subfield SFx) is generated.
- the voltage Vt may be set so that a voltage obtained by superimposing the voltage Vp on the voltage Vt is equal to the voltage Vi2.
- switching element Q72 and switching elements Q71L1 to Q71Ln are turned off, switching elements Q71H1 to Q71Hn are turned on, and the rising ramp waveform voltage generated in Miller integrating circuit 61 is turned on.
- the up slope waveform voltage for the initialization operation can be generated by superimposing the voltage Vp of the power source E71 on the top.
- Miller integrating circuit 62 includes transistor Q62, capacitor C62, resistor R62, and diode Di62 for preventing backflow. Then, by applying a constant voltage to the input terminal IN62 (giving a constant voltage difference between two circles shown as the input terminal IN62), an up-slope waveform voltage that gradually rises toward the voltage Vr (The initialization period Pia1 of the subfield SF1, which is an image display subfield, the end of the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8, the end of the timing detection period Po of the timing detection subfield SFo, and the y coordinate detection subfield SFy An upward ramp waveform voltage generated in each period of the erasing period Peby and the erasing period Pedx of the x-coordinate detection subfield SFx is generated.
- Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63. Then, by applying a constant voltage to the input terminal IN63 (giving a constant voltage difference between two circles shown as the input terminal IN63), a downward ramp waveform voltage (gradiently decreasing toward the voltage Vi4 ( Initialization periods Pia1, Pib2 to Pib8 of the subfields SF1 to SF8 which are image display subfields, an initialization period Pico of the timing detection subfield SFo, an initialization period Piby of the y coordinate detection subfield SFy, and an x coordinate detection sub A downward ramp waveform voltage generated in each period of the initialization period Pidx of the field SFx).
- the switching element Q69 is a separation switch, and prevents a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 33.
- switching elements and transistors can be configured using generally known semiconductor elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the respective switching elements and transistors generated by the timing generation circuit 35.
- FIG. 7 is a circuit diagram schematically showing a configuration example of the sustain electrode drive circuit 34 of the plasma display apparatus 100 according to the embodiment of the present invention.
- the sustain electrode driving circuit 34 includes a sustain pulse generating circuit 80 and a constant voltage generating circuit 85. Each circuit block operates based on the timing signal supplied from the timing generation circuit 35, but details of the timing signal path are omitted in FIG.
- Sustain pulse generation circuit 80 has a power recovery circuit 81, a switching element Q83, and a switching element Q84.
- the power recovery circuit 81 includes a power recovery capacitor C20, a switching element Q21, a switching element Q22, a backflow prevention diode Di21, a diode Di22, a resonance inductor L21, and an inductor L22.
- the power recovery circuit 81 recovers the power stored in the panel 10 from the panel 10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L22, and stores it in the capacitor C20. Then, the recovered power is supplied to the panel 10 again from the capacitor C20 by LC resonance between the interelectrode capacitance of the panel 10 and the inductor L21, and is reused as power when driving the sustain electrodes SU1 to SUn.
- Switching element Q83 clamps sustain electrodes SU1 to SUn to voltage Vs, and switching element Q84 clamps sustain electrodes SU1 to SUn to voltage 0 (V).
- sustain pulse generating circuit 80 generates a sustain pulse of voltage Vs and applies it to sustain electrodes SU1 to SUn. Further, the timing detection pulses V2 and V4 are applied to the sustain electrodes SU1 to SUn in the timing detection period Po of the timing detection subfield SFo, and the voltage Vs is applied in the erasure period Pedx of the x coordinate detection subfield SFx.
- the constant voltage generation circuit 85 includes a switching element Q86 and a switching element Q87. Then, the constant voltage generation circuit 85 writes the initialization periods Pia1, Pib2 to Pib8 and the writing periods Pw1 to Pw8 of the subfields SF1 to SF8, which are image display subfields, and the initialization period Pico and the writing of the timing detection subfield SFo.
- the voltage Ve is applied to the sustain electrodes SU1 to SUn. Apply.
- sustain electrode drive circuit 34 may be turned off in order to set sustain electrodes SU1 to SUn to a high impedance state.
- these switching elements can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements are controlled by timing signals corresponding to the respective switching elements generated by the timing generation circuit 35.
- FIG. 8 is a circuit diagram schematically showing a configuration example of the data electrode driving circuit 32 of the plasma display device 100 according to the embodiment of the present invention.
- the data electrode drive circuit 32 operates based on the image data supplied from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35. In FIG. 8, details of the paths of these signals are omitted. To do.
- the data electrode drive circuit 32 includes switching elements Q91H1 to Q91Hm and switching elements Q91L1 to Q91Lm. Then, voltage 0 (V) is applied to data electrode Dj by turning on switching element Q91Lj, and voltage Vd is applied to data electrode Dj by turning on switching element Q91Hj. In this way, the data electrode driving circuit 32 applies the write pulse of the voltage Vd to the write period Pwo of the subfields SF1 to SF8 which are image display subfields and the write period Pwo of the timing detection subfield SFo.
- FIG. 9 is a diagram schematically showing an example of the operation when detecting the position coordinates of the light pen 50 in the plasma display system 30 according to the embodiment of the present invention.
- the image display area is indicated by a broken line, but this broken line is not actually displayed on the panel 10.
- FIG. 10 is a diagram schematically showing an example of a driving voltage waveform when the position coordinates of the light pen 50 are detected in the plasma display system 30 according to the embodiment of the present invention.
- FIG. 10 shows scan electrode SC1, scan electrode SCn, data electrode D1, and data in timing detection subfield SFo, y-coordinate detection subfield SFy, and x-coordinate detection subfield SFx following image display subfield SF8.
- a driving voltage waveform applied to each of the electrodes Dm, a coordinate reference signal input to the coordinate calculation circuit 56, and a light reception signal output from the light receiving element 52 are shown.
- the drive voltage waveforms applied to sustain electrodes SU1 to SUn are omitted, but the drive voltage waveforms shown in FIG. 10 are the same as the drive voltage waveforms shown in FIGS.
- time Toy from time to1 to time ty0 is determined in advance, and time Tox from time to1 to time tx0 is determined in advance.
- the timing detection circuit 54 can generate a coordinate reference signal having rising edges at each of the time ty0 and the time tx0 and output it to the coordinate calculation circuit 56 as shown in FIG. it can.
- the timing detection circuit 54 emits light of five consecutive times in which the intervals of light emission are time To0, time To1, time To2, and time To3 (output from the light receiving element 52 based on these light emission). Is detected by detecting the received light signal).
- a y-coordinate detection pattern in which linear light emission extended in the first direction (row direction) sequentially moves in the second direction (column direction) is displayed on the panel 10.
- a y-coordinate detection pattern in which linear light emission extended in the first direction (row direction) sequentially moves in the second direction (column direction) is displayed on the panel 10.
- one horizontal line Ly that sequentially moves from the upper end (first row) to the lower end (nth row) of the image display region is displayed in the image display region of the panel 10. Is done.
- the tip of the light pen 50 is in contact with (or close to) the “coordinates (x, y)” of the image display surface of the panel 10, at the time tyy when the horizontal line Ly passes the coordinates (x, y), the light
- the light receiving element 52 of the pen 50 receives the light emission of the horizontal line Ly.
- the light pen 50 outputs a light reception signal indicating that the light receiving element 52 has received the light emission of the horizontal line Ly at time tyy.
- an x-coordinate detection pattern in which linear light emission extended in the second direction (column direction) sequentially moves in the first direction (row direction) is displayed on the panel. 10 is displayed. Accordingly, as shown in FIG. 9, the image display area of the panel 10 is sequentially moved from the left end portion (first pixel column) to the right end portion (m / 3 pixel row) of the image display area. One vertical line Lx is displayed.
- the tip of the light pen 50 is in contact with (or close to) the “coordinate (x, y)” of the image display surface of the panel 10, at the time txx when the vertical line Lx passes the coordinate (x, y),
- the light receiving element 52 of the light pen 50 receives the light emission of the vertical line Lx. Accordingly, as shown in FIG. 10, the light pen 50 outputs a light reception signal indicating that the light receiving element 52 has received the light emission of the vertical line Lx at time txx.
- the coordinate calculation circuit 56 shown in FIG. 5 is based on the coordinate reference signal output from the timing detection circuit 54 and the light reception signal output from the light receiving element 52 in the y coordinate detection period Py of the y coordinate detection subfield SFy.
- the time Tyy from the time ty0 to the time tyy is measured using the counter provided for.
- the time Tyy is divided by the time Ty1 in the arithmetic circuit provided inside. The division result is the y coordinate of the position of the light pen 50 in the image display area.
- the coordinate calculation circuit 56 is provided internally based on the coordinate reference signal output from the timing detection circuit 54 and the light reception signal output from the light receiving element 52 in the x coordinate detection period Px of the x coordinate detection subfield SFx.
- a time Txx from time tx0 to time txx is measured using a counter. Then, the time Txx is divided by the time Tx1 in the arithmetic circuit provided inside. This division result is the x coordinate of the position of the light pen 50 in the image display area.
- the coordinate calculation circuit 56 in the present embodiment calculates the position (coordinates (x, y)) of the light pen 50 in the image display area.
- FIG. 11 is a diagram schematically showing an example of an operation when handwriting input is performed with the light pen 50 in the plasma display system 30 according to the embodiment of the present invention.
- the image display area is indicated by a broken line, but this broken line is not actually displayed on the panel 10.
- the drawing circuit 44 outputs a drawing signal of a drawing pattern (for example, a pattern such as a white circle) having a predetermined color and size around a pixel corresponding to the coordinates (x, y) calculated by the coordinate calculation circuit 56. Write to memory 47.
- a drawing pattern for example, a pattern such as a white circle
- the coordinates (x, y) calculated by the coordinate calculation circuit 56 also correspond to the movement of the light pen 50. Change.
- the drawing circuit 44 sequentially writes a drawing signal corresponding to the drawing pattern whose position has changed in the image memory 47 while changing the position of the drawing pattern in accordance with the changing coordinates (x, y).
- the drawing signal indicating the locus of the light pen 50 is accumulated in the image memory 47 of the drawing circuit 44.
- the drawing signal stored in the image memory 47 is read for each field and output to the image signal processing circuit 31.
- the image signal processing circuit 31 combines the drawing signal output from the drawing circuit 44 and the image signal, and generates image data based on the combined signal.
- the panel 10 displays an image in which an image indicating the locus of the light pen 50 (a graphic input by handwriting using the light pen 50) is superimposed on the image signal.
- the image display system for example, the plasma display system 30
- the plasma display system 30 in the present embodiment can generate a stable discharge
- the y coordinate detection pattern and the x coordinate detection pattern with high accuracy are displayed on the panel 10. Can be displayed.
- the light pen 50 can calculate the position coordinates (x coordinate, y coordinate) with higher accuracy. Therefore, in the plasma display system 30 in the present embodiment, the locus of the light pen 50 can be drawn based on accurate position coordinates.
- timing detection discharge is generated four times at predetermined time intervals (for example, time To1, time To2, and time To3) in the timing detection subfield SFo.
- the number of timing detection discharges may be two or more.
- the present embodiment it is desirable to set the time intervals for generating the timing detection discharge a plurality of times in order to easily identify the first timing detection discharge.
- the configuration in which the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx are provided in each field has been described.
- the present invention is not limited to this configuration. Absent.
- the configuration may be such that those subfields are generated at a rate of once in a plurality of fields.
- the plasma display device and the light pen may be electrically connected by an electric cable or the like, and a signal may be transmitted and received between the light pen and the plasma display device via the electric cable.
- the timing detection subfield SFo may not be provided.
- each operation has been described by taking a plasma display device using a plasma display panel as an image display unit as an example of the image display device.
- the image display device is not limited to the plasma display device.
- the same effect as that described above can be obtained by applying the same configuration as that described above.
- one field has a plurality of image display subfields and a subfield for detecting position coordinates.
- the present invention is not limited to this configuration. is not.
- one field may be composed of only the image display subfield.
- the forced initializing operation has been described as an initializing operation that forcibly generates initializing discharge in all the discharge cells in the image display area of the panel. It is not limited to this configuration.
- the forced initializing waveform is applied only to some discharge cells in the image display area of the panel and the initializing discharge is forcibly generated only in the discharge cells. It shall be included in the conversion operation.
- a configuration in which the drawing circuit 44 is provided in the plasma display device is shown, but the present invention is not limited to this configuration.
- a computer connected to the plasma display device may have a function corresponding to the drawing circuit 44, and a drawing signal may be generated using the computer.
- the drive voltage waveforms shown in FIGS. 3, 4, and 10 are merely examples in the embodiment of the present invention, and the present invention is not limited to these drive voltage waveforms.
- circuit configurations shown in FIGS. 5, 6, 7, and 8 are merely examples in the embodiment of the present invention, and the present invention is not limited to these circuit configurations. .
- Each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or substantially the same as each operation shown in the embodiment.
- a microcomputer or a computer programmed to operate may be used.
- the specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 14 of 1024. It is just an example.
- the present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with panel specifications, panel characteristics, plasma display device specifications, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.
- the present invention can stably generate a discharge for detecting the position coordinates of the light pen and accurately detect the position coordinates of the light pen, the driving method of the image display apparatus, the image display apparatus, and the image display Useful as a system.
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Abstract
An objective of the present invention is to stably generate electricity discharges. To this end, provided is an image display device drive method wherein: a field is generated comprising a plurality of image display subfields, a y-coordinate detection subfield, and an x-coordinate detection subfield, and either the y-coordinate detection subfield or the x-coordinate detection subfield is generated at the end of the field. The image display subfield further comprises a preservation period in which a rising oblique waveform voltage, which rises to a first voltage after the generation of a preservation pulse, is applied to a scanning electrode. Either the y-coordinate detection subfield or the x-coordinate detection subfield which is generated at the end of the field further comprises a deletion period in which a rising oblique waveform voltage, which rises to a second voltage which is greater than the first voltage, and a falling oblique waveform voltage, are applied to the scanning electrode.
Description
本発明は、画素を構成する複数の発光素子における発光と非発光の2値制御を組み合わせて画像表示領域に画像を表示する画像表示装置の駆動方法、画像表示装置、およびライトペンを用いて画像表示装置に文字や図画の手書き入力ができる画像表示システムに関する。
The present invention relates to a driving method of an image display apparatus that displays an image in an image display area by combining binary control of light emission and non-light emission in a plurality of light emitting elements constituting a pixel, an image display apparatus, and an image using a light pen. The present invention relates to an image display system capable of handwritten input of characters and drawings on a display device.
画素を構成する複数の発光素子のそれぞれにおける発光と非発光の2値制御を組み合わせて画像表示領域に画像を表示する画像表示装置として代表的なものにプラズマディスプレイパネル(以下、「パネル」と略記する)がある。
A plasma display panel (hereinafter abbreviated as “panel”) is a typical image display device that displays an image in an image display area by combining binary control of light emission and non-light emission in each of a plurality of light emitting elements constituting a pixel. There is).
パネルは、対向配置された前面基板と背面基板との間に、画素を構成する発光素子である放電セルが多数形成されている。
In the panel, a large number of discharge cells, which are light-emitting elements constituting pixels, are formed between a front substrate and a rear substrate that are arranged to face each other.
前面基板は、1対の走査電極と維持電極とからなる表示電極対が前面側のガラス基板上に互いに平行に複数対形成されている。背面基板は、背面側のガラス基板上に互いに平行なデータ電極が複数形成されている。
In the front substrate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate. The back substrate has a plurality of parallel data electrodes formed on a glass substrate on the back side.
各放電セル内には、赤色(R)、緑色(G)および青色(B)のいずれかの蛍光体が塗布され、放電ガスが封入されている。そして、各放電セルでは、ガス放電を起こすことで紫外線を発生し、この紫外線で蛍光体を励起発光する。
Each discharge cell is coated with one of red (R), green (G), and blue (B) phosphors, and a discharge gas is enclosed therein. In each discharge cell, an ultraviolet ray is generated by causing a gas discharge, and the phosphor is excited to emit light by the ultraviolet ray.
発光素子における発光と非発光との2値制御を組み合わせてパネルの画像表示領域に画像を表示する方法としては一般にサブフィールド法が用いられている。
A subfield method is generally used as a method of displaying an image in an image display area of a panel by combining binary control of light emission and non-light emission in a light emitting element.
サブフィールド法では、1フィールドを、発光輝度が互いに異なる複数のサブフィールドに分割する。そして、各放電セルでは、表示すべき階調値に応じた組合せで各サブフィールドの発光・非発光を制御する。これにより各放電セルが表示すべき階調値に応じた明るさで発光し、パネルの画像表示領域に、様々な階調値の組合せで構成されたカラーの画像が表示される。
In the subfield method, one field is divided into a plurality of subfields having different emission luminances. In each discharge cell, light emission / non-light emission of each subfield is controlled by a combination according to the gradation value to be displayed. As a result, each discharge cell emits light with brightness corresponding to the gradation value to be displayed, and a color image composed of various combinations of gradation values is displayed in the image display area of the panel.
このような画像表示装置には、「ライトペン」と呼ばれるポインティングデバイスを使用して、パネル上に、文字や図画を手書き入力することができる機能を有するものがある。
Some of such image display apparatuses have a function of allowing handwriting input of characters and drawings on a panel using a pointing device called “light pen”.
ライトペンを用いた手書き入力機能を実現するために、画像表示領域内におけるライトペンの位置を検出する技術が開示されている。以下、画像表示領域内におけるライトペンの位置を表す座標を「位置座標」と記す。
In order to realize a handwriting input function using a light pen, a technique for detecting the position of the light pen in an image display area is disclosed. Hereinafter, the coordinates representing the position of the light pen in the image display area are referred to as “position coordinates”.
例えば、特許文献1に記載されたプラズマディスプレイ装置では、横座標検出用パターンを表示する横座標検出サブフィールドを1フィールド内に設ける。そして、この横座標検出サブフィールドの発光をライトペンで検出し、その発光が検出されたタイミングにもとづきライトペンの位置(横座標)を検出する。
For example, in the plasma display device described in Patent Document 1, an abscissa detection subfield for displaying an abscissa detection pattern is provided in one field. Then, the light emission of this abscissa detection subfield is detected by the light pen, and the position (abscissa) of the light pen is detected based on the timing at which the light emission is detected.
また、特許文献2に記載されたプラズマディスプレイ装置では、位置座標検出用の光信号を発生する位置検出期間を、ライトペンの位置座標を検出するときのみ1フィールド内に設ける。そして、この光信号をライトペンで検出し、その光信号が検出されたタイミングにもとづきライトペンの位置座標を検出する。
In the plasma display device described in Patent Document 2, a position detection period for generating a light signal for detecting position coordinates is provided in one field only when detecting the position coordinates of the light pen. Then, this light signal is detected by the light pen, and the position coordinates of the light pen are detected based on the timing at which the light signal is detected.
本開示における画像表示装置は、複数の走査電極および維持電極と複数のデータ電極とを有する画像表示部と、1フィールドを複数のサブフィールドで構成して画像表示部を駆動する駆動回路とを備える。この画像表示装置において、駆動回路は、画像表示サブフィールド、y座標検出サブフィールド、およびx座標検出サブフィールドを有するフィールドを発生するとともに、y座標検出サブフィールドまたはx座標検出サブフィールドをそのフィールドの最後に発生する。駆動回路は、画像表示サブフィールドの維持期間では、走査電極および維持電極に交互に維持パルスを印加した後に第1の電圧まで上昇する上り傾斜波形電圧を走査電極に印加する。また、駆動回路は、フィールドの最後に発生するy座標検出サブフィールドまたはx座標検出サブフィールドに、第1の電圧よりも高い第2の電圧まで上昇する上り傾斜波形電圧と下り傾斜波形電圧を走査電極に印加する消去期間を設ける。
An image display device according to the present disclosure includes an image display unit having a plurality of scan electrodes, sustain electrodes, and a plurality of data electrodes, and a drive circuit configured to form one field by a plurality of subfields and drive the image display unit. . In this image display device, the drive circuit generates a field having an image display subfield, a y-coordinate detection subfield, and an x-coordinate detection subfield, and the y-coordinate detection subfield or the x-coordinate detection subfield is set in the field. It happens last. In the sustain period of the image display subfield, the drive circuit applies an upward ramp waveform voltage that rises to the first voltage after alternately applying a sustain pulse to the scan electrode and the sustain electrode, to the scan electrode. In addition, the driving circuit scans an up-slope waveform voltage and a down-slope waveform voltage that rise to a second voltage higher than the first voltage in the y-coordinate detection subfield or the x-coordinate detection subfield generated at the end of the field. An erasing period to be applied to the electrode is provided.
これにより、放電を安定に発生し、ライトペンの位置座標を精度良く検出することが可能になる。
This makes it possible to generate a stable discharge and detect the position coordinates of the light pen with high accuracy.
本開示における画像表示システムは、上述の画像表示装置と、ライトペンと、座標算出回路および描画回路とを備える。ライトペンは、受光素子を有し、y座標検出サブフィールドにおいて画像表示部に生じる発光、およびx座標検出サブフィールドにおいて画像表示部に生じる発光を受光して受光信号を出力する。座標算出回路は、受光信号にもとづき、y座標検出サブフィールドにおいて画像表示部に生じる発光のうちのライトペンが受光する発光の位置を表す座標、およびx座標検出サブフィールドにおいて画像表示部に生じる発光のうちのライトペンが受光する発光の位置を表す座標を算出する。描画回路は、座標算出回路が算出した座標にもとづく画像を画像表示部に表示するための描画信号を作成する。そして、画像表示装置は、描画信号にもとづく画像を画像表示部に表示する。
An image display system according to the present disclosure includes the above-described image display device, a light pen, a coordinate calculation circuit, and a drawing circuit. The light pen has a light receiving element, and receives light emission generated in the image display unit in the y coordinate detection subfield and light emission generated in the image display unit in the x coordinate detection subfield, and outputs a light reception signal. The coordinate calculation circuit, based on the light reception signal, coordinates indicating the position of light emission received by the light pen in the light emission generated in the image display unit in the y coordinate detection subfield, and light emission generated in the image display unit in the x coordinate detection subfield. The coordinates representing the light emission position received by the light pen are calculated. The drawing circuit creates a drawing signal for displaying an image based on the coordinates calculated by the coordinate calculation circuit on the image display unit. Then, the image display device displays an image based on the drawing signal on the image display unit.
これにより、放電を安定に発生し、ライトペンの位置座標を精度良く検出することが可能になる。
This makes it possible to generate a stable discharge and detect the position coordinates of the light pen with high accuracy.
以下、本発明の実施の形態における画像表示装置および画像表示システムについて、図面を用いて説明する。なお、以下の実施の形態では、画像表示装置および画像表示システムの一例として、プラズマディスプレイパネルを有するプラズマディスプレイ装置およびプラズマディスプレイシステムの説明を行う。
Hereinafter, an image display device and an image display system according to embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a plasma display device having a plasma display panel and a plasma display system will be described as an example of an image display device and an image display system.
(実施の形態)
図1は、本発明の実施の形態におけるプラズマディスプレイ装置に用いるパネルの構造の一例を示す分解斜視図である。 (Embodiment)
FIG. 1 is an exploded perspective view showing an example of the structure of a panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
図1は、本発明の実施の形態におけるプラズマディスプレイ装置に用いるパネルの構造の一例を示す分解斜視図である。 (Embodiment)
FIG. 1 is an exploded perspective view showing an example of the structure of a panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
ガラス製の前面基板11上には、走査電極12と維持電極13とからなる表示電極対14が複数形成されている。そして、表示電極対14を覆うように誘電体層15が形成され、その誘電体層15上に保護層16が形成されている。前面基板11は画像が表示される画像表示面となる。
A plurality of display electrode pairs 14 each including a scanning electrode 12 and a sustaining electrode 13 are formed on a glass front substrate 11. A dielectric layer 15 is formed so as to cover the display electrode pair 14, and a protective layer 16 is formed on the dielectric layer 15. The front substrate 11 serves as an image display surface on which an image is displayed.
背面基板21上にはデータ電極22が複数形成され、データ電極22を覆うように誘電体層23が形成され、さらにその上に井桁状の隔壁24が形成されている。そして、隔壁24の側面および誘電体層23の表面には赤色(R)に発光する蛍光体層25R、緑色(G)に発光する蛍光体層25G、および青色(B)に発光する蛍光体層25Bが設けられている。以下、蛍光体層25R、蛍光体層25G、蛍光体層25Bをまとめて蛍光体層25とも記す。
A plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is further formed thereon. The phosphor layer 25R that emits red (R), the phosphor layer 25G that emits green (G), and the phosphor layer that emits blue (B) are formed on the side surfaces of the barrier ribs 24 and the surface of the dielectric layer 23. 25B is provided. Hereinafter, the phosphor layer 25R, the phosphor layer 25G, and the phosphor layer 25B are collectively referred to as a phosphor layer 25.
これら前面基板11と背面基板21とを、微小な空間を挟んで表示電極対14とデータ電極22とが交差するように対向配置し、前面基板11と背面基板21との間隙に放電空間を設ける。そして、その外周部をガラスフリット等の封着材によって封着する。その放電空間には、例えばネオンとキセノンの混合ガスを放電ガスとして封入する。
The front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 intersect each other with a minute space therebetween, and a discharge space is provided in the gap between the front substrate 11 and the rear substrate 21. . And the outer peripheral part is sealed with sealing materials, such as glass frit. For example, a mixed gas of neon and xenon is sealed in the discharge space as a discharge gas.
放電空間は隔壁24によって複数の区画に仕切られており、表示電極対14とデータ電極22とが交差する部分に、画素を構成する発光素子である放電セルが形成される。
The discharge space is partitioned into a plurality of sections by the barrier ribs 24, and discharge cells, which are light-emitting elements constituting the pixels, are formed at the intersections between the display electrode pairs 14 and the data electrodes 22.
そして、これらの放電セルで放電を発生し、蛍光体層25を発光(放電セルを点灯)することにより、パネル10にカラーの画像を表示する。
Then, discharge is generated in these discharge cells, and the phosphor layer 25 emits light (discharge cells are turned on), thereby displaying a color image on the panel 10.
なお、パネル10においては、表示電極対14が延伸する方向に配列された連続する3つの放電セルで1つの画素を構成する。この3つの放電セルとは、蛍光体層25Rを有し赤色(R)に発光する放電セル(以下、「赤の放電セル」、または「赤のピクセル」と記す)と、蛍光体層25Gを有し緑色(G)に発光する放電セル(以下、「緑の放電セル」、または「緑のピクセル」と記す)と、蛍光体層25Bを有し青色(B)に発光する放電セル(以下、「青の放電セル」、または「青のピクセル」と記す)である。
In the panel 10, one pixel is composed of three consecutive discharge cells arranged in the direction in which the display electrode pair 14 extends. The three discharge cells are a discharge cell having a phosphor layer 25R and emitting red (R) light (hereinafter referred to as “red discharge cell” or “red pixel”), and a phosphor layer 25G. Discharge cells (hereinafter referred to as “green discharge cells” or “green pixels”) having a green color (G), and discharge cells (hereinafter referred to as “green pixels”) having a phosphor layer 25B. , “Blue discharge cells” or “blue pixels”).
なお、パネル10の構造は上述したものに限られるわけではなく、例えばストライプ状の隔壁を備えたものであってもよい。
Note that the structure of the panel 10 is not limited to the above-described structure, and may be, for example, provided with a stripe-shaped partition wall.
図2は、本発明の実施の形態におけるプラズマディスプレイ装置に用いるパネルの電極配列の一例を示す図である。
FIG. 2 is a diagram showing an example of the electrode arrangement of the panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
パネル10には、第1の方向に延長されたn本の走査電極SC1~SCn(図1の走査電極12)およびn本の維持電極SU1~SUn(図1の維持電極13)が配列され、第1の方向に交差する第2の方向に延長されたm本のデータ電極D1~Dm(図1のデータ電極22)が配列されている。
In the panel 10, n scan electrodes SC1 to SCn (scan electrode 12 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 13 in FIG. 1) extended in the first direction are arranged. The m data electrodes D1 to Dm (data electrode 22 in FIG. 1) extended in the second direction intersecting the first direction are arranged.
以下、第1の方向を行方向(または水平方向、またはライン方向)と呼称し、第2の方向を列方向(または垂直方向)と呼称する。
Hereinafter, the first direction is referred to as a row direction (or horizontal direction or line direction), and the second direction is referred to as a column direction (or vertical direction).
そして、1対の走査電極SCi(i=1~n)および維持電極SUiと1つのデータ電極Dj(j=1~m)とが交差した領域に発光素子としての放電セルが1つ形成される。すなわち、1対の表示電極対14上には、m個の放電セルが形成され、m/3個の画素が形成される。そして、放電セルは放電空間内にm×n個形成され、m×n個の放電セルが形成された領域がパネル10の画像表示領域となる。例えば、画素数が1920×1080個のパネルでは、m=1920×3=5760となり、n=1080となる。
One discharge cell as a light emitting element is formed in a region where a pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects with one data electrode Dj (j = 1 to m). . In other words, m discharge cells are formed on one pair of display electrodes 14 and m / 3 pixels are formed. Then, m × n discharge cells are formed in the discharge space, and an area where m × n discharge cells are formed becomes an image display area of the panel 10. For example, in a panel having 1920 × 1080 pixels, m = 1920 × 3 = 5760 and n = 1080.
例えば、データ電極Dp(p=3×q-2 : qはm/3以下の正の整数)を有する放電セルには赤の蛍光体が蛍光体層25Rとして塗布されており、この放電セルは赤の放電セルとなる。データ電極Dp+1を有する放電セルには緑の蛍光体が蛍光体層25Gとして塗布されており、この放電セルは緑の放電セルとなる。データ電極Dp+2を有する放電セルには青の蛍光体が蛍光体層25Bとして塗布されており、この放電セルは青の放電セルとなる。そして、互いに隣接する赤の放電セル、緑の放電セルおよび青の放電セルが一組となって1つの画素を構成する。
For example, a red phosphor is applied as a phosphor layer 25R to a discharge cell having a data electrode Dp (p = 3 × q−2: q is a positive integer of m / 3 or less). It becomes a red discharge cell. The discharge cell having the data electrode Dp + 1 is coated with a green phosphor as the phosphor layer 25G, and this discharge cell becomes a green discharge cell. A blue phosphor is applied as a phosphor layer 25B to the discharge cell having the data electrode Dp + 2, and this discharge cell becomes a blue discharge cell. A red discharge cell, a green discharge cell, and a blue discharge cell adjacent to each other constitute a set to constitute one pixel.
次に、本実施の形態におけるプラズマディスプレイ装置において発生する駆動電圧波形について図3と図4を用いて説明する。
Next, driving voltage waveforms generated in the plasma display device according to the present embodiment will be described with reference to FIGS.
本実施の形態においては、1フィールドに、パネル10に画像を表示するための複数の画像表示サブフィールド、タイミング検出サブフィールドSFo、y座標検出サブフィールドSFy、およびx座標検出サブフィールドSFxを備える。以下、画像表示サブフィールドを単にサブフィールドとも記す。
In this embodiment, one field includes a plurality of image display subfields for displaying an image on the panel 10, a timing detection subfield SFo, a y coordinate detection subfield SFy, and an x coordinate detection subfield SFx. Hereinafter, the image display subfield is also simply referred to as a subfield.
各画像表示サブフィールドは、初期化期間、書込み期間および維持期間を有する。
Each image display subfield has an initialization period, an address period, and a sustain period.
初期化期間では、各放電セルに初期化放電を発生し、続く書込み動作に必要な壁電荷を放電セル内に形成する。加えて、書込み動作に必要なプライミング粒子(放電の発生を補助する荷電粒子)を放電セル内に発生する。書込み期間では、発光を行うべき放電セルに書込み放電を発生する。維持期間では、走査電極と維持電極とに交互に維持パルスを印加し、書込み放電を発生した放電セルに維持放電を発生させる。
In the initialization period, initialization discharge is generated in each discharge cell, and wall charges necessary for the subsequent address operation are formed in the discharge cell. In addition, priming particles (charged particles that assist the generation of discharge) necessary for the address operation are generated in the discharge cell. In the address period, an address discharge is generated in the discharge cells that should emit light. In the sustain period, sustain pulses are alternately applied to the scan electrodes and the sustain electrodes, and a sustain discharge is generated in the discharge cells that have generated the address discharge.
初期化期間における初期化動作には、「強制初期化動作」と「選択初期化動作」があり、発生する駆動電圧波形が互いに異なる。強制初期化動作では、直前のサブフィールドでの放電の有無にかかわらず放電セルに強制的に初期化放電を発生する。選択初期化動作では、直前のサブフィールドの書込み期間で書込み放電を発生した放電セルだけに選択的に初期化放電を発生する。
The initialization operation in the initialization period includes “forced initialization operation” and “selective initialization operation”, and generated drive voltage waveforms are different from each other. In the forced initializing operation, an initializing discharge is forcibly generated in the discharge cells regardless of the presence or absence of discharge in the immediately preceding subfield. In the selective initializing operation, initializing discharge is selectively generated only in the discharge cells that have generated address discharge in the address period of the immediately preceding subfield.
本実施の形態では、1フィールドに含まれる複数のサブフィールドのうち、最初のサブフィールド(例えば、サブフィールドSF1)を強制初期化動作を行うサブフィールド(強制初期化サブフィールド)とし、他のサブフィールド(例えば、サブフィールドSF2以降のサブフィールド)を選択初期化動作を行うサブフィールド(選択初期化サブフィールド)とする例を説明する。
In the present embodiment, among the plurality of subfields included in one field, the first subfield (for example, subfield SF1) is set as a subfield (forced initialization subfield) for performing a forced initialization operation, and other subfields are included. An example will be described in which a field (for example, a subfield after subfield SF2) is used as a subfield (selective initialization subfield) for performing a selective initialization operation.
また、画像表示サブフィールドにおいては、各サブフィールドに輝度重みをそれぞれ設定する。本実施の形態では、一例として、1フィールドに8つのサブフィールド(サブフィールドSF1~SF8)を備え、各サブフィールドにそれぞれ(1、34、21、13、8、5、3、2)の輝度重みを設定する例を挙げる。
Also, in the image display subfield, a luminance weight is set for each subfield. In the present embodiment, as an example, one field has eight subfields (subfields SF1 to SF8), and each subfield has a luminance of (1, 34, 21, 13, 8, 5, 3, 2). An example of setting a weight is given.
画像表示領域内におけるライトペンの位置は、x座標とy座標で表される。x座標検出サブフィールドSFx、y座標検出サブフィールドSFyは、画像表示領域内におけるライトペンの位置(位置座標)のx座標、y座標を検出するためのサブフィールドである。
The position of the light pen in the image display area is represented by the x coordinate and the y coordinate. The x-coordinate detection subfield SFx and the y-coordinate detection subfield SFy are subfields for detecting the x-coordinate and y-coordinate of the position (position coordinate) of the light pen in the image display area.
なお、ライトペンは、プラズマディスプレイシステムに備えられたものであり、使用者がパネル上に文字や図画を手書き入力するためのものである。ライトペンの詳細は後述する。
The light pen is provided in the plasma display system, and is used by a user to input characters and drawings on the panel by handwriting. Details of the light pen will be described later.
本実施の形態におけるプラズマディスプレイシステムでは、ライトペンとプラズマディスプレイ装置との間で無線通信を行う。ライトペンは、ライトペンの内部でライトペンの位置座標を算出し、算出した位置座標のデータをライトペンからプラズマディスプレイ装置へ無線通信によって送信する。
In the plasma display system in this embodiment, wireless communication is performed between the light pen and the plasma display device. The light pen calculates the position coordinates of the light pen inside the light pen, and transmits data of the calculated position coordinates from the light pen to the plasma display device by wireless communication.
ライトペンの内部でライトペンの位置座標を算出する際には、プラズマディスプレイ装置においてy座標検出サブフィールドSFyおよびx座標検出サブフィールドSFxが発生するタイミングを、ライトペンが正確に把握する必要がある。
When calculating the position coordinates of the light pen inside the light pen, it is necessary for the light pen to accurately grasp the timing at which the y coordinate detection subfield SFy and the x coordinate detection subfield SFx occur in the plasma display device. .
本実施の形態のタイミング検出サブフィールドSFoは、位置座標を検出するための基準となる信号(座標基準信号)をライトペン自らが高い精度で発生できるようにするためのものである。
The timing detection subfield SFo of the present embodiment is for enabling the light pen itself to generate a signal (coordinate reference signal) serving as a reference for detecting position coordinates with high accuracy.
なお、本実施の形態では、1フィールドにおいて、複数の画像表示サブフィールド(例えば、サブフィールドSF1~SF8)、タイミング検出サブフィールドSFo、y座標検出サブフィールドSFy、x座標検出サブフィールドSFxの順番で各サブフィールドが発生する例を説明するが、各サブフィールドの発生順序は何らこの順番に限定されるものではない。
In this embodiment, in one field, a plurality of image display subfields (for example, subfields SF1 to SF8), a timing detection subfield SFo, a y coordinate detection subfield SFy, and an x coordinate detection subfield SFx are arranged in this order. An example in which each subfield occurs will be described, but the generation order of each subfield is not limited to this order.
また、タイミング検出サブフィールドSFo、y座標検出サブフィールドSFyおよびx座標検出サブフィールドSFxは、必ずしも毎フィールドに設けなくともよい。例えば、映像信号やプラズマディスプレイ装置の使用状態等に応じて、複数フィールドに1回の割合でタイミング検出サブフィールドSFo、y座標検出サブフィールドSFyおよびx座標検出サブフィールドSFxを発生する構成としてもよい。
Also, the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx are not necessarily provided in each field. For example, the timing detection subfield SFo, the y-coordinate detection subfield SFy, and the x-coordinate detection subfield SFx may be generated at a rate of once per a plurality of fields in accordance with the video signal, the usage state of the plasma display device, and the like. .
図3は、本発明の実施の形態における画像表示サブフィールドのサブフィールドSF1~SF3においてパネル10の各電極に印加する駆動電圧波形の一例を概略的に示す図である。
FIG. 3 schematically shows an example of a drive voltage waveform applied to each electrode of panel 10 in subfields SF1 to SF3 of the image display subfield in the embodiment of the present invention.
図3には、維持電極SU1~SUn、書込み期間において最初に書込み動作を行う走査電極SC1、書込み期間において最後に書込み動作を行う走査電極SCn(例えば、走査電極SC1080)、データ電極D1~データ電極Dm(例えば、データ電極D5760)のそれぞれに印加する駆動電圧波形を示す。また、以下における走査電極SCi、維持電極SUi、データ電極Dkは、各電極の中から画像データ(サブフィールド毎の発光・非発光を示すデータ)にもとづき選択された電極を表す。
FIG. 3 shows sustain electrodes SU1 to SUn, scan electrode SC1 that performs the address operation first in the address period, scan electrode SCn that performs the address operation last in the address period (for example, scan electrode SC1080), and data electrode D1 to data electrode. The drive voltage waveform applied to each of Dm (for example, data electrode D5760) is shown. Scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected based on image data (data indicating light emission / non-light emission for each subfield) from among the electrodes.
なお、サブフィールドSF3以降の各サブフィールドは、維持パルスの発生数を除き、サブフィールドSF2とほぼ同様の駆動電圧波形を発生する。
It should be noted that each subfield after subfield SF3 generates a drive voltage waveform substantially similar to that of subfield SF2, except for the number of sustain pulses.
まず、強制初期化サブフィールドであるサブフィールドSF1について説明する。なお、ここでは、サブフィールドSF1の初期化期間Pia1を第1期間Pi1、第2期間Pi2、第3期間Pi3、第4期間Pi4の4つの期間に分け、それぞれの期間について説明する。
First, the subfield SF1, which is a forced initialization subfield, will be described. Here, the initialization period Pia1 of the subfield SF1 is divided into four periods of a first period Pi1, a second period Pi2, a third period Pi3, and a fourth period Pi4, and each period will be described.
強制初期化動作を行うサブフィールドSF1の初期化期間Pia1の第1期間Pi1では、維持電極SU1~SUnに電圧0(V)を印加し、データ電極D1~Dmは電圧0(V)を印加した後にハイインピーダンス状態にする。
In the first period Pi1 of the initialization period Pia1 of the subfield SF1 in which the forced initialization operation is performed, the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn, and the voltage 0 (V) is applied to the data electrodes D1 to Dm. A high impedance state is set later.
走査電極SC1~SCnには、電圧0(V)を印加した後に電圧Vi1を印加し、電圧Vi1から電圧Vi2まで緩やかに上昇する傾斜波形電圧(以下、「上り傾斜波形電圧」と呼称する)を印加する。
A scan waveform SC1 to SCn is applied with voltage Vi1 after voltage 0 (V) is applied, and a ramp waveform voltage (hereinafter referred to as “upward ramp waveform voltage”) that gradually rises from voltage Vi1 to voltage Vi2. Apply.
電圧Vi1は、維持電極SU1~SUnに対して放電開始電圧よりも低い電圧に設定し、電圧Vi2は、維持電極SU1~SUnに対して放電開始電圧を超える電圧に設定する。
The voltage Vi1 is set to a voltage lower than the discharge start voltage for the sustain electrodes SU1 to SUn, and the voltage Vi2 is set to a voltage exceeding the discharge start voltage for the sustain electrodes SU1 to SUn.
この上り傾斜波形電圧が上昇する間に、各放電セルの走査電極SC1~SCnと維持電極SU1~SUnとの間、および走査電極SC1~SCnとデータ電極D1~Dmとの間に、それぞれ微弱な初期化放電が持続して発生する。
While the rising ramp waveform voltage rises, it is weak between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, and between the scan electrodes SC1 to SCn and the data electrodes D1 to Dm, respectively. Initializing discharge is generated continuously.
そして、走査電極SC1~SCn上に負極性の壁電圧が蓄積され、データ電極D1~Dm上および維持電極SU1~SUn上には正極性の壁電圧が蓄積される。さらに、以降の放電の発生を補助するプライミング粒子が放電セル内に発生する。この電極上の壁電圧とは、電極を覆う誘電体層上、保護層上、蛍光体層上等に蓄積された壁電荷により生じる電圧を表す。
Then, negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Furthermore, priming particles that assist the generation of the subsequent discharge are generated in the discharge cell. The wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.
なお、データ電極D1~Dmは、電圧0(V)を印加した後にハイインピーダンス状態にしているので、走査電極SC1~SCnに印加する電圧が上昇するにつれて、データ電極D1~Dmの電圧も、電圧0(V)から徐々に正の方向へ上昇する。
Since the data electrodes D1 to Dm are in a high impedance state after the voltage 0 (V) is applied, as the voltage applied to the scan electrodes SC1 to SCn rises, the voltage of the data electrodes D1 to Dm also increases. It gradually rises from 0 (V) in the positive direction.
これにより、走査電極SC1~SCnと維持電極SU1~SUnとの間の放電が、走査電極SC1~SCnとデータ電極D1~Dmとの間の放電よりも先に発生する。その結果、初期化放電が安定に発生する。これは、次のような理由による。
Thus, discharge between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn occurs before discharge between scan electrodes SC1 to SCn and data electrodes D1 to Dm. As a result, the initialization discharge is stably generated. This is due to the following reason.
保護層16は、放電セルにおける放電開始電圧を下げるために、2次電子放出係数が大きく耐久性に優れた酸化マグネシウム(MgO)を主成分とする材料で形成されている。一方、蛍光体層25は、保護層16と比較して、2次電子放出係数が小さい。
The protective layer 16 is formed of a material mainly composed of magnesium oxide (MgO) having a large secondary electron emission coefficient and excellent durability in order to lower the discharge start voltage in the discharge cell. On the other hand, the phosphor layer 25 has a smaller secondary electron emission coefficient than the protective layer 16.
したがって、放電が相対的に発生しやすい走査電極SC1~SCnと維持電極SU1~SUnとの間の放電を先に発生させ、その放電で発生したプライミング粒子を用いて走査電極SC1~SCnとデータ電極D1~Dmとの間の放電を発生させることで、安定に初期化放電を発生させることができる。
Therefore, discharge between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, which are relatively likely to generate discharge, is first generated, and scan electrodes SC1 to SCn and data electrodes are generated using priming particles generated by the discharge. By generating the discharge between D1 and Dm, the initialization discharge can be generated stably.
走査電極SC1~SCnに印加する電圧が電圧Vi2に到達したら、走査電極SC1~SCnの電圧を、電圧Vi2よりも低い電圧Vi3まで一旦下げ、その後、電圧0(V)に下げる。電圧Vi3は、電圧Vi2よりも低い電圧で、かつ維持電極SU1~SUnに対して放電開始電圧未満の電圧に設定する。本実施の形態では電圧Vi3を約200(V)とする例を示すが、電圧Vi3は放電セルに放電が発生しない電圧であればよい。また、電圧Vi2から電圧0(V)まで急峻に電圧を下げてもよい。
When the voltage applied to scan electrodes SC1 to SCn reaches voltage Vi2, the voltage of scan electrodes SC1 to SCn is once lowered to voltage Vi3 lower than voltage Vi2, and then lowered to voltage 0 (V). The voltage Vi3 is set to a voltage lower than the voltage Vi2 and lower than the discharge start voltage with respect to the sustain electrodes SU1 to SUn. Although an example in which the voltage Vi3 is about 200 (V) is shown in this embodiment, the voltage Vi3 may be a voltage that does not cause discharge in the discharge cells. Further, the voltage may be sharply decreased from the voltage Vi2 to the voltage 0 (V).
サブフィールドSF1の初期化期間Pia1の第2期間Pi2では、データ電極D1~Dmには電圧0(V)を印加し、維持電極SU1~SUnには正の電圧Veを印加する。
In the second period Pi2 of the initialization period Pia1 of the subfield SF1, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn.
なお、図3に示すように、維持電極SU1~SUnは電圧Veを印加した後にハイインピーダンス状態にしてもいが、例えば維持電極SU1~SUnに電圧Veを印加したままにしてもよい。
As shown in FIG. 3, the sustain electrodes SU1 to SUn may be in a high impedance state after the voltage Ve is applied. For example, the voltage Ve may be kept applied to the sustain electrodes SU1 to SUn.
走査電極SC1~SCnには、放電開始電圧未満となる電圧(例えば、電圧0(V))から負の電圧Vi4まで緩やかに下降する傾斜波形電圧(以下、単に「下り傾斜波形電圧」とも記す)を印加する。電圧Vi4は、維持電極SU1~SUnに対して放電開始電圧を超える電圧に設定する。
The scan electrodes SC1 to SCn have a ramp waveform voltage that gradually falls from a voltage that is less than the discharge start voltage (eg, voltage 0 (V)) to a negative voltage Vi4 (hereinafter also simply referred to as “down ramp waveform voltage”). Is applied. Voltage Vi4 is set to a voltage exceeding the discharge start voltage with respect to sustain electrodes SU1 to SUn.
この下り傾斜波形電圧を走査電極SC1~SCnに印加する間に、各放電セルの走査電極SC1~SCnと維持電極SU1~SUnとの間、および走査電極SC1~SCnとデータ電極D1~Dmとの間に、それぞれ微弱な初期化放電が持続して発生する。これにより、走査電極SC1~SCn上の負極性の壁電圧および維持電極SU1~SUn上の正極性の壁電圧が弱められ、データ電極D1~Dm上の正極性の壁電圧は、続く書込み期間Pw1での書込み動作に適した電圧に調整される。また、プライミング粒子が放電セル内に発生する。
While this downward ramp waveform voltage is applied to scan electrodes SC1 to SCn, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn of each discharge cell, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm. In the meantime, weak initializing discharges are continuously generated. As a result, the negative wall voltage on scan electrodes SC1 to SCn and the positive wall voltage on sustain electrodes SU1 to SUn are weakened, and the positive wall voltage on data electrodes D1 to Dm remains in the subsequent writing period Pw1. The voltage is adjusted to a voltage suitable for the write operation. Further, priming particles are generated in the discharge cell.
下り傾斜波形電圧が電圧Vi4に到達したら、走査電極SC1~SCnに印加する電圧を電圧0(V)にする。
When the downward ramp waveform voltage reaches the voltage Vi4, the voltage applied to the scan electrodes SC1 to SCn is set to voltage 0 (V).
サブフィールドSF1の初期化期間Pia1の第3期間Pi3では、維持電極SU1~SUnおよびデータ電極D1~Dmに電圧0(V)を印加したまま、走査電極SC1~SCnに電圧0(V)から電圧Vrまで緩やかに上昇する上り傾斜波形電圧を印加する。
In the third period Pi3 of the initialization period Pia1 of the subfield SF1, the voltage 0 (V) is applied to the scan electrodes SC1 to SCn while the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn and the data electrodes D1 to Dm. An upward ramp waveform voltage that gradually rises to Vr is applied.
第2期間Pi2において壁電圧が適切に調整されず、異常な壁電荷が残留している放電セルでは、この上り傾斜波形電圧を走査電極SC1~SCnに印加する間に放電が発生し、その異常な壁電荷が消去される。
In the discharge cell in which the wall voltage is not properly adjusted in the second period Pi2 and abnormal wall charges remain, a discharge is generated while the upward ramp waveform voltage is applied to the scan electrodes SC1 to SCn. Wall charges are erased.
一方、第2期間Pi2において壁電圧が適切に調整された放電セルでは、放電は発生しない。
On the other hand, no discharge occurs in the discharge cell in which the wall voltage is appropriately adjusted in the second period Pi2.
上り傾斜波形電圧が電圧Vrに到達したら、走査電極SC1~SCnに印加する電圧を電圧0(V)まで下げる。
When the rising ramp waveform voltage reaches the voltage Vr, the voltage applied to the scan electrodes SC1 to SCn is lowered to the voltage 0 (V).
サブフィールドSF1の初期化期間Pia1の第4期間Pi4では、第2期間Pi2と同様に、データ電極D1~Dmに電圧0(V)を印加し、維持電極SU1~SUnに正の電圧Veを印加する。
In the fourth period Pi4 of the initialization period Pia1 of the subfield SF1, as in the second period Pi2, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn. To do.
図3に示すように、維持電極SU1~SUnは電圧Veを印加した後にハイインピーダンス状態にしてもいが、例えば維持電極SU1~SUnに電圧Veを印加したままにしてもよい。
As shown in FIG. 3, the sustain electrodes SU1 to SUn may be in a high impedance state after the voltage Ve is applied. For example, the voltage Ve may be applied to the sustain electrodes SU1 to SUn.
走査電極SC1~SCnには、電圧0(V)から負の電圧Vi4まで緩やかに下降する下り傾斜波形電圧を印加する。
The downward ramp waveform voltage that gently falls from the voltage 0 (V) to the negative voltage Vi4 is applied to the scan electrodes SC1 to SCn.
第2期間Pi2において壁電圧が適切に調整されずに異常な壁電荷が残留し、第3期間Pi3において放電が発生した放電セルでは、この下り傾斜波形電圧を走査電極SC1~SCnに印加する間に放電が発生する。これにより、異常な壁電荷が消去され、この放電セル内の壁電圧は続く書込み期間Pw1での書込み動作に適した値に調整される。
In the discharge cell where the wall voltage is not properly adjusted in the second period Pi2 and abnormal wall charges remain and discharge occurs in the third period Pi3, the downward ramp waveform voltage is applied to the scan electrodes SC1 to SCn. Discharge occurs. As a result, abnormal wall charges are erased, and the wall voltage in the discharge cell is adjusted to a value suitable for the address operation in the subsequent address period Pw1.
一方、第2期間Pi2において壁電圧が適切に調整され、第3期間Pi3において放電が発生しなかった放電セルでは、放電は発生しない。
On the other hand, no discharge occurs in the discharge cells in which the wall voltage is appropriately adjusted in the second period Pi2 and no discharge occurs in the third period Pi3.
下り傾斜波形電圧が電圧Vi4に到達したら、走査電極SC1~SCnに印加する電圧を電圧Vcにする。
When the descending ramp waveform voltage reaches the voltage Vi4, the voltage applied to the scan electrodes SC1 to SCn is set to the voltage Vc.
初期化期間Pia1に発生する上述の駆動電圧波形が、強制初期化波形(第1の強制初期化波形)である。この強制初期化動作により、初期化放電が発生した各放電セルの壁電圧をほぼ均一な状態にすることができる。
The above-mentioned drive voltage waveform generated in the initialization period Pia1 is a forced initialization waveform (first forced initialization waveform). By this forced initializing operation, the wall voltage of each discharge cell in which the initializing discharge has occurred can be made substantially uniform.
なお、本実施の形態では、強制初期化動作を、パネルの画像表示領域内にある全ての放電セルに強制的に初期化放電を発生する初期化動作として説明するが、本発明は何らこの構成に限定されない。本実施の形態では、例えば、パネルの画像表示領域内にある一部の放電セルにのみ強制初期化波形を印加する動作も強制初期化動作とし、その強制初期化動作を行うサブフィールドを強制初期化サブフィールドとする。例えば、奇数フィールドのサブフィールドSF1では奇数行の走査電極SC(2N-1)(Nは1以上の整数)にのみ強制初期化波形を印加し、他の走査電極SC(2N)には後述の選択初期化波形を印加し、偶数フィールドのサブフィールドSF1では偶数行の走査電極SC(2N)にのみ強制初期化波形を印加し、他の走査電極SC(2N-1)には選択初期化波形を印加する、というように、フィールド毎に強制初期化波形を印加する走査電極SC1~SCnを変更してもよい。これは、以下の説明における強制初期化動作を行う全てのサブフィールドについても同様である。
In the present embodiment, the forced initializing operation is described as an initializing operation for forcibly generating an initializing discharge in all the discharge cells in the image display area of the panel. It is not limited to. In the present embodiment, for example, an operation for applying a forced initialization waveform only to a part of the discharge cells in the image display area of the panel is also a forced initialization operation, and a subfield for performing the forced initialization operation is forcibly initialized. Subfield. For example, in the odd-field subfield SF1, the forced initializing waveform is applied only to the odd-numbered scan electrodes SC (2N-1) (N is an integer of 1 or more), and the other scan electrodes SC (2N) are described later. A selective initialization waveform is applied. In the even-field subfield SF1, a forced initialization waveform is applied only to the even-numbered scan electrode SC (2N), and a selective initialization waveform is applied to the other scan electrode SC (2N-1). For example, the scan electrodes SC1 to SCn to which the forced initialization waveform is applied may be changed for each field. The same applies to all subfields that perform the forced initialization operation in the following description.
サブフィールドSF1の書込み期間Pw1では、データ電極D1~Dmには電圧0(V)を印加し、維持電極SU1~SUnには電圧Veを印加し、走査電極SC1~SCnには電圧Vcを印加する。
In address period Pw1 of subfield SF1, voltage 0 (V) is applied to data electrodes D1 to Dm, voltage Ve is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn. .
次に、1行目の走査電極SC1に負の電圧Vaの負極性の走査パルスを印加する。そして、データ電極D1~Dmのうちの1行目において発光するべき放電セルのデータ電極Dkに正の電圧Vdの正極性の書込みパルスを印加する。
Next, a negative scan pulse having a negative voltage Va is applied to the scan electrode SC1 in the first row. Then, a positive address pulse of a positive voltage Vd is applied to the data electrode Dk of the discharge cell that should emit light in the first row of the data electrodes D1 to Dm.
なお、本実施の形態では、初期化期間Pia1が終了してから書込み期間Pw1の最初の書込みパルスを発生するまでの時間(走査電極SC1に電圧Vcを印加してから最初の走査パルスを印加するまでの期間)をTw0とし、走査電極SC1~SCnのそれぞれに走査パルスを印加する時間(走査パルスの幅のことであり、データ電極Dkに印加する書込みパルスの幅もこれにほぼ等しい)をTw1とする。本実施の形態では、期間Tw0は、例えば約50μsecであり、Tw1は、例えば約1μsecである。
In this embodiment, the time from the end of the initialization period Pia1 to the generation of the first address pulse in the address period Pw1 (the first scan pulse is applied after the voltage Vc is applied to the scan electrode SC1). Tw0, and the time for applying the scan pulse to each of the scan electrodes SC1 to SCn (the width of the scan pulse, and the width of the write pulse applied to the data electrode Dk is substantially equal to this) Tw1 And In the present embodiment, the period Tw0 is about 50 μsec, for example, and Tw1 is about 1 μsec, for example.
書込みパルスの電圧Vdを印加したデータ電極Dkと走査パルスの電圧Vaを印加した走査電極SC1との交差部にある放電セルでは、データ電極Dkと走査電極SC1との間に放電が発生し、維持電極SU1と走査電極SC1との間にも放電が発生する。こうして、走査パルスの電圧Vaと書込みパルスの電圧Vdとが同時に印加された放電セル(発光するべき放電セル)に書込み放電が発生する。
In the discharge cell at the intersection of the data electrode Dk to which the address pulse voltage Vd is applied and the scan electrode SC1 to which the scan pulse voltage Va is applied, a discharge occurs between the data electrode Dk and the scan electrode SC1, and is maintained. A discharge is also generated between the electrode SU1 and the scan electrode SC1. Thus, address discharge is generated in the discharge cells (discharge cells to emit light) to which the scan pulse voltage Va and the address pulse voltage Vd are simultaneously applied.
書込み放電が発生した放電セルでは、走査電極SC1上に正極性の壁電圧が蓄積され、維持電極SU1上に負極性の壁電圧が蓄積され、データ電極Dk上にも負極性の壁電圧が蓄積される。
In the discharge cell in which the address discharge has occurred, positive wall voltage is accumulated on scan electrode SC1, negative wall voltage is accumulated on sustain electrode SU1, and negative wall voltage is also accumulated on data electrode Dk. Is done.
なお、書込みパルスを印加しなかった放電セルでは、データ電極Dh(データ電極Dhはデータ電極D1~Dmのうちデータ電極Dkを除いたもの)と走査電極SC1との交差部の電圧は放電開始電圧を超えないので、書込み放電は発生しない。
In a discharge cell to which no address pulse is applied, the voltage at the intersection of data electrode Dh (data electrode Dh is data electrode D1-Dm excluding data electrode Dk) and scan electrode SC1 is the discharge start voltage. Therefore, the address discharge does not occur.
なお、走査パルスおよび書込みパルスの各電圧は、書込み放電が維持放電と比較して弱い放電となるように調整される。そのため、書込み放電による発光は維持放電による発光と比較して輝度が低い。これは、書込み放電による発光がパネル10に画像を表示する際の妨げとならないようにするためである。
The voltages of the scan pulse and the address pulse are adjusted so that the address discharge is weaker than the sustain discharge. Therefore, the light emission due to the address discharge has lower luminance than the light emission due to the sustain discharge. This is to prevent light emission due to the address discharge from hindering display of an image on the panel 10.
次に、2行目の走査電極SC2に電圧Vaの走査パルスを印加するとともに、2行目に発光するべき放電セルに対応するデータ電極Dkに電圧Vdの書込みパルスを印加する。これにより、走査パルスと書込みパルスとが同時に印加された2行目の放電セルでは書込み放電が発生する。書込みパルスが印加されなかった放電セルでは書込み放電は発生しない。こうして、2行目の放電セルにおける書込み動作を行う。
Next, a scan pulse of voltage Va is applied to scan electrode SC2 in the second row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light in the second row. As a result, address discharge occurs in the discharge cells in the second row to which the scan pulse and address pulse are simultaneously applied. Address discharge does not occur in the discharge cells to which no address pulse is applied. Thus, the address operation in the discharge cells in the second row is performed.
同様の書込み動作を、走査電極SC3、走査電極SC4、・・・、走査電極SCnという順番で、n行目の放電セルに至るまで順次行い、サブフィールドSF1の書込み期間Pw1が終了する。このように、書込み期間Pw1では、発光するべき放電セルに選択的に書込み放電を発生し、その放電セルに維持放電のための壁電荷を形成する。
The same addressing operation is sequentially performed in the order of scan electrode SC3, scan electrode SC4,..., Scan electrode SCn up to the discharge cell in the n-th row, and the address period Pw1 of subfield SF1 ends. As described above, in the address period Pw1, address discharge is selectively generated in the discharge cells to emit light, and wall charges for sustain discharge are formed in the discharge cells.
なお、本発明は、走査電極SC1~SCnに走査パルスを印加する順番が何ら上述した順番に限定されるものではない。走査電極SC1~SCnに走査パルスを印加する順番は、画像表示装置における仕様等に応じて任意に設定すればよい。
In the present invention, the order in which the scan pulses are applied to the scan electrodes SC1 to SCn is not limited to the order described above. The order in which the scan pulses are applied to the scan electrodes SC1 to SCn may be arbitrarily set according to the specifications of the image display device.
サブフィールドSF1の維持期間Ps1では、データ電極D1~Dmに電圧0(V)を印加する。そして、走査電極SC1~SCnに正の電圧Vsの維持パルスを印加するとともに、維持電極SU1~SUnに電圧0(V)を印加する。
In the sustain period Ps1 of the subfield SF1, voltage 0 (V) is applied to the data electrodes D1 to Dm. Then, a sustain pulse of positive voltage Vs is applied to scan electrodes SC1 to SCn, and voltage 0 (V) is applied to sustain electrodes SU1 to SUn.
この維持パルスの印加により、直前の書込み期間Pw1に書込み放電を発生した放電セルでは、走査電極SCiと維持電極SUiとの間に維持放電が発生する。そして、維持放電によって発生した紫外線により、この放電セルの蛍光体層25が発光する。
By applying the sustain pulse, a sustain discharge is generated between the scan electrode SCi and the sustain electrode SUi in the discharge cell that has generated the address discharge in the immediately preceding address period Pw1. The phosphor layer 25 of the discharge cell emits light due to the ultraviolet rays generated by the sustain discharge.
また、この維持放電により、走査電極SCi上に負極性の壁電圧が蓄積され、維持電極SUi上に正極性の壁電圧が蓄積される。さらに、データ電極Dk上にも正極性の壁電圧が蓄積される。ただし、直前の書込み期間Pw1において書込み放電が発生しなかった放電セルでは維持放電は発生せず、初期化期間Pia1の終了時における壁電圧が保たれる。
Also, due to the sustain discharge, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is also accumulated on the data electrode Dk. However, the sustain discharge does not occur in the discharge cells in which the address discharge has not occurred in the immediately preceding address period Pw1, and the wall voltage at the end of the initialization period Pia1 is maintained.
続いて、走査電極SC1~SCnに電圧0(V)を印加し、維持電極SU1~SUnに電圧Vsの維持パルスを印加する。直前に維持放電を発生した放電セルでは再び維持放電が発生し、維持電極SUi上に負極性の壁電圧が蓄積され、走査電極SCi上に正極性の壁電圧が蓄積される。
Subsequently, voltage 0 (V) is applied to scan electrodes SC1 to SCn, and a sustain pulse of voltage Vs is applied to sustain electrodes SU1 to SUn. In the discharge cell that has generated a sustain discharge immediately before, a sustain discharge occurs again, and a negative wall voltage is accumulated on the sustain electrode SUi, and a positive wall voltage is accumulated on the scan electrode SCi.
以降同様に、走査電極SC1~SCnと維持電極SU1~SUnとに、輝度重みに所定の輝度倍数を乗じた数の維持パルスを交互に印加する。こうして、直前の書込み期間Pw1において書込み放電を発生した放電セルは、輝度重みに応じた回数の維持放電が発生し、輝度重みに応じた輝度で発光する。
Thereafter, similarly, the number of sustain pulses obtained by multiplying the brightness weight by a predetermined brightness multiple is alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. In this way, the discharge cells that have generated the address discharge in the immediately preceding address period Pw1 generate the sustain discharge the number of times corresponding to the luminance weight, and emit light with the luminance corresponding to the luminance weight.
そして、維持パルスの発生後(維持期間Ps1において維持動作が終了した後)には、維持電極SU1~SUnおよびデータ電極D1~Dmに電圧0(V)を印加したまま、走査電極SC1~SCnに電圧0(V)から第1の電圧である正の電圧Vrまで緩やかに上昇する上り傾斜波形電圧を印加する。以下、この上り傾斜波形電圧を「第1のランプ波形電圧」と記す。
After the sustain pulse is generated (after the sustain operation is completed in sustain period Ps1), voltage 0 (V) is applied to sustain electrodes SU1 to SUn and data electrodes D1 to Dm, and applied to scan electrodes SC1 to SCn. An upward ramp waveform voltage that gradually rises from the voltage 0 (V) to the positive voltage Vr that is the first voltage is applied. Hereinafter, this upward ramp waveform voltage is referred to as a “first ramp waveform voltage”.
維持放電を発生した放電セルでは、維持電極SUi上に負極性の壁電圧が蓄積され、走査電極SCi上に正極性の壁電圧が蓄積されているので、それらの放電セルの放電開始電圧を超える電圧に電圧Vrを設定する。これにより、走査電極SC1~SCnにこの第1のランプ波形電圧を印加する間に、維持放電を発生した放電セルの維持電極SUiと走査電極SCiとの間に、微弱な放電(消去放電)が持続して発生する。
In the discharge cells that have generated the sustain discharge, the negative wall voltage is accumulated on the sustain electrode SUi and the positive wall voltage is accumulated on the scan electrode SCi, so that the discharge start voltage of those discharge cells is exceeded. The voltage Vr is set as the voltage. As a result, a weak discharge (erase discharge) is generated between sustain electrode SUi and scan electrode SCi of the discharge cell in which the sustain discharge is generated while applying the first ramp waveform voltage to scan electrodes SC1 to SCn. It occurs continuously.
これにより、データ電極Dk上の正極性の壁電圧を残したまま、走査電極SCi上の壁電圧および維持電極SUi上の壁電圧が弱められ、放電セル内の不要な壁電荷が消去される。
Thereby, the wall voltage on the scan electrode SCi and the wall voltage on the sustain electrode SUi are weakened while leaving the positive wall voltage on the data electrode Dk, and unnecessary wall charges in the discharge cell are erased.
なお、第1の電圧である電圧Vrは電圧Vsに近似した電圧値であることが望ましく、本実施の形態では、電圧Vrを電圧Vsに等しい電圧値に設定している。
Note that the voltage Vr as the first voltage is preferably a voltage value approximate to the voltage Vs, and in this embodiment, the voltage Vr is set to a voltage value equal to the voltage Vs.
第1のランプ波形電圧が電圧Vrに到達したら、走査電極SC1~SCnに印加する電圧を電圧0(V)まで下げる。こうして、維持期間Ps1の最後に行う消去動作が終了し、サブフィールドSF1が終了する。
When the first ramp waveform voltage reaches the voltage Vr, the voltage applied to the scan electrodes SC1 to SCn is lowered to the voltage 0 (V). Thus, the erase operation performed at the end of sustain period Ps1 ends, and subfield SF1 ends.
次に、選択初期化サブフィールドについてサブフィールドSF2を例に挙げて説明する。なお、本実施の形態では、サブフィールドSF3以降の初期化期間Pib3~Pib8においても、サブフィールドSF2の初期化期間Pib2と同様の駆動電圧波形を各電極に印加して、選択初期化動作を行う。
Next, the selective initialization subfield will be described by taking the subfield SF2 as an example. In the present embodiment, in the initialization periods Pib3 to Pib8 after the subfield SF3, the same drive voltage waveform as that in the initialization period Pib2 of the subfield SF2 is applied to each electrode to perform the selective initialization operation. .
サブフィールドSF2の初期化期間Pib2では、データ電極D1~Dmには電圧0(V)を印加し、維持電極SU1~SUnには正の電圧Veを印加する。
In the initialization period Pib2 of the subfield SF2, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn.
走査電極SC1~SCnには、放電開始電圧未満となる電圧(例えば、電圧0(V))から負の電圧Vi4まで下降する下り傾斜波形電圧を印加する。この下り傾斜波形電圧は、初期化期間Pia1の第2期間Pi2および第4期間Pi4で発生した下り傾斜波形電圧とほぼ同じ波形形状を有する。
A downward ramp waveform voltage that drops from a voltage that is lower than the discharge start voltage (for example, voltage 0 (V)) to a negative voltage Vi4 is applied to scan electrodes SC1 to SCn. The downward ramp waveform voltage has substantially the same waveform shape as the downward ramp waveform voltage generated in the second period Pi2 and the fourth period Pi4 of the initialization period Pia1.
この下り傾斜波形電圧を走査電極SC1~SCnに印加する間に、直前のサブフィールドSF1の維持期間Ps1で維持放電を発生した放電セルに微弱な初期化放電が発生する。
While applying this downward ramp waveform voltage to scan electrodes SC1 to SCn, a weak initializing discharge is generated in the discharge cell that has generated a sustain discharge in sustain period Ps1 of immediately preceding subfield SF1.
この初期化放電により、走査電極SCi上の壁電圧および維持電極SUi上の壁電圧が弱められる。また、直前の維持放電によってデータ電極Dk上に蓄積された正極性の壁電圧は、過剰な部分が放電され、書込み動作に適した壁電圧に調整される。
This initialization discharge weakens the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. In addition, the positive wall voltage accumulated on the data electrode Dk by the last sustain discharge is adjusted to a wall voltage suitable for the address operation by discharging an excessive portion.
一方、直前のサブフィールドSF1の維持期間Ps1に維持放電を発生しなかった放電セルでは、初期化放電は発生せず、サブフィールドSF1の初期化期間Pia1終了時における壁電圧が保たれる。
On the other hand, in the discharge cells that did not generate the sustain discharge in the sustain period Ps1 of the immediately preceding subfield SF1, the initialization discharge does not occur, and the wall voltage at the end of the initialization period Pia1 of the subfield SF1 is maintained.
下り傾斜波形電圧が電圧Vi4に到達したら、走査電極SC1~SCnに印加する電圧を電圧Vcにする。
When the descending ramp waveform voltage reaches the voltage Vi4, the voltage applied to the scan electrodes SC1 to SCn is set to the voltage Vc.
このように、サブフィールドSF2の初期化期間Pib2では、直前のサブフィールドSF1の書込み期間Pw1で書込み動作を行った放電セル(すなわち、維持期間Ps1で維持動作を行った放電セル)に初期化放電を発生する選択初期化動作を行う。これにより、その放電セル内の壁電圧を、続く書込み期間Pw2における書込み動作に適した壁電圧に調整する。さらに、書込み放電の発生を補助するプライミング粒子を放電セル内に発生する。
As described above, in the initialization period Pib2 of the subfield SF2, the initializing discharge is performed on the discharge cell that has performed the address operation in the address period Pw1 of the immediately preceding subfield SF1 (that is, the discharge cell that has performed the sustain operation in the sustain period Ps1). Select initialization operation that generates Thereby, the wall voltage in the discharge cell is adjusted to a wall voltage suitable for the address operation in the subsequent address period Pw2. Further, priming particles that assist the generation of the address discharge are generated in the discharge cell.
この初期化期間Pib2に発生する上述の駆動電圧波形が、選択初期化波形である。
The above-mentioned drive voltage waveform generated in the initialization period Pib2 is a selective initialization waveform.
なお、電圧Vi4および電圧Veは、パネル10の特性やプラズマディスプレイ装置100の仕様等に応じて、上述の動作を満たす電圧値に設定する。
The voltage Vi4 and the voltage Ve are set to voltage values that satisfy the above-described operation according to the characteristics of the panel 10, the specifications of the plasma display device 100, and the like.
サブフィールドSF2の書込み期間Pw2および維持期間Ps2は、維持パルスの発生数を除き、サブフィールドSF1の書込み期間Pw1および維持期間Ps1と同様の駆動電圧波形を各電極に印加するので説明を省略する。
In the address period Pw2 and the sustain period Ps2 in the subfield SF2, the drive voltage waveforms similar to those in the address period Pw1 and the sustain period Ps1 in the subfield SF1 are applied to the respective electrodes, except for the number of sustain pulses generated, and thus the description thereof is omitted.
サブフィールドSF3以降の各サブフィールドでは、維持パルスの発生数を除き、サブフィールドSF2と同様の駆動電圧波形を各電極に印加するので説明を省略する。
In each subfield after subfield SF3, the drive voltage waveform similar to that in subfield SF2 is applied to each electrode except for the number of sustain pulses, and the description thereof is omitted.
なお、本実施の形態では、強制初期化動作を行うサブフィールドをサブフィールドSF1とする例を説明したが、本発明は何らこの構成に限定されない。強制初期化動作を行うサブフィールドはサブフィールドSF2以降のサブフィールドであってもよい。
In the present embodiment, an example has been described in which the subfield for performing the forced initialization operation is the subfield SF1, but the present invention is not limited to this configuration. The subfield in which the forced initialization operation is performed may be a subfield after subfield SF2.
なお、本実施の形態では、強制初期化動作を1フィールドに1回行う例を説明したが、本発明は何らこの構成に限定されない。強制初期化動作を行う回数は複数フィールドに1回であってもよい。
In the present embodiment, the example in which the forced initialization operation is performed once per field has been described, but the present invention is not limited to this configuration. The number of times of performing the forced initialization operation may be once in a plurality of fields.
次に、タイミング検出サブフィールドSFo、y座標検出サブフィールドSFyおよびx座標検出サブフィールドSFxについて説明する。なお、座標検出サブフィールドは、タイミング検出サブフィールドSFo、y座標検出サブフィールドSFyおよびx座標検出サブフィールドSFxの総称である。
Next, the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx will be described. The coordinate detection subfield is a generic name for the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx.
図4は、本発明の実施の形態におけるタイミング検出サブフィールドSFo、y座標検出サブフィールドSFyおよびx座標検出サブフィールドSFxにおいてパネル10の各電極に印加する駆動電圧波形の一例を概略的に示す図である。
FIG. 4 schematically shows an example of a drive voltage waveform applied to each electrode of panel 10 in timing detection subfield SFo, y coordinate detection subfield SFy, and x coordinate detection subfield SFx in the embodiment of the present invention. It is.
図4には、タイミング検出サブフィールドSFo、y座標検出サブフィールドSFyおよびx座標検出サブフィールドSFxにおいて、維持電極SU1~SUn、走査電極SC1~SCn、データ電極D1~Dmのそれぞれに印加する駆動電圧波形を示す。また、図4には、タイミング検出サブフィールドSFoの直前のサブフィールドSF8の維持期間Ps8の一部、およびサブフィールドSF1の一部もあわせて示す。
FIG. 4 shows drive voltages applied to sustain electrodes SU1 to SUn, scan electrodes SC1 to SCn, and data electrodes D1 to Dm in timing detection subfield SFo, y coordinate detection subfield SFy, and x coordinate detection subfield SFx. Waveform is shown. FIG. 4 also shows a part of the sustain period Ps8 of the subfield SF8 immediately before the timing detection subfield SFo and a part of the subfield SF1.
タイミング検出サブフィールドSFoは、初期化期間Pico、書込み期間Pwo、およびタイミング検出期間Poを有する。
The timing detection subfield SFo has an initialization period Pico, an address period Pwo, and a timing detection period Po.
初期化期間Picoでは強制初期化動作を行う。なお、初期化期間Picoでは、画像表示サブフィールドのサブフィールドSF1の初期化期間Pia1とは異なる駆動電圧波形を各電極に印加する。ここでは、初期化期間Picoを第6期間Pi6、第7期間Pi7の2つの期間に分け、それぞれの期間について説明する。
In the initialization period Pico, a forced initialization operation is performed. In the initialization period Pico, a driving voltage waveform different from that in the initialization period Pia1 of the subfield SF1 of the image display subfield is applied to each electrode. Here, the initialization period Pico is divided into two periods of a sixth period Pi6 and a seventh period Pi7, and each period will be described.
初期化期間Picoの第6期間Pi6では、初期化期間Pia1の第1期間Pi1と同様の駆動電圧波形を各電極に印加する。
In the sixth period Pi6 of the initialization period Pico, the same drive voltage waveform as that in the first period Pi1 of the initialization period Pia1 is applied to each electrode.
すなわち、維持電極SU1~SUnに電圧0(V)を印加し、データ電極D1~Dmは電圧0(V)を印加した後にハイインピーダンス状態にする。走査電極SC1~SCnには、電圧0(V)を印加した後に電圧Vi1を印加し、電圧Vi1から電圧Vi2まで緩やかに上昇する上り傾斜波形電圧を印加する。電圧Vi1は、維持電極SU1~SUnに対して放電開始電圧よりも低い電圧に設定する。電圧Vi2は、維持電極SU1~SUnに対して放電開始電圧を超える電圧に設定する。
That is, the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn, and the data electrodes D1 to Dm are set to the high impedance state after the voltage 0 (V) is applied. A voltage Vi1 is applied to scan electrodes SC1 to SCn after voltage 0 (V) is applied, and an upward ramp waveform voltage that gradually rises from voltage Vi1 to voltage Vi2 is applied. Voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to sustain electrodes SU1 to SUn. Voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrodes SU1 to SUn.
この上り傾斜波形電圧は、初期化期間Pia1の第1期間Pi1で発生した上り傾斜波形電圧とほぼ同じ波形形状を有する。
The upslope waveform voltage has substantially the same waveform shape as the upslope waveform voltage generated in the first period Pi1 of the initialization period Pia1.
この上り傾斜波形電圧が上昇する間に、各放電セルの走査電極SC1~SCnと維持電極SU1~SUnとの間、および走査電極SC1~SCnとデータ電極D1~Dmとの間に、それぞれ微弱な初期化放電が持続して発生する。
While the rising ramp waveform voltage rises, it is weak between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, and between the scan electrodes SC1 to SCn and the data electrodes D1 to Dm, respectively. Initializing discharge is generated continuously.
このとき、データ電極D1~Dmはハイインピーダンス状態なので、サブフィールドSF1の初期化期間Pia1と同様に、走査電極SC1~SCnと維持電極SU1~SUnとの間の放電が、走査電極SC1~SCnとデータ電極D1~Dmとの間の放電よりも先に発生する。そのため、この初期化放電は安定に発生する。
At this time, since the data electrodes D1 to Dm are in a high impedance state, the discharge between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn is caused to occur between the scan electrodes SC1 to SCn as in the initialization period Pia1 of the subfield SF1. It occurs before the discharge between the data electrodes D1 to Dm. Therefore, this initialization discharge is generated stably.
そして、走査電極SC1~SCn上に負極性の壁電圧が蓄積され、データ電極D1~Dm上および維持電極SU1~SUn上には正極性の壁電圧が蓄積される。さらに、後続の書込み放電の発生を補助するプライミング粒子が放電セル内に発生する。
Then, negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Furthermore, priming particles that assist the generation of the subsequent address discharge are generated in the discharge cell.
走査電極SC1~SCnに印加する電圧が電圧Vi2に到達したら、走査電極SC1~SCnの電圧を、電圧Vi2よりも低い電圧Vi3まで一旦下げ、その後、電圧0(V)に下げる。ただし、本発明は何らこの構成に限定されるものではなく、例えば、電圧Vi2から電圧0(V)まで急峻に電圧を下げてもよい。
When the voltage applied to scan electrodes SC1 to SCn reaches voltage Vi2, the voltage of scan electrodes SC1 to SCn is once lowered to voltage Vi3 lower than voltage Vi2, and then lowered to voltage 0 (V). However, the present invention is not limited to this configuration. For example, the voltage may be sharply decreased from voltage Vi2 to voltage 0 (V).
初期化期間Picoの第7期間Pi7では、サブフィールドSF2の初期化期間Pib2と同様の駆動電圧波形を各電極に印加する。
In the seventh period Pi7 of the initialization period Pico, the same drive voltage waveform as that in the initialization period Pib2 of the subfield SF2 is applied to each electrode.
すなわち、データ電極D1~Dmには電圧0(V)を印加し、維持電極SU1~SUnには正の電圧Veを印加する。走査電極SC1~SCnには、放電開始電圧未満となる電圧(例えば、電圧0(V))から負の電圧Vi4まで下降する下り傾斜波形電圧を印加する。この下り傾斜波形電圧は、初期化期間Pib2で発生した下り傾斜波形電圧とほぼ同じ波形形状を有する。
That is, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn. A downward ramp waveform voltage that falls from a voltage (for example, voltage 0 (V)) that is lower than the discharge start voltage to a negative voltage Vi4 is applied to scan electrodes SC1 to SCn. This downward ramp waveform voltage has substantially the same waveform shape as the downward ramp waveform voltage generated in the initialization period Pib2.
この下り傾斜波形電圧を走査電極SC1~SCnに印加する間に、走査電極SC1~SCnとデータ電極D1~Dmとの間、および走査電極SCiと維持電極SUiとの間に微弱な初期化放電が発生する。
While applying this downward ramp waveform voltage to scan electrodes SC1 to SCn, a weak initializing discharge is generated between scan electrodes SC1 to SCn and data electrodes D1 to Dm, and between scan electrode SCi and sustain electrode SUi. appear.
この初期化放電により、走査電極SC1~SCn上の壁電圧および維持電極SU1~SUn上の壁電圧が弱められ、データ電極D1~Dm上に蓄積された正極性の壁電圧は、過剰な部分が放電され、後続の書込み動作に適した壁電圧に調整される。
This initialization discharge weakens the wall voltage on scan electrodes SC1 to SCn and the wall voltage on sustain electrodes SU1 to SUn, and the positive wall voltage accumulated on data electrodes D1 to Dm has an excessive portion. It is discharged and adjusted to a wall voltage suitable for the subsequent address operation.
下り傾斜波形電圧が電圧Vi4に到達したら、走査電極SC1~SCnに印加する電圧を電圧Vcにする。
When the descending ramp waveform voltage reaches the voltage Vi4, the voltage applied to the scan electrodes SC1 to SCn is set to the voltage Vc.
この初期化期間Picoに発生する上述の駆動電圧波形が、強制初期化波形(第2の強制初期化波形)である。この初期化期間Picoでは、パネル10の画像表示領域における全ての放電セルで強制的に初期化放電を発生する。各放電セル間には、放電の履歴に応じて壁電圧のばらつきが生じるが、この強制初期化動作により、各放電セルの壁電圧をほぼ均一な状態にすることができる。そして、各放電セル内の壁電圧は、続く書込み期間Pwoにおける書込み動作に適した壁電圧に調整され、さらに、書込み放電の発生を補助するプライミング粒子が放電セル内に発生する。
The above-mentioned drive voltage waveform generated in the initialization period Pico is a forced initialization waveform (second forced initialization waveform). In this initialization period Pico, initialization discharge is forcibly generated in all the discharge cells in the image display area of panel 10. Although the wall voltage varies between the discharge cells depending on the discharge history, the wall voltage of each discharge cell can be made substantially uniform by this forced initialization operation. The wall voltage in each discharge cell is adjusted to a wall voltage suitable for the address operation in the subsequent address period Pwo, and priming particles that assist the generation of the address discharge are generated in the discharge cell.
タイミング検出サブフィールドSFoの書込み期間Pwoでは、データ電極D1~Dmには電圧0(V)を印加し、維持電極SU1~SUnには電圧Veを印加し、走査電極SC1~SCnには電圧Vcを印加する。
In the address period Pwo of the timing detection subfield SFo, the voltage 0 (V) is applied to the data electrodes D1 to Dm, the voltage Ve is applied to the sustain electrodes SU1 to SUn, and the voltage Vc is applied to the scan electrodes SC1 to SCn. Apply.
次に、データ電極D1~Dmに電圧Vdの書込みパルスを印加するとともに走査電極SC1~SCnに電圧Vaの走査パルスを印加し、各放電セルに書込み放電を発生させる。
Next, an address pulse of the voltage Vd is applied to the data electrodes D1 to Dm and a scan pulse of the voltage Va is applied to the scan electrodes SC1 to SCn to generate an address discharge in each discharge cell.
本実施の形態では、図4に示すように、全てのデータ電極D1~Dmに書込みパルスを印加したまま、走査電極SC1から走査電極SCnまでの各電極に順次走査パルスを印加するが、例えば、全ての走査電極SC1~SCnに一斉に走査パルスを印加して、パネル10の画像表示領域内にある全ての放電セルに一斉に書込み放電を発生させてもよい。
In the present embodiment, as shown in FIG. 4, the scan pulse is sequentially applied to each of the electrodes from the scan electrode SC1 to the scan electrode SCn while applying the write pulse to all the data electrodes D1 to Dm. It is also possible to apply a scan pulse to all the scan electrodes SC1 to SCn at a time and generate an address discharge in all the discharge cells in the image display area of the panel 10 at the same time.
パネル10の画像表示領域内にある全ての放電セルに書込み放電を発生し終えた後は、データ電極D1~Dmに電圧0(V)を印加する。また、走査電極SC1~SCnには電圧Vcを印加し、その後、電圧0(V)を印加する。また、維持電極SU1~SUnへの印加電圧を電圧Veから電圧0(V)にする。本実施の形態では、この状態を、時刻to0から時間To0の間、維持する。したがって、この期間は、放電セルに最後の書込み放電が発生した後、放電が発生しない状態が維持される。なお、時刻to0は、最後の書込み放電を発生させるための走査パルスを走査電極SCnに印加した時刻である。
After completing the address discharge in all the discharge cells in the image display area of the panel 10, the voltage 0 (V) is applied to the data electrodes D1 to Dm. Further, voltage Vc is applied to scan electrodes SC1 to SCn, and then voltage 0 (V) is applied. Further, the voltage applied to sustain electrodes SU1 to SUn is changed from voltage Ve to voltage 0 (V). In the present embodiment, this state is maintained from time to0 to time To0. Therefore, during this period, after the last address discharge occurs in the discharge cells, a state in which no discharge occurs is maintained. Time to0 is the time when the scan pulse for generating the last address discharge is applied to scan electrode SCn.
そして、本実施の形態では、時間To0を、後述する時間To1、時間To2、時間To3のいずれよりも長い時間に設定する。本実施の形態では、時間To0は、例えば、約50μsecである。
In this embodiment, the time To0 is set to a time longer than any of the time To1, the time To2, and the time To3 described later. In the present embodiment, the time To0 is about 50 μsec, for example.
次に、タイミング検出サブフィールドSFoのタイミング検出期間Poでは、ライトペンにおける位置座標算出時の基準となる複数回の発光(タイミング検出用の発光)をパネル10に生じさせる。すなわち、あらかじめ定められた所定の時間間隔(本実施の形態では、例えば、時間To1、時間To2、時間To3)で、パネル10の画像表示領域内の全ての放電セルに、タイミング検出用の発光を生じさせるタイミング検出放電を複数回(本実施の形態では、例えば、4回)発生させる。
Next, in the timing detection period Po of the timing detection subfield SFo, the panel 10 is caused to emit a plurality of times of light emission (light emission for timing detection) as a reference when calculating the position coordinates of the light pen. That is, light emission for timing detection is emitted to all the discharge cells in the image display area of the panel 10 at a predetermined time interval (in this embodiment, for example, time To1, time To2, and time To3 in this embodiment). The timing detection discharge to be generated is generated a plurality of times (in this embodiment, for example, four times).
具体的には、時刻to0から時間To0が経過した後の時刻to1において、維持電極SU1~SUnに電圧0(V)を印加するとともに走査電極SC1~SCnに電圧Vsoのタイミング検出パルスV1を印加する。これにより、パネル10の画像表示領域内にある全ての放電セルに1回目のタイミング検出放電が発生し、パネル10の画像表示面の全面が発光する(1回目のタイミング検出用の発光)。
Specifically, at time to1 after time To0 has elapsed from time to0, voltage 0 (V) is applied to sustain electrodes SU1 to SUn, and timing detection pulse V1 of voltage Vso is applied to scan electrodes SC1 to SCn. . As a result, the first timing detection discharge is generated in all the discharge cells in the image display area of the panel 10, and the entire image display surface of the panel 10 emits light (first timing detection light emission).
なお、このタイミング検出放電は、維持放電と同様に、書込み放電と比較して強い放電である。
Note that this timing detection discharge is a stronger discharge than the address discharge, similarly to the sustain discharge.
次に、時刻to1から時間To1が経過した後の時刻to2において、走査電極SC1~SCnに電圧0(V)を印加するとともに維持電極SU1~SUnに電圧Vsoのタイミング検出パルスV2を印加する。これにより、パネル10の画像表示領域内にある全ての放電セルに2回目のタイミング検出放電が発生し、パネル10の画像表示面の全面が発光する(2回目のタイミング検出用の発光)。
Next, at time to2 after time To1 has elapsed from time to1, voltage 0 (V) is applied to scan electrodes SC1 to SCn and timing detection pulse V2 of voltage Vso is applied to sustain electrodes SU1 to SUn. Thereby, the second timing detection discharge is generated in all the discharge cells in the image display area of the panel 10, and the entire image display surface of the panel 10 emits light (second timing detection light emission).
次に、時刻to2から時間To2が経過した後の時刻to3において、維持電極SU1~SUnに電圧0(V)を印加するとともに走査電極SC1~SCnに電圧Vsoのタイミング検出パルスV3を印加する。これにより、パネル10の画像表示領域内にある全ての放電セルに3回目のタイミング検出放電が発生し、パネル10の画像表示面の全面が発光する(3回目のタイミング検出用の発光)。
Next, at time to3 after time To2 has elapsed from time to2, voltage 0 (V) is applied to sustain electrodes SU1 to SUn, and timing detection pulse V3 of voltage Vso is applied to scan electrodes SC1 to SCn. As a result, the third timing detection discharge is generated in all the discharge cells in the image display region of the panel 10, and the entire image display surface of the panel 10 emits light (third timing detection light emission).
次に、時刻to3から時間To3が経過した後の時刻to4において、走査電極SC1~SCnに電圧0(V)を印加するとともに維持電極SU1~SUnに電圧Vsoのタイミング検出パルスV4を印加する。これにより、パネル10の画像表示領域内にある全ての放電セルに4回目のタイミング検出放電が発生し、パネル10の画像表示面の全面が発光する(4回目のタイミング検出用の発光)。
Next, at time to4 after time To3 has elapsed from time to3, voltage 0 (V) is applied to scan electrodes SC1 to SCn, and timing detection pulse V4 of voltage Vso is applied to sustain electrodes SU1 to SUn. As a result, the fourth timing detection discharge is generated in all the discharge cells in the image display area of the panel 10, and the entire image display surface of the panel 10 emits light (fourth timing detection light emission).
このように、タイミング検出サブフィールドSFoでは、あらかじめ定められた所定の時間間隔(本実施の形態では、例えば、時間To1、時間To2、時間To3)で複数回(本実施の形態では、例えば、4回)のタイミング検出放電を発生し、パネル10の画像表示面の全面を所定の時間間隔(例えば、時間To1、時間To2、時間To3)で複数回(例えば、4回)発光させる。そして、ライトペンは、この発光を受光して座標基準信号(ライトペンの位置座標(x座標、y座標)を算出する際に基準となる信号)を作成する。
Thus, in the timing detection subfield SFo, a predetermined time interval (in the present embodiment, for example, time To1, time To2, and time To3 in this embodiment) is multiple times (in this embodiment, for example, 4 Timing detection discharge is generated, and the entire image display surface of the panel 10 is caused to emit light a plurality of times (for example, four times) at predetermined time intervals (for example, time To1, time To2, and time To3). Then, the light pen receives this light emission and creates a coordinate reference signal (a signal that becomes a reference when calculating the position coordinates (x coordinate, y coordinate) of the light pen).
タイミング検出サブフィールドSFoでは、パネル10の画像表示面の全面が同じタイミングで一斉に光るので、ライトペンの先端部がパネル10の画像表示領域内のどこにあったとしても、ライトペンは同じタイミングでこの発光を受光することができる。
In the timing detection subfield SFo, the entire surface of the image display surface of the panel 10 shines at the same timing, so that the light pen is at the same timing no matter where the tip of the light pen is in the image display area of the panel 10. This light emission can be received.
本実施の形態では、例えば、時間To1は約40μsecであり、時間To2は約20μsecであり、時間To3は約30μsecである。しかし、本発明は時間To0~To3の各時間が何ら上述した数値に限定されるものではなく、各時間はプラズマディスプレイシステムの仕様等に応じて適切に設定すればよい。
In this embodiment, for example, the time To1 is about 40 μsec, the time To2 is about 20 μsec, and the time To3 is about 30 μsec. However, the present invention is not limited to the numerical values described above for the times To0 to To3, and each time may be set appropriately according to the specifications of the plasma display system.
そして、ライトペンは、所定の時間間隔(例えば、時間To1、時間To2、時間To3)で発生する複数回(例えば、4回)の発光を検出したら座標基準信号を作成する。
The light pen generates a coordinate reference signal when it detects a plurality of times (for example, four times) of light emission occurring at a predetermined time interval (for example, time To1, time To2, and time To3).
タイミング検出サブフィールドSFoのタイミング検出期間Poにおいて、タイミング検出パルスV4の発生後(タイミング検出期間Poの最後)には、サブフィールドSF1の維持期間Ps1の最後に行う消去動作と同様の消去動作を行う。すなわち、維持電極SU1~SUnおよびデータ電極D1~Dmに電圧0(V)を印加したまま、走査電極SC1~SCnに電圧0(V)から第1の電圧(電圧Vr)まで緩やかに上昇する第1のランプ波形電圧を印加する。第1のランプ波形電圧が電圧Vrに到達したら、その後、走査電極SC1~SCnに印加する電圧を電圧0(V)まで下降する。これにより、パネル10の画像表示領域内にある全ての放電セルに微弱な消去放電が発生する。
In the timing detection period Po of the timing detection subfield SFo, after the generation of the timing detection pulse V4 (the end of the timing detection period Po), an erase operation similar to the erase operation performed at the end of the sustain period Ps1 of the subfield SF1 is performed. . In other words, the scan electrodes SC1 to SCn gradually increase from the voltage 0 (V) to the first voltage (voltage Vr) while the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn and the data electrodes D1 to Dm. A ramp waveform voltage of 1 is applied. When the first ramp waveform voltage reaches the voltage Vr, the voltage applied to the scan electrodes SC1 to SCn is lowered to the voltage 0 (V). Thereby, a weak erasure discharge is generated in all the discharge cells in the image display area of the panel 10.
なお、本実施の形態において、電圧Vsoは電圧Vsに等しい電圧に設定されており、例えば、電圧Vsoは約205(V)である。しかし、電圧Vsoは電圧Vsと異なる電圧であってもよい。電圧Vsoはタイミング検出放電が発生する電圧であればよい。
In this embodiment, the voltage Vso is set to a voltage equal to the voltage Vs. For example, the voltage Vso is about 205 (V). However, the voltage Vso may be a voltage different from the voltage Vs. The voltage Vso may be any voltage that generates timing detection discharge.
続いて、y座標検出サブフィールドSFyとx座標検出サブフィールドSFxを発生する。
Subsequently, a y-coordinate detection subfield SFy and an x-coordinate detection subfield SFx are generated.
y座標検出サブフィールドSFyは、初期化期間Piby、y座標検出期間Py、および消去期間Pebyを有する。
The y coordinate detection subfield SFy has an initialization period Piby, a y coordinate detection period Py, and an erase period Peby.
初期化期間Pibyでは、画像表示サブフィールドのサブフィールドSF2の初期化期間Pib2と同様の駆動電圧波形を各電極に印加して同様の選択初期化動作を行うので、説明を省略する。
In the initialization period Piby, a drive voltage waveform similar to that in the initialization period Pib2 of the subfield SF2 of the image display subfield is applied to each electrode to perform the same selective initialization operation, and thus description thereof is omitted.
初期化期間Pibyの直前にあるタイミング検出サブフィールドSFoのタイミング検出期間Poでは、パネル10の画像表示領域内にある全ての放電セルにタイミング検出放電が発生するので、初期化期間Pibyにおいても、それら全ての放電セルに微弱な初期化放電が発生する。これにより、パネル10の画像表示領域内にある全ての放電セルの壁電圧が、続くy座標検出期間Pyにおけるy座標検出パターン表示動作に適した壁電圧に調整される。さらに、y座標検出期間Pyにおける放電の発生を補助するプライミング粒子が放電セル内に発生する。
In the timing detection period Po of the timing detection subfield SFo immediately before the initialization period Piby, timing detection discharges are generated in all the discharge cells in the image display area of the panel 10, and therefore in the initialization period Piby A weak initializing discharge is generated in all discharge cells. Thereby, the wall voltage of all the discharge cells in the image display area of the panel 10 is adjusted to the wall voltage suitable for the y coordinate detection pattern display operation in the subsequent y coordinate detection period Py. Furthermore, priming particles that assist the generation of discharge in the y-coordinate detection period Py are generated in the discharge cell.
次に、y座標検出サブフィールドSFyのy座標検出期間Pyでは、維持電極SU1~SUnに電圧Veを印加し、データ電極D1~Dmに電圧0(V)を印加し、走査電極SC1~SCnに電圧Vcを印加する。そして、期間Ty0の間、この状態を維持する。この期間Ty0は、上述した期間Tw0よりも長い時間であり、例えば、約700μsecに設定されている。
Next, in the y coordinate detection period Py of the y coordinate detection subfield SFy, the voltage Ve is applied to the sustain electrodes SU1 to SUn, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the scan electrodes SC1 to SCn are applied. A voltage Vc is applied. Then, this state is maintained during the period Ty0. This period Ty0 is longer than the above-described period Tw0, and is set to about 700 μsec, for example.
次に、期間Ty0の後の時刻ty0で、データ電極D1~Dmに正極性のy座標検出電圧Vdyを印加し、1行目の走査電極SC1に電圧Vayの負極性のy座標検出パルスを印加する。y座標検出電圧Vdyは電圧0(V)よりも高い電圧であり、y座標検出パルスの電圧Vayは電圧Vcよりも低い負の電圧である。なお、図4では、y座標検出パルスのパルス幅をTy1として示している。
Next, at time ty0 after period Ty0, positive y coordinate detection voltage Vdy is applied to data electrodes D1 to Dm, and negative y coordinate detection pulse of voltage Vay is applied to scan electrode SC1 in the first row. To do. The y coordinate detection voltage Vdy is a voltage higher than the voltage 0 (V), and the voltage Vay of the y coordinate detection pulse is a negative voltage lower than the voltage Vc. In FIG. 4, the pulse width of the y coordinate detection pulse is shown as Ty1.
y座標検出電圧Vdyを印加したデータ電極D1~Dmと、電圧Vayのy座標検出パルスを印加した走査電極SC1との交差部にある1行目の放電セルでは、データ電極D1~Dmと走査電極SC1との交差部の電圧差が放電開始電圧を超え、データ電極D1~Dmと走査電極SC1との間、および維持電極SU1と走査電極SC1との間に放電が発生する。
In the discharge cell in the first row at the intersection of the data electrodes D1 to Dm to which the y coordinate detection voltage Vdy is applied and the scan electrode SC1 to which the y coordinate detection pulse of the voltage Vay is applied, the data electrodes D1 to Dm and the scan electrodes The voltage difference at the intersection with SC1 exceeds the discharge start voltage, and discharge occurs between data electrodes D1 to Dm and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1.
この放電は、書込み放電と同程度の強さの放電であり、維持放電と比較して弱い放電である。
This discharge is as strong as the address discharge and is weaker than the sustain discharge.
このようにして、1行目を構成する全ての放電セルに放電が発生し、それらの放電セルが一斉に発光する。例えば、パネル10の画像表示領域がm×n個の放電セルで構成され、m=1920×3=5760であり、n=1080(すなわち、画像表示領域における画素数が1920×1080)であれば、1行目を構成する5760個の放電セル(1920個の画素)が一斉に発光する。そして、この発光は、y座標検出のための発光となる。
Thus, discharge occurs in all the discharge cells constituting the first row, and these discharge cells emit light all at once. For example, if the image display area of the panel 10 is composed of m × n discharge cells, m = 1920 × 3 = 5760, and n = 1080 (that is, the number of pixels in the image display area is 1920 × 1080). The 5760 discharge cells (1920 pixels) constituting the first row emit light all at once. And this light emission becomes light emission for y coordinate detection.
以下、1つの行を構成する放電セルの集合体を「放電セル行」と記し、1つの行を構成する画素の集合体を「画素行」と記す。本実施の形態では、放電セル行と画素行とは実質的に同じものであり、上述の動作では、1行目の画素行(1行目の放電セル行)が一斉に発光する。
Hereinafter, an aggregate of discharge cells constituting one row is referred to as “discharge cell row”, and an aggregate of pixels constituting one row is referred to as “pixel row”. In this embodiment, the discharge cell row and the pixel row are substantially the same, and in the above operation, the first pixel row (first discharge cell row) emits light all at once.
この放電が発生した放電セルでは、走査電極SC1上に正極性の壁電圧が蓄積され、維持電極SU1上に負極性の壁電圧が蓄積され、データ電極D1~Dm上にも負極性の壁電圧が蓄積される。
In the discharge cell in which this discharge has occurred, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also formed on data electrodes D1 to Dm. Is accumulated.
次に、データ電極D1~Dmにy座標検出電圧Vdyを印加したまま、2行目の走査電極SC2に電圧Vayのy座標検出パルスを印加する。これにより、2行目の画素行(2行目の放電セル行)にy座標検出のための発光が生じる。
Next, with the y coordinate detection voltage Vdy applied to the data electrodes D1 to Dm, a y coordinate detection pulse of the voltage Vay is applied to the scan electrode SC2 in the second row. As a result, light emission for y coordinate detection occurs in the second pixel row (second discharge cell row).
同様の動作を、データ電極D1~Dmにy座標検出電圧Vdyを印加したまま、走査電極SC3、走査電極SC4、・・・、走査電極SCnという順番で、n行目の放電セルに至るまで順次行い、3行目からn行目(例えば、1080行目)までの各画素行(放電セル行)にy座標検出のための発光を順次発生させる。
The same operation is performed in the order of scan electrode SC3, scan electrode SC4,..., Scan electrode SCn with the y coordinate detection voltage Vdy being applied to the data electrodes D1 to Dm until the discharge cell in the n-th row is reached. Then, light emission for y coordinate detection is sequentially generated in each pixel row (discharge cell row) from the third row to the nth row (for example, 1080th row).
これにより、y座標検出サブフィールドSFyのy座標検出期間Pyでは、発光する1本の横線(すなわち、発光する1つの画素行)が、パネル10の画像表示領域の上端部(1行目の画素行)から下端部(n行目の画素行)まで1行ずつ順次移動するパターン(y座標検出パターン)が表示される。すなわち、このy座標検出パターンとは、画像表示領域の1行目からn行目までの各画素行が、1行毎に順次発光するパターンである。
As a result, in the y coordinate detection period Py of the y coordinate detection subfield SFy, one horizontal line that emits light (that is, one pixel row that emits light) corresponds to the upper end portion (pixels in the first row) of the image display area of the panel 10. A pattern (y-coordinate detection pattern) that sequentially moves one line at a time from the lower line to the lower end (nth pixel line) is displayed. That is, the y-coordinate detection pattern is a pattern in which each pixel row from the first row to the n-th row of the image display area sequentially emits light for each row.
パネル10にy座標検出パターンを表示すると、画像表示領域の1行目からn行目までの各画素行が、1行毎に順次発光するので、ライトペンの先端部がパネル10の画像表示領域内のどこにあるかによって、ライトペンがこの発光を受光するタイミングは変化する。ライトペンでこの発光がいつ受光されたのか、その受光タイミングを検出することで、画像表示領域におけるライトペンの位置(x座標、y座標)のy座標が検出される。
When the y-coordinate detection pattern is displayed on the panel 10, each pixel row from the first row to the n-th row of the image display region emits light sequentially for each row, so that the tip of the light pen is the image display region of the panel 10 The timing at which the light pen receives this light emission varies depending on where the light pen is. The y coordinate of the position (x coordinate, y coordinate) of the light pen in the image display area is detected by detecting the light reception timing when the light emission is received by the light pen.
なお、y座標検出パターンがパネル10に表示される期間は非常に短い。そのため、y座標検出パターンが使用者に認識される可能性は低く、たとえ使用者に認識されたとしても、それはごく僅かな輝度の変化に過ぎない。
Note that the period during which the y-coordinate detection pattern is displayed on the panel 10 is very short. Therefore, the possibility that the y-coordinate detection pattern is recognized by the user is low, and even if it is recognized by the user, it is only a slight change in luminance.
本実施の形態では、走査電極SC1~SCnのそれぞれにy座標検出パルスを印加する時間をTy1とする。このTy1は、例えば、約1μsecである。したがって、例えば、n=1080であり、初期化期間Pibyが終了してから最初のy座標検出パルスが発生するまでの期間Ty0が約700μsecであれば、y座標検出期間Pyの時間は、Ty0+Ty1×1080=約1780μsecとなる。
In this embodiment, the time for applying the y-coordinate detection pulse to each of the scan electrodes SC1 to SCn is Ty1. This Ty1 is, for example, about 1 μsec. Therefore, for example, if n = 1080 and the period Ty0 from the end of the initialization period Piby to the generation of the first y coordinate detection pulse is about 700 μsec, the time of the y coordinate detection period Py is Ty0 + Ty1 × 1080 = about 1780 μsec.
y座標検出サブフィールドSFyの消去期間Pebyでは、維持電極SU1~SUnに電圧0(V)を印加し、データ電極D1~Dmは電圧0(V)を印加した後にハイインピーダンス状態にする。
In the erasing period Peby of the y coordinate detection subfield SFy, the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn, and the data electrodes D1 to Dm are set to the high impedance state after the voltage 0 (V) is applied.
走査電極SC1~SCnには、電圧0(V)から第1の電圧(電圧Vr)まで緩やかに上昇する上り傾斜波形電圧を印加する。上り傾斜波形電圧が電圧Vrに到達したら、走査電極SC1~SCnの電圧を一旦電圧0(V)まで下げる。次に、走査電極SC1~SCnに電圧Vrよりも低い電圧Vi1を印加し、電圧Vi1から第1の電圧よりも高い第2の電圧(電圧Vi2)まで緩やかに上昇する上り傾斜波形電圧を印加する。電圧Vi2は、維持電極SU1~SUnに対して放電開始電圧を超える電圧に設定する。
The upward ramp waveform voltage that gently rises from the voltage 0 (V) to the first voltage (voltage Vr) is applied to the scan electrodes SC1 to SCn. When the rising ramp waveform voltage reaches voltage Vr, the voltages of scan electrodes SC1 to SCn are once lowered to voltage 0 (V). Next, a voltage Vi1 lower than the voltage Vr is applied to the scan electrodes SC1 to SCn, and an upward ramp waveform voltage that gradually rises from the voltage Vi1 to a second voltage (voltage Vi2) higher than the first voltage is applied. . Voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrodes SU1 to SUn.
この上り傾斜波形電圧が上昇する間に、走査電極SC1~SCnと維持電極SU1~SUnとの間、および走査電極SC1~SCnとデータ電極D1~Dmとの間に、それぞれ微弱な消去放電が発生する。
While the rising ramp waveform voltage rises, a weak erasing discharge is generated between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm. To do.
このとき、データ電極D1~Dmがハイインピーダンス状態なので、サブフィールドSF1の初期化期間Pia1と同様に、走査電極SC1~SCnと維持電極SU1~SUnとの間の放電が、走査電極SC1~SCnとデータ電極D1~Dmとの間の放電よりも先に発生する。そのため、この消去放電は安定に発生する。
At this time, since the data electrodes D1 to Dm are in the high impedance state, the discharge between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn is caused to occur between the scan electrodes SC1 to SCn, as in the initialization period Pia1 of the subfield SF1. It occurs before the discharge between the data electrodes D1 to Dm. Therefore, this erasing discharge is generated stably.
こうして、パネル10の画像表示領域内にある全ての放電セルの壁電圧が、続くx座標検出サブフィールドSFxにおける初期化動作に適した壁電圧に調整される。さらに、x座標検出サブフィールドSFxにおける放電の発生を補助するプライミング粒子が放電セル内に発生する。
Thus, the wall voltage of all the discharge cells in the image display area of panel 10 is adjusted to the wall voltage suitable for the initialization operation in the subsequent x coordinate detection subfield SFx. Furthermore, priming particles that assist the generation of discharge in the x-coordinate detection subfield SFx are generated in the discharge cell.
なお、図4には、走査電極SC1~SCnに、電圧0(V)から正の電圧Vi2まで2回に分けて上昇する上り傾斜波形電圧を印加する例を示したが、2回目の上り傾斜波形電圧を放電セルに印加するときに強放電が発生するのを防止するため、図4に示すように、2回目の上り傾斜電圧の開始電圧を1回目の上り傾斜電圧の最大電圧以下の電圧値に設定することが望ましい。
FIG. 4 shows an example in which the rising ramp waveform voltage that rises in two steps from the voltage 0 (V) to the positive voltage Vi2 is applied to the scan electrodes SC1 to SCn. In order to prevent a strong discharge from occurring when a waveform voltage is applied to the discharge cell, as shown in FIG. 4, the start voltage of the second rising ramp voltage is equal to or lower than the maximum voltage of the first rising ramp voltage. It is desirable to set it to a value.
また、本実施の形態において、この上り傾斜波形電圧は、何ら2回に分けて発生する構成に限定されるものではなく、この上り傾斜波形電圧は、電圧0(V)から電圧Vi2まで連続して上昇する波形形状であってもよい。以下、この上り傾斜波形電圧を「第2のランプ波形電圧」と記す。したがって、図4に示す第2の上りランプ波形電圧は電圧0(V)から電圧Vi2まで2回に分けて上昇する波形形状となるが、電圧0(V)から電圧Vi2まで連続して上昇する波形形状のものも第2のランプ波形電圧に含まれる。
Further, in the present embodiment, the upward ramp waveform voltage is not limited to a configuration that is generated in two steps, and the upward ramp waveform voltage is continuous from voltage 0 (V) to voltage Vi2. It may be a waveform shape that rises. Hereinafter, this upward ramp waveform voltage is referred to as a “second ramp waveform voltage”. Therefore, the second up-ramp waveform voltage shown in FIG. 4 has a waveform shape that rises in two steps from voltage 0 (V) to voltage Vi2, but rises continuously from voltage 0 (V) to voltage Vi2. A waveform having a waveform shape is also included in the second ramp waveform voltage.
第2のランプ波形電圧が電圧Vi2に到達したら、走査電極SC1~SCnに印加する電圧を、電圧Vi2よりも低い電圧Vi3まで一旦下げ、その後、電圧0(V)にする。ただし、本発明は何らこの構成に限定されるものではなく、例えば、電圧Vi2から電圧0(V)まで急峻に電圧を下げてもよい。
When the second ramp waveform voltage reaches the voltage Vi2, the voltage applied to the scan electrodes SC1 to SCn is once lowered to the voltage Vi3 lower than the voltage Vi2, and then set to the voltage 0 (V). However, the present invention is not limited to this configuration. For example, the voltage may be sharply decreased from voltage Vi2 to voltage 0 (V).
続くx座標検出サブフィールドSFxは、初期化期間Pidx、x座標検出期間Px、および消去期間Pedxを有する。
The subsequent x-coordinate detection subfield SFx has an initialization period Pidx, an x-coordinate detection period Px, and an erase period Pedx.
初期化期間Pidxでは、y座標検出サブフィールドSFyの初期化期間Pibyと同様の駆動電圧波形を各電極に印加し、初期化期間Pibyと同様の選択初期化動作を行う。ただし、初期化期間Pidxでは、初期化期間Pibyに発生する下り傾斜波形電圧と同じ勾配で下降するが、それよりも振幅が大きい下り傾斜波形電圧を走査電極SC~SCnに印加する。
In the initialization period Pidx, a drive voltage waveform similar to that in the initialization period Piby of the y coordinate detection subfield SFy is applied to each electrode, and a selective initialization operation similar to that in the initialization period Piby is performed. However, in the initialization period Pidx, a downward ramp waveform voltage having a larger amplitude than that of the downward ramp waveform voltage generated in the initialization period Piby is applied to the scan electrodes SC to SCn.
初期化期間Pidxでは、データ電極D1~Dmに電圧0(V)を印加し、維持電極SU1~SUnに電圧Veを印加する。そして、走査電極SC1~SCnに、放電開始電圧未満となる電圧(例えば、電圧0(V))から負の電圧Vaまで下降する下り傾斜波形電圧を印加する。
In the initialization period Pidx, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the voltage Ve is applied to the sustain electrodes SU1 to SUn. Then, a downward ramp waveform voltage that falls from a voltage (for example, voltage 0 (V)) that is lower than the discharge start voltage to a negative voltage Va is applied to scan electrodes SC1 to SCn.
負の電圧Vaは、負の電圧Vi4よりも電圧値が低い。すなわち、電圧Vaの絶対値は電圧Vi4の絶対値よりも値が大きい。本実施の形態において、電圧Vaは、例えば約-200(V)であり、電圧Vi4は、例えば約-175(V)である。
The negative voltage Va has a lower voltage value than the negative voltage Vi4. That is, the absolute value of the voltage Va is larger than the absolute value of the voltage Vi4. In the present embodiment, the voltage Va is about −200 (V), for example, and the voltage Vi4 is about −175 (V), for example.
初期化期間Pidxの直前にあるy座標検出サブフィールドSFyでは、パネル10の画像表示領域内にある全ての放電セルにy座標検出のための放電および消去放電が発生するので、初期化期間Pidxにおいても、それら全ての放電セルに微弱な初期化放電が発生する。これにより、パネル10の画像表示領域内にある全ての放電セルの壁電圧が、続くx座標検出期間Pxにおけるx座標検出パターン表示動作に適した壁電圧に調整される。さらに、x座標検出期間Pxにおける放電の発生を補助するプライミング粒子が放電セル内に発生する。
In the y-coordinate detection subfield SFy immediately before the initialization period Pidx, the discharge and erasure discharge for detecting the y-coordinate occur in all the discharge cells in the image display area of the panel 10, and therefore, in the initialization period Pidx However, a weak initializing discharge is generated in all the discharge cells. Thereby, the wall voltage of all the discharge cells in the image display area of the panel 10 is adjusted to the wall voltage suitable for the x coordinate detection pattern display operation in the subsequent x coordinate detection period Px. Furthermore, priming particles that assist the generation of discharge in the x-coordinate detection period Px are generated in the discharge cell.
なお、本実施の形態では、x座標検出サブフィールドSFxの初期化期間Pidxに発生する下り傾斜波形電圧の到達電位を、電圧Vi4よりも低い(絶対値が大きい)電圧Vaとし、データ電極D1~Dm上に残留する正極性の壁電圧を、画像表示サブフィールドのサブフィールドSF1~SF8の各初期化期間Pia1、Pib2~Pib8終了時(あるいは初期化期間Pico、Piby終了時)にデータ電極D1~Dm上に残留する正極性の壁電圧よりも低い値に調整している。
In the present embodiment, the arrival potential of the downward ramp waveform voltage generated in the initialization period Pidx of the x-coordinate detection subfield SFx is set to the voltage Va lower than the voltage Vi4 (larger absolute value), and the data electrodes D1 to The positive wall voltage remaining on Dm is applied to the data electrodes D1 to D1 at the end of the initialization periods Pia1, Pib2 to Pib8 of the subfields SF1 to SF8 of the image display subfield (or at the end of the initialization periods Pico and Piby). It is adjusted to a value lower than the positive wall voltage remaining on Dm.
このように壁電圧を低くすることで、x座標検出サブフィールドSFxのx座標検出期間Pxにおいて、走査電極SC1~SCnに電圧Vaxを印加するときに流れる暗電流を抑制することができる。暗電流を抑制することで壁電荷の減少を抑えることができるので、これにより、x座標検出期間Pxにおける壁電荷の減少を抑制することができる。
By reducing the wall voltage in this way, it is possible to suppress the dark current that flows when the voltage Vax is applied to the scan electrodes SC1 to SCn in the x coordinate detection period Px of the x coordinate detection subfield SFx. Since the decrease in wall charge can be suppressed by suppressing the dark current, the decrease in wall charge in the x coordinate detection period Px can thereby be suppressed.
次に、x座標検出サブフィールドSFxのx座標検出期間Pxでは、まず、データ電極D1~Dmに電圧0(V)を印加し、維持電極SU1~SUnに電圧Veを印加し、走査電極SC1~SCnに電圧Vcを印加する。そして、期間Tx0の間、この状態を維持する。
Next, in the x coordinate detection period Px of the x coordinate detection subfield SFx, first, the voltage 0 (V) is applied to the data electrodes D1 to Dm, the voltage Ve is applied to the sustain electrodes SU1 to SUn, and the scan electrodes SC1 to SCn are applied. A voltage Vc is applied to SCn. Then, this state is maintained during the period Tx0.
この期間Tx0は、上述した期間Tw0よりも長い時間に設定する。期間Tx0は、200μsec以上1msec以下の間で設定することが望ましく、本実施の形態では、例えば、約700μsecに設定されている。
This period Tx0 is set to be longer than the period Tw0 described above. The period Tx0 is desirably set between 200 μsec and 1 msec, and is set to about 700 μsec in the present embodiment, for example.
次に、期間Tx0の経過後に、走査電極SC1~SCnに負極性のx座標検出電圧Vaxを印加し、走査電極SC1~SCnに印加する電圧がx座標検出電圧Vaxに到達した後の時刻tx0で、1~3列目のデータ電極D1~D3に電圧Vdxの正極性のx座標検出パルスを印加する。x座標検出パルスの電圧Vdxは電圧0(V)よりも高い電圧であり、x座標検出電圧Vaxは電圧Vcよりも低い負の電圧である。なお、図4では、x座標検出パルスのパルス幅をTx1として示し、また、走査電極SC1~SCnに印加する駆動電圧波形を、電圧Vcから電圧Vaxまで比較的緩やかに電圧が下降する駆動電圧波形として示している。
Next, at the time tx0 after the elapse of the period Tx0, the negative x-coordinate detection voltage Vax is applied to the scan electrodes SC1 to SCn, and the voltage applied to the scan electrodes SC1 to SCn reaches the x-coordinate detection voltage Vax. A positive x coordinate detection pulse of voltage Vdx is applied to data electrodes D1 to D3 in the first to third columns. The voltage Vdx of the x coordinate detection pulse is higher than the voltage 0 (V), and the x coordinate detection voltage Vax is a negative voltage lower than the voltage Vc. In FIG. 4, the pulse width of the x-coordinate detection pulse is shown as Tx1, and the drive voltage waveform applied to scan electrodes SC1 to SCn is a drive voltage waveform in which the voltage drops relatively slowly from voltage Vc to voltage Vax. As shown.
なお、データ電極D1~D3は、1つの画素を構成する赤の放電セル、緑の放電セル、青の放電セルに対応しており、この画素は、例えば画像表示領域の左端に配置された画素である。
The data electrodes D1 to D3 correspond to a red discharge cell, a green discharge cell, and a blue discharge cell constituting one pixel, and the pixel is a pixel arranged at the left end of the image display area, for example. It is.
電圧Vdxのx座標検出パルスを印加したデータ電極D1~D3と、x座標検出電圧Vaxを印加した走査電極SC1~SCnとの交差部にある放電セルでは、データ電極D1~D3と走査電極SC1~SCnとの交差部の電圧差が放電開始電圧を超え、データ電極D1~D3と走査電極SC1~SCnとの間、および維持電極SU1~SUnと走査電極SC1~SCnとの間に放電が発生する。
In the discharge cell at the intersection of the data electrodes D1 to D3 to which the x coordinate detection pulse of the voltage Vdx is applied and the scan electrodes SC1 to SCn to which the x coordinate detection voltage Vax is applied, the data electrodes D1 to D3 and the scan electrodes SC1 to SC1 The voltage difference at the intersection with SCn exceeds the discharge start voltage, and discharge occurs between data electrodes D1 to D3 and scan electrodes SC1 to SCn and between sustain electrodes SU1 to SUn and scan electrodes SC1 to SCn. .
この放電は、書込み放電と同程度か、もしくはさらに弱い放電であり、維持放電と比較して弱い放電である。
This discharge is the same as or weaker than the address discharge, and is weaker than the sustain discharge.
このようにして、1列目を構成する全ての画素に放電が発生し、それらの画素が一斉に発光する。例えば、パネル10の画像表示領域がm×n個の放電セルで構成され、m=1920×3=5760であり、n=1080(すなわち、画像表示領域における画素数が1920×1080)であれば、1列目を構成する1080個の画素(3列×1080個の放電セル)が一斉に発光する。そして、この発光は、x座標検出のための発光となる。
In this way, discharge occurs in all the pixels constituting the first column, and these pixels emit light all at once. For example, if the image display area of the panel 10 is composed of m × n discharge cells, m = 1920 × 3 = 5760, and n = 1080 (that is, the number of pixels in the image display area is 1920 × 1080). The 1080 pixels (3 columns × 1080 discharge cells) constituting the first column emit light all at once. And this light emission becomes light emission for x coordinate detection.
以下、1つの列を構成する放電セルの集合体を「放電セル列」と記す。また、互いに隣接する3列の放電セル列で構成される放電セルの集合体(画素の列)を「画素列」と記す。上述の動作では、1列目の画素列(すなわち、1列目、2列目および3列目の放電セル列)が一斉に発光する。
Hereinafter, an assembly of discharge cells constituting one column is referred to as a “discharge cell column”. Further, an assembly of discharge cells (pixel column) composed of three adjacent discharge cell columns is referred to as a “pixel column”. In the above-described operation, the first pixel column (that is, the first, second, and third discharge cell columns) emits light all at once.
この放電が発生した放電セルでは、走査電極SC1~SCn上に正極性の壁電圧が蓄積され、維持電極SU1~SUn上に負極性の壁電圧が蓄積され、データ電極D1~D3上にも負極性の壁電圧が蓄積される。
In the discharge cell in which this discharge has occurred, positive wall voltage is accumulated on scan electrodes SC1 to SCn, negative wall voltage is accumulated on sustain electrodes SU1 to SUn, and negative electrodes are also formed on data electrodes D1 to D3. Sex wall voltage is accumulated.
次に、走査電極SC1~SCnにx座標検出電圧Vaxを印加したまま、4列目~6列目のデータ電極D4~D6に電圧Vdxのx座標検出パルスを印加する。これにより、2列目の画素列(4列目、5列目および6列目の放電セル列)にx座標検出のための発光が生じる。
Next, with the x coordinate detection voltage Vax being applied to the scan electrodes SC1 to SCn, the x coordinate detection pulse of the voltage Vdx is applied to the data electrodes D4 to D6 in the fourth column to the sixth column. As a result, light emission for x coordinate detection occurs in the second pixel column (fourth, fifth, and sixth discharge cell columns).
同様の動作を、走査電極SC1~SCnにx座標検出電圧Vaxを印加したまま、データ電極D7~D9、データ電極D10~D12、・・・、データ電極Dm-2~Dmという順番で、互いに隣接する3本のデータ電極22毎に、m列目の放電セルに至るまで順次行い、3列目から最終列目(例えば、1920列目)までの各画素列にx座標検出のための発光を順次発生させる。
Similar operations are performed adjacent to each other in the order of data electrodes D7 to D9, data electrodes D10 to D12,..., Data electrodes Dm-2 to Dm, with the x coordinate detection voltage Vax being applied to scan electrodes SC1 to SCn. Each of the three data electrodes 22 is sequentially performed until reaching the m-th discharge cell, and light emission for x coordinate detection is performed on each pixel column from the third column to the last column (for example, 1920 column). Generate sequentially.
これにより、x座標検出サブフィールドSFxのx座標検出期間Pxでは、発光する1本の縦線(すなわち、発光する1つの画素列)が、パネル10の画像表示領域の左端部(1列目の画素列)から右端部(m/3列目の画素列)まで1列ずつ順次移動するパターン(x座標検出パターン)が表示される。すなわち、このx座標検出パターンとは、画像表示領域の1列目から最終列目までの各画素列が、1列毎に順次発光するパターンである。言い換えると、このx座標検出パターンとは、互いに隣接する3つの放電セル列が、画像表示領域の左端部(1列目)から右端部(m列目)まで、3列ずつ順次発光するパターンである。
As a result, in the x coordinate detection period Px of the x coordinate detection subfield SFx, one vertical line that emits light (that is, one pixel column that emits light) corresponds to the left end (first column) of the image display area of the panel 10. A pattern (x-coordinate detection pattern) that sequentially moves one column at a time from the pixel column) to the right end (m / 3th pixel column) is displayed. That is, the x coordinate detection pattern is a pattern in which each pixel column from the first column to the last column in the image display area sequentially emits light for each column. In other words, the x-coordinate detection pattern is a pattern in which three discharge cell columns adjacent to each other sequentially emit light by three columns from the left end (first column) to the right end (m column) of the image display area. is there.
パネル10にx座標検出パターンを表示すると、画像表示領域の1列目から最終列目までの各画素列が、1列毎に順次発光するので、ライトペンの先端部がパネル10の画像表示領域内のどこにあるかによって、ライトペンがこの発光を受光するタイミングは変化する。ライトペンでこの発光がいつ受光されたのか、その受光タイミングを検出することで、画像表示領域におけるライトペンの位置(x座標、y座標)のx座標が検出される。
When the x-coordinate detection pattern is displayed on the panel 10, each pixel column from the first column to the last column in the image display region sequentially emits light for each column, so that the tip of the light pen is the image display region of the panel 10. The timing at which the light pen receives this light emission varies depending on where the light pen is. By detecting the light reception timing when this light emission is received by the light pen, the x coordinate of the position (x coordinate, y coordinate) of the light pen in the image display area is detected.
なお、x座標検出パターンがパネル10に表示される期間は非常に短い。そのため、x座標検出パターンが使用者に認識される可能性は低く、たとえ使用者に認識されたとしても、それはごく僅かな輝度の変化に過ぎない。
Note that the period during which the x-coordinate detection pattern is displayed on the panel 10 is very short. Therefore, the possibility that the x coordinate detection pattern is recognized by the user is low, and even if it is recognized by the user, it is only a slight change in luminance.
本実施の形態では、データ電極D1~Dmのそれぞれにx座標検出パルスを印加する時間をTx1とする。このTx1は、例えば、約1μsecである。したがって、例えば、m=1920×3であり、初期化期間Pidxが終了してから最初のx座標検出パルスが発生するまでの期間Tx0が約700μsecであれば、x座標検出期間Pxの時間は、Tx0+Tx1×1920=約2620μsecとなる。
In this embodiment, the time for applying the x-coordinate detection pulse to each of the data electrodes D1 to Dm is Tx1. This Tx1 is about 1 μsec, for example. Therefore, for example, if m = 1920 × 3 and the period Tx0 from the end of the initialization period Pidx to the generation of the first x-coordinate detection pulse is about 700 μsec, the time of the x-coordinate detection period Px is Tx0 + Tx1 × 1920 = about 2620 μsec.
x座標検出サブフィールドSFxの消去期間Pedxでは、維持電極SU1~SUnに電圧0(V)を印加し、データ電極D1~Dmは電圧0(V)を印加した後にハイインピーダンス状態にする。
In the erasing period Pedx of the x-coordinate detection subfield SFx, the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn, and the data electrodes D1 to Dm are set to the high impedance state after the voltage 0 (V) is applied.
走査電極SC1~SCnには、y座標検出サブフィールドSFyの消去期間Pebyと同様に第2のランプ波形電圧を印加する。すなわち、電圧0(V)から第1の電圧(電圧Vr)まで緩やかに上昇する上り傾斜波形電圧を印加し、上り傾斜波形電圧が電圧Vrに到達したら、走査電極SC1~SCnの電圧を一旦電圧0(V)まで下げる。次に、走査電極SC1~SCnに電圧Vrよりも低い電圧Vi1を印加し、電圧Vi1から第1の電圧よりも高い第2の電圧(電圧Vi2)まで緩やかに上昇する上り傾斜波形電圧を印加する。電圧Vi2は、維持電極SU1~SUnに対して放電開始電圧を超える電圧に設定する。
The second ramp waveform voltage is applied to the scan electrodes SC1 to SCn in the same manner as the erase period Peby of the y coordinate detection subfield SFy. That is, when an upward ramp waveform voltage that gradually rises from the voltage 0 (V) to the first voltage (voltage Vr) is applied and the upward ramp waveform voltage reaches the voltage Vr, the voltages of the scan electrodes SC1 to SCn are temporarily set to voltages. Reduce to 0 (V). Next, a voltage Vi1 lower than the voltage Vr is applied to the scan electrodes SC1 to SCn, and an upward ramp waveform voltage that gradually rises from the voltage Vi1 to a second voltage (voltage Vi2) higher than the first voltage is applied. . Voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrodes SU1 to SUn.
この第2のランプ波形電圧が上昇する間に、走査電極SC1~SCnと維持電極SU1~SUnとの間、および走査電極SC1~SCnとデータ電極D1~Dmとの間に、それぞれ微弱な消去放電が発生する。
While the second ramp waveform voltage rises, weak erase discharges are generated between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm, respectively. Will occur.
このとき、データ電極D1~Dmがハイインピーダンス状態なので、サブフィールドSF1の初期化期間Pia1と同様に、走査電極SC1~SCnと維持電極SU1~SUnとの間の放電が、走査電極SC1~SCnとデータ電極D1~Dmとの間の放電よりも先に発生する。そのため、この消去放電は安定に発生する。
At this time, since the data electrodes D1 to Dm are in the high impedance state, the discharge between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn is caused to occur between the scan electrodes SC1 to SCn, as in the initialization period Pia1 of the subfield SF1. It occurs before the discharge between the data electrodes D1 to Dm. Therefore, this erasing discharge is generated stably.
こうして、パネル10の画像表示領域内にある全ての放電セルにおいて、走査電極SC1~SCn上に負極性の壁電圧が蓄積され、データ電極D1~Dm上および維持電極SU1~SUn上に正極性の壁電圧が蓄積される。
Thus, in all the discharge cells in the image display area of panel 10, negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive polarity is applied to data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Wall voltage is accumulated.
第2のランプ波形電圧が電圧Vi2に到達したら、走査電極SC1~SCnに印加する電圧を、電圧Vi2よりも低い電圧Vi3まで一旦下げ、その後、電圧0(V)にする。ただし、本発明は何らこの構成に限定されるものではなく、例えば、電圧Vi2から電圧0(V)まで急峻に電圧を下げてもよい。
When the second ramp waveform voltage reaches the voltage Vi2, the voltage applied to the scan electrodes SC1 to SCn is once lowered to the voltage Vi3 lower than the voltage Vi2, and then set to the voltage 0 (V). However, the present invention is not limited to this configuration. For example, the voltage may be sharply decreased from voltage Vi2 to voltage 0 (V).
次に、データ電極D1~Dmに電圧0(V)を印加し、維持電極SU1~SUnに電圧Veよりも高い電圧Vsを印加する。そして、走査電極SC1~SCnに、放電開始電圧未満となる電圧(例えば、電圧0(V))から負の電圧Vi4まで下降する下り傾斜波形電圧を印加する。以下、この下り傾斜波形電圧を「第3のランプ波形電圧」と記す。
Next, a voltage 0 (V) is applied to the data electrodes D1 to Dm, and a voltage Vs higher than the voltage Ve is applied to the sustain electrodes SU1 to SUn. Then, a downward ramp waveform voltage that drops from a voltage (for example, voltage 0 (V)) that is lower than the discharge start voltage to a negative voltage Vi4 is applied to scan electrodes SC1 to SCn. Hereinafter, this downward ramp waveform voltage is referred to as a “third ramp waveform voltage”.
この第3のランプ波形電圧を走査電極SC1~SCnに印加する間に、走査電極SC1~SCnと維持電極SU1~SUnとの間、および走査電極SC1~SCnとデータ電極D1~Dmとの間に、それぞれ微弱な消去放電が発生する。
While this third ramp waveform voltage is applied to scan electrodes SC1 to SCn, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm. In this case, a weak erasing discharge is generated.
これにより、走査電極SC1~SCn上の壁電圧および維持電極SU1~SUn上の壁電圧が弱められ、データ電極D1~Dm上に蓄積された正極性の壁電圧も弱められる。
Thereby, the wall voltage on scan electrodes SC1 to SCn and the wall voltage on sustain electrodes SU1 to SUn are weakened, and the positive wall voltage accumulated on data electrodes D1 to Dm is also weakened.
こうして、パネル10の画像表示領域内にある全ての放電セルの壁電圧が、続く画像表示サブフィールドのサブフィールドSF1における初期化動作に適した壁電圧に調整される。さらに、続く初期化放電の発生を補助するプライミング粒子が放電セル内に発生する。
Thus, the wall voltage of all the discharge cells in the image display area of panel 10 is adjusted to the wall voltage suitable for the initialization operation in subfield SF1 of the subsequent image display subfield. Furthermore, priming particles that assist the generation of the subsequent initializing discharge are generated in the discharge cell.
第3のランプ波形電圧が電圧Vi4に到達したら、走査電極SC1~SCnに印加する電圧を電圧Vcにする。また、維持電極SU1~SUnに印加する電圧を電圧Vsから電圧Veにする。そして、次のフィールドのサブフィールドSF1が開始するまで、この状態(休止状態)を維持する。図4には、この休止状態を休止期間BLKと示す。
When the third ramp waveform voltage reaches the voltage Vi4, the voltage applied to the scan electrodes SC1 to SCn is set to the voltage Vc. Further, the voltage applied to sustain electrodes SU1 to SUn is changed from voltage Vs to voltage Ve. Then, this state (pause state) is maintained until the subfield SF1 of the next field starts. FIG. 4 shows this dormant state as a dormant period BLK.
なお、本実施の形態におけるy座標検出サブフィールドSFyの消去期間Pebyおよびx座標検出サブフィールドSFxの消去期間Pedxにおいて、走査電極SC1~SCnに、電圧0(V)から、第1の電圧(電圧Vr)よりも高い第2の電圧(電圧Vi2)まで上昇する第2のランプ波形電圧を印加するのは以下の理由による。
Note that, in the erase period Peby of the y-coordinate detection subfield SFy and the erase period Pedx of the x-coordinate detection subfield SFx in the present embodiment, the scan electrodes SC1 to SCn are supplied with the first voltage (voltage) from the voltage 0 (V). The second ramp waveform voltage rising to the second voltage (voltage Vi2) higher than Vr) is applied for the following reason.
画像表示サブフィールドであるサブフィールドSF1~SF8の維持期間Ps1~Ps8では、相対的に強い放電である維持放電が終了した後に消去動作を行う。同様に、タイミング検出サブフィールドSFoのタイミング検出期間Poにおいても、維持放電と同様に相対的に強い放電であるタイミング検出放電が終了した後に消去動作を行う。したがって、これらのサブフィールドでは、電圧0(V)から第1の電圧(電圧Vr)まで上昇する第1の消去ランプであっても十分に消去放電が発生するだけの壁電荷が、消去動作の直前に放電セル内に蓄積されている。
In the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8 that are image display subfields, the erase operation is performed after the sustain discharge, which is a relatively strong discharge, is completed. Similarly, in the timing detection period Po of the timing detection subfield SFo, similarly to the sustain discharge, the erase operation is performed after the timing detection discharge, which is a relatively strong discharge, is completed. Therefore, in these subfields, the wall charge sufficient to generate an erasing discharge is sufficient for the erasing operation even in the first erasing lamp that rises from the voltage 0 (V) to the first voltage (voltage Vr). Accumulated in the discharge cell immediately before.
一方、y座標検出サブフィールドSFyおよびx座標検出サブフィールドSFxでは、維持放電と比較して弱い放電であるy座標検出のための放電およびx座標検出のための放電が終了した後に消去動作を行う。
On the other hand, in the y-coordinate detection subfield SFy and the x-coordinate detection subfield SFx, the erase operation is performed after the discharge for y-coordinate detection and the discharge for x-coordinate detection, which are weaker discharges than the sustain discharge, are completed. .
そのため、これらの消去動作の直前に放電セル内に蓄積される壁電荷は、維持動作が終了した後に放電セル内に蓄積される壁電荷と比較して少なく、第1の電圧(電圧Vr)までしか上昇しない第1の消去ランプでは、消去放電が安定に発生しない可能性がある。
Therefore, the wall charges stored in the discharge cells immediately before these erasing operations are less than the wall charges stored in the discharge cells after the sustain operation is completed, and the first charge (voltage Vr) is reached. In the first erase lamp that only rises, there is a possibility that the erase discharge does not occur stably.
そこで、本実施の形態では、安定に消去放電を発生させるために、y座標検出サブフィールドSFyの消去期間Pebyおよびx座標検出サブフィールドSFxの消去期間Pedxにおいて、第1の電圧(電圧Vr)よりも高い第2の電圧(電圧Vi2)まで上昇する第2のランプ波形電圧を用いて消去動作を行う。
Therefore, in the present embodiment, in order to generate an erasing discharge stably, in the erasing period Peby of the y-coordinate detection subfield SFy and the erasing period Pedx of the x-coordinate detection subfield SFx, the first voltage (voltage Vr) is used. The erase operation is performed using the second ramp waveform voltage that rises to a higher second voltage (voltage Vi2).
なお、本実施の形態におけるx座標検出サブフィールドSFxの消去期間Pedxにおいて、走査電極SC1~SCnに、第2のランプ波形電圧に続いて電圧0(V)から負の電圧Vi4まで下降する第3のランプ波形電圧を印加するのは以下の理由による。
In the erasing period Pedx of the x-coordinate detection subfield SFx in the present embodiment, the third voltage that drops from the voltage 0 (V) to the negative voltage Vi4 is applied to the scan electrodes SC1 to SCn following the second ramp waveform voltage. The ramp waveform voltage is applied for the following reason.
x座標検出サブフィールドSFxが終了してから次のフィールドのサブフィールドSF1が開始するまでの休止期間BLKは、放電が発生しない休止状態が維持された期間である。例えば、画像信号に応じて輝度倍数が変化する構成では、画像信号に応じて維持パルスの発生数が変わるため休止期間BLKの長さも変化する。
The rest period BLK from the end of the x coordinate detection subfield SFx to the start of the subfield SF1 of the next field is a period in which a rest state in which no discharge occurs is maintained. For example, in a configuration in which the luminance multiple is changed according to the image signal, the length of the pause period BLK is also changed because the number of sustain pulses generated is changed according to the image signal.
この休止期間BLKでは、放電が発生しないので、時間の経過と共にプライミング粒子が減少し、放電セル内の壁電荷の状態も変化する。したがって、この休止期間BLKが長くなると、次のフィールドの最初に発生する放電が不安定になる可能性がある。
In this rest period BLK, since no discharge occurs, the priming particles decrease with the passage of time, and the state of the wall charge in the discharge cell also changes. Therefore, if the pause period BLK is long, the discharge generated at the beginning of the next field may become unstable.
そこで、本実施の形態では、プライミング粒子をさらに発生させるとともに、放電セル内の壁電荷をさらに弱めて壁電荷の状態変化を抑制するために、x座標検出サブフィールドSFxの消去期間Pedxにおいて、第2のランプ波形電圧によって消去放電を発生させた後に、電圧Vi4まで下降する第3のランプ波形電圧を走査電極SC1~SCnに印加し、消去放電をさらに発生させている。
Therefore, in this embodiment, in order to further generate priming particles and further weaken the wall charge in the discharge cell to suppress the change in the state of the wall charge, in the erasing period Pedx of the x coordinate detection subfield SFx, After the erase discharge is generated by the ramp waveform voltage of 2, the third ramp waveform voltage that drops to the voltage Vi4 is applied to the scan electrodes SC1 to SCn to further generate the erase discharge.
これにより、次のフィールドのサブフィールドSF1の開始直前において、放電セル内に十分なプライミング粒子を残留させ、放電セル内の壁電荷の状態をより安定に保つことができる。したがって、サブフィールドSF1の初期化放電をより安定に発生させることが可能となる。
Thereby, immediately before the start of the subfield SF1 of the next field, sufficient priming particles remain in the discharge cell, and the wall charge state in the discharge cell can be kept more stable. Therefore, it is possible to generate the initialization discharge of subfield SF1 more stably.
なお、相対的に強い放電が発生した後の消去動作を第2のランプ波形電圧によって行うと、消去動作が過剰になり望ましくない。そのため、本実施の形態では、維持期間Ps1~Ps8の最後およびタイミング検出期間Poの最後では、第1のランプ波形電圧によって消去動作を行う。
Note that if the erase operation after the relatively strong discharge is generated by the second ramp waveform voltage, the erase operation becomes excessive, which is not desirable. Therefore, in the present embodiment, the erasing operation is performed with the first ramp waveform voltage at the end of the sustain periods Ps1 to Ps8 and at the end of the timing detection period Po.
以上が、タイミング検出サブフィールドSFo、y座標検出サブフィールドSFyおよびx座標検出サブフィールドSFxの駆動電圧波形の概要である。
The above is the outline of the drive voltage waveforms of the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx.
なお、図4には、y座標検出サブフィールドSFyの後にx座標検出サブフィールドSFxを発生する例を示したが、例えば、x座標検出サブフィールドSFxの後にy座標検出サブフィールドSFyを発生してもよい。ただし、その構成では、図4に示したx座標検出サブフィールドSFxの消去期間Pedxに発生する駆動電圧波形をy座標検出サブフィールドSFyの消去期間Pebyで発生し、図4に示したy座標検出サブフィールドSFyの消去期間Pebyに発生する駆動電圧波形をx座標検出サブフィールドSFxの消去期間Pedxで発生するものとする。
FIG. 4 shows an example in which the x coordinate detection subfield SFx is generated after the y coordinate detection subfield SFy. For example, the y coordinate detection subfield SFy is generated after the x coordinate detection subfield SFx. Also good. However, in this configuration, the drive voltage waveform generated during the erasing period Pedx of the x-coordinate detection subfield SFx shown in FIG. 4 is generated during the erasing period Peby of the y-coordinate detection subfield SFy, and the y-coordinate detection shown in FIG. It is assumed that the drive voltage waveform generated in the erase period Peby of the subfield SFy is generated in the erase period Pedx of the x coordinate detection subfield SFx.
なお、本実施の形態において各電極に印加する電圧値は、例えば、電圧Vi1=150(V)、電圧Vi2=350(V)、電圧Vi3=200(V)、電圧Vi4=-175(V)、電圧Va=電圧Vay=電圧Vax=-200(V)、電圧Vc=-50(V)、電圧Vs=電圧Vso=205(V)、電圧Vr=205(V)、電圧Ve=155(V)、電圧Vd=電圧Vdy=電圧Vdx=55(V)である。
Note that the voltage values applied to the electrodes in this embodiment are, for example, the voltage Vi1 = 150 (V), the voltage Vi2 = 350 (V), the voltage Vi3 = 200 (V), and the voltage Vi4 = −175 (V). , Voltage Va = voltage Vay = voltage Vax = −200 (V), voltage Vc = −50 (V), voltage Vs = voltage Vso = 205 (V), voltage Vr = 205 (V), voltage Ve = 155 (V ), Voltage Vd = voltage Vdy = voltage Vdx = 55 (V).
なお、本実施の形態において、電圧Va、電圧Vay、および電圧Vaxは互いに等しい電圧に設定され、電圧Vd、電圧Vdy、および電圧Vdxは互いに等しい電圧に設定されているが、これらの電圧は互いに異なる電圧であってもよい。
In this embodiment, the voltage Va, the voltage Vay, and the voltage Vax are set to be equal to each other, and the voltage Vd, the voltage Vdy, and the voltage Vdx are set to be equal to each other. Different voltages may be used.
なお、本実施の形態では、サブフィールドSF1の初期化期間Pia1で発生する上り傾斜波形電圧の電圧Vi2と、タイミング検出サブフィールドSFoの初期化期間Picoで発生する上り傾斜波形電圧の電圧Vi2と、y座標検出サブフィールドSFyの消去期間Pebyおよびx座標検出サブフィールドSFxの消去期間Pedxで発生する第2のランプ波形電圧の電圧Vi2とを互いに等しい電圧としているが、各電圧Vi2は互いに異なる電圧に設定されていてもよい。
In the present embodiment, an upward ramp waveform voltage voltage Vi2 generated in the initialization period Pia1 of the subfield SF1, an upward ramp waveform voltage voltage Vi2 generated in the initialization period Pico of the timing detection subfield SFo, and The voltage Vi2 of the second ramp waveform voltage generated in the erase period Peby of the y-coordinate detection subfield SFy and the erase period Pedx of the x-coordinate detection subfield SFx is set to be equal to each other, but the voltages Vi2 are different from each other. It may be set.
また、サブフィールドSF1の初期化期間Pia1、タイミング検出サブフィールドSFoの初期化期間Pico、y座標検出サブフィールドSFyの消去期間Pebyおよびx座標検出サブフィールドSFxの消去期間Pedxに発生する上り傾斜波形電圧の勾配は約1.5(V/μsec)である。また、画像表示サブフィールド(サブフィールドSF1~SF8)の各初期化期間Pia1、Pib2~Pib8、タイミング検出サブフィールドSFoの初期化期間Pico、y座標検出サブフィールドSFyの初期化期間Piby、およびx座標検出サブフィールドSFxの初期化期間Pidxに発生する下り傾斜波形電圧の勾配は約-2.5(V/μsec)である。また、画像表示サブフィールド(サブフィールドSF1~SF8)の各維持期間Ps1~Ps8の最後およびタイミング検出サブフィールドSFoのタイミング検出期間Poの最後に発生する第1のランプ波形電圧の勾配は約10(V/μsec)である。
In addition, an upward ramp waveform voltage generated in the initialization period Pia1 of the subfield SF1, the initialization period Pico of the timing detection subfield SFo, the erase period Peby of the y coordinate detection subfield SFy, and the erase period Pedx of the x coordinate detection subfield SFx. The slope of is about 1.5 (V / μsec). Also, the initialization periods Pia1, Pib2 to Pib8 of the image display subfield (subfields SF1 to SF8), the initialization period Pico of the timing detection subfield SFo, the initialization period Piby of the y coordinate detection subfield SFy, and the x coordinate The gradient of the falling ramp waveform voltage generated in the initialization period Pidx of the detection subfield SFx is about −2.5 (V / μsec). The gradient of the first ramp waveform voltage generated at the end of each sustain period Ps1 to Ps8 of the image display subfield (subfields SF1 to SF8) and at the end of the timing detection period Po of the timing detection subfield SFo is about 10 ( V / μsec).
なお、本実施の形態において、上述した電圧値や勾配等の具体的な数値は単なる一例に過ぎず、本発明は、各電圧値や勾配等が上述した数値に限定されるものではない。各電圧値や勾配等は、パネルの放電特性やプラズマディスプレイ装置の仕様等にもとづき最適に設定することが望ましい。
In the present embodiment, the specific numerical values such as the voltage value and the gradient described above are merely examples, and the present invention is not limited to the numerical values described above for each voltage value and the gradient. Each voltage value, gradient, and the like are preferably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.
なお、本実施の形態において、1フィールドにタイミング検出サブフィールドSFoを設け、図4に示した波形形状でタイミング検出サブフィールドSFoの各駆動電圧波形を発生する理由は、以下の通りである。
In the present embodiment, the reason why the timing detection subfield SFo is provided in one field and each drive voltage waveform of the timing detection subfield SFo is generated with the waveform shape shown in FIG. 4 is as follows.
本実施の形態では、プラズマディスプレイ装置とライトペンとの間で無線通信を行う。そのため、本実施の形態では、ライトペン自らが座標基準信号(y座標検出期間Pyおよびx座標検出期間Pxの発生タイミングを示す信号)を発生できるようにするために、1フィールドにタイミング検出サブフィールドSFoを設ける。ライトペンは、タイミング検出サブフィールドSFoにおいて、タイミング検出放電によってパネル10に特定の時間間隔で発生する発光を検知し、座標基準信号を発生する。そして、この座標基準信号にもとづき、ライトペンは、ライトペンの位置座標を自ら算出する。
In this embodiment, wireless communication is performed between the plasma display device and the light pen. Therefore, in the present embodiment, the light pen itself can generate a coordinate reference signal (a signal indicating the generation timing of the y-coordinate detection period Py and the x-coordinate detection period Px), and the timing detection subfield in one field. SFo is provided. In the timing detection subfield SFo, the light pen detects light emission generated at a specific time interval on the panel 10 by timing detection discharge, and generates a coordinate reference signal. Based on this coordinate reference signal, the light pen calculates the position coordinates of the light pen itself.
また、本実施の形態では、ライトペンにおける座標基準信号の発生精度を高めるために、図4に示した波形形状でタイミング検出サブフィールドSFoの各駆動電圧波形を発生し、時間To0を、時間To1よりも長い時間に設定する。望ましくは、時間To0を、時間To1、時間To2、時間To3のいずれの時間よりも長い時間に設定する。これは、以下のような理由による。
Further, in this embodiment, in order to increase the accuracy of generating the coordinate reference signal in the light pen, each drive voltage waveform of the timing detection subfield SFo is generated with the waveform shape shown in FIG. 4, and the time To0 is set to the time To1. Set to a longer time. Desirably, the time To0 is set to a time longer than any of the time To1, the time To2, and the time To3. This is due to the following reasons.
ライトペンが有する受光素子は、書込み放電によって発生する発光も検出する。そのため、時間To0の設定値によっては、ライトペンが、タイミング検出サブフィールドSFoの書込み期間Pwoにおいて書込み放電によって発生する発光を、タイミング検出放電による発光と誤認識する可能性がある。
The light receiving element of the light pen also detects light emission generated by address discharge. Therefore, depending on the set value of time To0, the light pen may misrecognize the light emission generated by the address discharge in the address period Pwo of the timing detection subfield SFo as the light emission by the timing detection discharge.
しかし、時間To0が、時間To1よりも長い時間に設定されていれば、ライトペンが画像表示領域内のどの位置にあっても、ライトペンが書込み放電による発光を検出した時刻から時刻to1までの間隔は時間To1よりも長くなる。これにより、ライトペンが、タイミング検出サブフィールドSFoの書込み期間Pwoにおいて発生する書込み放電による発光を、タイミング検出放電による発光と誤認識することを防止することができる。そして、時間To0が、時間To1、時間To2、時間To3のいずれの時間よりも長い時間に設定されていれば、より高精度に、その誤認識を防止することができ、画像表示領域内におけるライトペンの位置(位置座標)をより正確に検出することが可能となる。
However, if the time To0 is set to a time longer than the time To1, no matter where the light pen is in the image display area, the time from the time when the light pen detects light emission due to the write discharge to the time to1 The interval is longer than time To1. Thereby, it is possible to prevent the light pen from erroneously recognizing light emission due to the address discharge generated in the address period Pwo of the timing detection subfield SFo as light emission due to the timing detection discharge. If the time To0 is set to a time longer than any of the time To1, the time To2, and the time To3, the erroneous recognition can be prevented with higher accuracy, and the write in the image display area can be prevented. It becomes possible to detect the position (position coordinates) of the pen more accurately.
以上のように、本実施の形態における画像表示装置では、上述した動作により、パネル10に画像信号に応じた画像を表示しつつ、画像表示領域内におけるライトペンの位置(位置座標)を検出するための放電を安定に発生し、ライトペンの位置座標を高精度に算出することができる。
As described above, the image display device according to the present embodiment detects the position (positional coordinates) of the light pen in the image display area while displaying an image corresponding to the image signal on the panel 10 by the above-described operation. Discharge can be generated stably, and the position coordinates of the light pen can be calculated with high accuracy.
次に、本実施の形態における画像表示システムの構成について説明する。なお、以下では、画像表示装置としてプラズマディスプレイ装置を用いたプラズマディスプレイシステムを本実施の形態における画像表示システムの一例として挙げ、その構成について説明する。
Next, the configuration of the image display system in the present embodiment will be described. In the following, a plasma display system using a plasma display device as an image display device will be described as an example of the image display system in this embodiment, and the configuration thereof will be described.
図5は、本発明の実施の形態におけるプラズマディスプレイ装置100を構成する回路ブロックおよびプラズマディスプレイシステム30の一例を概略的に示す図である。
FIG. 5 is a diagram schematically showing an example of a circuit block and a plasma display system 30 constituting the plasma display device 100 according to the embodiment of the present invention.
本実施の形態に示すプラズマディスプレイシステム30は、プラズマディスプレイ装置100とライトペン50とを構成要素に含む。
The plasma display system 30 shown in the present embodiment includes a plasma display device 100 and a light pen 50 as components.
プラズマディスプレイ装置100は、パネル10と、1フィールドに複数のサブフィールドを備えてパネル10を駆動する駆動回路を備えている。駆動回路は、画像信号処理回路31、データ電極駆動回路32、走査電極駆動回路33、維持電極駆動回路34、タイミング発生回路35、描画回路44、受信回路46、および各回路ブロックに必要な電源を供給する電源回路(図示せず)を備えている。
The plasma display device 100 includes a panel 10 and a driving circuit that drives the panel 10 with a plurality of subfields in one field. The drive circuit supplies power necessary for the image signal processing circuit 31, the data electrode drive circuit 32, the scan electrode drive circuit 33, the sustain electrode drive circuit 34, the timing generation circuit 35, the drawing circuit 44, the reception circuit 46, and each circuit block. A power supply circuit (not shown) for supplying is provided.
画像信号処理回路31には、画像信号、描画回路44から出力される描画信号、およびタイミング発生回路35から供給されるタイミング信号が入力される。画像信号処理回路31は、画像信号と描画信号とを合成した画像をパネル10に表示するために、画像信号と描画信号とを合成し、その合成後の信号にもとづき各放電セルに赤、緑、青の各階調値(1フィールドで表現される階調値)を設定する。そして、画像信号処理回路31は、各放電セルに設定した赤、緑、青の階調値を、サブフィールド毎の点灯・非点灯を示す画像データ(発光・非発光をデジタル信号の「1」、「0」に対応させたデータのこと)に変換し、その画像データ(赤の画像データ、緑の画像データ、および青の画像データ)を出力する。
The image signal processing circuit 31 receives an image signal, a drawing signal output from the drawing circuit 44, and a timing signal supplied from the timing generation circuit 35. The image signal processing circuit 31 combines the image signal and the drawing signal in order to display an image obtained by combining the image signal and the drawing signal on the panel 10, and applies red, green to each discharge cell based on the combined signal. , Blue gradation values (gradation values expressed by one field) are set. Then, the image signal processing circuit 31 uses the red, green, and blue gradation values set for each discharge cell as image data indicating lighting / non-lighting for each subfield (light emission / non-light emission is “1” of the digital signal). , Data corresponding to “0”), and output the image data (red image data, green image data, and blue image data).
タイミング発生回路35は、水平同期信号および垂直同期信号にもとづき、各回路ブロックの動作を制御する各種のタイミング信号を発生する。そして、発生したタイミング信号をそれぞれの回路ブロック(データ電極駆動回路32、走査電極駆動回路33、維持電極駆動回路34、および画像信号処理回路31等)へ供給する。
The timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal. The generated timing signal is supplied to each circuit block (data electrode drive circuit 32, scan electrode drive circuit 33, sustain electrode drive circuit 34, image signal processing circuit 31, etc.).
データ電極駆動回路32は、画像信号処理回路31から出力される画像データとタイミング発生回路35から供給されるタイミング信号とにもとづき、画像表示サブフィールドであるサブフィールドSF1~SF8の各書込み期間Pw1~Pw8およびタイミング検出サブフィールドSFoの書込み期間Pwoでは電圧Vdの書込みパルスを、y座標検出サブフィールドSFyのy座標検出期間Pyではy座標検出電圧Vdyを、x座標検出サブフィールドSFxのx座標検出期間Pxでは電圧Vdxのx座標検出パルスを、各データ電極D1~Dmに印加する。
Based on the image data output from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35, the data electrode driving circuit 32 performs the writing periods Pw1 to Pw1 of the subfields SF1 to SF8 which are image display subfields. In the writing period Pwo of Pw8 and the timing detection subfield SFo, the writing pulse of the voltage Vd is used, in the y coordinate detection period Py of the y coordinate detection subfield SFy, the y coordinate detection voltage Vdy is used, and in the x coordinate detection subfield SFx, the x coordinate detection period. In Px, an x-coordinate detection pulse of voltage Vdx is applied to each data electrode D1 to Dm.
維持電極駆動回路34は、維持パルス発生回路、電圧Veを発生する回路(図5には示さず)を備え、タイミング発生回路35から供給されるタイミング信号にもとづいて各駆動電圧波形を作成し、維持電極SU1~SUnのそれぞれに印加する。画像表示サブフィールドであるサブフィールドSF1~SF8の各維持期間Ps1~Ps8では電圧Vsの維持パルスを、タイミング検出サブフィールドSFoのタイミング検出期間Poでは電圧Vso(本実施の形態では、電圧Vsに等しい)のタイミング検出パルスV2、V4を、x座標検出サブフィールドSFxの消去期間Pedxでは電圧Vsを、画像表示サブフィールドであるサブフィールドSF1~SF8の各初期化期間Pia1、Pib2~Pib8と各書込み期間Pw1~Pw8、タイミング検出サブフィールドSFoの初期化期間Picoと書込み期間Pwo、y座標検出サブフィールドSFyの初期化期間Pibyとy座標検出期間Py、およびx座標検出サブフィールドSFxの初期化期間Pidxとx座標検出期間Pxでは電圧Veを、維持電極SU1~SUnに印加する。
Sustain electrode drive circuit 34 includes a sustain pulse generation circuit and a circuit (not shown in FIG. 5) for generating voltage Ve, and generates each drive voltage waveform based on the timing signal supplied from timing generation circuit 35. The voltage is applied to each of the sustain electrodes SU1 to SUn. In the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8, which are image display subfields, the sustain pulse of the voltage Vs is used. In the timing detection period Po of the timing detection subfield SFo, the voltage Vso (equal to the voltage Vs in the present embodiment). ) Of the timing detection pulses V2 and V4, the voltage Vs in the erasing period Pedx of the x-coordinate detection subfield SFx, the initialization periods Pia1, Pib2 to Pib8 and the writing periods of the subfields SF1 to SF8 which are image display subfields. Pw1 to Pw8, timing detection subfield SFo initialization period Pico and writing period Pwo, y coordinate detection subfield SFy initialization period Piby and y coordinate detection period Py, and x coordinate detection subfield SFx initialization period Pidx x coordinate detection period A voltage Ve at x, it is applied to sustain electrodes SU1 ~ SUn.
走査電極駆動回路33は、傾斜波形電圧発生回路、維持パルス発生回路、走査パルス発生回路(図5には示さず)を備え、タイミング発生回路35から供給されるタイミング信号にもとづいて各駆動電圧波形を作成し、走査電極SC1~SCnのそれぞれに印加する。傾斜波形電圧発生回路は、タイミング信号にもとづき、画像表示サブフィールドであるサブフィールドSF1~SF8の各初期化期間Pia1、Pib2~Pib8と各維持期間Pw1~Pw8、タイミング検出サブフィールドSFoの初期化期間Picoとタイミング検出期間Po、y座標検出サブフィールドSFyの初期化期間Pibyと消去期間Peby、およびx座標検出サブフィールドSFxの初期化期間Pidxと消去期間Pedxにおいて、傾斜波形電圧を走査電極SC1~SCnに印加する。維持パルス発生回路は、タイミング信号にもとづき、画像表示サブフィールドであるサブフィールドSF1~SF8の各維持期間Ps1~Ps8では維持パルスを、タイミング検出サブフィールドSFoのタイミング検出期間Poでは電圧Vso(本実施の形態では、電圧Vsに等しい)のタイミング検出パルスV1、V3を、走査電極SC1~SCnに印加する。走査パルス発生回路は、複数の走査電極駆動IC(走査IC)を備え、タイミング信号にもとづき、画像表示サブフィールドであるサブフィールドSF1~SF8の各書込み期間Pw1~Pw8、およびタイミング検出サブフィールドSFoの書込み期間Pwoでは電圧Vcと電圧Vaの走査パルスを、y座標検出サブフィールドSFyのy座標検出期間Pyでは電圧Vcと電圧Vayのy座標検出パルスを、x座標検出サブフィールドSFxのx座標検出期間Pxでは電圧Vcとx座標検出電圧Vaxを、走査電極SC1~SCnに印加する。
Scan electrode drive circuit 33 includes a ramp waveform voltage generation circuit, a sustain pulse generation circuit, and a scan pulse generation circuit (not shown in FIG. 5), and each drive voltage waveform is based on a timing signal supplied from timing generation circuit 35. Is applied to each of scan electrodes SC1 to SCn. The ramp waveform voltage generating circuit, based on the timing signal, initializes the initialization periods Pia1, Pib2 to Pib8 and the sustain periods Pw1 to Pw8 of the subfields SF1 to SF8, which are image display subfields, and the initialization period of the timing detection subfield SFo. In Pico, the timing detection period Po, the initialization period Piby and the erasure period Peby of the y coordinate detection subfield SFy, and the initialization period Pidx and the erasure period Pedx of the x coordinate detection subfield SFx, the ramp waveform voltage is applied to the scan electrodes SC1 to SCn. Apply to. Based on the timing signal, the sustain pulse generating circuit generates sustain pulses in the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8 that are image display subfields, and the voltage Vso (this implementation) in the timing detection period Po of the timing detection subfield SFo. In this embodiment, timing detection pulses V1 and V3 equal to the voltage Vs) are applied to the scan electrodes SC1 to SCn. The scan pulse generation circuit includes a plurality of scan electrode driving ICs (scan ICs), and based on the timing signal, the writing periods Pw1 to Pw8 of the subfields SF1 to SF8 that are image display subfields and the timing detection subfield Sfo In the writing period Pwo, scanning pulses of the voltage Vc and the voltage Va are used, in the y coordinate detection period Py of the y coordinate detection subfield SFy, the y coordinate detection pulse of the voltage Vc and voltage Vay is used, and the x coordinate detection period of the x coordinate detection subfield SFx. In Px, voltage Vc and x-coordinate detection voltage Vax are applied to scan electrodes SC1 to SCn.
ライトペン50は、使用者がパネル10の画像表示領域に文字や図画等を手書き入力するときに使用される。ライトペン50は、棒状に形成されており、受光素子52、タイミング検出回路54、座標算出回路56、および送信回路58を備えている。
The light pen 50 is used when the user inputs characters, drawings and the like in the image display area of the panel 10 by handwriting. The light pen 50 is formed in a rod shape and includes a light receiving element 52, a timing detection circuit 54, a coordinate calculation circuit 56, and a transmission circuit 58.
また、図5には示していないが、ライトペン50は、接触スイッチを有する。接触スイッチは、ライトペン50の先端部に設けられ、ライトペン50がパネル10の前面基板11(パネル10の画像表示面)に接触したときに、その接触を検知する。
Although not shown in FIG. 5, the light pen 50 has a contact switch. The contact switch is provided at the tip of the light pen 50 and detects the contact when the light pen 50 contacts the front substrate 11 of the panel 10 (the image display surface of the panel 10).
受光素子52は、パネル10の画像表示面に生じる発光を受光して電気信号(受光信号)に変換する。そして、その受光信号を、タイミング検出回路54および座標算出回路56に出力する。なお、本実施の形態において、ライトペン50の位置座標(x、y)とは、受光素子52が画像表示面に生じる発光を受光する位置のことである。
The light receiving element 52 receives light emitted from the image display surface of the panel 10 and converts it into an electric signal (light receiving signal). Then, the light reception signal is output to the timing detection circuit 54 and the coordinate calculation circuit 56. In the present embodiment, the position coordinates (x, y) of the light pen 50 are positions where the light receiving element 52 receives light emitted from the image display surface.
タイミング検出回路54、座標算出回路56、および送信回路58は、接触スイッチが接触を検知している期間(接触スイッチを設けない非接触型のライトペンでは、例えば手動スイッチがオンされている期間)、以下の動作をする。
The timing detection circuit 54, the coordinate calculation circuit 56, and the transmission circuit 58 have a period during which the contact switch detects contact (for example, a period during which the manual switch is turned on in a non-contact type light pen without a contact switch). The following operations are performed.
タイミング検出回路54は、受光信号にもとづき、タイミング検出サブフィールドSFoのタイミング検出期間Poに発生するタイミング検出用の発光(タイミング検出放電によって生じる発光)を検出する。具体的には、タイミング検出回路54は、タイミング検出回路54が有するタイマー(図5には示さず)を用いて、複数(例えば、5回)の発光の時間間隔を計測する。そして、その時間間隔があらかじめ定められた所定の時間間隔(例えば、時間To0、時間To1、時間To2、時間To3)に合致するかどうかを、タイミング検出回路54に設定された複数のしきい値(例えば、時間To0、時間To1、時間To2、時間To3に相当するしきい値)と計測された時間間隔とを比較することで判定する。
The timing detection circuit 54 detects light emission for timing detection (light emission generated by the timing detection discharge) generated in the timing detection period Po of the timing detection subfield SFo based on the light reception signal. Specifically, the timing detection circuit 54 measures a time interval of a plurality of (for example, five times) emission using a timer (not shown in FIG. 5) included in the timing detection circuit 54. Then, whether or not the time interval matches a predetermined time interval (for example, time To0, time To1, time To2, time To3) is determined by a plurality of threshold values (set in the timing detection circuit 54). For example, the determination is made by comparing the measured time interval with a threshold value corresponding to time To0, time To1, time To2, and time To3.
そして、タイミング検出回路54は、その連続する複数回(例えば、5回)の発光のうちの1つを基準にして座標基準信号を作成する。例えば、図4に示す例では、タイミング検出サブフィールドSFoのタイミング検出期間Poの時刻to1に発生した発光を基準にして座標基準信号を作成する。
Then, the timing detection circuit 54 generates a coordinate reference signal based on one of the continuous plural times (for example, five times) of light emission. For example, in the example illustrated in FIG. 4, the coordinate reference signal is generated based on the light emission generated at the time to1 in the timing detection period Po of the timing detection subfield SFo.
なお、時刻to1は、タイミング検出サブフィールドSFoのタイミング検出期間Poにおいて走査電極SC1~SCnに1回目のタイミング検出パルスV1を印加する時刻である。
The time to1 is the time when the first timing detection pulse V1 is applied to the scan electrodes SC1 to SCn in the timing detection period Po of the timing detection subfield SFo.
また、座標基準信号は、図4には示していないが、例えば、時刻ty0と時刻tx0とのそれぞれに立上りエッジがある信号のことである。時刻ty0は、y座標検出サブフィールドSFyのy座標検出期間Pyにおいて1行目の走査電極SC1にy座標検出パルスを印加する時刻である。また、時刻tx0は、x座標検出サブフィールドSFxのx座標検出期間Pxにおいて1列目の画素列に対応するデータ電極D1~D3にx座標検出パルスを印加する時刻である。
The coordinate reference signal is not shown in FIG. 4, but is, for example, a signal having rising edges at time ty0 and time tx0. Time ty0 is a time at which a y-coordinate detection pulse is applied to scan electrode SC1 in the first row in y-coordinate detection period Py of y-coordinate detection subfield SFy. Time tx0 is a time at which an x-coordinate detection pulse is applied to the data electrodes D1 to D3 corresponding to the first pixel column in the x-coordinate detection period Px of the x-coordinate detection subfield SFx.
したがって、時刻to1がわかれば、時刻ty0と時刻tx0とのそれぞれに立上りエッジがある座標基準信号を発生することができる。
Therefore, if the time to1 is known, a coordinate reference signal having rising edges at each of the time ty0 and the time tx0 can be generated.
そして、タイミング検出回路54は、その座標基準信号を座標算出回路56に出力する。
Then, the timing detection circuit 54 outputs the coordinate reference signal to the coordinate calculation circuit 56.
なお、本実施の形態では、時刻to1を基準にして座標基準信号を発生する例を説明しているが、本発明は何らこの構成に限定されるものではない。座標基準信号は、2回目のタイミング検出パルスV2を発生する時刻to2を基準にして発生してもよく、あるいは、3回目のタイミング検出パルスV3を発生する時刻to3や4回目のタイミング検出パルスV4を発生する時刻to4等を基準にして発生してもよい。
In this embodiment, an example in which a coordinate reference signal is generated with reference to time to1 has been described, but the present invention is not limited to this configuration. The coordinate reference signal may be generated on the basis of the time to2 at which the second timing detection pulse V2 is generated, or the time to3 at which the third timing detection pulse V3 is generated or the fourth timing detection pulse V4. You may generate | occur | produce on the basis of the time to4 etc. which generate | occur | produce.
また、座標基準信号も、何ら時刻ty0と時刻tx0とのそれぞれに立上りエッジがある信号に限定されるものではない。座標基準信号は、y座標検出パターンによる発光およびx座標検出パターンによる発光を受光素子52が受光したときに、その時刻を特定するための基準にすることができる信号であればよい。
Also, the coordinate reference signal is not limited to a signal having rising edges at time ty0 and time tx0. The coordinate reference signal may be any signal that can be used as a reference for specifying the time when the light receiving element 52 receives light emission by the y coordinate detection pattern and light emission by the x coordinate detection pattern.
座標算出回路56は、時間の長さを計測するカウンタと、カウンタの出力に演算を施す演算回路とを備える(図5には示さず)。
The coordinate calculation circuit 56 includes a counter that measures the length of time and an arithmetic circuit that performs an operation on the output of the counter (not shown in FIG. 5).
そして、座標算出回路56は、座標基準信号および受光信号にもとづき、y座標検出パターンの発光を示す信号およびx座標検出パターンの発光を示す信号を受光信号から選択的に取り出し、画像表示領域におけるライトペン50の位置(x座標、y座標)を算出する。
Then, based on the coordinate reference signal and the light reception signal, the coordinate calculation circuit 56 selectively extracts a signal indicating the light emission of the y coordinate detection pattern and a signal indicating the light emission of the x coordinate detection pattern from the light reception signal, and writes the light in the image display area. The position (x coordinate, y coordinate) of the pen 50 is calculated.
具体的には、座標算出回路56は、座標基準信号にもとづき、時刻ty0から、時刻ty0以降に最初に受光素子52で発光が受光される時刻(時刻tyy)までの時間(時間Tyy)をカウンタで測定する。そして、演算回路において時間Tyyを時間Ty1(y座標検出パルスのパルス幅)で除算する。こうして画像表示領域におけるライトペン50の位置のy座標を算出する。
Specifically, the coordinate calculation circuit 56 counts the time (time Tyy) from time ty0 to the time (time tyy) from which light is first received by the light receiving element 52 after time ty0 based on the coordinate reference signal. Measure with Then, the time Tyy is divided by the time Ty1 (pulse width of the y coordinate detection pulse) in the arithmetic circuit. In this way, the y coordinate of the position of the light pen 50 in the image display area is calculated.
次に、座標算出回路56は、座標基準信号にもとづき、時刻tx0から、時刻tx0以降に最初に受光素子52で発光が受光される時刻(時刻txx)までの時間(時間Txx)をカウンタで測定する。そして、演算回路において時間Txxを時間Tx1(x座標検出パルスのパルス幅)で除算する。こうして画像表示領域におけるライトペン50の位置のx座標を算出する。
Next, the coordinate calculation circuit 56 measures, based on the coordinate reference signal, a time (time Txx) from time tx0 to time (time txx) when light is first received by the light receiving element 52 after time tx0. To do. Then, the time Txx is divided by the time Tx1 (pulse width of the x coordinate detection pulse) in the arithmetic circuit. In this way, the x coordinate of the position of the light pen 50 in the image display area is calculated.
なお、時刻tyyは、ライトペン50の受光素子52がy座標検出パターンによりパネル10に生じる発光を受光した時刻であり、時刻txxは、ライトペン50の受光素子52がx座標検出パターンによりパネル10に生じる発光を受光した時刻である。
The time tyy is the time when the light receiving element 52 of the light pen 50 receives light emitted from the panel 10 by the y coordinate detection pattern, and the time txx is the time when the light receiving element 52 of the light pen 50 receives the panel 10 by the x coordinate detection pattern. It is the time when the light emission generated in
座標算出回路56は、このようにして算出したライトペン50の位置座標(x、y)を送信回路58に出力する。
The coordinate calculation circuit 56 outputs the position coordinates (x, y) of the light pen 50 calculated in this way to the transmission circuit 58.
送信回路58は、電気信号をエンコードし、エンコード後の信号を例えば赤外線等の無線信号に変換して発信する発信回路を有する(図5には示さず)。そして、座標算出回路56が算出したライトペン50の位置(座標(x、y))を表す信号をエンコードした後に無線信号に変換し、プラズマディスプレイ装置100の受信回路46に無線送信する。
The transmission circuit 58 has a transmission circuit that encodes an electric signal and converts the encoded signal into a radio signal such as infrared rays and transmits the signal (not shown in FIG. 5). Then, a signal representing the position (coordinates (x, y)) of the light pen 50 calculated by the coordinate calculation circuit 56 is encoded, converted into a wireless signal, and wirelessly transmitted to the reception circuit 46 of the plasma display device 100.
なお、ライトペン50は、接触スイッチが接触を検知していない期間(接触スイッチを設けない非接触型のライトペンでは、例えば手動スイッチがオフされている期間)も上述の動作をするように構成されてもよい。
The light pen 50 is configured to perform the above-described operation even during a period in which the contact switch does not detect contact (in a non-contact type light pen without a contact switch, for example, a period in which the manual switch is turned off). May be.
受信回路46は、ライトペン50の送信回路58から無線送信される無線信号を受信し、その受信信号をデコードして電気信号に変換する変換回路を有する(図5には示さず)。そして、送信回路58から無線送信される無線信号をライトペン50の位置(x座標、y座標)を表す信号に変換して描画回路44に出力する。
The reception circuit 46 includes a conversion circuit that receives a wireless signal wirelessly transmitted from the transmission circuit 58 of the light pen 50, decodes the received signal, and converts it into an electrical signal (not shown in FIG. 5). The wireless signal wirelessly transmitted from the transmission circuit 58 is converted into a signal representing the position (x coordinate, y coordinate) of the light pen 50 and output to the drawing circuit 44.
描画回路44は、画像メモリ47を備える(図5にはメモリと記す)。描画回路44は、受信回路46で受信された信号(座標算出回路56が算出したx座標、y座標)にもとづき、パネル10の画像表示領域にライトペン50の軌跡を示すための描画信号を作成する。なお、この描画信号は、使用者が手書き入力した画像等をパネル10に表示するための信号であり、画像信号と実質的に同じものである。描画信号は、画像メモリ47に蓄積される。これにより、ライトペン50の過去の軌跡に現在のライトペン50の位置座標が加えられた描画信号が画像メモリ47に蓄積される。そして、描画回路44は、画像メモリ47に蓄積された描画信号を画像信号処理回路31に出力する。
The drawing circuit 44 includes an image memory 47 (referred to as memory in FIG. 5). The drawing circuit 44 generates a drawing signal for indicating the locus of the light pen 50 in the image display area of the panel 10 based on the signal received by the receiving circuit 46 (x coordinate and y coordinate calculated by the coordinate calculation circuit 56). To do. The drawing signal is a signal for displaying on the panel 10 an image or the like handwritten by the user, and is substantially the same as the image signal. The drawing signal is stored in the image memory 47. As a result, a drawing signal obtained by adding the current position coordinates of the light pen 50 to the past locus of the light pen 50 is accumulated in the image memory 47. The drawing circuit 44 outputs the drawing signal accumulated in the image memory 47 to the image signal processing circuit 31.
画像信号処理回路31は、上述したように、描画回路44から出力される描画信号と画像信号とを合成して画像データに変換し、後段の回路に出力する。こうして、ライトペン50によって手書き入力された図画が、画像信号による画像に合成されて、パネル10に表示される。
As described above, the image signal processing circuit 31 synthesizes the drawing signal output from the drawing circuit 44 and the image signal, converts the image signal into image data, and outputs the image data to a subsequent circuit. In this way, the graphic input handwritten by the light pen 50 is combined with the image based on the image signal and displayed on the panel 10.
なお、パネル10に示されたライトペン50の軌跡を消すために、ライトペン50に、「描画」モードと「消去」モードとを切り換えるスイッチを設けてもよい。そして、ライトペン50が「消去」モードのときには、パネル10に示されたライトペン50の軌跡を再度ライトペン50でなぞることで、画像メモリ47に蓄積された描画信号を部分的、または全体的に消去する。例えば、ライトペンをこのように構成してもよい。
In addition, in order to erase the locus of the light pen 50 shown on the panel 10, the light pen 50 may be provided with a switch for switching between the “drawing” mode and the “erasing” mode. When the light pen 50 is in the “erase” mode, the trace of the light pen 50 shown on the panel 10 is traced with the light pen 50 again, so that the drawing signal stored in the image memory 47 can be partially or totally. To erase. For example, the light pen may be configured in this way.
なお、ライトペン50は、ライトペン50の先端部がパネル10の画像表示面に接触しているときのみ、受光素子52が、受光した発光を受光信号に変換し、以降の回路に出力する構成であってもよい。
The light pen 50 is configured so that the light receiving element 52 converts the received light emission into a light reception signal and outputs it to a subsequent circuit only when the tip of the light pen 50 is in contact with the image display surface of the panel 10. It may be.
次に、プラズマディスプレイ装置100の走査電極駆動回路33、維持電極駆動回路34、データ電極駆動回路32について説明する。
Next, the scan electrode drive circuit 33, the sustain electrode drive circuit 34, and the data electrode drive circuit 32 of the plasma display apparatus 100 will be described.
図6は、本発明の実施の形態におけるプラズマディスプレイ装置100の走査電極駆動回路33の一構成例を概略的に示す回路図である。
FIG. 6 is a circuit diagram schematically showing a configuration example of the scan electrode driving circuit 33 of the plasma display device 100 according to the embodiment of the present invention.
走査電極駆動回路33は、維持パルス発生回路55と、傾斜波形電圧発生回路60と、走査パルス発生回路70とを備えている。なお、各回路ブロックは、タイミング発生回路35から供給されるタイミング信号にもとづき動作するが、図6では、タイミング信号の経路の詳細は省略する。また、以下、走査パルス発生回路70に入力される電圧を「基準電位A」と記す。
The scan electrode drive circuit 33 includes a sustain pulse generation circuit 55, a ramp waveform voltage generation circuit 60, and a scan pulse generation circuit 70. Each circuit block operates based on the timing signal supplied from the timing generation circuit 35, but details of the timing signal path are omitted in FIG. Hereinafter, the voltage input to the scan pulse generation circuit 70 is referred to as “reference potential A”.
維持パルス発生回路55は、電力回収回路51と、スイッチング素子Q55と、スイッチング素子Q56と、スイッチング素子Q59とを有する。電力回収回路51は、電力回収用のコンデンサC10、スイッチング素子Q11、スイッチング素子Q12、逆流防止用のダイオードDi11、ダイオードDi12、共振用のインダクタL11、インダクタL12を有する。
Sustain pulse generation circuit 55 has power recovery circuit 51, switching element Q55, switching element Q56, and switching element Q59. The power recovery circuit 51 includes a power recovery capacitor C10, a switching element Q11, a switching element Q12, a backflow prevention diode Di11, a diode Di12, a resonance inductor L11, and an inductor L12.
電力回収回路51は、パネル10に蓄えられた電力を、パネル10の電極間容量とインダクタL12とをLC共振させてパネル10から回収し、コンデンサC10に蓄える。そして、回収した電力を、パネル10の電極間容量とインダクタL11とをLC共振させてコンデンサC10からパネル10に再度供給し、走査電極SC1~SCnを駆動するときの電力として再利用する。
The power recovery circuit 51 recovers the power stored in the panel 10 from the panel 10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L12, and stores it in the capacitor C10. Then, the recovered power is supplied to the panel 10 again from the capacitor C10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L11, and reused as power when driving the scan electrodes SC1 to SCn.
スイッチング素子Q55は、走査電極SC1~SCnを電圧Vsにクランプし、スイッチング素子Q56は、走査電極SC1~SCnを電圧0(V)にクランプする。スイッチング素子Q59は分離スイッチであり、走査電極駆動回路33を構成するスイッチング素子の寄生ダイオード等を介して電流が逆流するのを防止する。
Switching element Q55 clamps scan electrodes SC1 to SCn to voltage Vs, and switching element Q56 clamps scan electrodes SC1 to SCn to voltage 0 (V). The switching element Q59 is a separation switch, and prevents a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 33.
走査パルス発生回路70は、スイッチング素子Q71H1~Q71Hn、スイッチング素子Q71L1~Q71Ln、スイッチング素子Q72、負の電圧Vaを発生する電源、電圧Vpを発生する電源E71を有する。そして、走査パルス発生回路70の基準電位Aに電圧Vpを重畳して電圧Vc(Vc=Va+Vp)を発生し、電圧Vaと電圧Vcとを切り換えながら走査電極SC1~SCnに印加することで走査パルスを発生する。例えば、電圧Va=-200(V)であり、電圧Vp=150(V)であれば、電圧Vc=-50(V)となる。
Scan pulse generation circuit 70 has switching elements Q71H1 to Q71Hn, switching elements Q71L1 to Q71Ln, switching element Q72, a power supply for generating negative voltage Va, and a power supply E71 for generating voltage Vp. Then, a voltage Vp (Vc = Va + Vp) is generated by superimposing the voltage Vp on the reference potential A of the scan pulse generating circuit 70, and applied to the scan electrodes SC1 to SCn while switching between the voltage Va and the voltage Vc. Is generated. For example, if the voltage Va = −200 (V) and the voltage Vp = 150 (V), the voltage Vc = −50 (V).
そして、走査パルス発生回路70は、走査電極SC1~SCnのそれぞれに、図3、図4に示したタイミングで走査パルスを順次印加する。なお、走査パルス発生回路70は、維持期間では維持パルス発生回路55の出力電圧をそのまま出力する。すなわち、基準電位Aの電圧を走査電極SC1~SCnへ出力する。
The scan pulse generation circuit 70 sequentially applies scan pulses to the scan electrodes SC1 to SCn at the timings shown in FIGS. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 55 as it is during the sustain period. That is, the reference potential A is output to scan electrodes SC1 to SCn.
また、走査パルス発生回路70は、図4に示したタイミングで、y座標検出サブフィールドSFyのy座標検出期間Pyでは電圧Vcと電圧Vay(=電圧Va)のy座標検出パルスを発生し、x座標検出サブフィールドSFxのx座標検出期間Pxでは電圧Vcとx座標検出電圧Vax(=電圧Va)を発生して、走査電極SC1~SCnに印加する。
Further, the scan pulse generation circuit 70 generates y coordinate detection pulses of the voltage Vc and the voltage Vay (= voltage Va) in the y coordinate detection period Py of the y coordinate detection subfield SFy at the timing shown in FIG. In the x-coordinate detection period Px of the coordinate detection subfield SFx, a voltage Vc and an x-coordinate detection voltage Vax (= voltage Va) are generated and applied to the scan electrodes SC1 to SCn.
傾斜波形電圧発生回路60は、ミラー積分回路61、ミラー積分回路62、ミラー積分回路63を備え、図3、図4に示した傾斜波形電圧を発生する。
The ramp waveform voltage generation circuit 60 includes a Miller integration circuit 61, a Miller integration circuit 62, and a Miller integration circuit 63, and generates the ramp waveform voltage shown in FIGS.
ミラー積分回路61は、トランジスタQ61とコンデンサC61と抵抗R61とを有する。そして、入力端子IN61に一定の電圧を印加する(入力端子IN61として図示される2つの丸の間に一定の電圧差を与える)ことにより、電圧Vt(=電圧Vi2)に向かって緩やかに上昇する上り傾斜波形電圧(画像表示サブフィールドであるサブフィールドSF1の初期化期間Pia1、タイミング検出サブフィールドSFoの初期化期間Pico、y座標検出サブフィールドSFyの消去期間Peby、およびx座標検出サブフィールドSFxの消去期間Pedx、の各期間に発生する上り傾斜波形電圧)を発生する。
Miller integrating circuit 61 includes transistor Q61, capacitor C61, and resistor R61. Then, by applying a constant voltage to the input terminal IN61 (giving a constant voltage difference between two circles illustrated as the input terminal IN61), the voltage gradually rises toward the voltage Vt (= voltage Vi2). Up-slope waveform voltage (initialization period Pia1 of subfield SF1, which is an image display subfield, initialization period Pico of timing detection subfield SFo, erase period Peby of y coordinate detection subfield SFy, and x coordinate detection subfield SFx The rising ramp waveform voltage generated in each period of the erasing period Pedx) is generated.
あるいは、電圧Vtに電圧Vpを重畳した電圧が電圧Vi2に等しくなるように電圧Vtを設定してもよい。この構成では、ミラー積分回路61を動作させているときは、スイッチング素子Q72およびスイッチング素子Q71L1~Q71Lnをオフにし、スイッチング素子Q71H1~Q71Hnをオンにして、ミラー積分回路61で発生した上り傾斜波形電圧に電源E71の電圧Vpを重畳することで初期化動作のための上り傾斜波形電圧を発生することができる。
Alternatively, the voltage Vt may be set so that a voltage obtained by superimposing the voltage Vp on the voltage Vt is equal to the voltage Vi2. In this configuration, when Miller integrating circuit 61 is operated, switching element Q72 and switching elements Q71L1 to Q71Ln are turned off, switching elements Q71H1 to Q71Hn are turned on, and the rising ramp waveform voltage generated in Miller integrating circuit 61 is turned on. The up slope waveform voltage for the initialization operation can be generated by superimposing the voltage Vp of the power source E71 on the top.
ミラー積分回路62は、トランジスタQ62とコンデンサC62と抵抗R62と逆流防止用のダイオードDi62とを有する。そして、入力端子IN62に一定の電圧を印加する(入力端子IN62として図示される2つの丸の間に一定の電圧差を与える)ことにより、電圧Vrに向かって緩やかに上昇する上り傾斜波形電圧(画像表示サブフィールドであるサブフィールドSF1の初期化期間Pia1とサブフィールドSF1~SF8の各維持期間Ps1~Ps8の最後、タイミング検出サブフィールドSFoのタイミング検出期間Poの最後、y座標検出サブフィールドSFyの消去期間Peby、およびx座標検出サブフィールドSFxの消去期間Pedx、の各期間に発生する上り傾斜波形電圧)を発生する。
Miller integrating circuit 62 includes transistor Q62, capacitor C62, resistor R62, and diode Di62 for preventing backflow. Then, by applying a constant voltage to the input terminal IN62 (giving a constant voltage difference between two circles shown as the input terminal IN62), an up-slope waveform voltage that gradually rises toward the voltage Vr ( The initialization period Pia1 of the subfield SF1, which is an image display subfield, the end of the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8, the end of the timing detection period Po of the timing detection subfield SFo, and the y coordinate detection subfield SFy An upward ramp waveform voltage generated in each period of the erasing period Peby and the erasing period Pedx of the x-coordinate detection subfield SFx is generated.
ミラー積分回路63は、トランジスタQ63とコンデンサC63と抵抗R63とを有する。そして、入力端子IN63に一定の電圧を印加する(入力端子IN63として図示される2つの丸の間に一定の電圧差を与える)ことにより、電圧Vi4に向かって緩やかに下降する下り傾斜波形電圧(画像表示サブフィールドであるサブフィールドSF1~SF8の各初期化期間Pia1、Pib2~Pib8、タイミング検出サブフィールドSFoの初期化期間Pico、y座標検出サブフィールドSFyの初期化期間Piby、およびx座標検出サブフィールドSFxの初期化期間Pidx、の各期間に発生する下り傾斜波形電圧)を発生する。
Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63. Then, by applying a constant voltage to the input terminal IN63 (giving a constant voltage difference between two circles shown as the input terminal IN63), a downward ramp waveform voltage (gradiently decreasing toward the voltage Vi4 ( Initialization periods Pia1, Pib2 to Pib8 of the subfields SF1 to SF8 which are image display subfields, an initialization period Pico of the timing detection subfield SFo, an initialization period Piby of the y coordinate detection subfield SFy, and an x coordinate detection sub A downward ramp waveform voltage generated in each period of the initialization period Pidx of the field SFx).
なお、スイッチング素子Q69は分離スイッチであり、走査電極駆動回路33を構成するスイッチング素子の寄生ダイオード等を介して電流が逆流するのを防止する。
Note that the switching element Q69 is a separation switch, and prevents a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 33.
なお、これらのスイッチング素子およびトランジスタは、MOSFETやIGBT等の一般に知られた半導体素子を用いて構成することができる。また、これらのスイッチング素子およびトランジスタは、タイミング発生回路35で発生したそれぞれのスイッチング素子およびトランジスタに対応するタイミング信号により制御される。
Note that these switching elements and transistors can be configured using generally known semiconductor elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the respective switching elements and transistors generated by the timing generation circuit 35.
図7は、本発明の実施の形態におけるプラズマディスプレイ装置100の維持電極駆動回路34の一構成例を概略的に示す回路図である。
FIG. 7 is a circuit diagram schematically showing a configuration example of the sustain electrode drive circuit 34 of the plasma display apparatus 100 according to the embodiment of the present invention.
維持電極駆動回路34は、維持パルス発生回路80と、一定電圧発生回路85とを備えている。なお、各回路ブロックは、タイミング発生回路35から供給されるタイミング信号にもとづき動作するが、図7では、タイミング信号の経路の詳細は省略する。
The sustain electrode driving circuit 34 includes a sustain pulse generating circuit 80 and a constant voltage generating circuit 85. Each circuit block operates based on the timing signal supplied from the timing generation circuit 35, but details of the timing signal path are omitted in FIG.
維持パルス発生回路80は、電力回収回路81と、スイッチング素子Q83と、スイッチング素子Q84とを有する。電力回収回路81は、電力回収用のコンデンサC20、スイッチング素子Q21、スイッチング素子Q22、逆流防止用のダイオードDi21、ダイオードDi22、共振用のインダクタL21、インダクタL22を有する。
Sustain pulse generation circuit 80 has a power recovery circuit 81, a switching element Q83, and a switching element Q84. The power recovery circuit 81 includes a power recovery capacitor C20, a switching element Q21, a switching element Q22, a backflow prevention diode Di21, a diode Di22, a resonance inductor L21, and an inductor L22.
電力回収回路81は、パネル10に蓄えられた電力を、パネル10の電極間容量とインダクタL22とをLC共振させてパネル10から回収し、コンデンサC20に蓄える。そして、回収した電力を、パネル10の電極間容量とインダクタL21とをLC共振させてコンデンサC20からパネル10に再度供給し、維持電極SU1~SUnを駆動するときの電力として再利用する。
The power recovery circuit 81 recovers the power stored in the panel 10 from the panel 10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L22, and stores it in the capacitor C20. Then, the recovered power is supplied to the panel 10 again from the capacitor C20 by LC resonance between the interelectrode capacitance of the panel 10 and the inductor L21, and is reused as power when driving the sustain electrodes SU1 to SUn.
スイッチング素子Q83は維持電極SU1~SUnを電圧Vsにクランプし、スイッチング素子Q84は維持電極SU1~SUnを電圧0(V)にクランプする。
Switching element Q83 clamps sustain electrodes SU1 to SUn to voltage Vs, and switching element Q84 clamps sustain electrodes SU1 to SUn to voltage 0 (V).
このようにして、維持パルス発生回路80は、電圧Vsの維持パルスを発生し、維持電極SU1~SUnに印加する。また、タイミング検出サブフィールドSFoのタイミング検出期間Poではタイミング検出パルスV2、V4を、x座標検出サブフィールドSFxの消去期間Pedxでは電圧Vsを、維持電極SU1~SUnに印加する。
Thus, sustain pulse generating circuit 80 generates a sustain pulse of voltage Vs and applies it to sustain electrodes SU1 to SUn. Further, the timing detection pulses V2 and V4 are applied to the sustain electrodes SU1 to SUn in the timing detection period Po of the timing detection subfield SFo, and the voltage Vs is applied in the erasure period Pedx of the x coordinate detection subfield SFx.
一定電圧発生回路85は、スイッチング素子Q86、スイッチング素子Q87を有する。そして、一定電圧発生回路85は、画像表示サブフィールドであるサブフィールドSF1~SF8の各初期化期間Pia1、Pib2~Pib8と各書込み期間Pw1~Pw8、タイミング検出サブフィールドSFoの初期化期間Picoと書込み期間Pwo、y座標検出サブフィールドSFyの初期化期間Pibyとy座標検出期間Py、およびx座標検出サブフィールドSFxの初期化期間Pidxとx座標検出期間Pxに、維持電極SU1~SUnに電圧Veを印加する。
The constant voltage generation circuit 85 includes a switching element Q86 and a switching element Q87. Then, the constant voltage generation circuit 85 writes the initialization periods Pia1, Pib2 to Pib8 and the writing periods Pw1 to Pw8 of the subfields SF1 to SF8, which are image display subfields, and the initialization period Pico and the writing of the timing detection subfield SFo. During the period Pwo, the initialization period Pby and y coordinate detection period Py of the y coordinate detection subfield SFy, and the initialization period Pidx and x coordinate detection period Px of the x coordinate detection subfield SFx, the voltage Ve is applied to the sustain electrodes SU1 to SUn. Apply.
なお、維持電極SU1~SUnをハイインピーダンス状態にするには、維持電極駆動回路34が有するこれらのスイッチング素子を全てオフにすればよい。
It should be noted that all of these switching elements of sustain electrode drive circuit 34 may be turned off in order to set sustain electrodes SU1 to SUn to a high impedance state.
なお、これらのスイッチング素子は、MOSFETやIGBT等の一般に知られた素子を用いて構成することができる。またこれらのスイッチング素子は、タイミング発生回路35で発生したそれぞれのスイッチング素子に対応するタイミング信号により制御される。
In addition, these switching elements can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements are controlled by timing signals corresponding to the respective switching elements generated by the timing generation circuit 35.
図8は、本発明の実施の形態におけるプラズマディスプレイ装置100のデータ電極駆動回路32の一構成例を概略的に示す回路図である。
FIG. 8 is a circuit diagram schematically showing a configuration example of the data electrode driving circuit 32 of the plasma display device 100 according to the embodiment of the present invention.
なお、データ電極駆動回路32は、画像信号処理回路31から供給される画像データおよびタイミング発生回路35から供給されるタイミング信号にもとづき動作するが、図8では、それらの信号の経路の詳細は省略する。
The data electrode drive circuit 32 operates based on the image data supplied from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35. In FIG. 8, details of the paths of these signals are omitted. To do.
データ電極駆動回路32は、スイッチング素子Q91H1~Q91Hm、スイッチング素子Q91L1~Q91Lmを有する。そして、スイッチング素子Q91Ljをオンにすることでデータ電極Djに電圧0(V)を印加し、スイッチング素子Q91Hjをオンにすることでデータ電極Djに電圧Vdを印加する。こうしてデータ電極駆動回路32は、画像表示サブフィールドであるサブフィールドSF1~SF8の各書込み期間Pw1~Pw8、およびタイミング検出サブフィールドSFoの書込み期間Pwoでは電圧Vdの書込みパルスを、y座標検出サブフィールドSFyのy座標検出期間Pyではy座標検出電圧Vdy(=電圧Vd)を、x座標検出サブフィールドSFxのx座標検出期間Pxでは電圧Vdx(=電圧Vd)のx座標検出パルスを、各データ電極D1~Dmに印加する。
The data electrode drive circuit 32 includes switching elements Q91H1 to Q91Hm and switching elements Q91L1 to Q91Lm. Then, voltage 0 (V) is applied to data electrode Dj by turning on switching element Q91Lj, and voltage Vd is applied to data electrode Dj by turning on switching element Q91Hj. In this way, the data electrode driving circuit 32 applies the write pulse of the voltage Vd to the write period Pwo of the subfields SF1 to SF8 which are image display subfields and the write period Pwo of the timing detection subfield SFo. In the y-coordinate detection period Py of SFy, the y-coordinate detection voltage Vdy (= voltage Vd) is used, and in the x-coordinate detection period Px of the x-coordinate detection subfield SFx, the x-coordinate detection pulse of the voltage Vdx (= voltage Vd) is used. Applied to D1 to Dm.
なお、データ電極D1~Dmをハイインピーダンス状態にするには、データ電極駆動回路32が有するこれらのスイッチング素子を全てオフにすればよい。
It should be noted that in order to set the data electrodes D1 to Dm in a high impedance state, all of these switching elements included in the data electrode driving circuit 32 may be turned off.
次に、本実施の形態における画像表示システムの一例であるプラズマディスプレイシステム30の動作について説明する。
Next, the operation of the plasma display system 30 which is an example of the image display system in the present embodiment will be described.
図9は、本発明の実施の形態におけるプラズマディスプレイシステム30においてライトペン50の位置座標を検出するときの動作の一例を概略的に示す図である。なお、図9では画像表示領域を破線で示しているが、この破線が実際にパネル10に表示されるわけではない。
FIG. 9 is a diagram schematically showing an example of the operation when detecting the position coordinates of the light pen 50 in the plasma display system 30 according to the embodiment of the present invention. In FIG. 9, the image display area is indicated by a broken line, but this broken line is not actually displayed on the panel 10.
図10は、本発明の実施の形態におけるプラズマディスプレイシステム30においてライトペン50の位置座標を検出するときの駆動電圧波形の一例を概略的に示す図である。
FIG. 10 is a diagram schematically showing an example of a driving voltage waveform when the position coordinates of the light pen 50 are detected in the plasma display system 30 according to the embodiment of the present invention.
図10には、画像表示サブフィールドであるサブフィールドSF8に続くタイミング検出サブフィールドSFo、y座標検出サブフィールドSFyおよびx座標検出サブフィールドSFxにおいて、走査電極SC1、走査電極SCn、データ電極D1、データ電極Dmのそれぞれに印加する駆動電圧波形、座標算出回路56に入力される座標基準信号、および受光素子52から出力される受光信号を示す。なお、図10では、維持電極SU1~SUnに印加する駆動電圧波形は省略するが、図10に示す駆動電圧波形は、図3、図4に示した駆動電圧波形と同じものである。
FIG. 10 shows scan electrode SC1, scan electrode SCn, data electrode D1, and data in timing detection subfield SFo, y-coordinate detection subfield SFy, and x-coordinate detection subfield SFx following image display subfield SF8. A driving voltage waveform applied to each of the electrodes Dm, a coordinate reference signal input to the coordinate calculation circuit 56, and a light reception signal output from the light receiving element 52 are shown. In FIG. 10, the drive voltage waveforms applied to sustain electrodes SU1 to SUn are omitted, but the drive voltage waveforms shown in FIG. 10 are the same as the drive voltage waveforms shown in FIGS.
本実施の形態におけるプラズマディスプレイ装置100では、時刻to1から時刻ty0までの時間Toyはあらかじめ定められており、時刻to1から時刻tx0までの時間Toxはあらかじめ定められている。
In plasma display device 100 in the present embodiment, time Toy from time to1 to time ty0 is determined in advance, and time Tox from time to1 to time tx0 is determined in advance.
したがって、タイミング検出回路54は、時刻to1を特定できれば、図10に示すように、時刻ty0と時刻tx0とのそれぞれに立上りエッジがある座標基準信号を発生し、座標算出回路56に出力することができる。
Therefore, when the time to1 can be specified, the timing detection circuit 54 can generate a coordinate reference signal having rising edges at each of the time ty0 and the time tx0 and output it to the coordinate calculation circuit 56 as shown in FIG. it can.
時刻to1は、上述したように、タイミング検出回路54が、発光の間隔が順に時間To0、時間To1、時間To2、時間To3となる連続する5回の発光(これらの発光にもとづき受光素子52から出力される受光信号)を検出することで、特定される。
At time to1, as described above, the timing detection circuit 54 emits light of five consecutive times in which the intervals of light emission are time To0, time To1, time To2, and time To3 (output from the light receiving element 52 based on these light emission). Is detected by detecting the received light signal).
y座標検出サブフィールドSFyのy座標検出期間Pyにおいては、第1の方向(行方向)に延長した線状の発光が第2の方向(列方向)に順次移動するy座標検出パターンをパネル10に表示する。これにより、パネル10の画像表示領域には、図9に示したように、画像表示領域の上端部(1行目)から下端部(n行目)まで順次移動する1本の横線Lyが表示される。
In the y-coordinate detection period Py of the y-coordinate detection subfield SFy, a y-coordinate detection pattern in which linear light emission extended in the first direction (row direction) sequentially moves in the second direction (column direction) is displayed on the panel 10. To display. Accordingly, as shown in FIG. 9, one horizontal line Ly that sequentially moves from the upper end (first row) to the lower end (nth row) of the image display region is displayed in the image display region of the panel 10. Is done.
ライトペン50の先端部がパネル10の画像表示面の「座標(x、y)」に接触(または近接)していれば、横線Lyが座標(x、y)を通過する時刻tyyにおいて、ライトペン50の受光素子52は横線Lyの発光を受光する。これにより、ライトペン50は、図10に示すように、受光素子52が横線Lyの発光を受光したことを示す受光信号を時刻tyyにおいて出力する。
If the tip of the light pen 50 is in contact with (or close to) the “coordinates (x, y)” of the image display surface of the panel 10, at the time tyy when the horizontal line Ly passes the coordinates (x, y), the light The light receiving element 52 of the pen 50 receives the light emission of the horizontal line Ly. Thereby, as shown in FIG. 10, the light pen 50 outputs a light reception signal indicating that the light receiving element 52 has received the light emission of the horizontal line Ly at time tyy.
続くx座標検出サブフィールドSFxのx座標検出期間Pxにおいては、第2の方向(列方向)に延長した線状の発光が第1の方向(行方向)に順次移動するx座標検出パターンをパネル10に表示する。これにより、パネル10の画像表示領域には、図9に示したように、画像表示領域の左端部(1列目の画素列)から右端部(m/3列目の画素列)まで順次移動する1本の縦線Lxが表示される。
In the subsequent x-coordinate detection period Px of the x-coordinate detection subfield SFx, an x-coordinate detection pattern in which linear light emission extended in the second direction (column direction) sequentially moves in the first direction (row direction) is displayed on the panel. 10 is displayed. Accordingly, as shown in FIG. 9, the image display area of the panel 10 is sequentially moved from the left end portion (first pixel column) to the right end portion (m / 3 pixel row) of the image display area. One vertical line Lx is displayed.
ライトペン50の先端部がパネル10の画像表示面の「座標(x、y)」に接触(または近接)していれば、縦線Lxが座標(x、y)を通過する時刻txxにおいて、ライトペン50の受光素子52は縦線Lxの発光を受光する。これにより、ライトペン50は、図10に示すように、受光素子52が縦線Lxの発光を受光したことを示す受光信号を時刻txxにおいて出力する。
If the tip of the light pen 50 is in contact with (or close to) the “coordinate (x, y)” of the image display surface of the panel 10, at the time txx when the vertical line Lx passes the coordinate (x, y), The light receiving element 52 of the light pen 50 receives the light emission of the vertical line Lx. Accordingly, as shown in FIG. 10, the light pen 50 outputs a light reception signal indicating that the light receiving element 52 has received the light emission of the vertical line Lx at time txx.
図5に示した座標算出回路56は、y座標検出サブフィールドSFyのy座標検出期間Pyにおいてタイミング検出回路54から出力される座標基準信号と、受光素子52から出力される受光信号にもとづき、内部に備えたカウンタを用いて時刻ty0から時刻tyyまでの時間Tyyを測定する。そして、内部に備えた演算回路において、時間Tyyを時間Ty1で除算する。この除算結果が画像表示領域におけるライトペン50の位置のy座標となる。
The coordinate calculation circuit 56 shown in FIG. 5 is based on the coordinate reference signal output from the timing detection circuit 54 and the light reception signal output from the light receiving element 52 in the y coordinate detection period Py of the y coordinate detection subfield SFy. The time Tyy from the time ty0 to the time tyy is measured using the counter provided for. The time Tyy is divided by the time Ty1 in the arithmetic circuit provided inside. The division result is the y coordinate of the position of the light pen 50 in the image display area.
また、座標算出回路56は、x座標検出サブフィールドSFxのx座標検出期間Pxにおいてタイミング検出回路54から出力される座標基準信号と、受光素子52から出力される受光信号にもとづき、内部に備えたカウンタを用いて時刻tx0から時刻txxまでの時間Txxを測定する。そして、内部に備えた演算回路において、時間Txxを時間Tx1で除算する。この除算結果が画像表示領域におけるライトペン50の位置のx座標となる。
The coordinate calculation circuit 56 is provided internally based on the coordinate reference signal output from the timing detection circuit 54 and the light reception signal output from the light receiving element 52 in the x coordinate detection period Px of the x coordinate detection subfield SFx. A time Txx from time tx0 to time txx is measured using a counter. Then, the time Txx is divided by the time Tx1 in the arithmetic circuit provided inside. This division result is the x coordinate of the position of the light pen 50 in the image display area.
本実施の形態における座標算出回路56は、このようにして、画像表示領域におけるライトペン50の位置(座標(x、y))を算出する。
In this way, the coordinate calculation circuit 56 in the present embodiment calculates the position (coordinates (x, y)) of the light pen 50 in the image display area.
図11は、本発明の実施の形態におけるプラズマディスプレイシステム30においてライトペン50による手書き入力を行うときの動作の一例を概略的に示す図である。なお、図11では画像表示領域を破線で示しているが、この破線が実際にパネル10に表示されるわけではない。
FIG. 11 is a diagram schematically showing an example of an operation when handwriting input is performed with the light pen 50 in the plasma display system 30 according to the embodiment of the present invention. In FIG. 11, the image display area is indicated by a broken line, but this broken line is not actually displayed on the panel 10.
描画回路44は、座標算出回路56が算出した座標(x、y)に対応する画素を中心に、所定の色および大きさの描画パターン(例えば、白色の丸等のパターン)の描画信号を画像メモリ47に書込む。
The drawing circuit 44 outputs a drawing signal of a drawing pattern (for example, a pattern such as a white circle) having a predetermined color and size around a pixel corresponding to the coordinates (x, y) calculated by the coordinate calculation circuit 56. Write to memory 47.
使用者がライトペン50の先端をパネル10の画像表示面に接触させたままライトペン50を移動させると、座標算出回路56が算出する座標(x、y)もライトペン50の移動に応じて変化する。
When the user moves the light pen 50 while the tip of the light pen 50 is in contact with the image display surface of the panel 10, the coordinates (x, y) calculated by the coordinate calculation circuit 56 also correspond to the movement of the light pen 50. Change.
描画回路44は、変化する座標(x、y)に応じて描画パターンの位置を変化させながら、位置が変化した描画パターンに応じた描画信号を画像メモリ47に順次書込んでいく。
The drawing circuit 44 sequentially writes a drawing signal corresponding to the drawing pattern whose position has changed in the image memory 47 while changing the position of the drawing pattern in accordance with the changing coordinates (x, y).
このようにして、描画回路44の画像メモリ47には、ライトペン50の軌跡を示す描画信号が蓄積されていく。画像メモリ47に蓄積された描画信号は1フィールド毎に読み出され、画像信号処理回路31に出力される。
In this way, the drawing signal indicating the locus of the light pen 50 is accumulated in the image memory 47 of the drawing circuit 44. The drawing signal stored in the image memory 47 is read for each field and output to the image signal processing circuit 31.
画像信号処理回路31は、描画回路44から出力される描画信号と画像信号とを合成し、その合成後の信号にもとづき画像データを生成する。こうして、パネル10には、図11に示すように、画像信号にライトペン50の軌跡を示す画像(ライトペン50を用いて手書き入力された図画)が重畳された画像が表示される。
The image signal processing circuit 31 combines the drawing signal output from the drawing circuit 44 and the image signal, and generates image data based on the combined signal. Thus, as shown in FIG. 11, the panel 10 displays an image in which an image indicating the locus of the light pen 50 (a graphic input by handwriting using the light pen 50) is superimposed on the image signal.
以上示したように、本実施の形態における画像表示システム(例えば、プラズマディスプレイシステム30)は、安定に放電を発生することができるので、精度の高いy座標検出パターンおよびx座標検出パターンをパネル10に表示することが可能となる。
As described above, since the image display system (for example, the plasma display system 30) in the present embodiment can generate a stable discharge, the y coordinate detection pattern and the x coordinate detection pattern with high accuracy are displayed on the panel 10. Can be displayed.
これにより、ライトペン50は、位置座標(x座標、y座標)をより高精度に算出することが可能となる。したがって、本実施の形態におけるプラズマディスプレイシステム30では、ライトペン50の軌跡を正確な位置座標にもとづき描画することができる。
Thereby, the light pen 50 can calculate the position coordinates (x coordinate, y coordinate) with higher accuracy. Therefore, in the plasma display system 30 in the present embodiment, the locus of the light pen 50 can be drawn based on accurate position coordinates.
なお、本実施の形態では、タイミング検出サブフィールドSFoにおいて、あらかじめ定められた所定の時間間隔(例えば、時間To1、時間To2、時間To3)で、タイミング検出放電を4回発生させる例を説明したが、タイミング検出放電の回数は2回以上であればよい。
In the present embodiment, an example has been described in which the timing detection discharge is generated four times at predetermined time intervals (for example, time To1, time To2, and time To3) in the timing detection subfield SFo. The number of timing detection discharges may be two or more.
なお、本実施の形態では、最初のタイミング検出放電を容易に特定できるようにするために、タイミング検出放電を複数回発生させるときの時間間隔は互いに異なる時間に設定することが望ましい。
In the present embodiment, it is desirable to set the time intervals for generating the timing detection discharge a plurality of times in order to easily identify the first timing detection discharge.
なお、本実施の形態では、各フィールドにタイミング検出サブフィールドSFo、y座標検出サブフィールドSFy、x座標検出サブフィールドSFxを設ける構成を説明したが、本発明は何らこの構成に限定されるものではない。例えば、複数フィールドに1回の割合でそれらのサブフィールドを発生する構成であってもよい。
In the present embodiment, the configuration in which the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx are provided in each field has been described. However, the present invention is not limited to this configuration. Absent. For example, the configuration may be such that those subfields are generated at a rate of once in a plurality of fields.
なお、本実施の形態では、プラズマディスプレイ装置とライトペンとの間で無線通信を行う例を説明したが、本発明は何らこの構成に限定されない。例えば、プラズマディスプレイ装置とライトペンとの間を電気ケーブル等によって電気的に接続し、その電気ケーブルを介してライトペンとプラズマディスプレイ装置との間で信号の送受信を行う構成であってもよい。また、その場合には、タイミング検出サブフィールドSFoを設けなくても良い。
In this embodiment, an example in which wireless communication is performed between the plasma display device and the light pen has been described, but the present invention is not limited to this configuration. For example, the plasma display device and the light pen may be electrically connected by an electric cable or the like, and a signal may be transmitted and received between the light pen and the plasma display device via the electric cable. In that case, the timing detection subfield SFo may not be provided.
なお、本発明の実施の形態では、画像表示部にプラズマディスプレイパネルを用いたプラズマディスプレイ装置を画像表示装置の一例として挙げて、各動作を説明した。しかし、本発明は、何ら画像表示装置がプラズマディスプレイ装置に限定されるものではない。例えば、液晶パネル、有機ELパネル、LEDパネル等を用いた画像表示装置においても、上述した構成と同様の構成を適用することで、上述した効果と同様の効果を得ることができる。
In the embodiment of the present invention, each operation has been described by taking a plasma display device using a plasma display panel as an image display unit as an example of the image display device. However, in the present invention, the image display device is not limited to the plasma display device. For example, even in an image display device using a liquid crystal panel, an organic EL panel, an LED panel, or the like, the same effect as that described above can be obtained by applying the same configuration as that described above.
なお、本発明の実施の形態では、1フィールドに、複数の画像表示サブフィールドと位置座標を検出するためのサブフィールドとを有する構成を説明したが、本発明は何らこの構成に限定されるものではない。例えば、使用者がライトペンを使用しないときは、1フィールドを画像表示サブフィールドだけで構成してもよい。
In the embodiment of the present invention, a configuration in which one field has a plurality of image display subfields and a subfield for detecting position coordinates has been described. However, the present invention is not limited to this configuration. is not. For example, when the user does not use the light pen, one field may be composed of only the image display subfield.
なお、本発明の実施の形態では、強制初期化動作を、パネルの画像表示領域内にある全ての放電セルに強制的に初期化放電を発生する初期化動作として説明したが、本発明は何らこの構成に限定されない。本発明の実施の形態では、パネルの画像表示領域内にある一部の放電セルにのみ強制初期化波形を印加してその放電セルにのみ強制的に初期化放電を発生する動作も、強制初期化動作に含めるものとする。
In the embodiment of the present invention, the forced initializing operation has been described as an initializing operation that forcibly generates initializing discharge in all the discharge cells in the image display area of the panel. It is not limited to this configuration. In the embodiment of the present invention, the forced initializing waveform is applied only to some discharge cells in the image display area of the panel and the initializing discharge is forcibly generated only in the discharge cells. It shall be included in the conversion operation.
なお、本発明の実施の形態では、描画回路44をプラズマディスプレイ装置に備えた構成を示したが、本発明は何らこの構成に限定されるものではない。例えば、プラズマディスプレイ装置に接続したコンピュータに描画回路44に相当する機能を持たせ、そのコンピュータを用いて描画信号を作成する構成であってもよい。
In the embodiment of the present invention, a configuration in which the drawing circuit 44 is provided in the plasma display device is shown, but the present invention is not limited to this configuration. For example, a computer connected to the plasma display device may have a function corresponding to the drawing circuit 44, and a drawing signal may be generated using the computer.
なお、本実施の形態ではパネルに接触しているときのみ手書き入力ができる接触型のライトペンを画像表示システムに用いる例を説明したが、本発明は何らこの構成に限定されない。パネルに接触していないときでも手書き入力ができる非接触型のライトペンを用いた画像表示システムにおいても、上述した構成と同様の構成を適用することができ、上述した効果と同様の効果を得ることができる。
In this embodiment, an example in which a contact-type light pen capable of handwriting input only when touching the panel is used in the image display system is described, but the present invention is not limited to this configuration. Even in an image display system using a non-contact type light pen capable of handwriting input even when not touching the panel, the same configuration as the above-described configuration can be applied, and the same effect as the above-described effect can be obtained. be able to.
なお、図3、図4、図10に示した駆動電圧波形は本発明の実施の形態における一例を示したものに過ぎず、本発明は何らこの駆動電圧波形に限定されるものではない。
The drive voltage waveforms shown in FIGS. 3, 4, and 10 are merely examples in the embodiment of the present invention, and the present invention is not limited to these drive voltage waveforms.
また、図5、図6、図7、図8に示した回路構成も本発明の実施の形態における一例を示したものに過ぎず、本発明は何らこれらの回路構成に限定されるものではない。
Further, the circuit configurations shown in FIGS. 5, 6, 7, and 8 are merely examples in the embodiment of the present invention, and the present invention is not limited to these circuit configurations. .
なお、本発明における実施の形態に示した各回路ブロックは、実施の形態に示した各動作を行う電気回路として構成されてもよく、あるいは、実施の形態に示した各動作と実質的に同じ動作をするようにプログラミングされたマイクロコンピュータやコンピュータ等を用いて構成されてもよい。
Each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or substantially the same as each operation shown in the embodiment. A microcomputer or a computer programmed to operate may be used.
なお、本発明の実施の形態において示した具体的な数値は、画面サイズが50インチ、表示電極対14の数が1024のパネル10の特性にもとづき設定したものであって、単に実施の形態における一例を示したものに過ぎない。本発明はこれらの数値に何ら限定されるものではなく、各数値はパネルの仕様やパネルの特性やプラズマディスプレイ装置の仕様等にあわせて最適に設定することが望ましい。また、これらの各数値は、上述した効果を得られる範囲でのばらつきを許容するものとする。
The specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 14 of 1024. It is just an example. The present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with panel specifications, panel characteristics, plasma display device specifications, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.
本発明は、ライトペンの位置座標を検出するための放電を安定に発生させ、ライトペンの位置座標を精度よく検出することができるので、画像表示装置の駆動方法、画像表示装置、および画像表示システムとして有用である。
Since the present invention can stably generate a discharge for detecting the position coordinates of the light pen and accurately detect the position coordinates of the light pen, the driving method of the image display apparatus, the image display apparatus, and the image display Useful as a system.
10 パネル
11 前面基板
12 走査電極
13 維持電極
14 表示電極対
15,23 誘電体層
16 保護層
21 背面基板
22 データ電極
24 隔壁
25,25R,25G,25B 蛍光体層
30 プラズマディスプレイシステム
31 画像信号処理回路
32 データ電極駆動回路
33 走査電極駆動回路
34 維持電極駆動回路
35 タイミング発生回路
44 描画回路
46 受信回路
47 画像メモリ
50 ライトペン
51,81 電力回収回路
52 受光素子
54 タイミング検出回路
55,80 維持パルス発生回路
56 座標算出回路
58 送信回路
60 傾斜波形電圧発生回路
61,62,63 ミラー積分回路
70 走査パルス発生回路
85 一定電圧発生回路
100 プラズマディスプレイ装置
Lx 縦線
Ly 横線
Di11,Di12,Di21,Di22,Di62 ダイオード
L11,L12,L21,L22 インダクタ
Q11,Q12,Q21,Q22,Q55,Q56,Q59,Q69,Q72,Q83,Q84,Q86,Q87,Q71H1~Q71Hn,Q71L1~Q71Ln,Q91H1~Q91Hm,Q91L1~Q91Lm スイッチング素子
C10,C20,C61,C62,C63 コンデンサ
R61,R62,R63 抵抗
Q61,Q62,Q63 トランジスタ
IN61,IN62,IN63 入力端子
E71 電源
SFx x座標検出サブフィールド
SFy y座標検出サブフィールド
SFo タイミング検出サブフィールド
SF1~SF8 画像表示サブフィールド DESCRIPTION OF SYMBOLS 10 Panel 11 Front substrate 12 Scan electrode 13 Sustain electrode 14 Display electrode pair 15, 23 Dielectric layer 16 Protective layer 21 Back substrate 22 Data electrode 24 Partition 25, 25R, 25G, 25B Phosphor layer 30 Plasma display system 31 Image signal processing Circuit 32 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35 Timing generation circuit 44 Drawing circuit 46 Reception circuit 47 Image memory 50 Light pen 51, 81 Power recovery circuit 52 Light receiving element 54 Timing detection circuit 55, 80 Sustain pulse Generation circuit 56 Coordinate calculation circuit 58 Transmission circuit 60 Ramp waveform voltage generation circuit 61, 62, 63 Miller integration circuit 70 Scanning pulse generation circuit 85 Constant voltage generation circuit 100 Plasma display device Lx Vertical line Ly Horizontal Di11, Di12, Di21, Di22, Di62 Diodes L11, L12, L21, L22 Inductors Q11, Q12, Q21, Q22, Q55, Q56, Q59, Q69, Q72, Q83, Q84, Q86, Q87, Q71H1 to Q71Hn, Q71L1 to Q71Ln, Q91H1 to Q91Hm, Q91L1 to Q91Lm Switching element C10, C20, C61, C62, C63 Capacitor R61, R62, R63 Resistor Q61, Q62, Q63 Transistor IN61, IN62, IN63 Input terminal E71 Power supply SFx x Coordinate detection subfield SFy y Coordinate detection subfield SFo Timing detection subfield SF1 to SF8 Image display subfield
11 前面基板
12 走査電極
13 維持電極
14 表示電極対
15,23 誘電体層
16 保護層
21 背面基板
22 データ電極
24 隔壁
25,25R,25G,25B 蛍光体層
30 プラズマディスプレイシステム
31 画像信号処理回路
32 データ電極駆動回路
33 走査電極駆動回路
34 維持電極駆動回路
35 タイミング発生回路
44 描画回路
46 受信回路
47 画像メモリ
50 ライトペン
51,81 電力回収回路
52 受光素子
54 タイミング検出回路
55,80 維持パルス発生回路
56 座標算出回路
58 送信回路
60 傾斜波形電圧発生回路
61,62,63 ミラー積分回路
70 走査パルス発生回路
85 一定電圧発生回路
100 プラズマディスプレイ装置
Lx 縦線
Ly 横線
Di11,Di12,Di21,Di22,Di62 ダイオード
L11,L12,L21,L22 インダクタ
Q11,Q12,Q21,Q22,Q55,Q56,Q59,Q69,Q72,Q83,Q84,Q86,Q87,Q71H1~Q71Hn,Q71L1~Q71Ln,Q91H1~Q91Hm,Q91L1~Q91Lm スイッチング素子
C10,C20,C61,C62,C63 コンデンサ
R61,R62,R63 抵抗
Q61,Q62,Q63 トランジスタ
IN61,IN62,IN63 入力端子
E71 電源
SFx x座標検出サブフィールド
SFy y座標検出サブフィールド
SFo タイミング検出サブフィールド
SF1~SF8 画像表示サブフィールド DESCRIPTION OF SYMBOLS 10 Panel 11 Front substrate 12 Scan electrode 13 Sustain electrode 14 Display electrode pair 15, 23 Dielectric layer 16 Protective layer 21 Back substrate 22 Data electrode 24 Partition 25, 25R, 25G, 25B Phosphor layer 30 Plasma display system 31 Image signal processing Circuit 32 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35 Timing generation circuit 44 Drawing circuit 46 Reception circuit 47 Image memory 50 Light pen 51, 81 Power recovery circuit 52 Light receiving element 54 Timing detection circuit 55, 80 Sustain pulse Generation circuit 56 Coordinate calculation circuit 58 Transmission circuit 60 Ramp waveform voltage generation circuit 61, 62, 63 Miller integration circuit 70 Scanning pulse generation circuit 85 Constant voltage generation circuit 100 Plasma display device Lx Vertical line Ly Horizontal Di11, Di12, Di21, Di22, Di62 Diodes L11, L12, L21, L22 Inductors Q11, Q12, Q21, Q22, Q55, Q56, Q59, Q69, Q72, Q83, Q84, Q86, Q87, Q71H1 to Q71Hn, Q71L1 to Q71Ln, Q91H1 to Q91Hm, Q91L1 to Q91Lm Switching element C10, C20, C61, C62, C63 Capacitor R61, R62, R63 Resistor Q61, Q62, Q63 Transistor IN61, IN62, IN63 Input terminal E71 Power supply SFx x Coordinate detection subfield SFy y Coordinate detection subfield SFo Timing detection subfield SF1 to SF8 Image display subfield
Claims (10)
- 複数の走査電極および維持電極と複数のデータ電極とを有する画像表示部を備えた画像表示装置の駆動方法であって、
画像表示サブフィールド、y座標検出サブフィールド、およびx座標検出サブフィールドを有するフィールドを発生するとともに、前記y座標検出サブフィールドまたは前記x座標検出サブフィールドを前記フィールドの最後に発生するサブフィールドとし、
前記画像表示サブフィールドは、前記走査電極および前記維持電極に交互に維持パルスを印加した後に第1の電圧まで上昇する上り傾斜波形電圧を前記走査電極に印加する維持期間を有し、
前記フィールドの最後に発生する前記y座標検出サブフィールドまたは前記x座標検出サブフィールドは、前記第1の電圧よりも高い第2の電圧まで上昇する上り傾斜波形電圧と下り傾斜波形電圧を前記走査電極に印加する消去期間を有する
ことを特徴とする画像表示装置の駆動方法。 A method of driving an image display device including an image display unit having a plurality of scan electrodes and sustain electrodes and a plurality of data electrodes,
Generating a field having an image display subfield, a y-coordinate detection subfield, and an x-coordinate detection subfield, and making the y-coordinate detection subfield or the x-coordinate detection subfield a subfield generated at the end of the field;
The image display subfield has a sustain period in which an upward ramp waveform voltage rising to a first voltage is applied to the scan electrode after alternately applying a sustain pulse to the scan electrode and the sustain electrode;
The y-coordinate detection subfield or the x-coordinate detection subfield generated at the end of the field generates an up-slope waveform voltage and a down-slope waveform voltage that rise to a second voltage that is higher than the first voltage. A driving method of an image display device, characterized by having an erasing period applied to the display. - 前記y座標検出サブフィールドおよび前記x座標検出サブフィールドは、前記第2の電圧まで上昇する上り傾斜波形電圧を前記走査電極に印加する消去期間を有する
ことを特徴とする請求項1に記載の画像表示装置の駆動方法。 2. The image according to claim 1, wherein the y-coordinate detection subfield and the x-coordinate detection subfield have an erasing period in which an upward ramp waveform voltage that rises to the second voltage is applied to the scan electrode. A driving method of a display device. - 前記y座標検出サブフィールドの直後に前記x座標検出サブフィールドを発生し、前記x座標検出サブフィールドを前記フィールドの最後に発生するサブフィールドとする
ことを特徴とする請求項1に記載の画像表示装置の駆動方法。 2. The image display according to claim 1, wherein the x coordinate detection subfield is generated immediately after the y coordinate detection subfield, and the x coordinate detection subfield is a subfield generated at the end of the field. Device driving method. - 前記消去期間において、前記第2の電圧まで上昇する上り傾斜波形電圧を前記走査電極に印加する間に、前記データ電極をハイインピーダンス状態にする
ことを特徴とする請求項1に記載の画像表示装置の駆動方法。 2. The image display device according to claim 1, wherein in the erasing period, the data electrode is set in a high impedance state while an upward ramp waveform voltage rising to the second voltage is applied to the scan electrode. Driving method. - 前記消去期間において前記第2の電圧まで上昇する上り傾斜波形電圧は、前記第1の電圧まで上昇する上り傾斜波形電圧と、前記第1の電圧以下の電圧から前記第2の電圧まで上昇する上り傾斜波形電圧の2つの上り傾斜波形電圧を含む波形形状を有する
ことを特徴とする請求項1に記載の画像表示装置の駆動方法。 The rising ramp waveform voltage rising to the second voltage in the erasing period includes an rising ramp waveform voltage rising to the first voltage, and an rising ramp waveform voltage rising from the voltage lower than the first voltage to the second voltage. 2. The driving method of an image display device according to claim 1, wherein the driving method has a waveform shape including two rising ramp waveform voltages of the ramp waveform voltage. - 前記y座標検出サブフィールドの最後に前記消去期間を発生し、前記x座標検出サブフィールドの最後に前記消去期間を発生する
ことを特徴とする請求項2に記載の画像表示装置の駆動方法。 3. The method of driving an image display device according to claim 2, wherein the erasing period is generated at the end of the y-coordinate detection subfield, and the erasing period is generated at the end of the x-coordinate detection subfield. - 複数の走査電極および維持電極と複数のデータ電極とを有する画像表示部と、1フィールドを複数のサブフィールドで構成して前記画像表示部を駆動する駆動回路とを備えた画像表示装置であって、
前記駆動回路は、
画像表示サブフィールド、y座標検出サブフィールド、およびx座標検出サブフィールドを有するフィールドを発生するとともに、前記y座標検出サブフィールドまたは前記x座標検出サブフィールドを前記フィールドの最後に発生し、
前記画像表示サブフィールドの維持期間では、前記走査電極および前記維持電極に交互に維持パルスを印加した後に第1の電圧まで上昇する上り傾斜波形電圧を前記走査電極に印加し、
前記フィールドの最後に発生する前記y座標検出サブフィールドまたは前記x座標検出サブフィールドに、前記第1の電圧よりも高い第2の電圧まで上昇する上り傾斜波形電圧と下り傾斜波形電圧を前記走査電極に印加する消去期間を設ける
ことを特徴とする画像表示装置。 An image display device comprising: an image display unit having a plurality of scan electrodes, sustain electrodes, and a plurality of data electrodes; and a drive circuit configured to drive one of the plurality of subfields to drive the image display unit. ,
The drive circuit is
Generating a field having an image display subfield, a y-coordinate detection subfield, and an x-coordinate detection subfield, and generating the y-coordinate detection subfield or the x-coordinate detection subfield at the end of the field;
In the sustain period of the image display subfield, an upward ramp waveform voltage that rises to a first voltage after applying a sustain pulse alternately to the scan electrode and the sustain electrode is applied to the scan electrode,
Ascending ramp waveform voltage and descending ramp waveform voltage rising to a second voltage higher than the first voltage are applied to the scan electrode in the y coordinate detection subfield or the x coordinate detection subfield generated at the end of the field. An image display device characterized by providing an erasing period to be applied to the display. - 前記駆動回路は、
前記y座標検出サブフィールドおよび前記x座標検出サブフィールドに、前記第2の電圧まで上昇する上り傾斜波形電圧を前記走査電極に印加する消去期間を設ける
ことを特徴とする請求項7に記載の画像表示装置。 The drive circuit is
8. The image according to claim 7, wherein an erasing period in which an ascending waveform voltage rising to the second voltage is applied to the scan electrode is provided in the y coordinate detection subfield and the x coordinate detection subfield. 9. Display device. - 前記駆動回路は、
前記y座標検出サブフィールドの直後に前記x座標検出サブフィールドを発生し、前記x座標検出サブフィールドを前記フィールドの最後に発生するサブフィールドとする
ことを特徴とする請求項7に記載の画像表示装置。 The drive circuit is
The image display according to claim 7, wherein the x-coordinate detection subfield is generated immediately after the y-coordinate detection subfield, and the x-coordinate detection subfield is a subfield generated at the end of the field. apparatus. - 複数の走査電極および維持電極と複数のデータ電極とを有する画像表示部を有する画像表示装置と、ライトペンと、座標算出回路および描画回路とを備えた画像表示システムであって、
前記画像表示装置は、
画像表示サブフィールド、y座標検出サブフィールド、およびx座標検出サブフィールドを有するフィールドを発生するとともに、前記y座標検出サブフィールドまたは前記x座標検出サブフィールドを前記フィールドの最後に発生し、
前記画像表示サブフィールドの維持期間では、前記走査電極および前記維持電極に交互に維持パルスを印加した後に第1の電圧まで上昇する上り傾斜波形電圧を前記走査電極に印加し、
前記フィールドの最後に発生する前記y座標検出サブフィールドまたは前記x座標検出サブフィールドに、前記第1の電圧よりも高い第2の電圧まで上昇する上り傾斜波形電圧と下り傾斜波形電圧を前記走査電極に印加する消去期間を設け、
前記ライトペンは、前記y座標検出サブフィールドにおいて前記画像表示部に生じる発光、および前記x座標検出サブフィールドにおいて前記画像表示部に生じる発光を受光して受光信号を出力し、
前記座標算出回路は、前記受光信号にもとづき、前記y座標検出サブフィールドにおいて前記画像表示部に生じる発光のうちの前記ライトペンが受光する発光の位置を表す座標、および前記x座標検出サブフィールドにおいて前記画像表示部に生じる発光のうちの前記ライトペンが受光する発光の位置を表す座標を算出し、
前記描画回路は、前記座標算出回路が算出した座標にもとづく画像を前記画像表示部に表示するための描画信号を作成し、
前記画像表示装置は、前記描画信号にもとづく画像を前記画像表示部に表示する
ことを特徴とする画像表示システム。 An image display system including an image display device having an image display unit having a plurality of scan electrodes and sustain electrodes and a plurality of data electrodes, a light pen, a coordinate calculation circuit, and a drawing circuit,
The image display device includes:
Generating a field having an image display subfield, a y-coordinate detection subfield, and an x-coordinate detection subfield, and generating the y-coordinate detection subfield or the x-coordinate detection subfield at the end of the field;
In the sustain period of the image display subfield, an upward ramp waveform voltage that rises to a first voltage after applying a sustain pulse alternately to the scan electrode and the sustain electrode is applied to the scan electrode,
Ascending ramp waveform voltage and descending ramp waveform voltage rising to a second voltage higher than the first voltage are applied to the scan electrode in the y coordinate detection subfield or the x coordinate detection subfield generated at the end of the field. An erasing period to be applied to
The light pen receives light emission generated in the image display unit in the y coordinate detection subfield and light emission generated in the image display unit in the x coordinate detection subfield, and outputs a light reception signal,
The coordinate calculation circuit is configured to, based on the light reception signal, a coordinate indicating a light emission position received by the light pen among light emission generated in the image display unit in the y coordinate detection subfield, and in the x coordinate detection subfield. Calculate coordinates indicating the position of light emission received by the light pen among the light emission generated in the image display unit,
The drawing circuit creates a drawing signal for displaying an image based on the coordinates calculated by the coordinate calculation circuit on the image display unit,
The image display system displays an image based on the drawing signal on the image display unit.
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JP2001318765A (en) * | 2000-05-10 | 2001-11-16 | Nec Corp | Coordinate position detector and coordinate position detection method for plasma display panel |
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WO2010143411A1 (en) * | 2009-06-10 | 2010-12-16 | パナソニック株式会社 | Plasma display panel drive method and plasma display device |
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WO2008120471A1 (en) * | 2007-04-02 | 2008-10-09 | Panasonic Corporation | Plasma display and driving method for plasma display panel |
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