WO2013125199A1 - Image display system - Google Patents

Image display system Download PDF

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Publication number
WO2013125199A1
WO2013125199A1 PCT/JP2013/000861 JP2013000861W WO2013125199A1 WO 2013125199 A1 WO2013125199 A1 WO 2013125199A1 JP 2013000861 W JP2013000861 W JP 2013000861W WO 2013125199 A1 WO2013125199 A1 WO 2013125199A1
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WO
WIPO (PCT)
Prior art keywords
coordinate
voltage
image display
signal
circuit
Prior art date
Application number
PCT/JP2013/000861
Other languages
French (fr)
Japanese (ja)
Inventor
井上　真一
貴彦 折口
剛 桑山
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2012038453A external-priority patent/JP2015092204A/en
Priority claimed from JP2012038452A external-priority patent/JP2015092303A/en
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2013125199A1 publication Critical patent/WO2013125199A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/033—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor
    • G06F3/0354—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
    • G06F3/03542—Light pens for emitting or receiving light
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/292—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for reset discharge, priming discharge or erase discharge occurring in a phase other than addressing
    • G09G3/2927—Details of initialising
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G09G3/2965—Driving circuits for producing the waveforms applied to the driving electrodes using inductors for energy recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp

Definitions

  • the present invention provides an image display device for displaying characters in an image display area by combining light emission and non-light emission binary control in a plurality of light emitting elements constituting a pixel, and an image in which characters and drawings can be input by hand using a light pen. It relates to a display system.
  • a plasma display panel (hereinafter abbreviated as “panel”) is a typical image display device that displays an image in an image display area by combining binary control of light emission and non-light emission in each of a plurality of light emitting elements constituting a pixel. There is).
  • a large number of discharge cells which are light-emitting elements constituting pixels, are formed between a front substrate and a rear substrate that are arranged to face each other.
  • the front substrate a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate.
  • the back substrate has a plurality of parallel data electrodes formed on a glass substrate on the back side.
  • Each discharge cell is coated with one of red (R), green (G), and blue (B) phosphors, and a discharge gas is enclosed therein.
  • R red
  • G green
  • B blue
  • an ultraviolet ray is generated by causing a gas discharge, and the phosphor is excited to emit light by the ultraviolet ray.
  • a subfield method is generally used as a method of displaying an image in an image display area of a panel by combining binary control of light emission and non-light emission in a light emitting element.
  • each discharge cell In the subfield method, one field is divided into a plurality of subfields having different emission luminances.
  • each discharge cell light emission / non-light emission of each subfield is controlled by a combination according to the gradation value to be displayed.
  • each discharge cell emits light with brightness corresponding to the gradation value to be displayed, and a color image composed of various combinations of gradation values is displayed in the image display area of the panel.
  • Some of such image display apparatuses have a function of allowing handwriting input of characters and drawings on a panel using a pointing device called “light pen”.
  • position coordinates In order to realize a handwriting input function using a light pen, a technique for detecting the position of the light pen in an image display area is disclosed.
  • position coordinates the coordinates representing the position of the light pen in the image display area.
  • an abscissa detection subfield for displaying an abscissa detection pattern is provided in one field. Then, the light emission of this abscissa detection subfield is detected by the light pen, and the position (abscissa) of the light pen is detected based on the timing at which the light emission is detected.
  • a position detection period for generating a light signal for detecting position coordinates is provided in one field only when detecting the position coordinates of the light pen. Then, this light signal is detected by the light pen, and the position coordinates of the light pen are detected based on the timing at which the light signal is detected.
  • An image display system includes an image display device including an image display unit having a plurality of electrodes in the x-coordinate direction that is a horizontal direction and the y-coordinate direction that is a vertical direction, and a light pen including a light receiving element and a switch.
  • a coordinate calculation circuit, a filter circuit, and a drawing circuit The image display unit of the image display device emits light in the y coordinate detection subfield and the x coordinate detection subfield.
  • the light pen receives light emitted from the image display unit in the y coordinate detection subfield and the x coordinate detection subfield and generates a light reception signal.
  • the coordinate calculation circuit outputs a first y-coordinate signal and a first x-coordinate signal representing a position on the image display unit of light emission received by the light pen based on the light reception signal.
  • the filter circuit applies a low-pass filter to the first x-coordinate signal and the first y-coordinate signal, and outputs a second x-coordinate signal and a second y-coordinate signal.
  • the drawing circuit creates a drawing signal based on the second x-coordinate signal and the second y-coordinate signal output from the filter circuit.
  • the image display device displays an image based on the drawing signal on the image display unit.
  • the filter circuit has different low-pass filter strengths depending on the state of the light pen switch.
  • FIG. 1 is an exploded perspective view showing an example of the structure of a panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
  • FIG. 2 is a diagram showing an example of the electrode arrangement of the panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
  • FIG. 3 is a diagram schematically showing an example of a drive voltage waveform applied to each electrode of the panel in the subfields SF1 to SF3 of the image display subfield in the embodiment of the present invention.
  • FIG. 4 is a diagram schematically showing an example of a drive voltage waveform applied to each electrode of the panel in the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx in the embodiment of the present invention.
  • FIG. 5 is a diagram schematically showing an example of a circuit block and a plasma display system constituting the plasma display device in the embodiment of the present invention.
  • FIG. 6 is a circuit diagram schematically showing a configuration example of the scan electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention.
  • FIG. 7 is a circuit diagram schematically showing a configuration example of the sustain electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention.
  • FIG. 8 is a circuit diagram schematically showing a configuration example of the data electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention.
  • FIG. 5 is a diagram schematically showing an example of a circuit block and a plasma display system constituting the plasma display device in the embodiment of the present invention.
  • FIG. 6 is a circuit diagram schematically showing a configuration example of the scan electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention.
  • FIG. 7 is a circuit diagram schematically showing
  • FIG. 9 is a diagram schematically showing an example of the operation when detecting the position coordinates of the light pen in the plasma display system according to the embodiment of the present invention.
  • FIG. 10 is a diagram schematically showing an example of a drive voltage waveform when detecting the position coordinates of the light pen in the plasma display system according to the embodiment of the present invention.
  • FIG. 11 is a block diagram schematically showing a configuration example of the filter circuit of the plasma display system in accordance with the exemplary embodiment of the present invention.
  • FIG. 12A is a diagram schematically showing an example of an operation when performing handwriting input with a light pen in the plasma display system in accordance with the exemplary embodiment of the present invention.
  • FIG. 12B is a diagram schematically illustrating another example of the operation when performing handwriting input with a light pen in the plasma display system according to the exemplary embodiment of the present invention.
  • FIG. 1 is an exploded perspective view showing an example of the structure of a panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
  • a plurality of display electrode pairs 14 each including a scanning electrode 12 and a sustaining electrode 13 are formed on a glass front substrate 11.
  • a dielectric layer 15 is formed so as to cover the display electrode pair 14, and a protective layer 16 is formed on the dielectric layer 15.
  • the front substrate 11 serves as an image display surface on which an image is displayed.
  • a plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is further formed thereon.
  • the phosphor layer 25R that emits red (R), the phosphor layer 25G that emits green (G), and the phosphor layer that emits blue (B) are formed on the side surfaces of the barrier ribs 24 and the surface of the dielectric layer 23. 25B is provided.
  • the phosphor layer 25R, the phosphor layer 25G, and the phosphor layer 25B are collectively referred to as a phosphor layer 25.
  • the front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 intersect each other with a minute space therebetween, and a discharge space is provided in the gap between the front substrate 11 and the rear substrate 21.
  • the outer peripheral part is sealed with sealing materials, such as glass frit.
  • sealing materials such as glass frit.
  • a mixed gas of neon and xenon is sealed in the discharge space as a discharge gas.
  • the discharge space is partitioned into a plurality of sections by the barrier ribs 24, and discharge cells, which are light-emitting elements constituting the pixels, are formed at the intersections between the display electrode pairs 14 and the data electrodes 22.
  • discharge is generated in these discharge cells, and the phosphor layer 25 emits light (discharge cells are turned on), thereby displaying a color image on the panel 10.
  • one pixel is composed of three consecutive discharge cells arranged in the direction in which the display electrode pair 14 extends.
  • the three discharge cells are a discharge cell having a phosphor layer 25R and emitting red (R) light (hereinafter referred to as “red discharge cell” or “red pixel”), and a phosphor layer 25G.
  • Discharge cells hereinafter referred to as “green discharge cells” or “green pixels”) having a green color (G)
  • green pixels having a phosphor layer 25B.
  • the structure of the panel 10 is not limited to the above-described structure, and may be, for example, provided with a stripe-shaped partition wall.
  • FIG. 2 is a diagram showing an example of the electrode arrangement of the panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
  • n scan electrodes SC1 to SCn scan electrode 12 in FIG. 1
  • n sustain electrodes SU1 to SUn sustain electrode 13 in FIG. 1 extended in the first direction
  • the m data electrodes D1 to Dm data electrode 22 in FIG. 1 extended in the second direction intersecting the first direction are arranged.
  • the first direction is referred to as a row direction (or horizontal direction, line direction, or x coordinate direction), and the second direction is referred to as a column direction (or vertical direction or y coordinate direction).
  • m discharge cells are formed on one pair of display electrodes 14 and m / 3 pixels are formed.
  • the discharge cell having the data electrode Dp + 1 is coated with a green phosphor as the phosphor layer 25G, and this discharge cell becomes a green discharge cell.
  • a blue phosphor is applied as a phosphor layer 25B to the discharge cell having the data electrode Dp + 2, and this discharge cell becomes a blue discharge cell.
  • a red discharge cell, a green discharge cell, and a blue discharge cell adjacent to each other constitute a set to constitute one pixel.
  • one field includes a plurality of image display subfields for displaying an image on the panel 10, a timing detection subfield SFo, a y coordinate detection subfield SFy, and an x coordinate detection subfield SFx.
  • the image display subfield is also simply referred to as a subfield.
  • Each image display subfield has an initialization period, an address period, and a sustain period.
  • initialization discharge is generated in each discharge cell, and wall charges necessary for the subsequent address operation are formed in the discharge cell.
  • priming particles charged particles that assist the generation of discharge
  • address period an address discharge is generated in the discharge cells that should emit light.
  • sustain pulses are alternately applied to the scan electrodes and the sustain electrodes, and a sustain discharge is generated in the discharge cells that have generated the address discharge.
  • the initialization operation in the initialization period includes “forced initialization operation” and “selective initialization operation”, and generated drive voltage waveforms are different from each other.
  • forced initializing operation an initializing discharge is forcibly generated in the discharge cells regardless of the presence or absence of discharge in the immediately preceding subfield.
  • selective initializing operation initializing discharge is selectively generated only in the discharge cells that have generated address discharge in the address period of the immediately preceding subfield.
  • the first subfield (for example, subfield SF1) is set as a subfield (forced initialization subfield) for performing a forced initialization operation, and other subfields are included.
  • a field for example, a subfield after subfield SF2
  • selective initialization subfield for performing a selective initialization operation.
  • a luminance weight is set for each subfield.
  • one field has eight subfields (subfields SF1 to SF8), and each subfield has a luminance of (1, 34, 21, 13, 8, 5, 3, 2).
  • An example of setting a weight is given.
  • the position of the light pen in the image display area is represented by the x coordinate and the y coordinate.
  • the x-coordinate detection subfield SFx and the y-coordinate detection subfield SFy are subfields for detecting the x-coordinate and y-coordinate of the position (position coordinate) of the light pen in the image display area.
  • the light pen is provided in the plasma display system, and is used by a user to input characters and drawings on the panel by handwriting. Details of the light pen will be described later.
  • wireless communication is performed between the light pen and the drawing apparatus.
  • the light pen calculates the position coordinates of the light pen inside the light pen, and transmits data of the calculated position coordinates from the light pen to the drawing apparatus by wireless communication.
  • the light pen side When a signal is wirelessly transmitted from the light pen to the plasma display device, the light pen side must encode the transmission signal in a form that allows wireless communication and wirelessly transmit, and the plasma display device side must decode the received signal. Don't be. The same applies when a signal is wirelessly transmitted from the plasma display device to the light pen.
  • the light pen wirelessly transmits a light reception signal to the plasma display apparatus and the plasma display apparatus receives the light reception signal and calculates the position coordinates. Therefore, it is preferable that the light pen itself calculates the position coordinates of the light pen and wirelessly transmits the calculated position coordinates to the plasma display device.
  • a timing detection subfield SFo is provided in one field so that the timing at which the y coordinate detection subfield SFy and the x coordinate detection subfield SFx are generated can be accurately grasped on the light pen side. That is, the timing detection subfield SFo is for allowing the light pen itself to generate a reference signal (coordinate reference signal) for detecting position coordinates with high accuracy.
  • timing detection subfield SFo a timing detection subfield SFo, a y coordinate detection subfield SFy, and an x coordinate detection subfield SFx are provided in each field.
  • the timing detection subfield SFo, the y coordinate detection subfield is described.
  • SFy and x-coordinate detection subfield SFx are not necessarily provided in each field.
  • the timing detection subfield SFo, the y-coordinate detection subfield SFy, and the x-coordinate detection subfield SFx may be generated at a rate of once per a plurality of fields in accordance with the video signal, the usage state of the plasma display device, and the like. .
  • FIG. 3 schematically shows an example of a drive voltage waveform applied to each electrode of panel 10 in subfields SF1 to SF3 of the image display subfield in the embodiment of the present invention.
  • FIG. 3 shows sustain electrodes SU1 to SUn, scan electrode SC1 that performs the address operation first in the address period, scan electrode SCn that performs the address operation last in the address period (for example, scan electrode SC1080), and data electrode D1 to data electrode.
  • the drive voltage waveform applied to each of Dm (for example, data electrode D5760) is shown.
  • Scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected based on image data (data indicating light emission / non-light emission for each subfield) from among the electrodes.
  • each subfield after subfield SF3 generates a drive voltage waveform substantially similar to that of subfield SF2, except for the number of sustain pulses.
  • the voltage 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn.
  • a scan waveform SC1 to SCn is applied with voltage Vi1 after voltage 0 (V) is applied, and a ramp waveform voltage (hereinafter referred to as “upward ramp waveform voltage”) that gradually rises from voltage Vi1 to voltage Vi2. Apply.
  • the voltage Vi1 is set to a voltage lower than the discharge start voltage for the sustain electrodes SU1 to SUn, and the voltage Vi2 is set to a voltage exceeding the discharge start voltage for the sustain electrodes SU1 to SUn.
  • negative wall voltage is accumulated on scan electrodes SC1 to SCn
  • positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn.
  • priming particles that assist the generation of the address discharge are generated in the discharge cell.
  • the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.
  • the voltage of scan electrodes SC1 to SCn is once lowered to voltage Vi3 lower than voltage Vi2, and then lowered to voltage 0 (V).
  • the voltage Vi3 is set to a voltage lower than the voltage Vi2 and lower than the discharge start voltage with respect to the sustain electrodes SU1 to SUn. Although an example in which the voltage Vi3 is about 200 (V) is shown in this embodiment, the voltage Vi3 may be a voltage that does not cause discharge in the discharge cells. Further, the voltage may be sharply decreased from the voltage Vi2 to the voltage 0 (V).
  • a voltage 0 (V) is applied to the data electrodes D1 to Dm, and a positive voltage Ve is applied to the sustain electrodes SU1 to SUn.
  • the scan electrodes SC1 to SCn have a ramp waveform voltage that gradually falls from a voltage that is less than the discharge start voltage (eg, voltage 0 (V)) to a negative voltage Vi4 (hereinafter also simply referred to as “down ramp waveform voltage”). Is applied. Voltage Vi4 is set to a voltage exceeding the discharge start voltage with respect to sustain electrodes SU1 to SUn.
  • the voltage applied to the scan electrodes SC1 to SCn is set to the voltage Vc.
  • the above-mentioned drive voltage waveform generated in the initialization period Pia1 is a forced initialization waveform.
  • the wall voltage of each discharge cell in which the initializing discharge has occurred can be made substantially uniform.
  • the forced initializing operation is described as an initializing operation for forcibly generating an initializing discharge in all the discharge cells in the image display area of panel 10, but the present invention is not limited to this. It is not limited to the configuration.
  • an operation for applying a forced initialization waveform only to a part of the discharge cells in the image display area of the panel is also a forced initialization operation, and a subfield for performing the forced initialization operation is forcibly initialized.
  • Subfield For example, in the odd-field subfield SF1, the forced initializing waveform is applied only to the odd-numbered scan electrodes SC (2N-1) (N is an integer of 1 or more), and the other scan electrodes SC (2N) are described later.
  • a selective initialization waveform is applied.
  • a forced initialization waveform is applied only to the even-numbered scan electrode SC (2N), and a selective initialization waveform is applied to the other scan electrode SC (2N-1).
  • the scan electrodes SC1 to SCn to which the forced initialization waveform is applied may be changed for each field. The same applies to all subfields that perform the forced initialization operation in the following description.
  • voltage 0 (V) is applied to data electrodes D1 to Dm
  • voltage Ve is applied to sustain electrodes SU1 to SUn
  • voltage Vc is applied to scan electrodes SC1 to SCn.
  • a negative scan pulse having a negative voltage Va is applied to the scan electrode SC1 in the first row.
  • a positive address pulse of a positive voltage Vd is applied to the data electrode Dk of the discharge cell that should emit light in the first row of the data electrodes D1 to Dm.
  • a scan pulse of voltage Va is applied to scan electrode SC2 in the second row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light in the second row.
  • address discharge occurs in the discharge cells in the second row to which the scan pulse and address pulse are simultaneously applied. Address discharge does not occur in the discharge cells to which no address pulse is applied. Thus, the address operation in the discharge cells in the second row is performed.
  • the order in which the scan pulses are applied to the scan electrodes SC1 to SCn is not limited to the order described above.
  • the order in which the scan pulses are applied to the scan electrodes SC1 to SCn may be arbitrarily set according to the specifications of the image display device.
  • voltage 0 (V) is applied to the data electrodes D1 to Dm. Then, a sustain pulse of positive voltage Vs is applied to scan electrodes SC1 to SCn, and voltage 0 (V) is applied to sustain electrodes SU1 to SUn.
  • a sustain discharge is generated between the scan electrode SCi and the sustain electrode SUi in the discharge cell that has generated the address discharge in the immediately preceding address period Pw1.
  • the phosphor layer 25 of the discharge cell emits light due to the ultraviolet rays generated by the sustain discharge.
  • a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is also accumulated on the data electrode Dk.
  • the sustain discharge does not occur in the discharge cells in which the address discharge has not occurred in the immediately preceding address period Pw1, and the wall voltage at the end of the initialization period Pia1 is maintained.
  • the number of sustain pulses obtained by multiplying the brightness weight by a predetermined brightness multiple is alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn.
  • the discharge cells that have generated the address discharge in the immediately preceding address period Pw1 generate the sustain discharge the number of times corresponding to the luminance weight, and emit light with the luminance corresponding to the luminance weight.
  • voltage 0 (V) is applied to sustain electrodes SU1 to SUn and data electrodes D1 to Dm, and applied to scan electrodes SC1 to SCn.
  • An upward ramp waveform voltage that gradually rises from the voltage 0 (V) to the positive voltage Vr is applied.
  • the negative wall voltage is accumulated on the sustain electrode SUi and the positive wall voltage is accumulated on the scan electrode SCi, so that the discharge start voltage of those discharge cells is exceeded.
  • the voltage Vr is set as the voltage.
  • the wall voltage on the scan electrode SCi and the wall voltage on the sustain electrode SUi are weakened while leaving the positive wall voltage on the data electrode Dk, and unnecessary wall charges in the discharge cell are erased.
  • the selective initialization subfield will be described by taking the subfield SF2 as an example.
  • the same drive voltage waveform as that in the initialization period Pib2 of the subfield SF2 is applied to each electrode to perform the selective initialization operation. .
  • the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn.
  • a downward ramp waveform voltage that falls from a voltage (for example, voltage 0 (V)) that is lower than the discharge start voltage to a negative voltage Vi4 is applied to scan electrodes SC1 to SCn.
  • This downward ramp waveform voltage has a waveform shape that drops to the same voltage Vi4 at the same gradient as the downward ramp waveform voltage generated in the initialization period Pia1.
  • This initialization discharge weakens the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi.
  • the positive wall voltage accumulated on the data electrode Dk by the last sustain discharge is adjusted to a wall voltage suitable for the address operation by discharging an excessive portion.
  • the initialization discharge does not occur, and the wall voltage at the end of the initialization period Pia1 of the subfield SF1 is maintained.
  • the voltage applied to the scan electrodes SC1 to SCn is set to the voltage Vc.
  • the above-mentioned drive voltage waveform generated in the initialization period Pib2 is a selective initialization waveform.
  • the voltage Vi4 and the voltage Ve are set to voltage values that satisfy the above-described operation according to the characteristics of the panel 10, the specifications of the plasma display device 30, and the like.
  • the drive voltage waveforms similar to those in the address period Pw1 and the sustain period Ps1 in the subfield SF1 are applied to the respective electrodes, except for the number of sustain pulses generated, and thus the description thereof is omitted.
  • each subfield after subfield SF3 the drive voltage waveform similar to that in subfield SF2 is applied to each electrode except for the number of sustain pulses, and the description thereof is omitted.
  • the subfield for performing the forced initialization operation is the subfield SF1, but the present invention is not limited to this configuration.
  • the subfield in which the forced initialization operation is performed may be a subfield after subfield SF2.
  • the present invention is not limited to this configuration.
  • the number of times of performing the forced initialization operation may be once in a plurality of fields.
  • the coordinate detection subfield is a generic name for the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx.
  • FIG. 4 schematically shows an example of a drive voltage waveform applied to each electrode of panel 10 in timing detection subfield SFo, y coordinate detection subfield SFy, and x coordinate detection subfield SFx in the embodiment of the present invention. It is.
  • FIG. 4 in the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx, the sustain electrodes SU1 to SUn, the scan electrode SC1, the scan electrode SCn, and the data electrodes D1 to Dm are applied.
  • a drive voltage waveform is shown.
  • FIG. 4 also shows a part of the sustain period Ps8 of the subfield SF8 immediately before the timing detection subfield SFo and a part of the subfield SF1.
  • the timing detection subfield SFo has an initialization period Piao, an address period Pwo, and a timing detection period Po.
  • a driving voltage waveform similar to that in the initialization period Pia1 of the subfield SF1 of the image display subfield is applied to each electrode to perform the same forced initialization operation, and thus description thereof is omitted.
  • the voltage 0 (V) is applied to the data electrodes D1 to Dm
  • the voltage Ve is applied to the sustain electrodes SU1 to SUn
  • the voltage Vc is applied to the scan electrodes SC1 to SCn.
  • an address pulse of the voltage Vd is applied to the data electrodes D1 to Dm and a scan pulse of the voltage Va is applied to the scan electrodes SC1 to SCn to generate an address discharge in each discharge cell.
  • the scan pulse is sequentially applied to each of the electrodes from the scan electrode SC1 to the scan electrode SCn while applying the write pulse to all the data electrodes D1 to Dm. It is also possible to apply a scan pulse to all the scan electrodes SC1 to SCn at a time and generate an address discharge in all the discharge cells in the image display area of the panel 10 at the same time.
  • the voltage 0 (V) is applied to the data electrodes D1 to Dm. Further, voltage Vc is applied to scan electrodes SC1 to SCn, and then voltage 0 (V) is applied. Further, the voltage applied to sustain electrodes SU1 to SUn is changed from voltage Ve to voltage 0 (V). In the present embodiment, this state is maintained from time to0 to time To0. Therefore, during this period, after the last address discharge occurs in the discharge cells, a state in which no discharge occurs is maintained. Time to0 is the time when the scan pulse for generating the last address discharge is applied to scan electrode SCn.
  • the time To0 is set to a time longer than any of the time To1, the time To2, and the time To3 described later.
  • the time To0 is about 50 ⁇ sec, for example.
  • the panel 10 is caused to emit a plurality of times of light emission (light emission for timing detection) as a reference when calculating the position coordinates of the light pen. That is, light emission for timing detection is emitted to all the discharge cells in the image display area of the panel 10 at a predetermined time interval (in this embodiment, for example, time To1, time To2, and time To3 in this embodiment).
  • the timing detection discharge to be generated is generated a plurality of times (in this embodiment, for example, four times).
  • timing detection pulse V1 of voltage Vso is applied to scan electrodes SC1 to SCn.
  • first timing detection discharge is generated in all the discharge cells in the image display area of the panel 10, and the entire image display surface of the panel 10 emits light (first timing detection light emission).
  • timing detection pulse V3 of voltage Vso is applied to scan electrodes SC1 to SCn.
  • the third timing detection discharge is generated in all the discharge cells in the image display region of the panel 10, and the entire image display surface of the panel 10 emits light (third timing detection light emission).
  • a predetermined time interval in the present embodiment, for example, time To1, time To2, and time To3 in this embodiment
  • time To1, time To2, and time To3 in this embodiment is multiple times (in this embodiment, for example, 4 Timing detection discharge is generated, and the entire image display surface of the panel 10 is caused to emit light a plurality of times (for example, four times) at predetermined time intervals (for example, time To1, time To2, and time To3).
  • the light pen receives this light emission and creates a coordinate reference signal (a signal that becomes a reference when calculating the position coordinates (x coordinate, y coordinate) of the light pen).
  • the entire surface of the image display surface of the panel 10 shines at the same timing, so that the light pen is at the same timing no matter where the tip of the light pen is in the image display area of the panel 10. This light emission can be received.
  • the time To1 is about 40 ⁇ sec
  • the time To2 is about 20 ⁇ sec
  • the time To3 is about 30 ⁇ sec.
  • the present invention is not limited to the numerical values described above for the times To0 to To3, and each time may be set appropriately according to the specifications of the plasma display system.
  • the light pen generates a coordinate reference signal when it detects a plurality of times (for example, four times) of light emission occurring at a predetermined time interval (for example, time To1, time To2, and time To3).
  • timing detection period Po of the timing detection subfield SFo after the generation of the timing detection pulse V4 (the end of the timing detection period Po), an erase operation similar to the erase operation performed at the end of the sustain period Ps1 of the subfield SF1 is performed. . Thereby, a weak erasure discharge is generated in all the discharge cells in the image display area of the panel 10.
  • the voltage Vso is set to a voltage equal to the voltage Vs.
  • the voltage Vso is about 205 (V).
  • the voltage Vso may be a voltage different from the voltage Vs.
  • the voltage Vso may be any voltage that generates timing detection discharge.
  • a y-coordinate detection subfield SFy and an x-coordinate detection subfield SFx are generated.
  • the y coordinate detection subfield SFy has an initialization period Piby and a y coordinate detection period Py.
  • timing detection discharges are generated in all the discharge cells in the image display area of the panel 10, and therefore in the initialization period Piby A weak initializing discharge is generated in all discharge cells.
  • the wall voltage of all the discharge cells in the image display area of the panel 10 is adjusted to the wall voltage suitable for the y coordinate detection pattern display operation in the subsequent y coordinate detection period Py.
  • priming particles that assist the generation of discharge in the y-coordinate detection period Py are generated in the discharge cell.
  • the voltage Ve is applied to the sustain electrodes SU1 to SUn
  • the voltage 0 (V) is applied to the data electrodes D1 to Dm
  • the scan electrodes SC1 to SCn are applied to SCn.
  • y coordinate detection voltage Vdy is a voltage higher than the voltage 0 (V)
  • the voltage Vay of the y coordinate detection pulse is a negative voltage lower than the voltage Vc.
  • the pulse width of the y coordinate detection pulse is shown as Ty1.
  • the data electrodes D1 to Dm and the scan electrodes The voltage difference at the intersection with SC1 exceeds the discharge start voltage, and discharge occurs between data electrodes D1 to Dm and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1.
  • discharge occurs in all the discharge cells constituting the first row, and these discharge cells emit light all at once.
  • the 5760 discharge cells (1920 pixels) constituting the first row emit light all at once. And this light emission becomes light emission for y coordinate detection.
  • discharge cell row an aggregate of discharge cells constituting one row
  • pixel row an aggregate of pixels constituting one row
  • the discharge cell row and the pixel row are substantially the same, and in the above operation, the first pixel row (first discharge cell row) emits light all at once.
  • a positive wall voltage is accumulated on scan electrode SC1
  • a negative wall voltage is accumulated on sustain electrode SU1
  • a negative wall voltage is also formed on data electrodes D1 to Dm. Is accumulated.
  • a y coordinate detection pulse of the voltage Vay is applied to the scan electrode SC2 in the second row.
  • light emission for y coordinate detection occurs in the second pixel row (second discharge cell row).
  • one horizontal line that emits light corresponds to the upper end portion (pixels in the first row) of the image display area of the panel 10.
  • a pattern (y-coordinate detection pattern) that sequentially moves one line at a time from the lower line to the lower end (nth pixel line) is displayed. That is, the y-coordinate detection pattern is a pattern in which each pixel row from the first row to the n-th row of the image display area sequentially emits light for each row.
  • each pixel row from the first row to the n-th row of the image display region emits light sequentially for each row, so that the tip of the light pen is the image display region of the panel 10
  • the timing at which the light pen receives this light emission varies depending on where the light pen is.
  • the y coordinate of the position (x coordinate, y coordinate) of the light pen in the image display area is detected by detecting the light reception timing when the light emission is received by the light pen.
  • the period during which the y-coordinate detection pattern is displayed on the panel 10 is very short. Therefore, the possibility that the y-coordinate detection pattern is recognized by the user is low, and even if it is recognized by the user, it is only a slight change in luminance.
  • the subsequent x coordinate detection subfield SFx has an initialization period Piax and an x coordinate detection period Px.
  • a driving voltage waveform similar to that in the initialization period Pia1 of the subfield SF1 of the image display subfield is applied to each electrode to perform the same forced initialization operation, and thus description thereof is omitted.
  • the initialization discharge is generated in all the discharge cells in the image display area of the panel 10.
  • the wall voltage of all the discharge cells in the image display area of the panel 10 is adjusted to the wall voltage suitable for the x coordinate detection pattern display operation in the subsequent x coordinate detection period Px.
  • priming particles that assist the generation of discharge in the x-coordinate detection period Px are generated in the discharge cell.
  • the voltage 0 (V) is applied to the data electrodes D1 to Dm
  • the voltage Ve is applied to the sustain electrodes SU1 to SUn
  • the scan electrodes SC1 to SCn are applied.
  • a voltage Vc is applied to SCn.
  • the negative x coordinate detection voltage Vax is applied to the scan electrodes SC1 to SCn, and the positive x coordinate of the voltage Vdx is applied to the data electrodes D1 to D3 in the first to third columns.
  • Apply detection pulse The voltage Vdx of the x coordinate detection pulse is higher than the voltage 0 (V), and the x coordinate detection voltage Vax is a negative voltage lower than the voltage Vc.
  • the pulse width of the x coordinate detection pulse is shown as Tx1.
  • the data electrodes D1 to D3 correspond to a red discharge cell, a green discharge cell, and a blue discharge cell constituting one pixel, and the pixel is a pixel arranged at the left end of the image display area, for example. It is.
  • the data electrodes D1 to D3 and the scan electrodes SC1 to SC1 In the discharge cell at the intersection of the data electrodes D1 to D3 to which the x coordinate detection pulse of the voltage Vdx is applied and the scan electrodes SC1 to SCn to which the x coordinate detection voltage Vax is applied, the data electrodes D1 to D3 and the scan electrodes SC1 to SC1 The voltage difference at the intersection with SCn exceeds the discharge start voltage, and discharge occurs between data electrodes D1 to D3 and scan electrodes SC1 to SCn and between sustain electrodes SU1 to SUn and scan electrodes SC1 to SCn. .
  • discharge occurs in all the pixels constituting the first column, and these pixels emit light all at once.
  • the 1080 pixels (3 columns ⁇ 1080 discharge cells) constituting the first column emit light all at once. And this light emission becomes light emission for x coordinate detection.
  • discharge cell column an assembly of discharge cells constituting one column
  • pixel column an assembly of discharge cells (pixel column) composed of three adjacent discharge cell columns
  • the first pixel column that is, the first, second, and third discharge cell columns
  • the x coordinate detection pulse of the voltage Vdx is applied to the data electrodes D4 to D6 in the fourth column to the sixth column.
  • light emission for x coordinate detection occurs in the second pixel column (fourth, fifth, and sixth discharge cell columns).
  • Similar operations are performed adjacent to each other in the order of data electrodes D7 to D9, data electrodes D10 to D12,..., Data electrodes Dm-2 to Dm, with the x coordinate detection voltage Vax being applied to scan electrodes SC1 to SCn.
  • Each of the three data electrodes 22 is sequentially performed until reaching the m-th discharge cell, and light emission for x coordinate detection is performed on each pixel column from the third column to the last column (for example, 1920 column). Generate sequentially.
  • the x coordinate detection pattern is a pattern in which each pixel column from the first column to the last column in the image display area sequentially emits light for each column.
  • the x-coordinate detection pattern is a pattern in which three discharge cell columns adjacent to each other sequentially emit light by three columns from the left end (first column) to the right end (m column) of the image display area. is there.
  • each pixel column from the first column to the last column in the image display region sequentially emits light for each column, so that the tip of the light pen is the image display region of the panel 10.
  • the timing at which the light pen receives this light emission varies depending on where the light pen is.
  • the x coordinate of the position (x coordinate, y coordinate) of the light pen in the image display area is detected.
  • the period during which the x-coordinate detection pattern is displayed on the panel 10 is very short. Therefore, the possibility that the x coordinate detection pattern is recognized by the user is low, and even if it is recognized by the user, it is only a slight change in luminance.
  • the above is the outline of the drive voltage waveforms of the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx.
  • voltage Vc ⁇ 50 (V)
  • voltage Vr 205 (V)
  • voltage Ve 155 (V )
  • the voltage Va, the voltage Vay, and the voltage Vax are set to be equal to each other, and the voltage Vd, the voltage Vdy, and the voltage Vdx are set to be equal to each other. Different voltages may be used.
  • a voltage Vi2 of the rising ramp waveform voltage generated in the initialization period Pia1 of the subfield SF1 a voltage Vi2 of the rising ramp waveform voltage generated in the initialization period Piao of the timing detection subfield SFo
  • the voltage Vi2 of the rising ramp waveform voltage generated in the initialization period Piax of the x-coordinate detection subfield SFx is set to be equal to each other, but each voltage Vi2 may be set to a different voltage.
  • the gradient of the rising ramp waveform voltage generated in the initialization period Pia1 of the subfield SF1, the initialization period Piao of the timing detection subfield SFo, and the initialization period Piax of the x coordinate detection subfield SFx is about 1.5 (V / ⁇ sec).
  • the gradient of the downward ramp waveform voltage generated in the initialization period Piax of the detection subfield SFx is about ⁇ 2.5 (V / ⁇ sec).
  • the gradient of the rising ramp waveform voltage generated at the end of each sustain period Ps1 to Ps8 of the image display subfield (subfields SF1 to SF8) and at the end of the timing detection period Po of the timing detection subfield SFo is about 10 (V / ⁇ sec).
  • the specific numerical values such as the voltage value and the gradient described above are merely examples, and the present invention is not limited to the numerical values described above for each voltage value and the gradient.
  • Each voltage value, gradient, and the like are preferably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.
  • the reason why the timing detection subfield SFo is provided in one field and each drive voltage waveform of the timing detection subfield SFo is generated with the waveform shape shown in FIG. 4 is as follows.
  • the light pen itself can generate a coordinate reference signal (a signal indicating the generation timing of the y-coordinate detection period Py and the x-coordinate detection period Px), and the timing detection subfield in one field.
  • SFo is provided.
  • the light pen detects light emission generated at a specific time interval on the panel 10 by timing detection discharge, and generates a coordinate reference signal. Based on this coordinate reference signal, the light pen calculates the position coordinates of the light pen itself.
  • each drive voltage waveform of the timing detection subfield SFo is generated with the waveform shape shown in FIG. 4, and the time To0 is set to the time To1.
  • the time To0 is set to a time longer than any of the time To1, the time To2, and the time To3. This is due to the following reasons.
  • the light receiving element of the light pen also detects light emission generated by address discharge. Therefore, depending on the set value of time To0, the light pen may misrecognize the light emission generated by the address discharge in the address period Pwo of the timing detection subfield SFo as the light emission by the timing detection discharge.
  • the time To0 is set to a time longer than the time To1, no matter where the light pen is in the image display area, the time from the time when the light pen detects light emission due to the write discharge to the time to1 The interval is longer than time To1. Thereby, it is possible to prevent the light pen from erroneously recognizing light emission due to the address discharge generated in the address period Pwo of the timing detection subfield SFo as light emission due to the timing detection discharge. If the time To0 is set to a time longer than any of the time To1, the time To2, and the time To3, the erroneous recognition can be prevented with higher accuracy, and the write in the image display area can be prevented. It becomes possible to detect the position (position coordinates) of the pen more accurately.
  • the image display device detects the position (positional coordinates) of the light pen in the image display area while displaying an image corresponding to the image signal on the panel 10 by the above-described operation. Discharge can be generated stably, and the position coordinates of the light pen can be calculated with high accuracy.
  • FIG. 5 is a diagram schematically showing an example of a circuit block and a plasma display system 100 that constitute the plasma display device 30 according to the embodiment of the present invention.
  • the plasma display system 100 shown in the present embodiment includes a plasma display device 30, a drawing device 40, and a light pen 50 as components.
  • the drawing device 40 includes a receiving circuit 42, a filter circuit 44, and a drawing circuit 46.
  • the plasma display device 30 includes a panel 10 and a driving circuit that drives the panel 10 with a plurality of subfields in one field.
  • the drive circuit includes an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit (not shown) that supplies power necessary for each circuit block. ).
  • the image signal processing circuit 31 receives an image signal, a drawing signal output from the drawing device 40, and a timing signal supplied from the timing generation circuit 35.
  • the image signal processing circuit 31 combines the image signal and the drawing signal in order to display an image obtained by combining the image signal and the drawing signal on the panel 10, and applies red, green to each discharge cell based on the combined signal. , Blue gradation values (gradation values expressed by one field) are set.
  • the image signal processing circuit 31 switches each of the image signal and the drawing signal and displays them on the panel 10, so that each discharge cell has a gradation value of red, green, and blue based on either the image signal or the drawing signal. Set.
  • the image signal processing circuit 31 uses the red, green, and blue gradation values set for each discharge cell as image data indicating lighting / non-lighting for each subfield (light emission / non-light emission is “1” of the digital signal). , Data corresponding to “0”), and output the image data (red image data, green image data, and blue image data).
  • the timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal.
  • the generated timing signal is supplied to each circuit block (data electrode drive circuit 32, scan electrode drive circuit 33, sustain electrode drive circuit 34, image signal processing circuit 31, etc.).
  • the data electrode driving circuit 32 Based on the image data output from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35, the data electrode driving circuit 32 performs the writing periods Pw1 to Pw1 of the subfields SF1 to SF8 which are image display subfields.
  • the writing pulse of the voltage Vd is used
  • the y coordinate detection period Py of the y coordinate detection subfield SFy the y coordinate detection voltage Vdy is used
  • the x coordinate detection subfield SFx the x coordinate detection period.
  • an x-coordinate detection pulse of voltage Vdx is applied to each data electrode D1 to Dm.
  • Sustain electrode drive circuit 34 includes a sustain pulse generation circuit and a circuit (not shown in FIG. 5) for generating voltage Ve, and generates each drive voltage waveform based on the timing signal supplied from timing generation circuit 35.
  • the voltage is applied to each of the sustain electrodes SU1 to SUn.
  • the sustain pulse of the voltage Vs is used in the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8, which are image display subfields.
  • the voltage Vso (equal to the voltage Vs in the present embodiment).
  • Scan electrode drive circuit 33 includes a ramp waveform voltage generation circuit, a sustain pulse generation circuit, and a scan pulse generation circuit (not shown in FIG. 5), and each drive voltage waveform is based on a timing signal supplied from timing generation circuit 35. Is applied to each of scan electrodes SC1 to SCn.
  • the ramp waveform voltage generating circuit based on the timing signal, initializes the initialization periods Pia1, Pib2 to Pib8 and the sustain periods Pw1 to Pw8 of the subfields SF1 to SF8, which are image display subfields, and the initialization period of the timing detection subfield SFo.
  • a ramp waveform voltage is applied to scan electrodes SC1 to SCn in Piao, timing detection period Po, initialization period Piby of y-coordinate detection subfield SFy, and initialization period Piax of x-coordinate detection subfield SFx.
  • the sustain pulse generating circuit Based on the timing signal, the sustain pulse generating circuit generates sustain pulses in the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8 that are image display subfields, and the voltage Vso (this implementation) in the timing detection period Po of the timing detection subfield SFo.
  • timing detection pulses V1 and V3 equal to the voltage Vs
  • the scan pulse generation circuit includes a plurality of scan electrode driving ICs (scan ICs), and based on the timing signal, the writing periods Pw1 to Pw8 of the subfields SF1 to SF8 that are image display subfields and the timing detection subfield Sfo
  • scanning pulses of the voltage Vc and the voltage Va are used, in the y coordinate detection period Py of the y coordinate detection subfield SFy, the y coordinate detection pulse of the voltage Vc and voltage Vay is used, and the x coordinate detection period of the x coordinate detection subfield SFx.
  • voltage Vc and x-coordinate detection voltage Vax are applied to scan electrodes SC1 to SCn.
  • the light pen 50 is used when the user inputs characters, drawings and the like in the image display area of the panel 10 by handwriting.
  • the light pen 50 is formed in a rod shape and includes a light receiving element 52, a contact switch 53, a timing detection circuit 54, a coordinate calculation circuit 56, and a transmission circuit 58.
  • the contact switch 53 is provided at the tip of the light pen 50 and detects whether or not the tip of the light pen 50 has contacted the front substrate 11 of the panel 10 (the image display surface of the panel 10). The contact switch 53 is turned on to output “1” if the tip of the light pen 50 is in contact with the panel 10, and is turned off to output “0” if not in contact.
  • the light receiving element 52 receives light emitted from the image display surface of the panel 10 and converts it into an electric signal (light receiving signal). Then, the light reception signal is output to the timing detection circuit 54 and the coordinate calculation circuit 56.
  • the position coordinates (x, y) of the light pen 50 are positions where the light receiving element 52 receives light emitted from the image display surface of the panel 10.
  • the timing detection circuit 54, the coordinate calculation circuit 56, and the transmission circuit 58 operate as follows regardless of whether or not the contact switch 53 detects contact.
  • the timing detection circuit 54 detects light emission for timing detection (light emission generated by the timing detection discharge) generated in the timing detection period Po of the timing detection subfield SFo based on the light reception signal. Specifically, the timing detection circuit 54 measures a time interval of a plurality of (for example, five times) emission using a timer (not shown in FIG. 5) included in the timing detection circuit 54. Then, whether or not the time interval matches a predetermined time interval (for example, time To0, time To1, time To2, time To3) is determined by a plurality of threshold values (set in the timing detection circuit 54). For example, the determination is made by comparing the measured time interval with a threshold value corresponding to time To0, time To1, time To2, and time To3.
  • a predetermined time interval for example, time To0, time To1, time To2, and time To3.
  • the timing detection circuit 54 generates a coordinate reference signal based on one of the continuous plural times (for example, five times) of light emission.
  • the coordinate reference signal is generated based on the light emission generated at the time to1 in the timing detection period Po of the timing detection subfield SFo.
  • the time to1 is the time when the first timing detection pulse V1 is applied to the scan electrodes SC1 to SCn in the timing detection period Po of the timing detection subfield SFo.
  • the coordinate reference signal is not shown in FIG. 4, but is, for example, a signal having rising edges at time ty0 and time tx0.
  • Time ty0 is a time at which a y-coordinate detection pulse is applied to scan electrode SC1 in the first row in y-coordinate detection period Py of y-coordinate detection subfield SFy.
  • Time tx0 is a time at which an x-coordinate detection pulse is applied to the data electrodes D1 to D3 corresponding to the first pixel column in the x-coordinate detection period Px of the x-coordinate detection subfield SFx.
  • the timing detection circuit 54 outputs the coordinate reference signal to the coordinate calculation circuit 56.
  • the coordinate reference signal may be generated on the basis of the time to2 at which the second timing detection pulse V2 is generated, or the time to3 at which the third timing detection pulse V3 is generated or the fourth timing detection pulse V4. You may generate
  • the coordinate reference signal is not limited to a signal having rising edges at time ty0 and time tx0.
  • the coordinate reference signal may be any signal that can be used as a reference for specifying the time when the light receiving element 52 receives light emission by the y coordinate detection pattern and light emission by the x coordinate detection pattern.
  • the coordinate calculation circuit 56 includes a counter that measures the length of time and an arithmetic circuit that performs an operation on the output of the counter (not shown in FIG. 5).
  • the coordinate calculation circuit 56 selectively extracts a signal indicating the light emission of the y coordinate detection pattern and a signal indicating the light emission of the x coordinate detection pattern from the light reception signal, and writes the light in the image display area.
  • the position (x coordinate, y coordinate) of the pen 50 is calculated.
  • the coordinate calculation circuit 56 counts the time (time Tyy) from time ty0 to the time (time tyy) from which light is first received by the light receiving element 52 after time ty0 based on the coordinate reference signal. Measure with Then, the time Tyy is divided by the time Ty1 (pulse width of the y coordinate detection pulse) in the arithmetic circuit. In this way, the y coordinate (that is, the first y coordinate) of the position of the light pen 50 in the image display area is calculated.
  • the coordinate calculation circuit 56 measures, based on the coordinate reference signal, a time (time Txx) from time tx0 to time (time txx) when light is first received by the light receiving element 52 after time tx0. To do. Then, the time Txx is divided by the time Tx1 (pulse width of the x coordinate detection pulse) in the arithmetic circuit. In this way, the x coordinate (that is, the first x coordinate) of the position of the light pen 50 in the image display area is calculated.
  • the time tyy is the time when the light receiving element 52 of the light pen 50 receives light emitted from the panel 10 by the y coordinate detection pattern
  • the time txx is the time when the light receiving element 52 of the light pen 50 receives the panel 10 by the x coordinate detection pattern. It is the time when the light emission generated in
  • the coordinate calculation circuit 56 outputs the position coordinates (x, y) of the light pen 50 calculated in this way to the transmission circuit 58.
  • the first x coordinate signal representing the first x coordinate and the first y coordinate signal representing the first y coordinate are output to the transmission circuit 58.
  • the transmission circuit 58 has a transmission circuit that encodes an electric signal and converts the encoded signal into a radio signal such as infrared rays and transmits the signal (not shown in FIG. 5).
  • the reception circuit 42 includes a conversion circuit that receives a wireless signal transmitted wirelessly from the transmission circuit 58 of the light pen 50, decodes the received signal, and converts it into an electrical signal (not shown in FIG. 5).
  • the wireless signal wirelessly transmitted from the transmission circuit 58 is converted into a signal representing the position coordinates (x, y) of the light pen 50 and a signal S representing the state of the contact switch 53 and output to the filter circuit 44.
  • each signal input to the filter circuit 44 will be referred to below.
  • the filter circuit 44 filters the x coordinate X (t) and the y coordinate Y (t) to obtain the second x coordinate and the second y coordinate, and outputs them to the subsequent circuit. That is, the second x coordinate signal representing the second x coordinate and the second y coordinate signal representing the second y coordinate are output to the drawing circuit 46.
  • the filter in the filter circuit 44 is a low-pass filter, and the strength of the filter is controlled according to the state S (t) indicating the state of the contact switch 53 of the light pen 50 and the moving speed of the light pen 50.
  • the signal of each coordinate after the filtering process is referred to as an x coordinate FX (t) and a y coordinate FY (t). That is, the x coordinate FX (t) is a second x coordinate signal, and the y coordinate FY (t) is a second y coordinate signal.
  • the filter circuit 44 outputs the filtered x-coordinate FX (t) and y-coordinate FY (t) to the drawing circuit 46, and sets a time delay corresponding to the time required for the filter processing to the state S (t). To a state FS (t) and output to the drawing circuit 46. Details of the filter circuit 44 will be described later.
  • the drawing circuit 46 includes an image memory 47.
  • the drawing circuit 46 has an x-coordinate FX (t ⁇ 1) and a y-coordinate FY (t ⁇ 1) representing the position coordinates one field before.
  • the drawing circuit 46 outputs the drawing signal stored in the image memory 47 to the image signal processing circuit 31. Therefore, the drawing signal output from the drawing circuit 46 represents the past locus of the position coordinates of the light pen 50 when the light pen 50 is in contact with the panel 10 and the current position coordinates of the light pen 50. Become.
  • the drawing signal is a signal for displaying on the panel 10 an image handwritten by the user or a cursor used as a pointer, and is substantially the same as the image signal.
  • the image signal processing circuit 31 synthesizes the drawing signal output from the drawing circuit 46 and the image signal (or selects one of the drawing signal and the image signal) and converts it into image data. , Output to the subsequent circuit. In this way, the graphic input handwritten by the light pen 50 is combined with the image based on the image signal (or alone) and displayed on the panel 10.
  • the light pen 50 may be provided with a switch for switching between the “drawing” mode and the “erasing” mode.
  • the trace of the light pen 50 shown on the panel 10 is traced with the light pen 50 again, so that the drawing signal stored in the image memory 47 can be partially or totally. You may comprise so that it may erase
  • FIG. 6 is a circuit diagram schematically showing a configuration example of the scan electrode drive circuit 33 of the plasma display device 30 according to the embodiment of the present invention.
  • the scan electrode drive circuit 33 includes a sustain pulse generation circuit 55, a ramp waveform voltage generation circuit 60, and a scan pulse generation circuit 70. Each circuit block operates based on the timing signal supplied from the timing generation circuit 35, but details of the timing signal path are omitted in FIG. Hereinafter, the voltage input to the scan pulse generation circuit 70 is referred to as “reference potential A”.
  • Sustain pulse generation circuit 55 has power recovery circuit 51, switching element Q55, switching element Q56, and switching element Q59.
  • the power recovery circuit 51 includes a power recovery capacitor C10, a switching element Q11, a switching element Q12, a backflow prevention diode Di11, a diode Di12, a resonance inductor L11, and an inductor L12.
  • the power recovery circuit 51 recovers the power stored in the panel 10 from the panel 10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L12, and stores it in the capacitor C10. Then, the recovered power is supplied to the panel 10 again from the capacitor C10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L11, and reused as power when driving the scan electrodes SC1 to SCn.
  • Switching element Q55 clamps scan electrodes SC1 to SCn to voltage Vs
  • switching element Q56 clamps scan electrodes SC1 to SCn to voltage 0 (V).
  • the switching element Q59 is a separation switch, and prevents a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 33.
  • the scan pulse generation circuit 70 sequentially applies scan pulses to the scan electrodes SC1 to SCn at the timings shown in FIGS. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 55 as it is during the sustain period. That is, the reference potential A is output to scan electrodes SC1 to SCn.
  • a voltage Vc and an x-coordinate detection voltage Vax are generated and applied to the scan electrodes SC1 to SCn.
  • the ramp waveform voltage generation circuit 60 includes a Miller integration circuit 61, a Miller integration circuit 62, and a Miller integration circuit 63, and generates the ramp waveform voltage shown in FIGS.
  • the voltage Vt may be set so that a voltage obtained by superimposing the voltage Vp on the voltage Vt is equal to the voltage Vi2.
  • switching element Q72 and switching elements Q71L1 to Q71Ln are turned off, switching elements Q71H1 to Q71Hn are turned on, and the rising ramp waveform voltage generated in Miller integrating circuit 61 is turned on.
  • the up slope waveform voltage for the initialization operation can be generated by superimposing the voltage Vp of the power source E71 on the top.
  • Miller integrating circuit 62 includes transistor Q62, capacitor C62, resistor R62, and diode Di62 for preventing backflow. Then, by applying a constant voltage to the input terminal IN62 (giving a constant voltage difference between two circles shown as the input terminal IN62), an up-slope waveform voltage that gradually rises toward the voltage Vr ( Ascending waveform voltage generated at the end of the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8, which are image display subfields, and at the end of the timing detection period Po of the timing detection subfield SFo.
  • Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63. Then, by applying a constant voltage to the input terminal IN63 (giving a constant voltage difference between two circles shown as the input terminal IN63), a downward ramp waveform voltage (gradiently decreasing toward the voltage Vi4 ( Initialization periods Pia1, Pib2 to Pib8 of subfields SF1 to SF8 which are image display subfields, initialization period Piao of timing detection subfield SFo, initialization period Piby of y coordinate detection subfield SFy, and x coordinate detection sub A downward ramp waveform voltage generated in each period of the initialization period Piax of the field SFx).
  • the switching element Q69 is a separation switch, and prevents a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 33.
  • switching elements and transistors can be configured using generally known semiconductor elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the respective switching elements and transistors generated by the timing generation circuit 35.
  • FIG. 7 is a circuit diagram schematically showing a configuration example of the sustain electrode drive circuit 34 of the plasma display device 30 according to the embodiment of the present invention.
  • the sustain electrode driving circuit 34 includes a sustain pulse generating circuit 80 and a constant voltage generating circuit 85. Each circuit block operates based on the timing signal supplied from the timing generation circuit 35, but details of the timing signal path are omitted in FIG.
  • Sustain pulse generation circuit 80 has a power recovery circuit 81, a switching element Q83, and a switching element Q84.
  • the power recovery circuit 81 includes a power recovery capacitor C20, a switching element Q21, a switching element Q22, a backflow prevention diode Di21, a diode Di22, a resonance inductor L21, and an inductor L22.
  • the power recovery circuit 81 recovers the power stored in the panel 10 from the panel 10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L22, and stores it in the capacitor C20. Then, the recovered power is supplied to the panel 10 again from the capacitor C20 by LC resonance between the interelectrode capacitance of the panel 10 and the inductor L21, and is reused as power when driving the sustain electrodes SU1 to SUn.
  • Switching element Q83 clamps sustain electrodes SU1 to SUn to voltage Vs, and switching element Q84 clamps sustain electrodes SU1 to SUn to voltage 0 (V).
  • sustain pulse generating circuit 80 generates a sustain pulse of voltage Vs and applies it to sustain electrodes SU1 to SUn.
  • the timing detection pulses V2 and V4 are applied to the sustain electrodes SU1 to SUn.
  • the constant voltage generation circuit 85 includes a switching element Q86 and a switching element Q87.
  • the constant voltage generation circuit 85 writes the initialization periods Pia1, Pib2 to Pib8 and the writing periods Pw1 to Pw8 of the subfields SF1 to SF8, which are image display subfields, and the initialization period Pioo of the timing detection subfield SFo.
  • the voltage Ve is applied to the sustain electrodes SU1 to SUn. Apply.
  • these switching elements can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements are controlled by timing signals corresponding to the respective switching elements generated by the timing generation circuit 35.
  • FIG. 8 is a circuit diagram schematically showing a configuration example of the data electrode driving circuit 32 of the plasma display device 30 according to the embodiment of the present invention.
  • the data electrode drive circuit 32 operates based on the image data supplied from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35. In FIG. 8, details of the paths of these signals are omitted. To do.
  • the data electrode drive circuit 32 includes switching elements Q91H1 to Q91Hm and switching elements Q91L1 to Q91Lm. Then, voltage 0 (V) is applied to data electrode Dj by turning on switching element Q91Lj, and voltage Vd is applied to data electrode Dj by turning on switching element Q91Hj. In this way, the data electrode driving circuit 32 generates an address pulse of the voltage Vd in the address periods Pw1 to Pw8 of the subfields SF1 to SF8 that are image display subfields, and an address pulse of the voltage Vd in the address period Pwo of the timing detection subfield SFo.
  • a pulse is applied to each data electrode D1-Dm.
  • FIG. 9 is a diagram schematically showing an example of the operation when detecting the position coordinates of the light pen 50 in the plasma display system 100 according to the embodiment of the present invention.
  • the image display area is indicated by a broken line, but this broken line is not actually displayed on the panel 10.
  • FIG. 10 is a diagram schematically showing an example of a drive voltage waveform when the position coordinate of the light pen 50 is detected in the plasma display system 100 according to the embodiment of the present invention.
  • FIG. 10 shows scan electrode SC1, scan electrode SCn, data electrode D1, and data in timing detection subfield SFo, y-coordinate detection subfield SFy, and x-coordinate detection subfield SFx following image display subfield SF8.
  • a driving voltage waveform applied to each of the electrodes Dm, a coordinate reference signal input to the coordinate calculation circuit 56, and a light reception signal output from the light receiving element 52 are shown.
  • the drive voltage waveforms applied to sustain electrodes SU1 to SUn are omitted, but the drive voltage waveforms shown in FIG. 10 are the same as the drive voltage waveforms shown in FIGS.
  • the time Toy from the time to1 to the time ty0 is determined in advance, and the time Tox from the time to1 to the time tx0 is predetermined.
  • the timing detection circuit 54 can generate a coordinate reference signal having rising edges at each of the time ty0 and the time tx0 and output it to the coordinate calculation circuit 56 as shown in FIG. it can.
  • the timing detection circuit 54 emits light of five consecutive times in which the intervals of light emission are time To0, time To1, time To2, and time To3 (output from the light receiving element 52 based on these light emission). Is detected by detecting the received light signal).
  • a y-coordinate detection pattern in which linear light emission extended in the first direction (row direction) sequentially moves in the second direction (column direction) is displayed on the panel 10.
  • a y-coordinate detection pattern in which linear light emission extended in the first direction (row direction) sequentially moves in the second direction (column direction) is displayed on the panel 10.
  • one horizontal line Ly that sequentially moves from the upper end (first row) to the lower end (nth row) of the image display region is displayed in the image display region of the panel 10. Is done.
  • the tip of the light pen 50 is in contact with (or close to) the “coordinates (x, y)” of the image display surface of the panel 10, at the time tyy when the horizontal line Ly passes the coordinates (x, y), the light
  • the light receiving element 52 of the pen 50 receives the light emission of the horizontal line Ly.
  • the light pen 50 outputs a light reception signal indicating that the light receiving element 52 has received the light emission of the horizontal line Ly at time tyy.
  • an x-coordinate detection pattern in which linear light emission extended in the second direction (column direction) sequentially moves in the first direction (row direction) is displayed on the panel. 10 is displayed. Accordingly, as shown in FIG. 9, the image display area of the panel 10 is sequentially moved from the left end portion (first pixel column) to the right end portion (m / 3 pixel row) of the image display area. One vertical line Lx is displayed.
  • the tip of the light pen 50 is in contact with (or close to) the “coordinate (x, y)” of the image display surface of the panel 10, at the time txx when the vertical line Lx passes the coordinate (x, y),
  • the light receiving element 52 of the light pen 50 receives the light emission of the vertical line Lx. Accordingly, as shown in FIG. 10, the light pen 50 outputs a light reception signal indicating that the light receiving element 52 has received the light emission of the vertical line Lx at time txx.
  • the coordinate calculation circuit 56 shown in FIG. 5 is based on the coordinate reference signal output from the timing detection circuit 54 and the light reception signal output from the light receiving element 52 in the y coordinate detection period Py of the y coordinate detection subfield SFy.
  • the time Tyy from the time ty0 to the time tyy is measured using the counter provided for.
  • the time Tyy is divided by the time Ty1 in the arithmetic circuit provided inside. The division result is the y coordinate of the position of the light pen 50 in the image display area.
  • the coordinate calculation circuit 56 is provided internally based on the coordinate reference signal output from the timing detection circuit 54 and the light reception signal output from the light receiving element 52 in the x coordinate detection period Px of the x coordinate detection subfield SFx.
  • a time Txx from time tx0 to time txx is measured using a counter. Then, the time Txx is divided by the time Tx1 in the arithmetic circuit provided inside. This division result is the x coordinate of the position of the light pen 50 in the image display area.
  • the coordinate calculation circuit 56 in the present embodiment calculates the position (coordinates (x, y)) of the light pen 50 in the image display area.
  • FIG. 11 is a block diagram schematically showing a configuration example of the filter circuit 44 of the plasma display system 100 in the embodiment of the present invention.
  • the filter circuit 44 includes a coefficient calculation unit 160, an x coordinate filter 170, and a y coordinate filter 180.
  • the x coordinate filter 170 is an IIR (Infinite Impulse Response) filter having multipliers 172 and 176, an adder 174, and a delay unit 175.
  • IIR Infinite Impulse Response
  • the multiplier 172 multiplies the input x coordinate X (t) by the filter coefficient Kx (t) and outputs the result.
  • the adder 174 adds the signal output from the multiplier 176 to the signal (X (t) ⁇ Kx (t)) output from the multiplier 172, and outputs the result. This output signal becomes the x-coordinate FX (t) after filtering.
  • the delay unit 175 delays the filtered x-coordinate FX (t) by one field (a time equal to one field of the image signal).
  • the multiplier 176 multiplies the x coordinate FX (t ⁇ 1) after one field delay by the cyclic coefficient (1 ⁇ Kx (t)) and outputs the result.
  • the x-coordinate filter 170 passes the x-coordinate X (t) through the IIR filter with the filter coefficient Kx (t) to the x-coordinate FX (t) and outputs it.
  • Y coordinate filter 180 is an IIR filter similar to x coordinate filter 170 having multipliers 182 and 186, adder 184, and delay unit 185.
  • the multiplier 182 multiplies the input y coordinate Y (t) by the filter coefficient Ky (t) and outputs the result.
  • the adder 184 adds the signal output from the multiplier 186 to the signal (Y (t) ⁇ Ky (t)) output from the multiplier 182 and outputs the result. This output signal becomes the y coordinate FY (t) after the filter processing.
  • the delay unit 185 delays the y coordinate FY (t) after the filtering process by one field (a time equal to one field of the image signal).
  • the multiplier 186 multiplies the y coordinate FY (t ⁇ 1) after one field delay by the cyclic coefficient (1 ⁇ Ky (t)) and outputs the result.
  • the y-coordinate filter 180 passes the y-coordinate Y (t) through the IIR filter having the filter coefficient Ky (t) to make the y-coordinate FY (t) and outputs it.
  • the filter coefficient Ky (t) is a numerical value between “0” and “1”.
  • the y-coordinate filter 180 becomes a strong low-pass filter as the filter coefficient Ky (t) becomes smaller and the cyclic coefficient (1-Ky (t)) becomes larger.
  • the filter coefficient Ky (t) becomes larger, the cyclic coefficient (1 ⁇ Ky (t)) becomes small and a low-pass filter is weak.
  • the filter coefficient Ky (t) “1”
  • the cyclic coefficient is “0”
  • the y-coordinate filter 180 does not function as a low-pass filter
  • y-coordinate FY (t) y-coordinate Y (t). .
  • the coefficient calculation unit 160 includes delay units 162 and 164 and a coefficient calculation unit 166.
  • the delay unit 162 delays the input x coordinate X (t) by one field and outputs the x coordinate X (t ⁇ 1).
  • the delay unit 164 delays the input y coordinate Y (t) by one field and outputs the y coordinate Y (t ⁇ 1).
  • the coefficient calculation unit 166 includes a speed calculation unit 167 that calculates a speed at which the light pen 50 moves on the panel 10.
  • the coefficient calculation unit 166 includes an x coordinate X (t), a y coordinate Y (t), and an x coordinate X (
  • the filter coefficient Kx (t) and the filter coefficient Ky (t) are calculated based on the t-1), the y coordinate Y (t-1), and the state S (t).
  • the filter coefficient Kx (t) and the filter coefficient Ky (t) are calculated based on the following calculation formula.
  • Kx (t) min (Rx (t) ⁇ ⁇ (S (t)), 1)
  • Ky (t) min (Ry (t) ⁇ ⁇ (S (t)), 1)
  • min (a, b) is a function that outputs the smaller one of “a” and “b”.
  • ⁇ (S (t)) is a variable set by the state S (t). In the present embodiment, for example, it is set as follows.
  • Rx (t) ⁇ x ⁇ (X (t) ⁇ X (t ⁇ 1)) ⁇ 2 + ⁇ x ⁇ (Y (t) ⁇ Y (t ⁇ 1)) ⁇ 2
  • Ry (t) ⁇ y ⁇ (X (t) ⁇ X (t ⁇ 1)) ⁇ 2 + ⁇ y ⁇ (Y (t) ⁇ Y (t ⁇ 1)) ⁇ 2
  • ⁇ represents a power.
  • Rx (t) and Ry (t) are the position coordinates (X (t), Y (t)) and the position coordinates (X (t ⁇ 1)) input one field before.
  • Y (t-1)) is a variable that changes according to the magnitude of the difference between the light pen 50 and the light pen 50 quickly moves on the panel 10 and increases as the amount of change in position coordinates increases. 10 gradually decreases when the amount of change in the position coordinate is small.
  • the speed calculation unit 167 included in the coefficient calculation unit 166 calculates the speed when the light pen 50 moves on the panel 10.
  • the filter circuit 44 in the present embodiment becomes a weak low-pass filter when the light pen 50 moves on the panel 10 quickly, and becomes a strong low-pass filter when the light pen 50 moves slowly on the panel 10.
  • the position coordinates (X (t), Y (t)) of the light pen 50 calculated by the coordinate calculation circuit 56 of the light pen 50 include errors caused by variations in discharge, noise, and the like. Since this error changes with time, even if the light pen 50 is stationary, the position coordinates (X (t), Y (t)) calculated by the coordinate calculation circuit 56 may vary with time. . When this error occurs, the drawing signal (for example, a cursor indicating the position of the light pen 50 displayed on the panel 10) sways due to the error.
  • the filter circuit 44 smoothes such a temporally varying error with a low-pass filter so as to make it difficult to see the fluctuation of the drawing signal caused by the error.
  • This error is relatively inconspicuous when the light pen 50 moves quickly over the panel 10, and is relatively conspicuous when the light pen 50 moves slowly over the panel 10 or is stationary.
  • the strong low-pass filter strongly smoothes the error and makes the fluctuation of the drawing signal caused by the error less noticeable.
  • the response of the drawing signal created in the drawing circuit 46 to the movement of the light pen 50 reduce. For example, if a strong low-pass filter is applied when the light pen 50 moves quickly on the panel 10, the followability of the cursor or the like displayed on the panel 10 to the light pen 50 is deteriorated.
  • the filter circuit 44 in the present embodiment is a weak low-pass filter when the light pen 50 moves quickly over the panel 10 and a strong low-pass filter when the light pen 50 moves slowly over the panel 10. become. Therefore, when the light pen 50 moves slowly on the panel 10 or is stationary, the error is relatively strongly smoothed, and a drawing signal (for example, the position of the light pen 50 indicating the position of the light pen 50 is generated due to the error). The shaking of the cursor etc. is less noticeable. Further, when the light pen 50 moves quickly on the panel 10, the followability of the drawing signal created in the drawing circuit 46 to the light pen 50 can be kept good.
  • the filter circuit 44 when the tip of the light pen 50 is in contact with the panel 10 (when the contact switch 53 is on), the low-pass filter becomes strong, and the tip of the light pen 50 contacts the panel 10. When not (when the contact switch 53 is off), the low-pass filter is weak.
  • the error when the user is touching the front end of the light pen 50 to the panel 10 for drawing, the error is relatively strongly smoothed, and a drawing signal (for example, the light pen 50 caused by the error) is generated.
  • a drawing signal for example, the light pen 50 caused by the error
  • the shaking of the cursor indicating the position of the position becomes inconspicuous.
  • the tip of the light pen 50 is not in contact with the panel 10, it is possible to maintain good followability of the drawing signal created in the drawing circuit 46 to the light pen 50.
  • the filter coefficient Kx (t) when the moving speed of the position coordinates is 14 (cm / sec) or more on the image display surface of the panel 10.
  • the moving speed of the position coordinates is 9 (cm / sec) on the image display surface of the panel 10.
  • the present invention is not limited to these numerical values, and each numerical value is desirably set optimally according to the specifications of the plasma display system 100, the size of the panel 10, and the like.
  • the constants ⁇ x, ⁇ x, ⁇ y, and ⁇ y described above are, for example, the size of the panel 10, the time (t), and the like so that the moving speed of the position coordinates on the image display surface of the panel 10 can be approximately calculated. It is set according to the time difference from the time (t-1).
  • the filter circuit 44 has a delay device inside (not shown in FIG. 11), and has a time delay corresponding to the time required for the filter processing of the x coordinate FX (t) and the y coordinate FY (t).
  • a state FS (t) is applied to S (t) and output to the drawing circuit 46.
  • FIG. 12A is a diagram schematically showing an example of an operation when performing handwriting input with the light pen 50 in the plasma display system 100 according to the embodiment of the present invention.
  • FIG. 12B is a diagram schematically showing another example of the operation when performing handwritten input with the light pen 50 in the plasma display system 100 according to the embodiment of the present invention.
  • the image display area is indicated by a broken line, but this broken line is not actually displayed on the panel 10.
  • the drawing circuit 46 has a drawing pattern of a predetermined color and size (for example, a white circle or the like) around the pixel corresponding to the x coordinate FX (t) and y coordinate FY (t) output from the filter circuit 44.
  • a drawing signal of a pattern (hereinafter referred to as “cursor 101”) is generated.
  • the plasma display device 30 displays an image based on the drawing signal stored in the image memory 47 of the drawing circuit 46 on the panel 10.
  • the panel 10 displays a graphic input by handwriting using the light pen 50.
  • the current drawing signal (drawing signal based on the x-coordinate FX (t) and y-coordinate FY (t)) is written in the image memory 47.
  • the drawing signal one field before (the drawing signal based on the x coordinate FX (t ⁇ 1) and the y coordinate FY (t ⁇ 1)) is deleted from the image memory 47.
  • the position coordinates of the light pen 50 are displayed on the panel 10. A cursor 101 is displayed. Therefore, it is possible to use the light pen 50 as a pointer. Further, if the light receiving element 52 can receive the light emitted from the panel 10 even if the light pen 50 is located farther from the panel 10 by attaching a lens to the tip of the light pen 50, the light pen 50 can be received.
  • the light pen 50 can also be used as a pointer from a distant position.
  • the cursor 101 is not displayed on the panel 10, or the cursor 101 is positioned at the coordinate position when the light receiving element 52 last received the light emission of the panel 10. It may be set appropriately such as displaying.
  • a coordinate reference signal can also be used as a masking signal for blocking light emission not related to position coordinate detection.
  • the coordinate calculation circuit 56 may receive the light reception signal only during the period when the coordinate reference signal is “1”.
  • the configuration in which the contact switch 53 is attached to the tip of the light pen 50 has been described.
  • a manual switch corresponding to the contact switch 53 is provided on the side surface of the light pen 50, and the user switches the switch. You may comprise so that operation of ON / OFF of can be operated.
  • the light pen 50 may include both the contact switch 53 and the manual switch.
  • each switch may have a different function, such as using the contact switch 53 as a handwriting input switch and using a manual switch for switching between display and non-display of the cursor.
  • timing detection discharge is generated four times at predetermined time intervals (for example, time To1, time To2, and time To3) in the timing detection subfield SFo.
  • the number of timing detection discharges may be two or more.
  • the present embodiment it is desirable to set the time intervals for generating the timing detection discharge a plurality of times in order to easily identify the first timing detection discharge.
  • the configuration in which the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx are provided in each field has been described.
  • the present invention is not limited to this configuration. Absent.
  • the configuration may be such that those subfields are generated at a rate of once in a plurality of fields.
  • the drawing device and the light pen may be electrically connected by an electric cable or the like, and a signal may be transmitted and received between the light pen and the drawing device via the electric cable.
  • the timing detection subfield SFo may not be provided.
  • each subfield is not limited to the order shown in the embodiment.
  • the y coordinate detection subfield SFy may be generated after the x coordinate detection subfield SFx.
  • an image display subfield may be generated after the y coordinate detection subfield SFy and the x coordinate detection subfield SFx.
  • the timing detection subfield SFo may be generated between the y coordinate detection subfield SFy and the x coordinate detection subfield SFx, and the timing detection subfield SFo is generated after the x coordinate detection subfield SFx. May be.
  • each operation has been described by taking a plasma display device using a plasma display panel as an image display unit as an example of the image display device.
  • the image display device is not limited to the plasma display device.
  • the same effect as that described above can be obtained by applying the same configuration as that described above.
  • one field has a plurality of image display subfields and a subfield for detecting position coordinates.
  • the present invention is not limited to this configuration. is not.
  • one field may be composed of only a plurality of image display subfields.
  • the forced initializing operation has been described as an initializing operation that forcibly generates initializing discharge in all the discharge cells in the image display area of the panel. It is not limited to this configuration.
  • the forced initializing waveform is applied only to some discharge cells in the image display area of the panel and the initializing discharge is forcibly generated only in the discharge cells. It shall be included in the conversion operation.
  • the drawing device 40 is provided independently of the plasma display device.
  • a computer connected to the plasma display device corresponds to the drawing device 40.
  • a rendering signal is created using the computer.
  • the present invention is not limited to this configuration.
  • the drawing device 40 may be provided as a single device, or the drawing device 40 may be provided in the plasma display device 30.
  • the drive voltage waveforms shown in FIGS. 3, 4, and 10 are merely examples in the embodiment of the present invention, and the present invention is not limited to these drive voltage waveforms.
  • circuit configurations shown in FIGS. 5, 6, 7, 8, and 11 are merely examples in the embodiment of the present invention, and the present invention is not limited to these circuit configurations. It is not a thing.
  • Each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or substantially the same as each operation shown in the embodiment.
  • a microcomputer or a computer programmed to operate may be used.
  • the specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 14 of 1024. It is just an example.
  • the present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with panel specifications, panel characteristics, plasma display device specifications, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.
  • the present invention is useful as an image display system because it can suppress fluctuations in position coordinates caused by noise or the like when handwritten input to the image display unit using a light pen.

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Abstract

This invention curbs position coordinate jitter that occurs in a light pen (50) due to noise and the like. Accordingly, the light pen receives light emissions generated in a panel (10) at a y-coordinate detection subfield and an x-coordinate detection subfield, and generates a light-receiving signal. A coordinate calculating circuit (56) outputs a first x-coordinate signal and a first y-coordinate signal on the basis of the light-receiving signal. A filter circuit (44) applies a low-pass filter to the first x-coordinate signal and the first y-coordinate signal, the low-pass filter being stronger when a contact switch (53) is ON than when the contact switch (53) is OFF. A drawing circuit (46) produces a drawing signal on the basis of a second x-coordinate signal and a second y-coordinate signal outputted from the filter circuit. A plasma display device (30) displays an image on the panel on the basis of the drawing signal.

Description

画像表示システムImage display system
　本発明は、画素を構成する複数の発光素子における発光と非発光の２値制御を組み合わせて画像表示領域に画像を表示する画像表示装置にライトペンを用いて文字や図画の手書き入力ができる画像表示システムに関する。 The present invention provides an image display device for displaying characters in an image display area by combining light emission and non-light emission binary control in a plurality of light emitting elements constituting a pixel, and an image in which characters and drawings can be input by hand using a light pen. It relates to a display system.
　画素を構成する複数の発光素子のそれぞれにおける発光と非発光の２値制御を組み合わせて画像表示領域に画像を表示する画像表示装置として代表的なものにプラズマディスプレイパネル（以下、「パネル」と略記する）がある。 A plasma display panel (hereinafter abbreviated as “panel”) is a typical image display device that displays an image in an image display area by combining binary control of light emission and non-light emission in each of a plurality of light emitting elements constituting a pixel. There is).
　パネルは、対向配置された前面基板と背面基板との間に、画素を構成する発光素子である放電セルが多数形成されている。 In the panel, a large number of discharge cells, which are light-emitting elements constituting pixels, are formed between a front substrate and a rear substrate that are arranged to face each other.
　前面基板は、１対の走査電極と維持電極とからなる表示電極対が前面側のガラス基板上に互いに平行に複数対形成されている。背面基板は、背面側のガラス基板上に互いに平行なデータ電極が複数形成されている。 In the front substrate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate. The back substrate has a plurality of parallel data electrodes formed on a glass substrate on the back side.
　各放電セル内には、赤色（Ｒ）、緑色（Ｇ）および青色（Ｂ）のいずれかの蛍光体が塗布され、放電ガスが封入されている。そして、各放電セルでは、ガス放電を起こすことで紫外線を発生し、この紫外線で蛍光体を励起発光する。 Each discharge cell is coated with one of red (R), green (G), and blue (B) phosphors, and a discharge gas is enclosed therein. In each discharge cell, an ultraviolet ray is generated by causing a gas discharge, and the phosphor is excited to emit light by the ultraviolet ray.
　発光素子における発光と非発光との２値制御を組み合わせてパネルの画像表示領域に画像を表示する方法としては一般にサブフィールド法が用いられている。 A subfield method is generally used as a method of displaying an image in an image display area of a panel by combining binary control of light emission and non-light emission in a light emitting element.
　サブフィールド法では、１フィールドを、発光輝度が互いに異なる複数のサブフィールドに分割する。そして、各放電セルでは、表示すべき階調値に応じた組合せで各サブフィールドの発光・非発光を制御する。これにより各放電セルが表示すべき階調値に応じた明るさで発光し、パネルの画像表示領域に、様々な階調値の組合せで構成されたカラーの画像が表示される。 In the subfield method, one field is divided into a plurality of subfields having different emission luminances. In each discharge cell, light emission / non-light emission of each subfield is controlled by a combination according to the gradation value to be displayed. As a result, each discharge cell emits light with brightness corresponding to the gradation value to be displayed, and a color image composed of various combinations of gradation values is displayed in the image display area of the panel.
　このような画像表示装置には、「ライトペン」と呼ばれるポインティングデバイスを使用して、パネル上に、文字や図画を手書き入力することができる機能を有するものがある。 Some of such image display apparatuses have a function of allowing handwriting input of characters and drawings on a panel using a pointing device called “light pen”.
　ライトペンを用いた手書き入力機能を実現するために、画像表示領域内におけるライトペンの位置を検出する技術が開示されている。以下、画像表示領域内におけるライトペンの位置を表す座標を「位置座標」と記す。 In order to realize a handwriting input function using a light pen, a technique for detecting the position of the light pen in an image display area is disclosed. Hereinafter, the coordinates representing the position of the light pen in the image display area are referred to as “position coordinates”.
　例えば、特許文献１に記載されたプラズマディスプレイ装置では、横座標検出用パターンを表示する横座標検出サブフィールドを１フィールド内に設ける。そして、この横座標検出サブフィールドの発光をライトペンで検出し、その発光が検出されたタイミングにもとづきライトペンの位置（横座標）を検出する。 For example, in the plasma display device described in Patent Document 1, an abscissa detection subfield for displaying an abscissa detection pattern is provided in one field. Then, the light emission of this abscissa detection subfield is detected by the light pen, and the position (abscissa) of the light pen is detected based on the timing at which the light emission is detected.
　また、特許文献２に記載されたプラズマディスプレイ装置では、位置座標検出用の光信号を発生する位置検出期間を、ライトペンの位置座標を検出するときのみ１フィールド内に設ける。そして、この光信号をライトペンで検出し、その光信号が検出されたタイミングにもとづきライトペンの位置座標を検出する。 In the plasma display device described in Patent Document 2, a position detection period for generating a light signal for detecting position coordinates is provided in one field only when detecting the position coordinates of the light pen. Then, this light signal is detected by the light pen, and the position coordinates of the light pen are detected based on the timing at which the light signal is detected.
特開昭５０－１０８８３８号公報JP 50-108838 A 特開２００１－３１８７６５号公報JP 2001-318765 A
　本開示における画像表示システムは、水平方向であるｘ座標方向および垂直方向であるｙ座標方向にそれぞれ複数の電極を有する画像表示部を備えた画像表示装置と、受光素子とスイッチとを有するライトペンと、座標算出回路と、フィルタ回路と、描画回路とを備える。画像表示装置の画像表示部は、ｙ座標検出サブフィールドおよびｘ座標検出サブフィールドにおいて発光する。ライトペンは、ｙ座標検出サブフィールドおよびｘ座標検出サブフィールドにおいて画像表示部に生じる発光を受光して受光信号を生成する。座標算出回路は、受光信号にもとづき、ライトペンが受光する発光の画像表示部上の位置を表す第１のｙ座標信号、および第１のｘ座標信号を出力する。フィルタ回路は、第１のｘ座標信号および第１のｙ座標信号にローパスフィルタをかけて第２のｘ座標信号および第２のｙ座標信号を出力する。描画回路は、フィルタ回路から出力される第２のｘ座標信号および第２のｙ座標信号にもとづく描画信号を作成する。画像表示装置は、描画信号にもとづく画像を画像表示部に表示する。そして、フィルタ回路は、ライトペンのスイッチの状態に応じてローパスフィルタの強さが異なる。 An image display system according to the present disclosure includes an image display device including an image display unit having a plurality of electrodes in the x-coordinate direction that is a horizontal direction and the y-coordinate direction that is a vertical direction, and a light pen including a light receiving element and a switch. A coordinate calculation circuit, a filter circuit, and a drawing circuit. The image display unit of the image display device emits light in the y coordinate detection subfield and the x coordinate detection subfield. The light pen receives light emitted from the image display unit in the y coordinate detection subfield and the x coordinate detection subfield and generates a light reception signal. The coordinate calculation circuit outputs a first y-coordinate signal and a first x-coordinate signal representing a position on the image display unit of light emission received by the light pen based on the light reception signal. The filter circuit applies a low-pass filter to the first x-coordinate signal and the first y-coordinate signal, and outputs a second x-coordinate signal and a second y-coordinate signal. The drawing circuit creates a drawing signal based on the second x-coordinate signal and the second y-coordinate signal output from the filter circuit. The image display device displays an image based on the drawing signal on the image display unit. The filter circuit has different low-pass filter strengths depending on the state of the light pen switch.
　これにより、ライトペンを用いて画像表示部に手書き入力する際に、ノイズ等によって発生する位置座標の揺れを抑えることが可能になる。 This makes it possible to suppress fluctuations in position coordinates caused by noise or the like when handwriting input to the image display unit using a light pen.
図１は、本発明の実施の形態におけるプラズマディスプレイ装置に用いるパネルの構造の一例を示す分解斜視図である。FIG. 1 is an exploded perspective view showing an example of the structure of a panel used in the plasma display device in accordance with the exemplary embodiment of the present invention. 図２は、本発明の実施の形態におけるプラズマディスプレイ装置に用いるパネルの電極配列の一例を示す図である。FIG. 2 is a diagram showing an example of the electrode arrangement of the panel used in the plasma display device in accordance with the exemplary embodiment of the present invention. 図３は、本発明の実施の形態における画像表示サブフィールドのサブフィールドＳＦ１～ＳＦ３においてパネルの各電極に印加する駆動電圧波形の一例を概略的に示す図である。FIG. 3 is a diagram schematically showing an example of a drive voltage waveform applied to each electrode of the panel in the subfields SF1 to SF3 of the image display subfield in the embodiment of the present invention. 図４は、本発明の実施の形態におけるタイミング検出サブフィールドＳＦｏ、ｙ座標検出サブフィールドＳＦｙおよびｘ座標検出サブフィールドＳＦｘにおいてパネルの各電極に印加する駆動電圧波形の一例を概略的に示す図である。FIG. 4 is a diagram schematically showing an example of a drive voltage waveform applied to each electrode of the panel in the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx in the embodiment of the present invention. is there. 図５は、本発明の実施の形態におけるプラズマディスプレイ装置を構成する回路ブロックおよびプラズマディスプレイシステムの一例を概略的に示す図である。FIG. 5 is a diagram schematically showing an example of a circuit block and a plasma display system constituting the plasma display device in the embodiment of the present invention. 図６は、本発明の実施の形態におけるプラズマディスプレイ装置の走査電極駆動回路の一構成例を概略的に示す回路図である。FIG. 6 is a circuit diagram schematically showing a configuration example of the scan electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention. 図７は、本発明の実施の形態におけるプラズマディスプレイ装置の維持電極駆動回路の一構成例を概略的に示す回路図である。FIG. 7 is a circuit diagram schematically showing a configuration example of the sustain electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention. 図８は、本発明の実施の形態におけるプラズマディスプレイ装置のデータ電極駆動回路の一構成例を概略的に示す回路図である。FIG. 8 is a circuit diagram schematically showing a configuration example of the data electrode driving circuit of the plasma display device in accordance with the exemplary embodiment of the present invention. 図９は、本発明の実施の形態におけるプラズマディスプレイシステムにおいてライトペンの位置座標を検出するときの動作の一例を概略的に示す図である。FIG. 9 is a diagram schematically showing an example of the operation when detecting the position coordinates of the light pen in the plasma display system according to the embodiment of the present invention. 図１０は、本発明の実施の形態におけるプラズマディスプレイシステムにおいてライトペンの位置座標を検出するときの駆動電圧波形の一例を概略的に示す図である。FIG. 10 is a diagram schematically showing an example of a drive voltage waveform when detecting the position coordinates of the light pen in the plasma display system according to the embodiment of the present invention. 図１１は、本発明の実施の形態におけるプラズマディスプレイシステムのフィルタ回路の一構成例を概略的に示すブロック図である。FIG. 11 is a block diagram schematically showing a configuration example of the filter circuit of the plasma display system in accordance with the exemplary embodiment of the present invention. 図１２Ａは、本発明の実施の形態におけるプラズマディスプレイシステムにおいてライトペンによる手書き入力を行うときの動作の一例を概略的に示す図である。FIG. 12A is a diagram schematically showing an example of an operation when performing handwriting input with a light pen in the plasma display system in accordance with the exemplary embodiment of the present invention. 図１２Ｂは、本発明の実施の形態におけるプラズマディスプレイシステムにおいてライトペンによる手書き入力を行うときの動作の他の一例を概略的に示す図である。FIG. 12B is a diagram schematically illustrating another example of the operation when performing handwriting input with a light pen in the plasma display system according to the exemplary embodiment of the present invention.
　以下、本発明の実施の形態における画像表示装置および画像表示システムについて、図面を用いて説明する。なお、以下の実施の形態では、画像表示装置および画像表示システムの一例として、プラズマディスプレイパネルを有するプラズマディスプレイ装置およびプラズマディスプレイシステムの説明を行う。 Hereinafter, an image display device and an image display system according to embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a plasma display device having a plasma display panel and a plasma display system will be described as an example of an image display device and an image display system.
　（実施の形態）
　図１は、本発明の実施の形態におけるプラズマディスプレイ装置に用いるパネルの構造の一例を示す分解斜視図である。 (Embodiment)
FIG. 1 is an exploded perspective view showing an example of the structure of a panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
　ガラス製の前面基板１１上には、走査電極１２と維持電極１３とからなる表示電極対１４が複数形成されている。そして、表示電極対１４を覆うように誘電体層１５が形成され、その誘電体層１５上に保護層１６が形成されている。前面基板１１は画像が表示される画像表示面となる。 A plurality of display electrode pairs 14 each including a scanning electrode 12 and a sustaining electrode 13 are formed on a glass front substrate 11. A dielectric layer 15 is formed so as to cover the display electrode pair 14, and a protective layer 16 is formed on the dielectric layer 15. The front substrate 11 serves as an image display surface on which an image is displayed.
　背面基板２１上にはデータ電極２２が複数形成され、データ電極２２を覆うように誘電体層２３が形成され、さらにその上に井桁状の隔壁２４が形成されている。そして、隔壁２４の側面および誘電体層２３の表面には赤色（Ｒ）に発光する蛍光体層２５Ｒ、緑色（Ｇ）に発光する蛍光体層２５Ｇ、および青色（Ｂ）に発光する蛍光体層２５Ｂが設けられている。以下、蛍光体層２５Ｒ、蛍光体層２５Ｇ、蛍光体層２５Ｂをまとめて蛍光体層２５とも記す。 A plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is further formed thereon. The phosphor layer 25R that emits red (R), the phosphor layer 25G that emits green (G), and the phosphor layer that emits blue (B) are formed on the side surfaces of the barrier ribs 24 and the surface of the dielectric layer 23. 25B is provided. Hereinafter, the phosphor layer 25R, the phosphor layer 25G, and the phosphor layer 25B are collectively referred to as a phosphor layer 25.
　これら前面基板１１と背面基板２１とを、微小な空間を挟んで表示電極対１４とデータ電極２２とが交差するように対向配置し、前面基板１１と背面基板２１との間隙に放電空間を設ける。そして、その外周部をガラスフリット等の封着材によって封着する。その放電空間には、例えばネオンとキセノンの混合ガスを放電ガスとして封入する。 The front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 intersect each other with a minute space therebetween, and a discharge space is provided in the gap between the front substrate 11 and the rear substrate 21. . And the outer peripheral part is sealed with sealing materials, such as glass frit. For example, a mixed gas of neon and xenon is sealed in the discharge space as a discharge gas.
　放電空間は隔壁２４によって複数の区画に仕切られており、表示電極対１４とデータ電極２２とが交差する部分に、画素を構成する発光素子である放電セルが形成される。 The discharge space is partitioned into a plurality of sections by the barrier ribs 24, and discharge cells, which are light-emitting elements constituting the pixels, are formed at the intersections between the display electrode pairs 14 and the data electrodes 22.
　そして、これらの放電セルで放電を発生し、蛍光体層２５を発光（放電セルを点灯）することにより、パネル１０にカラーの画像を表示する。 Then, discharge is generated in these discharge cells, and the phosphor layer 25 emits light (discharge cells are turned on), thereby displaying a color image on the panel 10.
　なお、パネル１０においては、表示電極対１４が延伸する方向に配列された連続する３つの放電セルで１つの画素を構成する。この３つの放電セルとは、蛍光体層２５Ｒを有し赤色（Ｒ）に発光する放電セル（以下、「赤の放電セル」、または「赤のピクセル」と記す）と、蛍光体層２５Ｇを有し緑色（Ｇ）に発光する放電セル（以下、「緑の放電セル」、または「緑のピクセル」と記す）と、蛍光体層２５Ｂを有し青色（Ｂ）に発光する放電セル（以下、「青の放電セル」、または「青のピクセル」と記す）である。 In the panel 10, one pixel is composed of three consecutive discharge cells arranged in the direction in which the display electrode pair 14 extends. The three discharge cells are a discharge cell having a phosphor layer 25R and emitting red (R) light (hereinafter referred to as “red discharge cell” or “red pixel”), and a phosphor layer 25G. Discharge cells (hereinafter referred to as “green discharge cells” or “green pixels”) having a green color (G), and discharge cells (hereinafter referred to as “green pixels”) having a phosphor layer 25B. , “Blue discharge cells” or “blue pixels”).
　なお、パネル１０の構造は上述したものに限られるわけではなく、例えばストライプ状の隔壁を備えたものであってもよい。 Note that the structure of the panel 10 is not limited to the above-described structure, and may be, for example, provided with a stripe-shaped partition wall.
　図２は、本発明の実施の形態におけるプラズマディスプレイ装置に用いるパネルの電極配列の一例を示す図である。 FIG. 2 is a diagram showing an example of the electrode arrangement of the panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
　パネル１０には、第１の方向に延長されたｎ本の走査電極ＳＣ１～ＳＣｎ（図１の走査電極１２）およびｎ本の維持電極ＳＵ１～ＳＵｎ（図１の維持電極１３）が配列され、第１の方向に交差する第２の方向に延長されたｍ本のデータ電極Ｄ１～Ｄｍ（図１のデータ電極２２）が配列されている。 In the panel 10, n scan electrodes SC1 to SCn (scan electrode 12 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 13 in FIG. 1) extended in the first direction are arranged. The m data electrodes D1 to Dm (data electrode 22 in FIG. 1) extended in the second direction intersecting the first direction are arranged.
　以下、第１の方向を行方向（または水平方向、またはライン方向、またはｘ座標方向）と呼称し、第２の方向を列方向（または垂直方向、またはｙ座標方向）と呼称する。 Hereinafter, the first direction is referred to as a row direction (or horizontal direction, line direction, or x coordinate direction), and the second direction is referred to as a column direction (or vertical direction or y coordinate direction).
　そして、１対の走査電極ＳＣｉ（ｉ＝１～ｎ）および維持電極ＳＵｉと１つのデータ電極Ｄｊ（ｊ＝１～ｍ）とが交差した領域に発光素子としての放電セルが１つ形成される。すなわち、１対の表示電極対１４上には、ｍ個の放電セルが形成され、ｍ／３個の画素が形成される。そして、放電セルは放電空間内にｍ×ｎ個形成され、ｍ×ｎ個の放電セルが形成された領域がパネル１０の画像表示領域となる。例えば、画素数が１９２０×１０８０個のパネルでは、ｍ＝１９２０×３＝５７６０となり、ｎ＝１０８０となる。 One discharge cell as a light emitting element is formed in a region where a pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects with one data electrode Dj (j = 1 to m). . In other words, m discharge cells are formed on one pair of display electrodes 14 and m / 3 pixels are formed. Then, m × n discharge cells are formed in the discharge space, and an area where m × n discharge cells are formed becomes an image display area of the panel 10. For example, in a panel having 1920 × 1080 pixels, m = 1920 × 3 = 5760 and n = 1080.
　例えば、データ電極Ｄｐ（ｐ＝３×ｑ－２　：　ｑはｍ／３以下の正の整数）を有する放電セルには赤の蛍光体が蛍光体層２５Ｒとして塗布されており、この放電セルは赤の放電セルとなる。データ電極Ｄｐ＋１を有する放電セルには緑の蛍光体が蛍光体層２５Ｇとして塗布されており、この放電セルは緑の放電セルとなる。データ電極Ｄｐ＋２を有する放電セルには青の蛍光体が蛍光体層２５Ｂとして塗布されており、この放電セルは青の放電セルとなる。そして、互いに隣接する赤の放電セル、緑の放電セルおよび青の放電セルが一組となって１つの画素を構成する。 For example, a red phosphor is applied as a phosphor layer 25R to a discharge cell having a data electrode Dp (p = 3 × q−2: q is a positive integer of m / 3 or less). It becomes a red discharge cell. The discharge cell having the data electrode Dp + 1 is coated with a green phosphor as the phosphor layer 25G, and this discharge cell becomes a green discharge cell. A blue phosphor is applied as a phosphor layer 25B to the discharge cell having the data electrode Dp + 2, and this discharge cell becomes a blue discharge cell. A red discharge cell, a green discharge cell, and a blue discharge cell adjacent to each other constitute a set to constitute one pixel.
　次に、本実施の形態におけるプラズマディスプレイ装置において発生する駆動電圧波形について図３と図４を用いて説明する。 Next, driving voltage waveforms generated in the plasma display device according to the present embodiment will be described with reference to FIGS.
　本実施の形態においては、１フィールドに、パネル１０に画像を表示するための複数の画像表示サブフィールド、タイミング検出サブフィールドＳＦｏ、ｙ座標検出サブフィールドＳＦｙ、およびｘ座標検出サブフィールドＳＦｘを備える。以下、画像表示サブフィールドを単にサブフィールドとも記す。 In this embodiment, one field includes a plurality of image display subfields for displaying an image on the panel 10, a timing detection subfield SFo, a y coordinate detection subfield SFy, and an x coordinate detection subfield SFx. Hereinafter, the image display subfield is also simply referred to as a subfield.
　各画像表示サブフィールドは、初期化期間、書込み期間および維持期間を有する。 Each image display subfield has an initialization period, an address period, and a sustain period.
　初期化期間では、各放電セルに初期化放電を発生し、続く書込み動作に必要な壁電荷を放電セル内に形成する。加えて、書込み動作に必要なプライミング粒子（放電の発生を補助する荷電粒子）を放電セル内に発生する。書込み期間では、発光を行うべき放電セルに書込み放電を発生する。維持期間では、走査電極と維持電極とに交互に維持パルスを印加し、書込み放電を発生した放電セルに維持放電を発生させる。 In the initialization period, initialization discharge is generated in each discharge cell, and wall charges necessary for the subsequent address operation are formed in the discharge cell. In addition, priming particles (charged particles that assist the generation of discharge) necessary for the address operation are generated in the discharge cell. In the address period, an address discharge is generated in the discharge cells that should emit light. In the sustain period, sustain pulses are alternately applied to the scan electrodes and the sustain electrodes, and a sustain discharge is generated in the discharge cells that have generated the address discharge.
　初期化期間における初期化動作には、「強制初期化動作」と「選択初期化動作」があり、発生する駆動電圧波形が互いに異なる。強制初期化動作では、直前のサブフィールドでの放電の有無にかかわらず放電セルに強制的に初期化放電を発生する。選択初期化動作では、直前のサブフィールドの書込み期間で書込み放電を発生した放電セルだけに選択的に初期化放電を発生する。 The initialization operation in the initialization period includes “forced initialization operation” and “selective initialization operation”, and generated drive voltage waveforms are different from each other. In the forced initializing operation, an initializing discharge is forcibly generated in the discharge cells regardless of the presence or absence of discharge in the immediately preceding subfield. In the selective initializing operation, initializing discharge is selectively generated only in the discharge cells that have generated address discharge in the address period of the immediately preceding subfield.
　本実施の形態では、１フィールドに含まれる複数のサブフィールドのうち、最初のサブフィールド（例えば、サブフィールドＳＦ１）を強制初期化動作を行うサブフィールド（強制初期化サブフィールド）とし、他のサブフィールド（例えば、サブフィールドＳＦ２以降のサブフィールド）を選択初期化動作を行うサブフィールド（選択初期化サブフィールド）とする例を説明する。 In the present embodiment, among the plurality of subfields included in one field, the first subfield (for example, subfield SF1) is set as a subfield (forced initialization subfield) for performing a forced initialization operation, and other subfields are included. An example will be described in which a field (for example, a subfield after subfield SF2) is used as a subfield (selective initialization subfield) for performing a selective initialization operation.
　また、画像表示サブフィールドにおいては、各サブフィールドに輝度重みをそれぞれ設定する。本実施の形態では、一例として、１フィールドに８つのサブフィールド（サブフィールドＳＦ１～ＳＦ８）を備え、各サブフィールドにそれぞれ（１、３４、２１、１３、８、５、３、２）の輝度重みを設定する例を挙げる。 Also, in the image display subfield, a luminance weight is set for each subfield. In the present embodiment, as an example, one field has eight subfields (subfields SF1 to SF8), and each subfield has a luminance of (1, 34, 21, 13, 8, 5, 3, 2). An example of setting a weight is given.
　画像表示領域内におけるライトペンの位置は、ｘ座標とｙ座標で表される。ｘ座標検出サブフィールドＳＦｘ、ｙ座標検出サブフィールドＳＦｙは、画像表示領域内におけるライトペンの位置（位置座標）のｘ座標、ｙ座標を検出するためのサブフィールドである。 The position of the light pen in the image display area is represented by the x coordinate and the y coordinate. The x-coordinate detection subfield SFx and the y-coordinate detection subfield SFy are subfields for detecting the x-coordinate and y-coordinate of the position (position coordinate) of the light pen in the image display area.
　なお、ライトペンは、プラズマディスプレイシステムに備えられたものであり、使用者がパネル上に文字や図画を手書き入力するためのものである。ライトペンの詳細は後述する。 The light pen is provided in the plasma display system, and is used by a user to input characters and drawings on the panel by handwriting. Details of the light pen will be described later.
　本実施の形態におけるプラズマディスプレイシステムでは、ライトペンと描画装置との間で無線通信を行う。ライトペンは、ライトペンの内部でライトペンの位置座標を算出し、算出した位置座標のデータをライトペンから描画装置へ無線通信によって送信する。 In the plasma display system in this embodiment, wireless communication is performed between the light pen and the drawing apparatus. The light pen calculates the position coordinates of the light pen inside the light pen, and transmits data of the calculated position coordinates from the light pen to the drawing apparatus by wireless communication.
　ライトペンからプラズマディスプレイ装置へ信号を無線送信する際には、ライトペン側で送信信号を無線通信が可能な形態にエンコードして無線送信し、プラズマディスプレイ装置側では受信した信号をデコードしなければならない。プラズマディスプレイ装置からライトペンへ信号を無線送信する場合も同様である。 When a signal is wirelessly transmitted from the light pen to the plasma display device, the light pen side must encode the transmission signal in a form that allows wireless communication and wirelessly transmit, and the plasma display device side must decode the received signal. Don't be. The same applies when a signal is wirelessly transmitted from the plasma display device to the light pen.
　このように、ライトペンとプラズマディスプレイ装置との間で無線通信を行う構成では、データの送受信に時間差が生じる。 As described above, in the configuration in which wireless communication is performed between the light pen and the plasma display device, a time difference occurs in data transmission / reception.
　そのため、ライトペンが受光信号をプラズマディスプレイ装置へ無線送信し、プラズマディスプレイ装置が受光信号を受信して位置座標を算出する構成では、正確な位置座標を算出することが困難である。したがって、ライトペン自らがライトペンの位置座標を算出し、算出した位置座標をプラズマディスプレイ装置に無線送信する方が望ましい。 Therefore, it is difficult to calculate an accurate position coordinate in a configuration in which the light pen wirelessly transmits a light reception signal to the plasma display apparatus and the plasma display apparatus receives the light reception signal and calculates the position coordinates. Therefore, it is preferable that the light pen itself calculates the position coordinates of the light pen and wirelessly transmits the calculated position coordinates to the plasma display device.
　ライトペンの内部でライトペンの位置座標を算出する際には、プラズマディスプレイ装置においてｙ座標検出サブフィールドＳＦｙおよびｘ座標検出サブフィールドＳＦｘが発生するタイミングを、ライトペンが正確に把握する必要がある。 When calculating the position coordinates of the light pen inside the light pen, it is necessary for the light pen to accurately grasp the timing at which the y coordinate detection subfield SFy and the x coordinate detection subfield SFx occur in the plasma display device. .
　本実施の形態では、ｙ座標検出サブフィールドＳＦｙおよびｘ座標検出サブフィールドＳＦｘが発生するタイミングを、ライトペン側で正確に把握できるようにするために、１フィールドにタイミング検出サブフィールドＳＦｏを設ける。すなわち、タイミング検出サブフィールドＳＦｏは、位置座標を検出するための基準となる信号（座標基準信号）をライトペン自らが高い精度で発生できるようにするためのものである。 In this embodiment, a timing detection subfield SFo is provided in one field so that the timing at which the y coordinate detection subfield SFy and the x coordinate detection subfield SFx are generated can be accurately grasped on the light pen side. That is, the timing detection subfield SFo is for allowing the light pen itself to generate a reference signal (coordinate reference signal) for detecting position coordinates with high accuracy.
　なお、本実施の形態では、各フィールドに、タイミング検出サブフィールドＳＦｏ、ｙ座標検出サブフィールドＳＦｙおよびｘ座標検出サブフィールドＳＦｘを設ける例を説明するが、タイミング検出サブフィールドＳＦｏ、ｙ座標検出サブフィールドＳＦｙおよびｘ座標検出サブフィールドＳＦｘは、必ずしも毎フィールドに設けなくともよい。例えば、映像信号やプラズマディスプレイ装置の使用状態等に応じて、複数フィールドに１回の割合でタイミング検出サブフィールドＳＦｏ、ｙ座標検出サブフィールドＳＦｙおよびｘ座標検出サブフィールドＳＦｘを発生する構成としてもよい。 In this embodiment, an example in which a timing detection subfield SFo, a y coordinate detection subfield SFy, and an x coordinate detection subfield SFx are provided in each field will be described. However, the timing detection subfield SFo, the y coordinate detection subfield is described. SFy and x-coordinate detection subfield SFx are not necessarily provided in each field. For example, the timing detection subfield SFo, the y-coordinate detection subfield SFy, and the x-coordinate detection subfield SFx may be generated at a rate of once per a plurality of fields in accordance with the video signal, the usage state of the plasma display device, and the like. .
　図３は、本発明の実施の形態における画像表示サブフィールドのサブフィールドＳＦ１～ＳＦ３においてパネル１０の各電極に印加する駆動電圧波形の一例を概略的に示す図である。 FIG. 3 schematically shows an example of a drive voltage waveform applied to each electrode of panel 10 in subfields SF1 to SF3 of the image display subfield in the embodiment of the present invention.
　図３には、維持電極ＳＵ１～ＳＵｎ、書込み期間において最初に書込み動作を行う走査電極ＳＣ１、書込み期間において最後に書込み動作を行う走査電極ＳＣｎ（例えば、走査電極ＳＣ１０８０）、データ電極Ｄ１～データ電極Ｄｍ（例えば、データ電極Ｄ５７６０）のそれぞれに印加する駆動電圧波形を示す。また、以下における走査電極ＳＣｉ、維持電極ＳＵｉ、データ電極Ｄｋは、各電極の中から画像データ（サブフィールド毎の発光・非発光を示すデータ）にもとづき選択された電極を表す。 FIG. 3 shows sustain electrodes SU1 to SUn, scan electrode SC1 that performs the address operation first in the address period, scan electrode SCn that performs the address operation last in the address period (for example, scan electrode SC1080), and data electrode D1 to data electrode. The drive voltage waveform applied to each of Dm (for example, data electrode D5760) is shown. Scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected based on image data (data indicating light emission / non-light emission for each subfield) from among the electrodes.
　なお、サブフィールドＳＦ３以降の各サブフィールドは、維持パルスの発生数を除き、サブフィールドＳＦ２とほぼ同様の駆動電圧波形を発生する。 It should be noted that each subfield after subfield SF3 generates a drive voltage waveform substantially similar to that of subfield SF2, except for the number of sustain pulses.
　強制初期化動作を行うサブフィールドＳＦ１の初期化期間Ｐｉａ１の前半部では、データ電極Ｄ１～Ｄｍ、維持電極ＳＵ１～ＳＵｎに、それぞれ電圧０（Ｖ）を印加する。走査電極ＳＣ１～ＳＣｎには、電圧０（Ｖ）を印加した後に電圧Ｖｉ１を印加し、電圧Ｖｉ１から電圧Ｖｉ２まで緩やかに上昇する傾斜波形電圧（以下、「上り傾斜波形電圧」と呼称する）を印加する。 In the first half of the initialization period Pia1 of the subfield SF1 in which the forced initialization operation is performed, the voltage 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn. A scan waveform SC1 to SCn is applied with voltage Vi1 after voltage 0 (V) is applied, and a ramp waveform voltage (hereinafter referred to as “upward ramp waveform voltage”) that gradually rises from voltage Vi1 to voltage Vi2. Apply.
　電圧Ｖｉ１は、維持電極ＳＵ１～ＳＵｎに対して放電開始電圧よりも低い電圧に設定し、電圧Ｖｉ２は、維持電極ＳＵ１～ＳＵｎに対して放電開始電圧を超える電圧に設定する。 The voltage Vi1 is set to a voltage lower than the discharge start voltage for the sustain electrodes SU1 to SUn, and the voltage Vi2 is set to a voltage exceeding the discharge start voltage for the sustain electrodes SU1 to SUn.
　この上り傾斜波形電圧が上昇する間に、各放電セルの走査電極ＳＣ１～ＳＣｎと維持電極ＳＵ１～ＳＵｎとの間、および走査電極ＳＣ１～ＳＣｎとデータ電極Ｄ１～Ｄｍとの間に、それぞれ微弱な初期化放電が持続して発生する。 While the rising ramp waveform voltage rises, it is weak between the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, and between the scan electrodes SC1 to SCn and the data electrodes D1 to Dm, respectively. Initializing discharge is generated continuously.
　そして、走査電極ＳＣ１～ＳＣｎ上に負極性の壁電圧が蓄積され、データ電極Ｄ１～Ｄｍ上および維持電極ＳＵ１～ＳＵｎ上には正極性の壁電圧が蓄積される。さらに、書込み放電の発生を補助するプライミング粒子が放電セル内に発生する。この電極上の壁電圧とは、電極を覆う誘電体層上、保護層上、蛍光体層上等に蓄積された壁電荷により生じる電圧を表す。 Then, negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Further, priming particles that assist the generation of the address discharge are generated in the discharge cell. The wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.
　走査電極ＳＣ１～ＳＣｎに印加する電圧が電圧Ｖｉ２に到達したら、走査電極ＳＣ１～ＳＣｎの電圧を、電圧Ｖｉ２よりも低い電圧Ｖｉ３まで一旦下げ、その後、電圧０（Ｖ）に下げる。電圧Ｖｉ３は、電圧Ｖｉ２よりも低い電圧で、かつ維持電極ＳＵ１～ＳＵｎに対して放電開始電圧未満の電圧に設定する。本実施の形態では電圧Ｖｉ３を約２００（Ｖ）とする例を示すが、電圧Ｖｉ３は放電セルに放電が発生しない電圧であればよい。また、電圧Ｖｉ２から電圧０（Ｖ）まで急峻に電圧を下げてもよい。 When the voltage applied to scan electrodes SC1 to SCn reaches voltage Vi2, the voltage of scan electrodes SC1 to SCn is once lowered to voltage Vi3 lower than voltage Vi2, and then lowered to voltage 0 (V). The voltage Vi3 is set to a voltage lower than the voltage Vi2 and lower than the discharge start voltage with respect to the sustain electrodes SU1 to SUn. Although an example in which the voltage Vi3 is about 200 (V) is shown in this embodiment, the voltage Vi3 may be a voltage that does not cause discharge in the discharge cells. Further, the voltage may be sharply decreased from the voltage Vi2 to the voltage 0 (V).
　サブフィールドＳＦ１の初期化期間Ｐｉａ１の後半部では、データ電極Ｄ１～Ｄｍには電圧０（Ｖ）を印加し、維持電極ＳＵ１～ＳＵｎには正の電圧Ｖｅを印加する。 In the latter half of the initialization period Pia1 of the subfield SF1, a voltage 0 (V) is applied to the data electrodes D1 to Dm, and a positive voltage Ve is applied to the sustain electrodes SU1 to SUn.
　走査電極ＳＣ１～ＳＣｎには、放電開始電圧未満となる電圧（例えば、電圧０（Ｖ））から負の電圧Ｖｉ４まで緩やかに下降する傾斜波形電圧（以下、単に「下り傾斜波形電圧」とも記す）を印加する。電圧Ｖｉ４は、維持電極ＳＵ１～ＳＵｎに対して放電開始電圧を超える電圧に設定する。 The scan electrodes SC1 to SCn have a ramp waveform voltage that gradually falls from a voltage that is less than the discharge start voltage (eg, voltage 0 (V)) to a negative voltage Vi4 (hereinafter also simply referred to as “down ramp waveform voltage”). Is applied. Voltage Vi4 is set to a voltage exceeding the discharge start voltage with respect to sustain electrodes SU1 to SUn.
　この下り傾斜波形電圧を走査電極ＳＣ１～ＳＣｎに印加する間に、各放電セルの走査電極ＳＣ１～ＳＣｎと維持電極ＳＵ１～ＳＵｎとの間、および走査電極ＳＣ１～ＳＣｎとデータ電極Ｄ１～Ｄｍとの間に、それぞれ微弱な初期化放電が持続して発生する。これにより、走査電極ＳＣ１～ＳＣｎ上の負極性の壁電圧および維持電極ＳＵ１～ＳＵｎ上の正極性の壁電圧が弱められ、データ電極Ｄ１～Ｄｍ上の正極性の壁電圧は、続く書込み期間Ｐｗ１での書込み動作に適した電圧に調整される。また、プライミング粒子が放電セル内に発生する。 While this downward ramp waveform voltage is applied to scan electrodes SC1 to SCn, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn of each discharge cell, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm. In the meantime, weak initializing discharges are continuously generated. As a result, the negative wall voltage on scan electrodes SC1 to SCn and the positive wall voltage on sustain electrodes SU1 to SUn are weakened, and the positive wall voltage on data electrodes D1 to Dm remains in the subsequent writing period Pw1. The voltage is adjusted to a voltage suitable for the write operation. Further, priming particles are generated in the discharge cell.
　下り傾斜波形電圧が電圧Ｖｉ４に到達したら、走査電極ＳＣ１～ＳＣｎに印加する電圧を電圧Ｖｃにする。 When the descending ramp waveform voltage reaches the voltage Vi4, the voltage applied to the scan electrodes SC1 to SCn is set to the voltage Vc.
　初期化期間Ｐｉａ１に発生する上述の駆動電圧波形が、強制初期化波形である。そして、この強制初期化動作により、初期化放電が発生した各放電セルの壁電圧をほぼ均一な状態にすることができる。 The above-mentioned drive voltage waveform generated in the initialization period Pia1 is a forced initialization waveform. By this forced initializing operation, the wall voltage of each discharge cell in which the initializing discharge has occurred can be made substantially uniform.
　なお、本実施の形態では、強制初期化動作を、パネル１０の画像表示領域内にある全ての放電セルに強制的に初期化放電を発生する初期化動作として説明するが、本発明は何らこの構成に限定されない。本実施の形態では、例えば、パネルの画像表示領域内にある一部の放電セルにのみ強制初期化波形を印加する動作も強制初期化動作とし、その強制初期化動作を行うサブフィールドを強制初期化サブフィールドとする。例えば、奇数フィールドのサブフィールドＳＦ１では奇数行の走査電極ＳＣ（２Ｎ－１）（Ｎは１以上の整数）にのみ強制初期化波形を印加し、他の走査電極ＳＣ（２Ｎ）には後述の選択初期化波形を印加し、偶数フィールドのサブフィールドＳＦ１では偶数行の走査電極ＳＣ（２Ｎ）にのみ強制初期化波形を印加し、他の走査電極ＳＣ（２Ｎ－１）には選択初期化波形を印加する、というように、フィールド毎に強制初期化波形を印加する走査電極ＳＣ１～ＳＣｎを変更してもよい。これは、以下の説明における強制初期化動作を行う全てのサブフィールドについても同様である。 In the present embodiment, the forced initializing operation is described as an initializing operation for forcibly generating an initializing discharge in all the discharge cells in the image display area of panel 10, but the present invention is not limited to this. It is not limited to the configuration. In the present embodiment, for example, an operation for applying a forced initialization waveform only to a part of the discharge cells in the image display area of the panel is also a forced initialization operation, and a subfield for performing the forced initialization operation is forcibly initialized. Subfield. For example, in the odd-field subfield SF1, the forced initializing waveform is applied only to the odd-numbered scan electrodes SC (2N-1) (N is an integer of 1 or more), and the other scan electrodes SC (2N) are described later. A selective initialization waveform is applied. In the even-field subfield SF1, a forced initialization waveform is applied only to the even-numbered scan electrode SC (2N), and a selective initialization waveform is applied to the other scan electrode SC (2N-1). For example, the scan electrodes SC1 to SCn to which the forced initialization waveform is applied may be changed for each field. The same applies to all subfields that perform the forced initialization operation in the following description.
　サブフィールドＳＦ１の書込み期間Ｐｗ１では、データ電極Ｄ１～Ｄｍには電圧０（Ｖ）を印加し、維持電極ＳＵ１～ＳＵｎには電圧Ｖｅを印加し、走査電極ＳＣ１～ＳＣｎには電圧Ｖｃを印加する。 In address period Pw1 of subfield SF1, voltage 0 (V) is applied to data electrodes D1 to Dm, voltage Ve is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn. .
　次に、１行目の走査電極ＳＣ１に負の電圧Ｖａの負極性の走査パルスを印加する。そして、データ電極Ｄ１～Ｄｍのうちの１行目において発光するべき放電セルのデータ電極Ｄｋに正の電圧Ｖｄの正極性の書込みパルスを印加する。 Next, a negative scan pulse having a negative voltage Va is applied to the scan electrode SC1 in the first row. Then, a positive address pulse of a positive voltage Vd is applied to the data electrode Dk of the discharge cell that should emit light in the first row of the data electrodes D1 to Dm.
　書込みパルスの電圧Ｖｄを印加したデータ電極Ｄｋと走査パルスの電圧Ｖａを印加した走査電極ＳＣ１との交差部にある放電セルでは、データ電極Ｄｋと走査電極ＳＣ１との間に放電が発生し、維持電極ＳＵ１と走査電極ＳＣ１との間にも放電が発生する。こうして、走査パルスの電圧Ｖａと書込みパルスの電圧Ｖｄとが同時に印加された放電セル（発光するべき放電セル）に書込み放電が発生する。 In the discharge cell at the intersection of the data electrode Dk to which the address pulse voltage Vd is applied and the scan electrode SC1 to which the scan pulse voltage Va is applied, a discharge occurs between the data electrode Dk and the scan electrode SC1, and is maintained. A discharge is also generated between the electrode SU1 and the scan electrode SC1. Thus, address discharge is generated in the discharge cells (discharge cells to emit light) to which the scan pulse voltage Va and the address pulse voltage Vd are simultaneously applied.
　書込み放電が発生した放電セルでは、走査電極ＳＣ１上に正極性の壁電圧が蓄積され、維持電極ＳＵ１上に負極性の壁電圧が蓄積され、データ電極Ｄｋ上にも負極性の壁電圧が蓄積される。 In the discharge cell in which the address discharge has occurred, positive wall voltage is accumulated on scan electrode SC1, negative wall voltage is accumulated on sustain electrode SU1, and negative wall voltage is also accumulated on data electrode Dk. Is done.
　なお、書込みパルスを印加しなかった放電セルでは、データ電極Ｄｈ（データ電極Ｄｈはデータ電極Ｄ１～Ｄｍのうちデータ電極Ｄｋを除いたもの）と走査電極ＳＣ１との交差部の電圧は放電開始電圧を超えないので、書込み放電は発生しない。 In a discharge cell to which no address pulse is applied, the voltage at the intersection of data electrode Dh (data electrode Dh is data electrode D1-Dm excluding data electrode Dk) and scan electrode SC1 is the discharge start voltage. Therefore, the address discharge does not occur.
　次に、２行目の走査電極ＳＣ２に電圧Ｖａの走査パルスを印加するとともに、２行目に発光するべき放電セルに対応するデータ電極Ｄｋに電圧Ｖｄの書込みパルスを印加する。これにより、走査パルスと書込みパルスとが同時に印加された２行目の放電セルでは書込み放電が発生する。書込みパルスが印加されなかった放電セルでは書込み放電は発生しない。こうして、２行目の放電セルにおける書込み動作を行う。 Next, a scan pulse of voltage Va is applied to scan electrode SC2 in the second row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light in the second row. As a result, address discharge occurs in the discharge cells in the second row to which the scan pulse and address pulse are simultaneously applied. Address discharge does not occur in the discharge cells to which no address pulse is applied. Thus, the address operation in the discharge cells in the second row is performed.
　同様の書込み動作を、走査電極ＳＣ３、走査電極ＳＣ４、・・・、走査電極ＳＣｎという順番で、ｎ行目の放電セルに至るまで順次行い、サブフィールドＳＦ１の書込み期間Ｐｗ１が終了する。このように、書込み期間Ｐｗ１では、発光するべき放電セルに選択的に書込み放電を発生し、その放電セルに維持放電のための壁電荷を形成する。 The same addressing operation is sequentially performed in the order of scan electrode SC3, scan electrode SC4,..., Scan electrode SCn up to the discharge cell in the n-th row, and the address period Pw1 of subfield SF1 ends. As described above, in the address period Pw1, address discharge is selectively generated in the discharge cells to emit light, and wall charges for sustain discharge are formed in the discharge cells.
　なお、本発明は、走査電極ＳＣ１～ＳＣｎに走査パルスを印加する順番が何ら上述した順番に限定されるものではない。走査電極ＳＣ１～ＳＣｎに走査パルスを印加する順番は、画像表示装置における仕様等に応じて任意に設定すればよい。 In the present invention, the order in which the scan pulses are applied to the scan electrodes SC1 to SCn is not limited to the order described above. The order in which the scan pulses are applied to the scan electrodes SC1 to SCn may be arbitrarily set according to the specifications of the image display device.
　サブフィールドＳＦ１の維持期間Ｐｓ１では、データ電極Ｄ１～Ｄｍに電圧０（Ｖ）を印加する。そして、走査電極ＳＣ１～ＳＣｎに正の電圧Ｖｓの維持パルスを印加するとともに、維持電極ＳＵ１～ＳＵｎに電圧０（Ｖ）を印加する。 In the sustain period Ps1 of the subfield SF1, voltage 0 (V) is applied to the data electrodes D1 to Dm. Then, a sustain pulse of positive voltage Vs is applied to scan electrodes SC1 to SCn, and voltage 0 (V) is applied to sustain electrodes SU1 to SUn.
　この維持パルスの印加により、直前の書込み期間Ｐｗ１に書込み放電を発生した放電セルでは、走査電極ＳＣｉと維持電極ＳＵｉとの間に維持放電が発生する。そして、維持放電によって発生した紫外線により、この放電セルの蛍光体層２５が発光する。 By applying the sustain pulse, a sustain discharge is generated between the scan electrode SCi and the sustain electrode SUi in the discharge cell that has generated the address discharge in the immediately preceding address period Pw1. The phosphor layer 25 of the discharge cell emits light due to the ultraviolet rays generated by the sustain discharge.
　また、この維持放電により、走査電極ＳＣｉ上に負極性の壁電圧が蓄積され、維持電極ＳＵｉ上に正極性の壁電圧が蓄積される。さらに、データ電極Ｄｋ上にも正極性の壁電圧が蓄積される。ただし、直前の書込み期間Ｐｗ１において書込み放電が発生しなかった放電セルでは維持放電は発生せず、初期化期間Ｐｉａ１の終了時における壁電圧が保たれる。 Also, due to the sustain discharge, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is also accumulated on the data electrode Dk. However, the sustain discharge does not occur in the discharge cells in which the address discharge has not occurred in the immediately preceding address period Pw1, and the wall voltage at the end of the initialization period Pia1 is maintained.
　続いて、走査電極ＳＣ１～ＳＣｎに電圧０（Ｖ）を印加し、維持電極ＳＵ１～ＳＵｎに電圧Ｖｓの維持パルスを印加する。直前に維持放電を発生した放電セルでは再び維持放電が発生し、維持電極ＳＵｉ上に負極性の壁電圧が蓄積され、走査電極ＳＣｉ上に正極性の壁電圧が蓄積される。 Subsequently, voltage 0 (V) is applied to scan electrodes SC1 to SCn, and a sustain pulse of voltage Vs is applied to sustain electrodes SU1 to SUn. In the discharge cell that has generated a sustain discharge immediately before, a sustain discharge occurs again, and a negative wall voltage is accumulated on the sustain electrode SUi, and a positive wall voltage is accumulated on the scan electrode SCi.
　以降同様に、走査電極ＳＣ１～ＳＣｎと維持電極ＳＵ１～ＳＵｎとに、輝度重みに所定の輝度倍数を乗じた数の維持パルスを交互に印加する。こうして、直前の書込み期間Ｐｗ１において書込み放電を発生した放電セルは、輝度重みに応じた回数の維持放電が発生し、輝度重みに応じた輝度で発光する。 Thereafter, similarly, the number of sustain pulses obtained by multiplying the brightness weight by a predetermined brightness multiple is alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. In this way, the discharge cells that have generated the address discharge in the immediately preceding address period Pw1 generate the sustain discharge the number of times corresponding to the luminance weight, and emit light with the luminance corresponding to the luminance weight.
　そして、維持パルスの発生後（維持期間Ｐｓ１において維持動作が終了した後）には、維持電極ＳＵ１～ＳＵｎおよびデータ電極Ｄ１～Ｄｍに電圧０（Ｖ）を印加したまま、走査電極ＳＣ１～ＳＣｎに電圧０（Ｖ）から正の電圧Ｖｒまで緩やかに上昇する上り傾斜波形電圧を印加する。 After the sustain pulse is generated (after the sustain operation is completed in sustain period Ps1), voltage 0 (V) is applied to sustain electrodes SU1 to SUn and data electrodes D1 to Dm, and applied to scan electrodes SC1 to SCn. An upward ramp waveform voltage that gradually rises from the voltage 0 (V) to the positive voltage Vr is applied.
　維持放電を発生した放電セルでは、維持電極ＳＵｉ上に負極性の壁電圧が蓄積され、走査電極ＳＣｉ上に正極性の壁電圧が蓄積されているので、それらの放電セルの放電開始電圧を超える電圧に電圧Ｖｒを設定する。これにより、走査電極ＳＣ１～ＳＣｎにこの上り傾斜波形電圧を印加する間に、維持放電を発生した放電セルの維持電極ＳＵｉと走査電極ＳＣｉとの間に微弱な放電（消去放電）が持続して発生する。 In the discharge cells that have generated the sustain discharge, the negative wall voltage is accumulated on the sustain electrode SUi and the positive wall voltage is accumulated on the scan electrode SCi, so that the discharge start voltage of those discharge cells is exceeded. The voltage Vr is set as the voltage. As a result, a weak discharge (erase discharge) is maintained between sustain electrode SUi and scan electrode SCi of the discharge cell that has generated the sustain discharge while applying this upward ramp waveform voltage to scan electrodes SC1 to SCn. appear.
　これにより、データ電極Ｄｋ上の正極性の壁電圧を残したまま、走査電極ＳＣｉ上の壁電圧および維持電極ＳＵｉ上の壁電圧が弱められ、放電セル内の不要な壁電荷が消去される。 Thereby, the wall voltage on the scan electrode SCi and the wall voltage on the sustain electrode SUi are weakened while leaving the positive wall voltage on the data electrode Dk, and unnecessary wall charges in the discharge cell are erased.
　上り傾斜波形電圧が電圧Ｖｒに到達したら、走査電極ＳＣ１～ＳＣｎに印加する電圧を電圧０（Ｖ）まで下げる。こうして、維持期間Ｐｓ１の最後に行う消去動作が終了し、サブフィールドＳＦ１が終了する。 When the rising ramp waveform voltage reaches the voltage Vr, the voltage applied to the scan electrodes SC1 to SCn is lowered to the voltage 0 (V). Thus, the erase operation performed at the end of sustain period Ps1 ends, and subfield SF1 ends.
　次に、選択初期化サブフィールドについてサブフィールドＳＦ２を例に挙げて説明する。なお、本実施の形態では、サブフィールドＳＦ３以降の初期化期間Ｐｉｂ３～Ｐｉｂ８においても、サブフィールドＳＦ２の初期化期間Ｐｉｂ２と同様の駆動電圧波形を各電極に印加して、選択初期化動作を行う。 Next, the selective initialization subfield will be described by taking the subfield SF2 as an example. In the present embodiment, in the initialization periods Pib3 to Pib8 after the subfield SF3, the same drive voltage waveform as that in the initialization period Pib2 of the subfield SF2 is applied to each electrode to perform the selective initialization operation. .
　サブフィールドＳＦ２の初期化期間Ｐｉｂ２では、データ電極Ｄ１～Ｄｍには電圧０（Ｖ）を印加し、維持電極ＳＵ１～ＳＵｎには正の電圧Ｖｅを印加する。走査電極ＳＣ１～ＳＣｎには、放電開始電圧未満となる電圧（例えば、電圧０（Ｖ））から負の電圧Ｖｉ４まで下降する下り傾斜波形電圧を印加する。この下り傾斜波形電圧は、初期化期間Ｐｉａ１で発生した下り傾斜波形電圧と同じ勾配で同じ電圧Ｖｉ４まで下降する波形形状を有する。 In the initialization period Pib2 of the subfield SF2, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn. A downward ramp waveform voltage that falls from a voltage (for example, voltage 0 (V)) that is lower than the discharge start voltage to a negative voltage Vi4 is applied to scan electrodes SC1 to SCn. This downward ramp waveform voltage has a waveform shape that drops to the same voltage Vi4 at the same gradient as the downward ramp waveform voltage generated in the initialization period Pia1.
　この下り傾斜波形電圧を走査電極ＳＣ１～ＳＣｎに印加する間に、直前のサブフィールドＳＦ１の維持期間Ｐｓ１で維持放電を発生した放電セルに微弱な初期化放電が発生する。 While applying this downward ramp waveform voltage to scan electrodes SC1 to SCn, a weak initializing discharge is generated in the discharge cell that has generated a sustain discharge in sustain period Ps1 of immediately preceding subfield SF1.
　この初期化放電により、走査電極ＳＣｉ上の壁電圧および維持電極ＳＵｉ上の壁電圧が弱められる。また、直前の維持放電によってデータ電極Ｄｋ上に蓄積された正極性の壁電圧は、過剰な部分が放電され、書込み動作に適した壁電圧に調整される。 This initialization discharge weakens the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. In addition, the positive wall voltage accumulated on the data electrode Dk by the last sustain discharge is adjusted to a wall voltage suitable for the address operation by discharging an excessive portion.
　一方、直前のサブフィールドＳＦ１の維持期間Ｐｓ１に維持放電を発生しなかった放電セルでは、初期化放電は発生せず、サブフィールドＳＦ１の初期化期間Ｐｉａ１終了時における壁電圧が保たれる。 On the other hand, in the discharge cells that did not generate the sustain discharge in the sustain period Ps1 of the immediately preceding subfield SF1, the initialization discharge does not occur, and the wall voltage at the end of the initialization period Pia1 of the subfield SF1 is maintained.
　下り傾斜波形電圧が電圧Ｖｉ４に到達したら、走査電極ＳＣ１～ＳＣｎに印加する電圧を電圧Ｖｃにする。 When the descending ramp waveform voltage reaches the voltage Vi4, the voltage applied to the scan electrodes SC1 to SCn is set to the voltage Vc.
　この初期化期間Ｐｉｂ２に発生する上述の駆動電圧波形が、選択初期化波形である。 The above-mentioned drive voltage waveform generated in the initialization period Pib2 is a selective initialization waveform.
　なお、電圧Ｖｉ４および電圧Ｖｅは、パネル１０の特性やプラズマディスプレイ装置３０の仕様等に応じて、上述の動作を満たす電圧値に設定する。 The voltage Vi4 and the voltage Ve are set to voltage values that satisfy the above-described operation according to the characteristics of the panel 10, the specifications of the plasma display device 30, and the like.
　サブフィールドＳＦ２の書込み期間Ｐｗ２および維持期間Ｐｓ２は、維持パルスの発生数を除き、サブフィールドＳＦ１の書込み期間Ｐｗ１および維持期間Ｐｓ１と同様の駆動電圧波形を各電極に印加するので説明を省略する。 In the address period Pw2 and the sustain period Ps2 in the subfield SF2, the drive voltage waveforms similar to those in the address period Pw1 and the sustain period Ps1 in the subfield SF1 are applied to the respective electrodes, except for the number of sustain pulses generated, and thus the description thereof is omitted.
　サブフィールドＳＦ３以降の各サブフィールドでは、維持パルスの発生数を除き、サブフィールドＳＦ２と同様の駆動電圧波形を各電極に印加するので説明を省略する。 In each subfield after subfield SF3, the drive voltage waveform similar to that in subfield SF2 is applied to each electrode except for the number of sustain pulses, and the description thereof is omitted.
　なお、本実施の形態では、強制初期化動作を行うサブフィールドをサブフィールドＳＦ１とする例を説明したが、本発明は何らこの構成に限定されない。強制初期化動作を行うサブフィールドはサブフィールドＳＦ２以降のサブフィールドであってもよい。 In the present embodiment, an example has been described in which the subfield for performing the forced initialization operation is the subfield SF1, but the present invention is not limited to this configuration. The subfield in which the forced initialization operation is performed may be a subfield after subfield SF2.
　なお、本実施の形態では、強制初期化動作を１フィールドに１回行う例を説明したが、本発明は何らこの構成に限定されない。強制初期化動作を行う回数は複数フィールドに１回であってもよい。 In the present embodiment, the example in which the forced initialization operation is performed once per field has been described, but the present invention is not limited to this configuration. The number of times of performing the forced initialization operation may be once in a plurality of fields.
　次に、タイミング検出サブフィールドＳＦｏ、ｙ座標検出サブフィールドＳＦｙおよびｘ座標検出サブフィールドＳＦｘについて説明する。なお、座標検出サブフィールドは、タイミング検出サブフィールドＳＦｏ、ｙ座標検出サブフィールドＳＦｙおよびｘ座標検出サブフィールドＳＦｘの総称である。 Next, the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx will be described. The coordinate detection subfield is a generic name for the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx.
　図４は、本発明の実施の形態におけるタイミング検出サブフィールドＳＦｏ、ｙ座標検出サブフィールドＳＦｙおよびｘ座標検出サブフィールドＳＦｘにおいてパネル１０の各電極に印加する駆動電圧波形の一例を概略的に示す図である。 FIG. 4 schematically shows an example of a drive voltage waveform applied to each electrode of panel 10 in timing detection subfield SFo, y coordinate detection subfield SFy, and x coordinate detection subfield SFx in the embodiment of the present invention. It is.
　図４には、タイミング検出サブフィールドＳＦｏ、ｙ座標検出サブフィールドＳＦｙおよびｘ座標検出サブフィールドＳＦｘにおいて、維持電極ＳＵ１～ＳＵｎ、走査電極ＳＣ１、走査電極ＳＣｎ、データ電極Ｄ１～Ｄｍのそれぞれに印加する駆動電圧波形を示す。また、図４には、タイミング検出サブフィールドＳＦｏの直前のサブフィールドＳＦ８の維持期間Ｐｓ８の一部、およびサブフィールドＳＦ１の一部もあわせて示す。 In FIG. 4, in the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx, the sustain electrodes SU1 to SUn, the scan electrode SC1, the scan electrode SCn, and the data electrodes D1 to Dm are applied. A drive voltage waveform is shown. FIG. 4 also shows a part of the sustain period Ps8 of the subfield SF8 immediately before the timing detection subfield SFo and a part of the subfield SF1.
　タイミング検出サブフィールドＳＦｏは、初期化期間Ｐｉａｏ、書込み期間Ｐｗｏ、およびタイミング検出期間Ｐｏを有する。 The timing detection subfield SFo has an initialization period Piao, an address period Pwo, and a timing detection period Po.
　初期化期間Ｐｉａｏでは、画像表示サブフィールドのサブフィールドＳＦ１の初期化期間Ｐｉａ１と同様の駆動電圧波形を各電極に印加して同様の強制初期化動作を行うので、説明を省略する。 In the initialization period Piao, a driving voltage waveform similar to that in the initialization period Pia1 of the subfield SF1 of the image display subfield is applied to each electrode to perform the same forced initialization operation, and thus description thereof is omitted.
　タイミング検出サブフィールドＳＦｏの書込み期間Ｐｗｏでは、データ電極Ｄ１～Ｄｍには電圧０（Ｖ）を印加し、維持電極ＳＵ１～ＳＵｎには電圧Ｖｅを印加し、走査電極ＳＣ１～ＳＣｎには電圧Ｖｃを印加する。 In the address period Pwo of the timing detection subfield SFo, the voltage 0 (V) is applied to the data electrodes D1 to Dm, the voltage Ve is applied to the sustain electrodes SU1 to SUn, and the voltage Vc is applied to the scan electrodes SC1 to SCn. Apply.
　次に、データ電極Ｄ１～Ｄｍに電圧Ｖｄの書込みパルスを印加するとともに走査電極ＳＣ１～ＳＣｎに電圧Ｖａの走査パルスを印加し、各放電セルに書込み放電を発生させる。 Next, an address pulse of the voltage Vd is applied to the data electrodes D1 to Dm and a scan pulse of the voltage Va is applied to the scan electrodes SC1 to SCn to generate an address discharge in each discharge cell.
　本実施の形態では、図４に示すように、全てのデータ電極Ｄ１～Ｄｍに書込みパルスを印加したまま、走査電極ＳＣ１から走査電極ＳＣｎまでの各電極に順次走査パルスを印加するが、例えば、全ての走査電極ＳＣ１～ＳＣｎに一斉に走査パルスを印加して、パネル１０の画像表示領域内にある全ての放電セルに一斉に書込み放電を発生させてもよい。 In the present embodiment, as shown in FIG. 4, the scan pulse is sequentially applied to each of the electrodes from the scan electrode SC1 to the scan electrode SCn while applying the write pulse to all the data electrodes D1 to Dm. It is also possible to apply a scan pulse to all the scan electrodes SC1 to SCn at a time and generate an address discharge in all the discharge cells in the image display area of the panel 10 at the same time.
　パネル１０の画像表示領域内にある全ての放電セルに書込み放電を発生し終えた後は、データ電極Ｄ１～Ｄｍに電圧０（Ｖ）を印加する。また、走査電極ＳＣ１～ＳＣｎには電圧Ｖｃを印加し、その後、電圧０（Ｖ）を印加する。また、維持電極ＳＵ１～ＳＵｎへの印加電圧を電圧Ｖｅから電圧０（Ｖ）にする。本実施の形態では、この状態を、時刻ｔｏ０から時間Ｔｏ０の間、維持する。したがって、この期間は、放電セルに最後の書込み放電が発生した後、放電が発生しない状態が維持される。なお、時刻ｔｏ０は、最後の書込み放電を発生させるための走査パルスを走査電極ＳＣｎに印加した時刻である。 After completing the address discharge in all the discharge cells in the image display area of the panel 10, the voltage 0 (V) is applied to the data electrodes D1 to Dm. Further, voltage Vc is applied to scan electrodes SC1 to SCn, and then voltage 0 (V) is applied. Further, the voltage applied to sustain electrodes SU1 to SUn is changed from voltage Ve to voltage 0 (V). In the present embodiment, this state is maintained from time to0 to time To0. Therefore, during this period, after the last address discharge occurs in the discharge cells, a state in which no discharge occurs is maintained. Time to0 is the time when the scan pulse for generating the last address discharge is applied to scan electrode SCn.
　そして、本実施の形態では、時間Ｔｏ０を、後述する時間Ｔｏ１、時間Ｔｏ２、時間Ｔｏ３のいずれよりも長い時間に設定する。本実施の形態では、時間Ｔｏ０は、例えば、約５０μｓｅｃである。 In this embodiment, the time To0 is set to a time longer than any of the time To1, the time To2, and the time To3 described later. In the present embodiment, the time To0 is about 50 μsec, for example.
　次に、タイミング検出サブフィールドＳＦｏのタイミング検出期間Ｐｏでは、ライトペンにおける位置座標算出時の基準となる複数回の発光（タイミング検出用の発光）をパネル１０に生じさせる。すなわち、あらかじめ定められた所定の時間間隔（本実施の形態では、例えば、時間Ｔｏ１、時間Ｔｏ２、時間Ｔｏ３）で、パネル１０の画像表示領域内の全ての放電セルに、タイミング検出用の発光を生じさせるタイミング検出放電を複数回（本実施の形態では、例えば、４回）発生させる。 Next, in the timing detection period Po of the timing detection subfield SFo, the panel 10 is caused to emit a plurality of times of light emission (light emission for timing detection) as a reference when calculating the position coordinates of the light pen. That is, light emission for timing detection is emitted to all the discharge cells in the image display area of the panel 10 at a predetermined time interval (in this embodiment, for example, time To1, time To2, and time To3 in this embodiment). The timing detection discharge to be generated is generated a plurality of times (in this embodiment, for example, four times).
　具体的には、時刻ｔｏ０から時間Ｔｏ０が経過した後の時刻ｔｏ１において、維持電極ＳＵ１～ＳＵｎに電圧０（Ｖ）を印加するとともに走査電極ＳＣ１～ＳＣｎに電圧Ｖｓｏのタイミング検出パルスＶ１を印加する。これにより、パネル１０の画像表示領域内にある全ての放電セルに１回目のタイミング検出放電が発生し、パネル１０の画像表示面の全面が発光する（１回目のタイミング検出用の発光）。 Specifically, at time to1 after time To0 has elapsed from time to0, voltage 0 (V) is applied to sustain electrodes SU1 to SUn, and timing detection pulse V1 of voltage Vso is applied to scan electrodes SC1 to SCn. . As a result, the first timing detection discharge is generated in all the discharge cells in the image display area of the panel 10, and the entire image display surface of the panel 10 emits light (first timing detection light emission).
　次に、時刻ｔｏ１から時間Ｔｏ１が経過した後の時刻ｔｏ２において、走査電極ＳＣ１～ＳＣｎに電圧０（Ｖ）を印加するとともに維持電極ＳＵ１～ＳＵｎに電圧Ｖｓｏのタイミング検出パルスＶ２を印加する。これにより、パネル１０の画像表示領域内にある全ての放電セルに２回目のタイミング検出放電が発生し、パネル１０の画像表示面の全面が発光する（２回目のタイミング検出用の発光）。 Next, at time to2 after time To1 has elapsed from time to1, voltage 0 (V) is applied to scan electrodes SC1 to SCn and timing detection pulse V2 of voltage Vso is applied to sustain electrodes SU1 to SUn. Thereby, the second timing detection discharge is generated in all the discharge cells in the image display area of the panel 10, and the entire image display surface of the panel 10 emits light (second timing detection light emission).
　次に、時刻ｔｏ２から時間Ｔｏ２が経過した後の時刻ｔｏ３において、維持電極ＳＵ１～ＳＵｎに電圧０（Ｖ）を印加するとともに走査電極ＳＣ１～ＳＣｎに電圧Ｖｓｏのタイミング検出パルスＶ３を印加する。これにより、パネル１０の画像表示領域内にある全ての放電セルに３回目のタイミング検出放電が発生し、パネル１０の画像表示面の全面が発光する（３回目のタイミング検出用の発光）。 Next, at time to3 after time To2 has elapsed from time to2, voltage 0 (V) is applied to sustain electrodes SU1 to SUn, and timing detection pulse V3 of voltage Vso is applied to scan electrodes SC1 to SCn. As a result, the third timing detection discharge is generated in all the discharge cells in the image display region of the panel 10, and the entire image display surface of the panel 10 emits light (third timing detection light emission).
　次に、時刻ｔｏ３から時間Ｔｏ３が経過した後の時刻ｔｏ４において、走査電極ＳＣ１～ＳＣｎに電圧０（Ｖ）を印加するとともに維持電極ＳＵ１～ＳＵｎに電圧Ｖｓｏのタイミング検出パルスＶ４を印加する。これにより、パネル１０の画像表示領域内にある全ての放電セルに４回目のタイミング検出放電が発生し、パネル１０の画像表示面の全面が発光する（４回目のタイミング検出用の発光）。 Next, at time to4 after time To3 has elapsed from time to3, voltage 0 (V) is applied to scan electrodes SC1 to SCn, and timing detection pulse V4 of voltage Vso is applied to sustain electrodes SU1 to SUn. As a result, the fourth timing detection discharge is generated in all the discharge cells in the image display area of the panel 10, and the entire image display surface of the panel 10 emits light (fourth timing detection light emission).
　このように、タイミング検出サブフィールドＳＦｏでは、あらかじめ定められた所定の時間間隔（本実施の形態では、例えば、時間Ｔｏ１、時間Ｔｏ２、時間Ｔｏ３）で複数回（本実施の形態では、例えば、４回）のタイミング検出放電を発生し、パネル１０の画像表示面の全面を所定の時間間隔（例えば、時間Ｔｏ１、時間Ｔｏ２、時間Ｔｏ３）で複数回（例えば、４回）発光させる。そして、ライトペンは、この発光を受光して座標基準信号（ライトペンの位置座標（ｘ座標、ｙ座標）を算出する際に基準となる信号）を作成する。 Thus, in the timing detection subfield SFo, a predetermined time interval (in the present embodiment, for example, time To1, time To2, and time To3 in this embodiment) is multiple times (in this embodiment, for example, 4 Timing detection discharge is generated, and the entire image display surface of the panel 10 is caused to emit light a plurality of times (for example, four times) at predetermined time intervals (for example, time To1, time To2, and time To3). Then, the light pen receives this light emission and creates a coordinate reference signal (a signal that becomes a reference when calculating the position coordinates (x coordinate, y coordinate) of the light pen).
　タイミング検出サブフィールドＳＦｏでは、パネル１０の画像表示面の全面が同じタイミングで一斉に光るので、ライトペンの先端部がパネル１０の画像表示領域内のどこにあったとしても、ライトペンは同じタイミングでこの発光を受光することができる。 In the timing detection subfield SFo, the entire surface of the image display surface of the panel 10 shines at the same timing, so that the light pen is at the same timing no matter where the tip of the light pen is in the image display area of the panel 10. This light emission can be received.
　本実施の形態では、例えば、時間Ｔｏ１は約４０μｓｅｃであり、時間Ｔｏ２は約２０μｓｅｃであり、時間Ｔｏ３は約３０μｓｅｃである。しかし、本発明は時間Ｔｏ０～Ｔｏ３の各時間が何ら上述した数値に限定されるものではなく、各時間はプラズマディスプレイシステムの仕様等に応じて適切に設定すればよい。 In this embodiment, for example, the time To1 is about 40 μsec, the time To2 is about 20 μsec, and the time To3 is about 30 μsec. However, the present invention is not limited to the numerical values described above for the times To0 to To3, and each time may be set appropriately according to the specifications of the plasma display system.
　そして、ライトペンは、所定の時間間隔（例えば、時間Ｔｏ１、時間Ｔｏ２、時間Ｔｏ３）で発生する複数回（例えば、４回）の発光を検出したら座標基準信号を作成する。 The light pen generates a coordinate reference signal when it detects a plurality of times (for example, four times) of light emission occurring at a predetermined time interval (for example, time To1, time To2, and time To3).
　タイミング検出サブフィールドＳＦｏのタイミング検出期間Ｐｏにおいて、タイミング検出パルスＶ４の発生後（タイミング検出期間Ｐｏの最後）には、サブフィールドＳＦ１の維持期間Ｐｓ１の最後に行う消去動作と同様の消去動作を行う。これにより、パネル１０の画像表示領域内にある全ての放電セルに微弱な消去放電が発生する。 In the timing detection period Po of the timing detection subfield SFo, after the generation of the timing detection pulse V4 (the end of the timing detection period Po), an erase operation similar to the erase operation performed at the end of the sustain period Ps1 of the subfield SF1 is performed. . Thereby, a weak erasure discharge is generated in all the discharge cells in the image display area of the panel 10.
　なお、本実施の形態において、電圧Ｖｓｏは電圧Ｖｓに等しい電圧に設定されており、例えば、電圧Ｖｓｏは約２０５（Ｖ）である。しかし、電圧Ｖｓｏは電圧Ｖｓと異なる電圧であってもよい。電圧Ｖｓｏはタイミング検出放電が発生する電圧であればよい。 In this embodiment, the voltage Vso is set to a voltage equal to the voltage Vs. For example, the voltage Vso is about 205 (V). However, the voltage Vso may be a voltage different from the voltage Vs. The voltage Vso may be any voltage that generates timing detection discharge.
　続いて、ｙ座標検出サブフィールドＳＦｙとｘ座標検出サブフィールドＳＦｘを発生する。 Subsequently, a y-coordinate detection subfield SFy and an x-coordinate detection subfield SFx are generated.
　ｙ座標検出サブフィールドＳＦｙは、初期化期間Ｐｉｂｙとｙ座標検出期間Ｐｙを有する。 The y coordinate detection subfield SFy has an initialization period Piby and a y coordinate detection period Py.
　初期化期間Ｐｉｂｙでは、画像表示サブフィールドのサブフィールドＳＦ２の初期化期間Ｐｉｂ２と同様の駆動電圧波形を各電極に印加して同様の選択初期化動作を行うので、説明を省略する。 In the initialization period Piby, a drive voltage waveform similar to that in the initialization period Pib2 of the subfield SF2 of the image display subfield is applied to each electrode to perform the same selective initialization operation, and thus description thereof is omitted.
　初期化期間Ｐｉｂｙの直前にあるタイミング検出サブフィールドＳＦｏのタイミング検出期間Ｐｏでは、パネル１０の画像表示領域内にある全ての放電セルにタイミング検出放電が発生するので、初期化期間Ｐｉｂｙにおいても、それら全ての放電セルに微弱な初期化放電が発生する。これにより、パネル１０の画像表示領域内にある全ての放電セルの壁電圧が、続くｙ座標検出期間Ｐｙにおけるｙ座標検出パターン表示動作に適した壁電圧に調整される。さらに、ｙ座標検出期間Ｐｙにおける放電の発生を補助するプライミング粒子が放電セル内に発生する。 In the timing detection period Po of the timing detection subfield SFo immediately before the initialization period Piby, timing detection discharges are generated in all the discharge cells in the image display area of the panel 10, and therefore in the initialization period Piby A weak initializing discharge is generated in all discharge cells. Thereby, the wall voltage of all the discharge cells in the image display area of the panel 10 is adjusted to the wall voltage suitable for the y coordinate detection pattern display operation in the subsequent y coordinate detection period Py. Furthermore, priming particles that assist the generation of discharge in the y-coordinate detection period Py are generated in the discharge cell.
　次に、ｙ座標検出サブフィールドＳＦｙのｙ座標検出期間Ｐｙでは、まず、維持電極ＳＵ１～ＳＵｎに電圧Ｖｅを印加し、データ電極Ｄ１～Ｄｍに電圧０（Ｖ）を印加し、走査電極ＳＣ１～ＳＣｎに電圧Ｖｃを印加する。 Next, in the y coordinate detection period Py of the y coordinate detection subfield SFy, first, the voltage Ve is applied to the sustain electrodes SU1 to SUn, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the scan electrodes SC1 to SCn. A voltage Vc is applied to SCn.
　次に、期間Ｔｙ０の後の時刻ｔｙ０で、データ電極Ｄ１～Ｄｍに正極性のｙ座標検出電圧Ｖｄｙを印加し、１行目の走査電極ＳＣ１に電圧Ｖａｙの負極性のｙ座標検出パルスを印加する。ｙ座標検出電圧Ｖｄｙは電圧０（Ｖ）よりも高い電圧であり、ｙ座標検出パルスの電圧Ｖａｙは電圧Ｖｃよりも低い負の電圧である。なお、図４では、ｙ座標検出パルスのパルス幅をＴｙ１として示している。 Next, at time ty0 after period Ty0, positive y coordinate detection voltage Vdy is applied to data electrodes D1 to Dm, and negative y coordinate detection pulse of voltage Vay is applied to scan electrode SC1 in the first row. To do. The y coordinate detection voltage Vdy is a voltage higher than the voltage 0 (V), and the voltage Vay of the y coordinate detection pulse is a negative voltage lower than the voltage Vc. In FIG. 4, the pulse width of the y coordinate detection pulse is shown as Ty1.
　ｙ座標検出電圧Ｖｄｙを印加したデータ電極Ｄ１～Ｄｍと、電圧Ｖａｙのｙ座標検出パルスを印加した走査電極ＳＣ１との交差部にある１行目の放電セルでは、データ電極Ｄ１～Ｄｍと走査電極ＳＣ１との交差部の電圧差が放電開始電圧を超え、データ電極Ｄ１～Ｄｍと走査電極ＳＣ１との間、および維持電極ＳＵ１と走査電極ＳＣ１との間に放電が発生する。 In the discharge cell in the first row at the intersection of the data electrodes D1 to Dm to which the y coordinate detection voltage Vdy is applied and the scan electrode SC1 to which the y coordinate detection pulse of the voltage Vay is applied, the data electrodes D1 to Dm and the scan electrodes The voltage difference at the intersection with SC1 exceeds the discharge start voltage, and discharge occurs between data electrodes D1 to Dm and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1.
　このようにして、１行目を構成する全ての放電セルに放電が発生し、それらの放電セルが一斉に発光する。例えば、パネル１０の画像表示領域がｍ×ｎ個の放電セルで構成され、ｍ＝１９２０×３＝５７６０であり、ｎ＝１０８０（すなわち、画像表示領域における画素数が１９２０×１０８０）であれば、１行目を構成する５７６０個の放電セル（１９２０個の画素）が一斉に発光する。そして、この発光は、ｙ座標検出のための発光となる。 Thus, discharge occurs in all the discharge cells constituting the first row, and these discharge cells emit light all at once. For example, if the image display area of the panel 10 is composed of m × n discharge cells, m = 1920 × 3 = 5760, and n = 1080 (that is, the number of pixels in the image display area is 1920 × 1080). The 5760 discharge cells (1920 pixels) constituting the first row emit light all at once. And this light emission becomes light emission for y coordinate detection.
　以下、１つの行を構成する放電セルの集合体を「放電セル行」と記し、１つの行を構成する画素の集合体を「画素行」と記す。本実施の形態では、放電セル行と画素行とは実質的に同じものであり、上述の動作では、１行目の画素行（１行目の放電セル行）が一斉に発光する。 Hereinafter, an aggregate of discharge cells constituting one row is referred to as “discharge cell row”, and an aggregate of pixels constituting one row is referred to as “pixel row”. In this embodiment, the discharge cell row and the pixel row are substantially the same, and in the above operation, the first pixel row (first discharge cell row) emits light all at once.
　この放電が発生した放電セルでは、走査電極ＳＣ１上に正極性の壁電圧が蓄積され、維持電極ＳＵ１上に負極性の壁電圧が蓄積され、データ電極Ｄ１～Ｄｍ上にも負極性の壁電圧が蓄積される。 In the discharge cell in which this discharge has occurred, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also formed on data electrodes D1 to Dm. Is accumulated.
　次に、データ電極Ｄ１～Ｄｍにｙ座標検出電圧Ｖｄｙを印加したまま、２行目の走査電極ＳＣ２に電圧Ｖａｙのｙ座標検出パルスを印加する。これにより、２行目の画素行（２行目の放電セル行）にｙ座標検出のための発光が生じる。 Next, with the y coordinate detection voltage Vdy applied to the data electrodes D1 to Dm, a y coordinate detection pulse of the voltage Vay is applied to the scan electrode SC2 in the second row. As a result, light emission for y coordinate detection occurs in the second pixel row (second discharge cell row).
　同様の動作を、データ電極Ｄ１～Ｄｍにｙ座標検出電圧Ｖｄｙを印加したまま、走査電極ＳＣ３、走査電極ＳＣ４、・・・、走査電極ＳＣｎという順番で、ｎ行目の放電セルに至るまで順次行い、３行目からｎ行目（例えば、１０８０行目）までの各画素行（放電セル行）にｙ座標検出のための発光を順次発生させる。 The same operation is performed in the order of scan electrode SC3, scan electrode SC4,..., Scan electrode SCn with the y coordinate detection voltage Vdy being applied to the data electrodes D1 to Dm until the discharge cell in the n-th row is reached. Then, light emission for y coordinate detection is sequentially generated in each pixel row (discharge cell row) from the third row to the nth row (for example, 1080th row).
　これにより、ｙ座標検出サブフィールドＳＦｙのｙ座標検出期間Ｐｙでは、発光する１本の横線（すなわち、発光する１つの画素行）が、パネル１０の画像表示領域の上端部（１行目の画素行）から下端部（ｎ行目の画素行）まで１行ずつ順次移動するパターン（ｙ座標検出パターン）が表示される。すなわち、このｙ座標検出パターンとは、画像表示領域の１行目からｎ行目までの各画素行が、１行毎に順次発光するパターンである。 As a result, in the y coordinate detection period Py of the y coordinate detection subfield SFy, one horizontal line that emits light (that is, one pixel row that emits light) corresponds to the upper end portion (pixels in the first row) of the image display area of the panel 10. A pattern (y-coordinate detection pattern) that sequentially moves one line at a time from the lower line to the lower end (nth pixel line) is displayed. That is, the y-coordinate detection pattern is a pattern in which each pixel row from the first row to the n-th row of the image display area sequentially emits light for each row.
　パネル１０にｙ座標検出パターンを表示すると、画像表示領域の１行目からｎ行目までの各画素行が、１行毎に順次発光するので、ライトペンの先端部がパネル１０の画像表示領域内のどこにあるかによって、ライトペンがこの発光を受光するタイミングは変化する。ライトペンでこの発光がいつ受光されたのか、その受光タイミングを検出することで、画像表示領域におけるライトペンの位置（ｘ座標、ｙ座標）のｙ座標が検出される。 When the y-coordinate detection pattern is displayed on the panel 10, each pixel row from the first row to the n-th row of the image display region emits light sequentially for each row, so that the tip of the light pen is the image display region of the panel 10 The timing at which the light pen receives this light emission varies depending on where the light pen is. The y coordinate of the position (x coordinate, y coordinate) of the light pen in the image display area is detected by detecting the light reception timing when the light emission is received by the light pen.
　なお、ｙ座標検出パターンがパネル１０に表示される期間は非常に短い。そのため、ｙ座標検出パターンが使用者に認識される可能性は低く、たとえ使用者に認識されたとしても、それはごく僅かな輝度の変化に過ぎない。 Note that the period during which the y-coordinate detection pattern is displayed on the panel 10 is very short. Therefore, the possibility that the y-coordinate detection pattern is recognized by the user is low, and even if it is recognized by the user, it is only a slight change in luminance.
　続くｘ座標検出サブフィールドＳＦｘは、初期化期間Ｐｉａｘとｘ座標検出期間Ｐｘを有する。 The subsequent x coordinate detection subfield SFx has an initialization period Piax and an x coordinate detection period Px.
　初期化期間Ｐｉａｘでは、画像表示サブフィールドのサブフィールドＳＦ１の初期化期間Ｐｉａ１と同様の駆動電圧波形を各電極に印加して同様の強制初期化動作を行うので、説明を省略する。 In the initialization period Piax, a driving voltage waveform similar to that in the initialization period Pia1 of the subfield SF1 of the image display subfield is applied to each electrode to perform the same forced initialization operation, and thus description thereof is omitted.
　ｘ座標検出サブフィールドＳＦｘの初期化期間Ｐｉａｘでは、パネル１０の画像表示領域内にある全ての放電セルに初期化放電が発生する。これにより、パネル１０の画像表示領域内にある全ての放電セルの壁電圧が、続くｘ座標検出期間Ｐｘにおけるｘ座標検出パターン表示動作に適した壁電圧に調整される。さらに、ｘ座標検出期間Ｐｘにおける放電の発生を補助するプライミング粒子が放電セル内に発生する。 In the initialization period Piax of the x-coordinate detection subfield SFx, the initialization discharge is generated in all the discharge cells in the image display area of the panel 10. Thereby, the wall voltage of all the discharge cells in the image display area of the panel 10 is adjusted to the wall voltage suitable for the x coordinate detection pattern display operation in the subsequent x coordinate detection period Px. Furthermore, priming particles that assist the generation of discharge in the x-coordinate detection period Px are generated in the discharge cell.
　次に、ｘ座標検出サブフィールドＳＦｘのｘ座標検出期間Ｐｘでは、まず、データ電極Ｄ１～Ｄｍに電圧０（Ｖ）を印加し、維持電極ＳＵ１～ＳＵｎに電圧Ｖｅを印加し、走査電極ＳＣ１～ＳＣｎに電圧Ｖｃを印加する。 Next, in the x coordinate detection period Px of the x coordinate detection subfield SFx, first, the voltage 0 (V) is applied to the data electrodes D1 to Dm, the voltage Ve is applied to the sustain electrodes SU1 to SUn, and the scan electrodes SC1 to SCn are applied. A voltage Vc is applied to SCn.
　次に、期間Ｔｘ０の後の時刻ｔｘ０で、走査電極ＳＣ１～ＳＣｎに負極性のｘ座標検出電圧Ｖａｘを印加し、１～３列目のデータ電極Ｄ１～Ｄ３に電圧Ｖｄｘの正極性のｘ座標検出パルスを印加する。ｘ座標検出パルスの電圧Ｖｄｘは電圧０（Ｖ）よりも高い電圧であり、ｘ座標検出電圧Ｖａｘは電圧Ｖｃよりも低い負の電圧である。なお、図４では、ｘ座標検出パルスのパルス幅をＴｘ１として示している。 Next, at time tx0 after the period Tx0, the negative x coordinate detection voltage Vax is applied to the scan electrodes SC1 to SCn, and the positive x coordinate of the voltage Vdx is applied to the data electrodes D1 to D3 in the first to third columns. Apply detection pulse. The voltage Vdx of the x coordinate detection pulse is higher than the voltage 0 (V), and the x coordinate detection voltage Vax is a negative voltage lower than the voltage Vc. In FIG. 4, the pulse width of the x coordinate detection pulse is shown as Tx1.
　なお、データ電極Ｄ１～Ｄ３は、１つの画素を構成する赤の放電セル、緑の放電セル、青の放電セルに対応しており、この画素は、例えば画像表示領域の左端に配置された画素である。 The data electrodes D1 to D3 correspond to a red discharge cell, a green discharge cell, and a blue discharge cell constituting one pixel, and the pixel is a pixel arranged at the left end of the image display area, for example. It is.
　電圧Ｖｄｘのｘ座標検出パルスを印加したデータ電極Ｄ１～Ｄ３と、ｘ座標検出電圧Ｖａｘを印加した走査電極ＳＣ１～ＳＣｎとの交差部にある放電セルでは、データ電極Ｄ１～Ｄ３と走査電極ＳＣ１～ＳＣｎとの交差部の電圧差が放電開始電圧を超え、データ電極Ｄ１～Ｄ３と走査電極ＳＣ１～ＳＣｎとの間、および維持電極ＳＵ１～ＳＵｎと走査電極ＳＣ１～ＳＣｎとの間に放電が発生する。 In the discharge cell at the intersection of the data electrodes D1 to D3 to which the x coordinate detection pulse of the voltage Vdx is applied and the scan electrodes SC1 to SCn to which the x coordinate detection voltage Vax is applied, the data electrodes D1 to D3 and the scan electrodes SC1 to SC1 The voltage difference at the intersection with SCn exceeds the discharge start voltage, and discharge occurs between data electrodes D1 to D3 and scan electrodes SC1 to SCn and between sustain electrodes SU1 to SUn and scan electrodes SC1 to SCn. .
　このようにして、１列目を構成する全ての画素に放電が発生し、それらの画素が一斉に発光する。例えば、パネル１０の画像表示領域がｍ×ｎ個の放電セルで構成され、ｍ＝１９２０×３＝５７６０であり、ｎ＝１０８０（すなわち、画像表示領域における画素数が１９２０×１０８０）であれば、１列目を構成する１０８０個の画素（３列×１０８０個の放電セル）が一斉に発光する。そして、この発光は、ｘ座標検出のための発光となる。 In this way, discharge occurs in all the pixels constituting the first column, and these pixels emit light all at once. For example, if the image display area of the panel 10 is composed of m × n discharge cells, m = 1920 × 3 = 5760, and n = 1080 (that is, the number of pixels in the image display area is 1920 × 1080). The 1080 pixels (3 columns × 1080 discharge cells) constituting the first column emit light all at once. And this light emission becomes light emission for x coordinate detection.
　以下、１つの列を構成する放電セルの集合体を「放電セル列」と記す。また、互いに隣接する３列の放電セル列で構成される放電セルの集合体（画素の列）を「画素列」と記す。上述の動作では、１列目の画素列（すなわち、１列目、２列目および３列目の放電セル列）が一斉に発光する。 Hereinafter, an assembly of discharge cells constituting one column is referred to as a “discharge cell column”. Further, an assembly of discharge cells (pixel column) composed of three adjacent discharge cell columns is referred to as a “pixel column”. In the above-described operation, the first pixel column (that is, the first, second, and third discharge cell columns) emits light all at once.
　この放電が発生した放電セルでは、走査電極ＳＣ１～ＳＣｎ上に正極性の壁電圧が蓄積され、維持電極ＳＵ１～ＳＵｎ上に負極性の壁電圧が蓄積され、データ電極Ｄ１～Ｄ３上にも負極性の壁電圧が蓄積される。 In the discharge cell in which this discharge has occurred, positive wall voltage is accumulated on scan electrodes SC1 to SCn, negative wall voltage is accumulated on sustain electrodes SU1 to SUn, and negative electrodes are also formed on data electrodes D1 to D3. Sex wall voltage is accumulated.
　次に、走査電極ＳＣ１～ＳＣｎにｘ座標検出電圧Ｖａｘを印加したまま、４列目～６列目のデータ電極Ｄ４～Ｄ６に電圧Ｖｄｘのｘ座標検出パルスを印加する。これにより、２列目の画素列（４列目、５列目および６列目の放電セル列）にｘ座標検出のための発光が生じる。 Next, with the x coordinate detection voltage Vax being applied to the scan electrodes SC1 to SCn, the x coordinate detection pulse of the voltage Vdx is applied to the data electrodes D4 to D6 in the fourth column to the sixth column. As a result, light emission for x coordinate detection occurs in the second pixel column (fourth, fifth, and sixth discharge cell columns).
　同様の動作を、走査電極ＳＣ１～ＳＣｎにｘ座標検出電圧Ｖａｘを印加したまま、データ電極Ｄ７～Ｄ９、データ電極Ｄ１０～Ｄ１２、・・・、データ電極Ｄｍ－２～Ｄｍという順番で、互いに隣接する３本のデータ電極２２毎に、ｍ列目の放電セルに至るまで順次行い、３列目から最終列目（例えば、１９２０列目）までの各画素列にｘ座標検出のための発光を順次発生させる。 Similar operations are performed adjacent to each other in the order of data electrodes D7 to D9, data electrodes D10 to D12,..., Data electrodes Dm-2 to Dm, with the x coordinate detection voltage Vax being applied to scan electrodes SC1 to SCn. Each of the three data electrodes 22 is sequentially performed until reaching the m-th discharge cell, and light emission for x coordinate detection is performed on each pixel column from the third column to the last column (for example, 1920 column). Generate sequentially.
　これにより、ｘ座標検出サブフィールドＳＦｘのｘ座標検出期間Ｐｘでは、発光する１本の縦線（すなわち、発光する１つの画素列）が、パネル１０の画像表示領域の左端部（１列目の画素列）から右端部（ｍ／３列目の画素列）まで１列ずつ順次移動するパターン（ｘ座標検出パターン）が表示される。すなわち、このｘ座標検出パターンとは、画像表示領域の１列目から最終列目までの各画素列が、１列毎に順次発光するパターンである。言い換えると、このｘ座標検出パターンとは、互いに隣接する３つの放電セル列が、画像表示領域の左端部（１列目）から右端部（ｍ列目）まで、３列ずつ順次発光するパターンである。 As a result, in the x coordinate detection period Px of the x coordinate detection subfield SFx, one vertical line that emits light (that is, one pixel column that emits light) corresponds to the left end (first column) of the image display area of the panel 10. A pattern (x-coordinate detection pattern) that sequentially moves one column at a time from the pixel column) to the right end (m / 3th pixel column) is displayed. That is, the x coordinate detection pattern is a pattern in which each pixel column from the first column to the last column in the image display area sequentially emits light for each column. In other words, the x-coordinate detection pattern is a pattern in which three discharge cell columns adjacent to each other sequentially emit light by three columns from the left end (first column) to the right end (m column) of the image display area. is there.
　パネル１０にｘ座標検出パターンを表示すると、画像表示領域の１列目から最終列目までの各画素列が、１列毎に順次発光するので、ライトペンの先端部がパネル１０の画像表示領域内のどこにあるかによって、ライトペンがこの発光を受光するタイミングは変化する。ライトペンでこの発光がいつ受光されたのか、その受光タイミングを検出することで、画像表示領域におけるライトペンの位置（ｘ座標、ｙ座標）のｘ座標が検出される。 When the x-coordinate detection pattern is displayed on the panel 10, each pixel column from the first column to the last column in the image display region sequentially emits light for each column, so that the tip of the light pen is the image display region of the panel 10. The timing at which the light pen receives this light emission varies depending on where the light pen is. By detecting the light reception timing when this light emission is received by the light pen, the x coordinate of the position (x coordinate, y coordinate) of the light pen in the image display area is detected.
　なお、ｘ座標検出パターンがパネル１０に表示される期間は非常に短い。そのため、ｘ座標検出パターンが使用者に認識される可能性は低く、たとえ使用者に認識されたとしても、それはごく僅かな輝度の変化に過ぎない。 Note that the period during which the x-coordinate detection pattern is displayed on the panel 10 is very short. Therefore, the possibility that the x coordinate detection pattern is recognized by the user is low, and even if it is recognized by the user, it is only a slight change in luminance.
　以上が、タイミング検出サブフィールドＳＦｏ、ｙ座標検出サブフィールドＳＦｙおよびｘ座標検出サブフィールドＳＦｘの駆動電圧波形の概要である。 The above is the outline of the drive voltage waveforms of the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx.
　なお、本実施の形態において各電極に印加する電圧値は、例えば、電圧Ｖｉ１＝１５０（Ｖ）、電圧Ｖｉ２＝３５０（Ｖ）、電圧Ｖｉ３＝２００（Ｖ）、電圧Ｖｉ４＝－１７５（Ｖ）、電圧Ｖａ＝電圧Ｖａｙ＝電圧Ｖａｘ＝－２００（Ｖ）、電圧Ｖｃ＝－５０（Ｖ）、電圧Ｖｓ＝電圧Ｖｓｏ＝２０５（Ｖ）、電圧Ｖｒ＝２０５（Ｖ）、電圧Ｖｅ＝１５５（Ｖ）、電圧Ｖｄ＝電圧Ｖｄｙ＝電圧Ｖｄｘ＝５５（Ｖ）である。 Note that the voltage values applied to the electrodes in this embodiment are, for example, the voltage Vi1 = 150 (V), the voltage Vi2 = 350 (V), the voltage Vi3 = 200 (V), and the voltage Vi4 = −175 (V). , Voltage Va = voltage Vay = voltage Vax = −200 (V), voltage Vc = −50 (V), voltage Vs = voltage Vso = 205 (V), voltage Vr = 205 (V), voltage Ve = 155 (V ), Voltage Vd = voltage Vdy = voltage Vdx = 55 (V).
　なお、本実施の形態において、電圧Ｖａ、電圧Ｖａｙ、および電圧Ｖａｘは互いに等しい電圧に設定され、電圧Ｖｄ、電圧Ｖｄｙ、および電圧Ｖｄｘは互いに等しい電圧に設定されているが、これらの電圧は互いに異なる電圧であってもよい。 In this embodiment, the voltage Va, the voltage Vay, and the voltage Vax are set to be equal to each other, and the voltage Vd, the voltage Vdy, and the voltage Vdx are set to be equal to each other. Different voltages may be used.
　なお、本実施の形態では、サブフィールドＳＦ１の初期化期間Ｐｉａ１で発生する上り傾斜波形電圧の電圧Ｖｉ２と、タイミング検出サブフィールドＳＦｏの初期化期間Ｐｉａｏで発生する上り傾斜波形電圧の電圧Ｖｉ２と、ｘ座標検出サブフィールドＳＦｘの初期化期間Ｐｉａｘで発生する上り傾斜波形電圧の電圧Ｖｉ２とを互いに等しい電圧としているが、各電圧Ｖｉ２は互いに異なる電圧に設定されていてもよい。 In the present embodiment, a voltage Vi2 of the rising ramp waveform voltage generated in the initialization period Pia1 of the subfield SF1, a voltage Vi2 of the rising ramp waveform voltage generated in the initialization period Piao of the timing detection subfield SFo, The voltage Vi2 of the rising ramp waveform voltage generated in the initialization period Piax of the x-coordinate detection subfield SFx is set to be equal to each other, but each voltage Vi2 may be set to a different voltage.
　また、サブフィールドＳＦ１の初期化期間Ｐｉａ１、タイミング検出サブフィールドＳＦｏの初期化期間Ｐｉａｏ、およびｘ座標検出サブフィールドＳＦｘの初期化期間Ｐｉａｘに発生する上り傾斜波形電圧の勾配は約１．５（Ｖ／μｓｅｃ）である。また、画像表示サブフィールド（サブフィールドＳＦ１～ＳＦ８）の各初期化期間Ｐｉａ１、Ｐｉｂ２～Ｐｉｂ８、タイミング検出サブフィールドＳＦｏの初期化期間Ｐｉａｏ、ｙ座標検出サブフィールドＳＦｙの初期化期間Ｐｉｂｙ、およびｘ座標検出サブフィールドＳＦｘの初期化期間Ｐｉａｘに発生する下り傾斜波形電圧の勾配は約－２．５（Ｖ／μｓｅｃ）である。また、画像表示サブフィールド（サブフィールドＳＦ１～ＳＦ８）の各維持期間Ｐｓ１～Ｐｓ８の最後およびタイミング検出サブフィールドＳＦｏのタイミング検出期間Ｐｏの最後に発生する上り傾斜波形電圧の勾配は約１０（Ｖ／μｓｅｃ）である。 The gradient of the rising ramp waveform voltage generated in the initialization period Pia1 of the subfield SF1, the initialization period Piao of the timing detection subfield SFo, and the initialization period Piax of the x coordinate detection subfield SFx is about 1.5 (V / Μsec). Also, the initialization periods Pia1, Pib2 to Pib8 of the image display subfield (subfields SF1 to SF8), the initialization period Piao of the timing detection subfield SFo, the initialization period Piby of the y coordinate detection subfield SFy, and the x coordinate The gradient of the downward ramp waveform voltage generated in the initialization period Piax of the detection subfield SFx is about −2.5 (V / μsec). The gradient of the rising ramp waveform voltage generated at the end of each sustain period Ps1 to Ps8 of the image display subfield (subfields SF1 to SF8) and at the end of the timing detection period Po of the timing detection subfield SFo is about 10 (V / μsec).
　なお、本実施の形態において、上述した電圧値や勾配等の具体的な数値は単なる一例に過ぎず、本発明は、各電圧値や勾配等が上述した数値に限定されるものではない。各電圧値や勾配等は、パネルの放電特性やプラズマディスプレイ装置の仕様等にもとづき最適に設定することが望ましい。 In the present embodiment, the specific numerical values such as the voltage value and the gradient described above are merely examples, and the present invention is not limited to the numerical values described above for each voltage value and the gradient. Each voltage value, gradient, and the like are preferably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.
　なお、本実施の形態において、１フィールドにタイミング検出サブフィールドＳＦｏを設け、図４に示した波形形状でタイミング検出サブフィールドＳＦｏの各駆動電圧波形を発生する理由は、以下の通りである。 In the present embodiment, the reason why the timing detection subfield SFo is provided in one field and each drive voltage waveform of the timing detection subfield SFo is generated with the waveform shape shown in FIG. 4 is as follows.
　本実施の形態では、描画装置とライトペンとの間で無線通信を行う。そのため、本実施の形態では、ライトペン自らが座標基準信号（ｙ座標検出期間Ｐｙおよびｘ座標検出期間Ｐｘの発生タイミングを示す信号）を発生できるようにするために、１フィールドにタイミング検出サブフィールドＳＦｏを設ける。ライトペンは、タイミング検出サブフィールドＳＦｏにおいて、タイミング検出放電によってパネル１０に特定の時間間隔で発生する発光を検知し、座標基準信号を発生する。そして、この座標基準信号にもとづき、ライトペンは、ライトペンの位置座標を自ら算出する。 In this embodiment, wireless communication is performed between the drawing apparatus and the light pen. Therefore, in the present embodiment, the light pen itself can generate a coordinate reference signal (a signal indicating the generation timing of the y-coordinate detection period Py and the x-coordinate detection period Px), and the timing detection subfield in one field. SFo is provided. In the timing detection subfield SFo, the light pen detects light emission generated at a specific time interval on the panel 10 by timing detection discharge, and generates a coordinate reference signal. Based on this coordinate reference signal, the light pen calculates the position coordinates of the light pen itself.
　また、本実施の形態では、ライトペンにおける座標基準信号の発生精度を高めるために、図４に示した波形形状でタイミング検出サブフィールドＳＦｏの各駆動電圧波形を発生し、時間Ｔｏ０を、時間Ｔｏ１よりも長い時間に設定する。望ましくは、時間Ｔｏ０を、時間Ｔｏ１、時間Ｔｏ２、時間Ｔｏ３のいずれの時間よりも長い時間に設定する。これは、以下のような理由による。 Further, in this embodiment, in order to increase the accuracy of generating the coordinate reference signal in the light pen, each drive voltage waveform of the timing detection subfield SFo is generated with the waveform shape shown in FIG. 4, and the time To0 is set to the time To1. Set to a longer time. Desirably, the time To0 is set to a time longer than any of the time To1, the time To2, and the time To3. This is due to the following reasons.
　ライトペンが有する受光素子は、書込み放電によって発生する発光も検出する。そのため、時間Ｔｏ０の設定値によっては、ライトペンが、タイミング検出サブフィールドＳＦｏの書込み期間Ｐｗｏにおいて書込み放電によって発生する発光を、タイミング検出放電による発光と誤認識する可能性がある。 The light receiving element of the light pen also detects light emission generated by address discharge. Therefore, depending on the set value of time To0, the light pen may misrecognize the light emission generated by the address discharge in the address period Pwo of the timing detection subfield SFo as the light emission by the timing detection discharge.
　しかし、時間Ｔｏ０が、時間Ｔｏ１よりも長い時間に設定されていれば、ライトペンが画像表示領域内のどの位置にあっても、ライトペンが書込み放電による発光を検出した時刻から時刻ｔｏ１までの間隔は時間Ｔｏ１よりも長くなる。これにより、ライトペンが、タイミング検出サブフィールドＳＦｏの書込み期間Ｐｗｏにおいて発生する書込み放電による発光を、タイミング検出放電による発光と誤認識することを防止することができる。そして、時間Ｔｏ０が、時間Ｔｏ１、時間Ｔｏ２、時間Ｔｏ３のいずれの時間よりも長い時間に設定されていれば、より高精度に、その誤認識を防止することができ、画像表示領域内におけるライトペンの位置（位置座標）をより正確に検出することが可能となる。 However, if the time To0 is set to a time longer than the time To1, no matter where the light pen is in the image display area, the time from the time when the light pen detects light emission due to the write discharge to the time to1 The interval is longer than time To1. Thereby, it is possible to prevent the light pen from erroneously recognizing light emission due to the address discharge generated in the address period Pwo of the timing detection subfield SFo as light emission due to the timing detection discharge. If the time To0 is set to a time longer than any of the time To1, the time To2, and the time To3, the erroneous recognition can be prevented with higher accuracy, and the write in the image display area can be prevented. It becomes possible to detect the position (position coordinates) of the pen more accurately.
　以上のように、本実施の形態における画像表示装置では、上述した動作により、パネル１０に画像信号に応じた画像を表示しつつ、画像表示領域内におけるライトペンの位置（位置座標）を検出するための放電を安定に発生し、ライトペンの位置座標を高精度に算出することができる。 As described above, the image display device according to the present embodiment detects the position (positional coordinates) of the light pen in the image display area while displaying an image corresponding to the image signal on the panel 10 by the above-described operation. Discharge can be generated stably, and the position coordinates of the light pen can be calculated with high accuracy.
　次に、本実施の形態における画像表示システムの構成について説明する。なお、以下では、画像表示装置としてプラズマディスプレイ装置を用いたプラズマディスプレイシステムを本実施の形態における画像表示システムの一例として挙げ、その構成について説明する。 Next, the configuration of the image display system in the present embodiment will be described. In the following, a plasma display system using a plasma display device as an image display device will be described as an example of the image display system in this embodiment, and the configuration thereof will be described.
　図５は、本発明の実施の形態におけるプラズマディスプレイ装置３０を構成する回路ブロックおよびプラズマディスプレイシステム１００の一例を概略的に示す図である。 FIG. 5 is a diagram schematically showing an example of a circuit block and a plasma display system 100 that constitute the plasma display device 30 according to the embodiment of the present invention.
　本実施の形態に示すプラズマディスプレイシステム１００は、プラズマディスプレイ装置３０と、描画装置４０と、ライトペン５０とを構成要素に含む。 The plasma display system 100 shown in the present embodiment includes a plasma display device 30, a drawing device 40, and a light pen 50 as components.
　描画装置４０は、受信回路４２、フィルタ回路４４、および描画回路４６を備えている。 The drawing device 40 includes a receiving circuit 42, a filter circuit 44, and a drawing circuit 46.
　プラズマディスプレイ装置３０は、パネル１０と、１フィールドに複数のサブフィールドを備えてパネル１０を駆動する駆動回路を備えている。駆動回路は、画像信号処理回路３１、データ電極駆動回路３２、走査電極駆動回路３３、維持電極駆動回路３４、タイミング発生回路３５、および各回路ブロックに必要な電源を供給する電源回路（図示せず）を備えている。 The plasma display device 30 includes a panel 10 and a driving circuit that drives the panel 10 with a plurality of subfields in one field. The drive circuit includes an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit (not shown) that supplies power necessary for each circuit block. ).
　画像信号処理回路３１には、画像信号、描画装置４０から出力される描画信号、およびタイミング発生回路３５から供給されるタイミング信号が入力される。画像信号処理回路３１は、画像信号と描画信号とを合成した画像をパネル１０に表示するために、画像信号と描画信号とを合成し、その合成後の信号にもとづき各放電セルに赤、緑、青の各階調値（１フィールドで表現される階調値）を設定する。あるいは、画像信号処理回路３１は、画像信号と描画信号を切り替えてパネル１０に表示するために、画像信号と描画信号のいずれかの信号にもとづき各放電セルに赤、緑、青の各階調値を設定する。そして、画像信号処理回路３１は、各放電セルに設定した赤、緑、青の階調値を、サブフィールド毎の点灯・非点灯を示す画像データ（発光・非発光をデジタル信号の「１」、「０」に対応させたデータのこと）に変換し、その画像データ（赤の画像データ、緑の画像データ、および青の画像データ）を出力する。 The image signal processing circuit 31 receives an image signal, a drawing signal output from the drawing device 40, and a timing signal supplied from the timing generation circuit 35. The image signal processing circuit 31 combines the image signal and the drawing signal in order to display an image obtained by combining the image signal and the drawing signal on the panel 10, and applies red, green to each discharge cell based on the combined signal. , Blue gradation values (gradation values expressed by one field) are set. Alternatively, the image signal processing circuit 31 switches each of the image signal and the drawing signal and displays them on the panel 10, so that each discharge cell has a gradation value of red, green, and blue based on either the image signal or the drawing signal. Set. Then, the image signal processing circuit 31 uses the red, green, and blue gradation values set for each discharge cell as image data indicating lighting / non-lighting for each subfield (light emission / non-light emission is “1” of the digital signal). , Data corresponding to “0”), and output the image data (red image data, green image data, and blue image data).
　タイミング発生回路３５は、水平同期信号および垂直同期信号にもとづき、各回路ブロックの動作を制御する各種のタイミング信号を発生する。そして、発生したタイミング信号をそれぞれの回路ブロック（データ電極駆動回路３２、走査電極駆動回路３３、維持電極駆動回路３４、および画像信号処理回路３１等）へ供給する。 The timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal. The generated timing signal is supplied to each circuit block (data electrode drive circuit 32, scan electrode drive circuit 33, sustain electrode drive circuit 34, image signal processing circuit 31, etc.).
　データ電極駆動回路３２は、画像信号処理回路３１から出力される画像データとタイミング発生回路３５から供給されるタイミング信号とにもとづき、画像表示サブフィールドであるサブフィールドＳＦ１～ＳＦ８の各書込み期間Ｐｗ１～Ｐｗ８およびタイミング検出サブフィールドＳＦｏの書込み期間Ｐｗｏでは電圧Ｖｄの書込みパルスを、ｙ座標検出サブフィールドＳＦｙのｙ座標検出期間Ｐｙではｙ座標検出電圧Ｖｄｙを、ｘ座標検出サブフィールドＳＦｘのｘ座標検出期間Ｐｘでは電圧Ｖｄｘのｘ座標検出パルスを、各データ電極Ｄ１～Ｄｍに印加する。 Based on the image data output from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35, the data electrode driving circuit 32 performs the writing periods Pw1 to Pw1 of the subfields SF1 to SF8 which are image display subfields. In the writing period Pwo of Pw8 and the timing detection subfield SFo, the writing pulse of the voltage Vd is used, in the y coordinate detection period Py of the y coordinate detection subfield SFy, the y coordinate detection voltage Vdy is used, and in the x coordinate detection subfield SFx, the x coordinate detection period. In Px, an x-coordinate detection pulse of voltage Vdx is applied to each data electrode D1 to Dm.
　維持電極駆動回路３４は、維持パルス発生回路、電圧Ｖｅを発生する回路（図５には示さず）を備え、タイミング発生回路３５から供給されるタイミング信号にもとづいて各駆動電圧波形を作成し、維持電極ＳＵ１～ＳＵｎのそれぞれに印加する。画像表示サブフィールドであるサブフィールドＳＦ１～ＳＦ８の各維持期間Ｐｓ１～Ｐｓ８では電圧Ｖｓの維持パルスを、タイミング検出サブフィールドＳＦｏのタイミング検出期間Ｐｏでは電圧Ｖｓｏ（本実施の形態では、電圧Ｖｓに等しい）のタイミング検出パルスＶ２、Ｖ４を、画像表示サブフィールドであるサブフィールドＳＦ１～ＳＦ８の各初期化期間Ｐｉａ１、Ｐｉｂ２～Ｐｉｂ８と各書込み期間Ｐｗ１～Ｐｗ８、タイミング検出サブフィールドＳＦｏの初期化期間Ｐｉａｏと書込み期間Ｐｗｏ、ｙ座標検出サブフィールドＳＦｙの初期化期間Ｐｉｂｙとｙ座標検出期間Ｐｙ、およびｘ座標検出サブフィールドＳＦｘの初期化期間Ｐｉａｘとｘ座標検出期間Ｐｘでは電圧Ｖｅを、維持電極ＳＵ１～ＳＵｎに印加する。 Sustain electrode drive circuit 34 includes a sustain pulse generation circuit and a circuit (not shown in FIG. 5) for generating voltage Ve, and generates each drive voltage waveform based on the timing signal supplied from timing generation circuit 35. The voltage is applied to each of the sustain electrodes SU1 to SUn. In the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8, which are image display subfields, the sustain pulse of the voltage Vs is used. In the timing detection period Po of the timing detection subfield SFo, the voltage Vso (equal to the voltage Vs in the present embodiment). ) Of timing detection pulses V2 and V4 in the initialization periods Pia1, Pib2 to Pib8 and the writing periods Pw1 to Pw8 of the subfields SF1 to SF8, which are image display subfields, and the initialization period Piao of the timing detection subfield SFo. In the writing period Pwo, the initialization period Piby and the y coordinate detection period Py of the y coordinate detection subfield SFy, and the initialization period Piax and the x coordinate detection period Px of the x coordinate detection subfield SFx, the voltage Ve and the sustain electrodes SU1 to SUn Apply to.
　走査電極駆動回路３３は、傾斜波形電圧発生回路、維持パルス発生回路、走査パルス発生回路（図５には示さず）を備え、タイミング発生回路３５から供給されるタイミング信号にもとづいて各駆動電圧波形を作成し、走査電極ＳＣ１～ＳＣｎのそれぞれに印加する。傾斜波形電圧発生回路は、タイミング信号にもとづき、画像表示サブフィールドであるサブフィールドＳＦ１～ＳＦ８の各初期化期間Ｐｉａ１、Ｐｉｂ２～Ｐｉｂ８と各維持期間Ｐｗ１～Ｐｗ８、タイミング検出サブフィールドＳＦｏの初期化期間Ｐｉａｏとタイミング検出期間Ｐｏ、ｙ座標検出サブフィールドＳＦｙの初期化期間Ｐｉｂｙ、およびｘ座標検出サブフィールドＳＦｘの初期化期間Ｐｉａｘにおいて、傾斜波形電圧を走査電極ＳＣ１～ＳＣｎに印加する。維持パルス発生回路は、タイミング信号にもとづき、画像表示サブフィールドであるサブフィールドＳＦ１～ＳＦ８の各維持期間Ｐｓ１～Ｐｓ８では維持パルスを、タイミング検出サブフィールドＳＦｏのタイミング検出期間Ｐｏでは電圧Ｖｓｏ（本実施の形態では、電圧Ｖｓに等しい）のタイミング検出パルスＶ１、Ｖ３を、走査電極ＳＣ１～ＳＣｎに印加する。走査パルス発生回路は、複数の走査電極駆動ＩＣ（走査ＩＣ）を備え、タイミング信号にもとづき、画像表示サブフィールドであるサブフィールドＳＦ１～ＳＦ８の各書込み期間Ｐｗ１～Ｐｗ８、およびタイミング検出サブフィールドＳＦｏの書込み期間Ｐｗｏでは電圧Ｖｃと電圧Ｖａの走査パルスを、ｙ座標検出サブフィールドＳＦｙのｙ座標検出期間Ｐｙでは電圧Ｖｃと電圧Ｖａｙのｙ座標検出パルスを、ｘ座標検出サブフィールドＳＦｘのｘ座標検出期間Ｐｘでは電圧Ｖｃとｘ座標検出電圧Ｖａｘを、走査電極ＳＣ１～ＳＣｎに印加する。 Scan electrode drive circuit 33 includes a ramp waveform voltage generation circuit, a sustain pulse generation circuit, and a scan pulse generation circuit (not shown in FIG. 5), and each drive voltage waveform is based on a timing signal supplied from timing generation circuit 35. Is applied to each of scan electrodes SC1 to SCn. The ramp waveform voltage generating circuit, based on the timing signal, initializes the initialization periods Pia1, Pib2 to Pib8 and the sustain periods Pw1 to Pw8 of the subfields SF1 to SF8, which are image display subfields, and the initialization period of the timing detection subfield SFo. A ramp waveform voltage is applied to scan electrodes SC1 to SCn in Piao, timing detection period Po, initialization period Piby of y-coordinate detection subfield SFy, and initialization period Piax of x-coordinate detection subfield SFx. Based on the timing signal, the sustain pulse generating circuit generates sustain pulses in the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8 that are image display subfields, and the voltage Vso (this implementation) in the timing detection period Po of the timing detection subfield SFo. In this embodiment, timing detection pulses V1 and V3 equal to the voltage Vs) are applied to the scan electrodes SC1 to SCn. The scan pulse generation circuit includes a plurality of scan electrode driving ICs (scan ICs), and based on the timing signal, the writing periods Pw1 to Pw8 of the subfields SF1 to SF8 that are image display subfields and the timing detection subfield Sfo In the writing period Pwo, scanning pulses of the voltage Vc and the voltage Va are used, in the y coordinate detection period Py of the y coordinate detection subfield SFy, the y coordinate detection pulse of the voltage Vc and voltage Vay is used, and the x coordinate detection period of the x coordinate detection subfield SFx. In Px, voltage Vc and x-coordinate detection voltage Vax are applied to scan electrodes SC1 to SCn.
　ライトペン５０は、使用者がパネル１０の画像表示領域に文字や図画等を手書き入力するときに使用される。ライトペン５０は、棒状に形成されており、受光素子５２、接触スイッチ５３、タイミング検出回路５４、座標算出回路５６、および送信回路５８を備えている。 The light pen 50 is used when the user inputs characters, drawings and the like in the image display area of the panel 10 by handwriting. The light pen 50 is formed in a rod shape and includes a light receiving element 52, a contact switch 53, a timing detection circuit 54, a coordinate calculation circuit 56, and a transmission circuit 58.
　接触スイッチ５３は、ライトペン５０の先端部に設けられ、ライトペン５０の先端部がパネル１０の前面基板１１（パネル１０の画像表示面）に接触したかどうかを検知する。接触スイッチ５３は、ライトペン５０の先端部がパネル１０に接触していればオンになって「１」を出力し、接触していなければオフになって「０」を出力する。 The contact switch 53 is provided at the tip of the light pen 50 and detects whether or not the tip of the light pen 50 has contacted the front substrate 11 of the panel 10 (the image display surface of the panel 10). The contact switch 53 is turned on to output “1” if the tip of the light pen 50 is in contact with the panel 10, and is turned off to output “0” if not in contact.
　受光素子５２は、パネル１０の画像表示面に生じる発光を受光して電気信号（受光信号）に変換する。そして、その受光信号を、タイミング検出回路５４および座標算出回路５６に出力する。なお、本実施の形態において、ライトペン５０の位置座標（ｘ、ｙ）とは、受光素子５２がパネル１０の画像表示面に生じる発光を受光する位置のことである。 The light receiving element 52 receives light emitted from the image display surface of the panel 10 and converts it into an electric signal (light receiving signal). Then, the light reception signal is output to the timing detection circuit 54 and the coordinate calculation circuit 56. In the present embodiment, the position coordinates (x, y) of the light pen 50 are positions where the light receiving element 52 receives light emitted from the image display surface of the panel 10.
　タイミング検出回路５４、座標算出回路５６、および送信回路５８は、接触スイッチ５３が接触を検知しているか否かにかかわらず、以下の動作をする。 The timing detection circuit 54, the coordinate calculation circuit 56, and the transmission circuit 58 operate as follows regardless of whether or not the contact switch 53 detects contact.
　タイミング検出回路５４は、受光信号にもとづき、タイミング検出サブフィールドＳＦｏのタイミング検出期間Ｐｏに発生するタイミング検出用の発光（タイミング検出放電によって生じる発光）を検出する。具体的には、タイミング検出回路５４は、タイミング検出回路５４が有するタイマー（図５には示さず）を用いて、複数（例えば、５回）の発光の時間間隔を計測する。そして、その時間間隔があらかじめ定められた所定の時間間隔（例えば、時間Ｔｏ０、時間Ｔｏ１、時間Ｔｏ２、時間Ｔｏ３）に合致するかどうかを、タイミング検出回路５４に設定された複数のしきい値（例えば、時間Ｔｏ０、時間Ｔｏ１、時間Ｔｏ２、時間Ｔｏ３に相当するしきい値）と計測された時間間隔とを比較することで判定する。 The timing detection circuit 54 detects light emission for timing detection (light emission generated by the timing detection discharge) generated in the timing detection period Po of the timing detection subfield SFo based on the light reception signal. Specifically, the timing detection circuit 54 measures a time interval of a plurality of (for example, five times) emission using a timer (not shown in FIG. 5) included in the timing detection circuit 54. Then, whether or not the time interval matches a predetermined time interval (for example, time To0, time To1, time To2, time To3) is determined by a plurality of threshold values (set in the timing detection circuit 54). For example, the determination is made by comparing the measured time interval with a threshold value corresponding to time To0, time To1, time To2, and time To3.
　そして、タイミング検出回路５４は、その連続する複数回（例えば、５回）の発光のうちの１つを基準にして座標基準信号を作成する。例えば、図４に示す例では、タイミング検出サブフィールドＳＦｏのタイミング検出期間Ｐｏの時刻ｔｏ１に発生した発光を基準にして座標基準信号を作成する。 Then, the timing detection circuit 54 generates a coordinate reference signal based on one of the continuous plural times (for example, five times) of light emission. For example, in the example illustrated in FIG. 4, the coordinate reference signal is generated based on the light emission generated at the time to1 in the timing detection period Po of the timing detection subfield SFo.
　なお、時刻ｔｏ１は、タイミング検出サブフィールドＳＦｏのタイミング検出期間Ｐｏにおいて走査電極ＳＣ１～ＳＣｎに１回目のタイミング検出パルスＶ１を印加する時刻である。 The time to1 is the time when the first timing detection pulse V1 is applied to the scan electrodes SC1 to SCn in the timing detection period Po of the timing detection subfield SFo.
　また、座標基準信号は、図４には示していないが、例えば、時刻ｔｙ０と時刻ｔｘ０とのそれぞれに立上りエッジがある信号のことである。時刻ｔｙ０は、ｙ座標検出サブフィールドＳＦｙのｙ座標検出期間Ｐｙにおいて１行目の走査電極ＳＣ１にｙ座標検出パルスを印加する時刻である。また、時刻ｔｘ０は、ｘ座標検出サブフィールドＳＦｘのｘ座標検出期間Ｐｘにおいて１列目の画素列に対応するデータ電極Ｄ１～Ｄ３にｘ座標検出パルスを印加する時刻である。 The coordinate reference signal is not shown in FIG. 4, but is, for example, a signal having rising edges at time ty0 and time tx0. Time ty0 is a time at which a y-coordinate detection pulse is applied to scan electrode SC1 in the first row in y-coordinate detection period Py of y-coordinate detection subfield SFy. Time tx0 is a time at which an x-coordinate detection pulse is applied to the data electrodes D1 to D3 corresponding to the first pixel column in the x-coordinate detection period Px of the x-coordinate detection subfield SFx.
　したがって、時刻ｔｏ１がわかれば、時刻ｔｙ０と時刻ｔｘ０とのそれぞれに立上りエッジがある座標基準信号を発生することができる。 Therefore, if the time to1 is known, a coordinate reference signal having rising edges at each of the time ty0 and the time tx0 can be generated.
　そして、タイミング検出回路５４は、その座標基準信号を座標算出回路５６に出力する。 Then, the timing detection circuit 54 outputs the coordinate reference signal to the coordinate calculation circuit 56.
　なお、本実施の形態では、時刻ｔｏ１を基準にして座標基準信号を発生する例を説明しているが、本発明は何らこの構成に限定されるものではない。座標基準信号は、２回目のタイミング検出パルスＶ２を発生する時刻ｔｏ２を基準にして発生してもよく、あるいは、３回目のタイミング検出パルスＶ３を発生する時刻ｔｏ３や４回目のタイミング検出パルスＶ４を発生する時刻ｔｏ４等を基準にして発生してもよい。 In this embodiment, an example in which a coordinate reference signal is generated with reference to time to1 has been described, but the present invention is not limited to this configuration. The coordinate reference signal may be generated on the basis of the time to2 at which the second timing detection pulse V2 is generated, or the time to3 at which the third timing detection pulse V3 is generated or the fourth timing detection pulse V4. You may generate | occur | produce on the basis of the time to4 etc. which generate | occur | produce.
　また、座標基準信号も、何ら時刻ｔｙ０と時刻ｔｘ０とのそれぞれに立上りエッジがある信号に限定されるものではない。座標基準信号は、ｙ座標検出パターンによる発光およびｘ座標検出パターンによる発光を受光素子５２が受光したときに、その時刻を特定するための基準にすることができる信号であればよい。 Also, the coordinate reference signal is not limited to a signal having rising edges at time ty0 and time tx0. The coordinate reference signal may be any signal that can be used as a reference for specifying the time when the light receiving element 52 receives light emission by the y coordinate detection pattern and light emission by the x coordinate detection pattern.
　座標算出回路５６は、時間の長さを計測するカウンタと、カウンタの出力に演算を施す演算回路とを備える（図５には示さず）。 The coordinate calculation circuit 56 includes a counter that measures the length of time and an arithmetic circuit that performs an operation on the output of the counter (not shown in FIG. 5).
　そして、座標算出回路５６は、座標基準信号および受光信号にもとづき、ｙ座標検出パターンの発光を示す信号およびｘ座標検出パターンの発光を示す信号を受光信号から選択的に取り出し、画像表示領域におけるライトペン５０の位置（ｘ座標、ｙ座標）を算出する。 Then, based on the coordinate reference signal and the light reception signal, the coordinate calculation circuit 56 selectively extracts a signal indicating the light emission of the y coordinate detection pattern and a signal indicating the light emission of the x coordinate detection pattern from the light reception signal, and writes the light in the image display area. The position (x coordinate, y coordinate) of the pen 50 is calculated.
　具体的には、座標算出回路５６は、座標基準信号にもとづき、時刻ｔｙ０から、時刻ｔｙ０以降に最初に受光素子５２で発光が受光される時刻（時刻ｔｙｙ）までの時間（時間Ｔｙｙ）をカウンタで測定する。そして、演算回路において時間Ｔｙｙを時間Ｔｙ１（ｙ座標検出パルスのパルス幅）で除算する。こうして画像表示領域におけるライトペン５０の位置のｙ座標（すなわち、第１のｙ座標）を算出する。 Specifically, the coordinate calculation circuit 56 counts the time (time Tyy) from time ty0 to the time (time tyy) from which light is first received by the light receiving element 52 after time ty0 based on the coordinate reference signal. Measure with Then, the time Tyy is divided by the time Ty1 (pulse width of the y coordinate detection pulse) in the arithmetic circuit. In this way, the y coordinate (that is, the first y coordinate) of the position of the light pen 50 in the image display area is calculated.
　次に、座標算出回路５６は、座標基準信号にもとづき、時刻ｔｘ０から、時刻ｔｘ０以降に最初に受光素子５２で発光が受光される時刻（時刻ｔｘｘ）までの時間（時間Ｔｘｘ）をカウンタで測定する。そして、演算回路において時間Ｔｘｘを時間Ｔｘ１（ｘ座標検出パルスのパルス幅）で除算する。こうして画像表示領域におけるライトペン５０の位置のｘ座標（すなわち、第１のｘ座標）を算出する。 Next, the coordinate calculation circuit 56 measures, based on the coordinate reference signal, a time (time Txx) from time tx0 to time (time txx) when light is first received by the light receiving element 52 after time tx0. To do. Then, the time Txx is divided by the time Tx1 (pulse width of the x coordinate detection pulse) in the arithmetic circuit. In this way, the x coordinate (that is, the first x coordinate) of the position of the light pen 50 in the image display area is calculated.
　なお、時刻ｔｙｙは、ライトペン５０の受光素子５２がｙ座標検出パターンによりパネル１０に生じる発光を受光した時刻であり、時刻ｔｘｘは、ライトペン５０の受光素子５２がｘ座標検出パターンによりパネル１０に生じる発光を受光した時刻である。 The time tyy is the time when the light receiving element 52 of the light pen 50 receives light emitted from the panel 10 by the y coordinate detection pattern, and the time txx is the time when the light receiving element 52 of the light pen 50 receives the panel 10 by the x coordinate detection pattern. It is the time when the light emission generated in
　座標算出回路５６は、このようにして算出したライトペン５０の位置座標（ｘ、ｙ）を送信回路５８に出力する。すなわち、第１のｘ座標を表す第１のｘ座標信号と、第１のｙ座標を表す第１のｙ座標信号を送信回路５８に出力する。 The coordinate calculation circuit 56 outputs the position coordinates (x, y) of the light pen 50 calculated in this way to the transmission circuit 58. In other words, the first x coordinate signal representing the first x coordinate and the first y coordinate signal representing the first y coordinate are output to the transmission circuit 58.
　送信回路５８は、電気信号をエンコードし、エンコード後の信号を例えば赤外線等の無線信号に変換して発信する発信回路を有する（図５には示さず）。そして、座標算出回路５６が算出したライトペン５０の位置座標（ｘ、ｙ）を表す信号、および接触スイッチ５３の状態を表す信号Ｓ（例えば、接触スイッチ５３がオンであれば「Ｓ＝１」、オフであれば「Ｓ＝０」）をエンコードした後に無線信号に変換し、描画装置４０の受信回路４２に無線送信する。 The transmission circuit 58 has a transmission circuit that encodes an electric signal and converts the encoded signal into a radio signal such as infrared rays and transmits the signal (not shown in FIG. 5). A signal indicating the position coordinates (x, y) of the light pen 50 calculated by the coordinate calculation circuit 56 and a signal S indicating the state of the contact switch 53 (for example, “S = 1” if the contact switch 53 is on). If it is off, “S = 0”) is encoded and then converted into a wireless signal, which is wirelessly transmitted to the receiving circuit 42 of the drawing apparatus 40.
　受信回路４２は、ライトペン５０の送信回路５８から無線送信される無線信号を受信し、その受信信号をデコードして電気信号に変換する変換回路を有する（図５には示さず）。そして、送信回路５８から無線送信される無線信号を、ライトペン５０の位置座標（ｘ、ｙ）を表す信号、および接触スイッチ５３の状態を表す信号Ｓに変換してフィルタ回路４４に出力する。 The reception circuit 42 includes a conversion circuit that receives a wireless signal transmitted wirelessly from the transmission circuit 58 of the light pen 50, decodes the received signal, and converts it into an electrical signal (not shown in FIG. 5). The wireless signal wirelessly transmitted from the transmission circuit 58 is converted into a signal representing the position coordinates (x, y) of the light pen 50 and a signal S representing the state of the contact switch 53 and output to the filter circuit 44.
　なお、ライトペン５０の位置座標（ｘ、ｙ）を表す信号、および接触スイッチ５３の状態を表す信号Ｓは時間ｔによって変化する変数であるため、以下、フィルタ回路４４に入力される各信号を、ｘ座標Ｘ（ｔ）、ｙ座標Ｙ（ｔ）、状態Ｓ（ｔ）と記す。すなわち、ｘ座標Ｘ（ｔ）は第１のｘ座標信号であり、ｙ座標Ｙ（ｔ）は第１のｙ座標信号である。 Since the signal representing the position coordinates (x, y) of the light pen 50 and the signal S representing the state of the contact switch 53 are variables that change with time t, each signal input to the filter circuit 44 will be referred to below. , X-coordinate X (t), y-coordinate Y (t), and state S (t). That is, the x coordinate X (t) is a first x coordinate signal, and the y coordinate Y (t) is a first y coordinate signal.
　フィルタ回路４４は、ｘ座標Ｘ（ｔ）、ｙ座標Ｙ（ｔ）にフィルタ処理を施して第２のｘ座標、第２のｙ座標とし、後段の回路に出力する。すなわち、第２のｘ座標を表す第２のｘ座標信号と、第２のｙ座標を表す第２のｙ座標信号を描画回路４６に出力する。 The filter circuit 44 filters the x coordinate X (t) and the y coordinate Y (t) to obtain the second x coordinate and the second y coordinate, and outputs them to the subsequent circuit. That is, the second x coordinate signal representing the second x coordinate and the second y coordinate signal representing the second y coordinate are output to the drawing circuit 46.
　フィルタ回路４４におけるフィルタは、ローパスフィルタであり、ライトペン５０の接触スイッチ５３の状態を表す状態Ｓ（ｔ）、およびライトペン５０の移動速度に応じてフィルタの強さが制御される。以下、フィルタ処理後の各座標の信号を、ｘ座標ＦＸ（ｔ）、ｙ座標ＦＹ（ｔ）と記す。すなわち、ｘ座標ＦＸ（ｔ）は第２のｘ座標信号であり、ｙ座標ＦＹ（ｔ）は第２のｙ座標信号である。 The filter in the filter circuit 44 is a low-pass filter, and the strength of the filter is controlled according to the state S (t) indicating the state of the contact switch 53 of the light pen 50 and the moving speed of the light pen 50. Hereinafter, the signal of each coordinate after the filtering process is referred to as an x coordinate FX (t) and a y coordinate FY (t). That is, the x coordinate FX (t) is a second x coordinate signal, and the y coordinate FY (t) is a second y coordinate signal.
　フィルタ回路４４は、フィルタ処理後のｘ座標ＦＸ（ｔ）、ｙ座標ＦＹ（ｔ）を描画回路４６に出力し、また、フィルタ処理に要した時間に応じた時間遅延を状態Ｓ（ｔ）に施して状態ＦＳ（ｔ）とし、描画回路４６に出力する。フィルタ回路４４の詳細は後述する。 The filter circuit 44 outputs the filtered x-coordinate FX (t) and y-coordinate FY (t) to the drawing circuit 46, and sets a time delay corresponding to the time required for the filter processing to the state S (t). To a state FS (t) and output to the drawing circuit 46. Details of the filter circuit 44 will be described later.
　描画回路４６は、画像メモリ４７を備える。描画回路４６は、状態ＦＳ（ｔ）＝１（接触スイッチ５３がオン状態）のときには、フィルタ回路４４から出力されるｘ座標ＦＸ（ｔ）、ｙ座標ＦＹ（ｔ）にもとづく描画信号を作成して画像メモリ４７に蓄積する。したがって、状態ＦＳ（ｔ）＝１の期間は、ライトペン５０の過去の位置座標の軌跡に現在のライトペン５０の位置座標が加えられた描画信号が画像メモリ４７に蓄積される。 The drawing circuit 46 includes an image memory 47. The drawing circuit 46 creates a drawing signal based on the x coordinate FX (t) and y coordinate FY (t) output from the filter circuit 44 when the state FS (t) = 1 (the contact switch 53 is on). And stored in the image memory 47. Accordingly, during the period of the state FS (t) = 1, a drawing signal obtained by adding the current position coordinates of the light pen 50 to the past position coordinates of the light pen 50 is accumulated in the image memory 47.
　また、描画回路４６は、状態ＦＳ（ｔ）＝０（接触スイッチ５３がオフ状態）のときには、１フィールド前の位置座標を表すｘ座標ＦＸ（ｔ－１）、ｙ座標ＦＹ（ｔ－１）にもとづき作成した描画信号を画像メモリ４７から消去し、ｘ座標ＦＸ（ｔ）、ｙ座標ＦＹ（ｔ）にもとづき作成した描画信号を画像メモリ４７に蓄積する。したがって、状態ＦＳ（ｔ）＝０のときに画像メモリ４７に蓄積される描画信号は、接触スイッチ５３がオン状態であったときのライトペン５０の位置座標の過去の軌跡と、ライトペン５０の現在の位置座標を表すものになる。 Further, when the state FS (t) = 0 (the contact switch 53 is in the off state), the drawing circuit 46 has an x-coordinate FX (t−1) and a y-coordinate FY (t−1) representing the position coordinates one field before. The drawing signal created on the basis of the image data is erased from the image memory 47, and the drawing signal created on the basis of the x coordinate FX (t) and the y coordinate FY (t) is stored in the image memory 47. Therefore, the drawing signal stored in the image memory 47 when the state FS (t) = 0 is the past locus of the position coordinates of the light pen 50 when the contact switch 53 is on, It represents the current position coordinates.
　そして、描画回路４６は、画像メモリ４７に蓄積された描画信号を画像信号処理回路３１に出力する。したがって、描画回路４６から出力される描画信号は、ライトペン５０がパネル１０に接触していたときのライトペン５０の位置座標の過去の軌跡と、ライトペン５０の現在の位置座標を表すものとなる。なお、この描画信号は、使用者が手書き入力した画像や、ポインタとして使用するカーソルをパネル１０に表示するための信号であり、画像信号と実質的に同じものである。 Then, the drawing circuit 46 outputs the drawing signal stored in the image memory 47 to the image signal processing circuit 31. Therefore, the drawing signal output from the drawing circuit 46 represents the past locus of the position coordinates of the light pen 50 when the light pen 50 is in contact with the panel 10 and the current position coordinates of the light pen 50. Become. The drawing signal is a signal for displaying on the panel 10 an image handwritten by the user or a cursor used as a pointer, and is substantially the same as the image signal.
　言い換えると、描画回路４６は、フィルタ回路４４から出力される位置座標（ＦＸ、ＦＹ）によって表されるパネル１０上の位置にカーソルを表示し、かつ状態ＦＳ＝０の期間の位置座標（ＦＸ、ＦＹ）の変化の軌跡はパネル１０に表示せず、状態ＦＳ＝１の期間の位置座標（ＦＸ、ＦＹ）の変化の軌跡をパネル１０に表示する描画信号を作成して出力する。 In other words, the drawing circuit 46 displays a cursor at a position on the panel 10 represented by the position coordinates (FX, FY) output from the filter circuit 44, and the position coordinates (FX, FX) during the period of the state FS = 0. The change trajectory of (FY) is not displayed on the panel 10, and a drawing signal for displaying on the panel 10 the trajectory of change of the position coordinates (FX, FY) in the period of the state FS = 1 is generated and output.
　画像信号処理回路３１は、上述したように、描画回路４６から出力される描画信号と画像信号とを合成し（あるいは、描画信号と画像信号のいずれか一方を選択し）て画像データに変換し、後段の回路に出力する。こうして、ライトペン５０によって手書き入力された図画が、画像信号による画像に合成されて（あるいは単体で）、パネル１０に表示される。 As described above, the image signal processing circuit 31 synthesizes the drawing signal output from the drawing circuit 46 and the image signal (or selects one of the drawing signal and the image signal) and converts it into image data. , Output to the subsequent circuit. In this way, the graphic input handwritten by the light pen 50 is combined with the image based on the image signal (or alone) and displayed on the panel 10.
　なお、パネル１０に示されたライトペン５０の軌跡を消すために、ライトペン５０に、「描画」モードと「消去」モードとを切り換えるスイッチを設けてもよい。そして、ライトペン５０が「消去」モードのときには、パネル１０に示されたライトペン５０の軌跡を再度ライトペン５０でなぞることで、画像メモリ４７に蓄積された描画信号を部分的、または全体的に消去するように構成してもよい。 In addition, in order to erase the locus of the light pen 50 shown on the panel 10, the light pen 50 may be provided with a switch for switching between the “drawing” mode and the “erasing” mode. When the light pen 50 is in the “erase” mode, the trace of the light pen 50 shown on the panel 10 is traced with the light pen 50 again, so that the drawing signal stored in the image memory 47 can be partially or totally. You may comprise so that it may erase | eliminate.
　次に、プラズマディスプレイ装置３０の走査電極駆動回路３３、維持電極駆動回路３４、データ電極駆動回路３２について説明する。 Next, the scan electrode drive circuit 33, the sustain electrode drive circuit 34, and the data electrode drive circuit 32 of the plasma display device 30 will be described.
　図６は、本発明の実施の形態におけるプラズマディスプレイ装置３０の走査電極駆動回路３３の一構成例を概略的に示す回路図である。 FIG. 6 is a circuit diagram schematically showing a configuration example of the scan electrode drive circuit 33 of the plasma display device 30 according to the embodiment of the present invention.
　走査電極駆動回路３３は、維持パルス発生回路５５と、傾斜波形電圧発生回路６０と、走査パルス発生回路７０とを備えている。なお、各回路ブロックは、タイミング発生回路３５から供給されるタイミング信号にもとづき動作するが、図６では、タイミング信号の経路の詳細は省略する。また、以下、走査パルス発生回路７０に入力される電圧を「基準電位Ａ」と記す。 The scan electrode drive circuit 33 includes a sustain pulse generation circuit 55, a ramp waveform voltage generation circuit 60, and a scan pulse generation circuit 70. Each circuit block operates based on the timing signal supplied from the timing generation circuit 35, but details of the timing signal path are omitted in FIG. Hereinafter, the voltage input to the scan pulse generation circuit 70 is referred to as “reference potential A”.
　維持パルス発生回路５５は、電力回収回路５１と、スイッチング素子Ｑ５５と、スイッチング素子Ｑ５６と、スイッチング素子Ｑ５９とを有する。電力回収回路５１は、電力回収用のコンデンサＣ１０、スイッチング素子Ｑ１１、スイッチング素子Ｑ１２、逆流防止用のダイオードＤｉ１１、ダイオードＤｉ１２、共振用のインダクタＬ１１、インダクタＬ１２を有する。 Sustain pulse generation circuit 55 has power recovery circuit 51, switching element Q55, switching element Q56, and switching element Q59. The power recovery circuit 51 includes a power recovery capacitor C10, a switching element Q11, a switching element Q12, a backflow prevention diode Di11, a diode Di12, a resonance inductor L11, and an inductor L12.
　電力回収回路５１は、パネル１０に蓄えられた電力を、パネル１０の電極間容量とインダクタＬ１２とをＬＣ共振させてパネル１０から回収し、コンデンサＣ１０に蓄える。そして、回収した電力を、パネル１０の電極間容量とインダクタＬ１１とをＬＣ共振させてコンデンサＣ１０からパネル１０に再度供給し、走査電極ＳＣ１～ＳＣｎを駆動するときの電力として再利用する。 The power recovery circuit 51 recovers the power stored in the panel 10 from the panel 10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L12, and stores it in the capacitor C10. Then, the recovered power is supplied to the panel 10 again from the capacitor C10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L11, and reused as power when driving the scan electrodes SC1 to SCn.
　スイッチング素子Ｑ５５は、走査電極ＳＣ１～ＳＣｎを電圧Ｖｓにクランプし、スイッチング素子Ｑ５６は、走査電極ＳＣ１～ＳＣｎを電圧０（Ｖ）にクランプする。スイッチング素子Ｑ５９は分離スイッチであり、走査電極駆動回路３３を構成するスイッチング素子の寄生ダイオード等を介して電流が逆流するのを防止する。 Switching element Q55 clamps scan electrodes SC1 to SCn to voltage Vs, and switching element Q56 clamps scan electrodes SC1 to SCn to voltage 0 (V). The switching element Q59 is a separation switch, and prevents a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 33.
　走査パルス発生回路７０は、スイッチング素子Ｑ７１Ｈ１～Ｑ７１Ｈｎ、スイッチング素子Ｑ７１Ｌ１～Ｑ７１Ｌｎ、スイッチング素子Ｑ７２、負の電圧Ｖａを発生する電源、電圧Ｖｐを発生する電源Ｅ７１を有する。そして、走査パルス発生回路７０の基準電位Ａに電圧Ｖｐを重畳して電圧Ｖｃ（Ｖｃ＝Ｖａ＋Ｖｐ）を発生し、電圧Ｖａと電圧Ｖｃとを切り換えながら走査電極ＳＣ１～ＳＣｎに印加することで走査パルスを発生する。例えば、電圧Ｖａ＝－２００（Ｖ）であり、電圧Ｖｐ＝１５０（Ｖ）であれば、電圧Ｖｃ＝－５０（Ｖ）となる。 Scan pulse generation circuit 70 has switching elements Q71H1 to Q71Hn, switching elements Q71L1 to Q71Ln, switching element Q72, a power supply for generating negative voltage Va, and a power supply E71 for generating voltage Vp. Then, a voltage Vp (Vc = Va + Vp) is generated by superimposing the voltage Vp on the reference potential A of the scan pulse generating circuit 70, and applied to the scan electrodes SC1 to SCn while switching between the voltage Va and the voltage Vc. Is generated. For example, if the voltage Va = −200 (V) and the voltage Vp = 150 (V), the voltage Vc = −50 (V).
　そして、走査パルス発生回路７０は、走査電極ＳＣ１～ＳＣｎのそれぞれに、図３、図４に示したタイミングで走査パルスを順次印加する。なお、走査パルス発生回路７０は、維持期間では維持パルス発生回路５５の出力電圧をそのまま出力する。すなわち、基準電位Ａの電圧を走査電極ＳＣ１～ＳＣｎへ出力する。 The scan pulse generation circuit 70 sequentially applies scan pulses to the scan electrodes SC1 to SCn at the timings shown in FIGS. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 55 as it is during the sustain period. That is, the reference potential A is output to scan electrodes SC1 to SCn.
　また、走査パルス発生回路７０は、図４に示したタイミングで、ｙ座標検出サブフィールドＳＦｙのｙ座標検出期間Ｐｙでは電圧Ｖｃと電圧Ｖａｙ（＝電圧Ｖａ）のｙ座標検出パルスを発生し、ｘ座標検出サブフィールドＳＦｘのｘ座標検出期間Ｐｘでは電圧Ｖｃとｘ座標検出電圧Ｖａｘ（＝電圧Ｖａ）を発生して、走査電極ＳＣ１～ＳＣｎに印加する。 Further, the scan pulse generation circuit 70 generates y coordinate detection pulses of the voltage Vc and the voltage Vay (= voltage Va) in the y coordinate detection period Py of the y coordinate detection subfield SFy at the timing shown in FIG. In the x-coordinate detection period Px of the coordinate detection subfield SFx, a voltage Vc and an x-coordinate detection voltage Vax (= voltage Va) are generated and applied to the scan electrodes SC1 to SCn.
　傾斜波形電圧発生回路６０は、ミラー積分回路６１、ミラー積分回路６２、ミラー積分回路６３を備え、図３、図４に示した傾斜波形電圧を発生する。 The ramp waveform voltage generation circuit 60 includes a Miller integration circuit 61, a Miller integration circuit 62, and a Miller integration circuit 63, and generates the ramp waveform voltage shown in FIGS.
　ミラー積分回路６１は、トランジスタＱ６１とコンデンサＣ６１と抵抗Ｒ６１とを有する。そして、入力端子ＩＮ６１に一定の電圧を印加する（入力端子ＩＮ６１として図示される２つの丸の間に一定の電圧差を与える）ことにより、電圧Ｖｔ（＝電圧Ｖｉ２）に向かって緩やかに上昇する上り傾斜波形電圧（画像表示サブフィールドであるサブフィールドＳＦ１の初期化期間Ｐｉａ１、タイミング検出サブフィールドＳＦｏの初期化期間Ｐｉａｏ、およびｘ座標検出サブフィールドＳＦｘの初期化期間Ｐｉａｘ、の各期間に発生する上り傾斜波形電圧）を発生する。 Miller integrating circuit 61 includes transistor Q61, capacitor C61, and resistor R61. Then, by applying a constant voltage to the input terminal IN61 (giving a constant voltage difference between two circles illustrated as the input terminal IN61), the voltage gradually rises toward the voltage Vt (= voltage Vi2). Up-slope waveform voltage (generated in each period of initialization period Pia1 of subfield SF1, which is an image display subfield, initialization period Piao of timing detection subfield SFo, and initialization period Piax of x coordinate detection subfield SFx) Ascending ramp waveform voltage).
　あるいは、電圧Ｖｔに電圧Ｖｐを重畳した電圧が電圧Ｖｉ２に等しくなるように電圧Ｖｔを設定してもよい。この構成では、ミラー積分回路６１を動作させているときは、スイッチング素子Ｑ７２およびスイッチング素子Ｑ７１Ｌ１～Ｑ７１Ｌｎをオフにし、スイッチング素子Ｑ７１Ｈ１～Ｑ７１Ｈｎをオンにして、ミラー積分回路６１で発生した上り傾斜波形電圧に電源Ｅ７１の電圧Ｖｐを重畳することで初期化動作のための上り傾斜波形電圧を発生することができる。 Alternatively, the voltage Vt may be set so that a voltage obtained by superimposing the voltage Vp on the voltage Vt is equal to the voltage Vi2. In this configuration, when Miller integrating circuit 61 is operated, switching element Q72 and switching elements Q71L1 to Q71Ln are turned off, switching elements Q71H1 to Q71Hn are turned on, and the rising ramp waveform voltage generated in Miller integrating circuit 61 is turned on. The up slope waveform voltage for the initialization operation can be generated by superimposing the voltage Vp of the power source E71 on the top.
　ミラー積分回路６２は、トランジスタＱ６２とコンデンサＣ６２と抵抗Ｒ６２と逆流防止用のダイオードＤｉ６２とを有する。そして、入力端子ＩＮ６２に一定の電圧を印加する（入力端子ＩＮ６２として図示される２つの丸の間に一定の電圧差を与える）ことにより、電圧Ｖｒに向かって緩やかに上昇する上り傾斜波形電圧（画像表示サブフィールドであるサブフィールドＳＦ１～ＳＦ８の各維持期間Ｐｓ１～Ｐｓ８の最後、およびタイミング検出サブフィールドＳＦｏのタイミング検出期間Ｐｏの最後に発生する上り傾斜波形電圧）を発生する。 Miller integrating circuit 62 includes transistor Q62, capacitor C62, resistor R62, and diode Di62 for preventing backflow. Then, by applying a constant voltage to the input terminal IN62 (giving a constant voltage difference between two circles shown as the input terminal IN62), an up-slope waveform voltage that gradually rises toward the voltage Vr ( Ascending waveform voltage generated at the end of the sustain periods Ps1 to Ps8 of the subfields SF1 to SF8, which are image display subfields, and at the end of the timing detection period Po of the timing detection subfield SFo.
　ミラー積分回路６３は、トランジスタＱ６３とコンデンサＣ６３と抵抗Ｒ６３とを有する。そして、入力端子ＩＮ６３に一定の電圧を印加する（入力端子ＩＮ６３として図示される２つの丸の間に一定の電圧差を与える）ことにより、電圧Ｖｉ４に向かって緩やかに下降する下り傾斜波形電圧（画像表示サブフィールドであるサブフィールドＳＦ１～ＳＦ８の各初期化期間Ｐｉａ１、Ｐｉｂ２～Ｐｉｂ８、タイミング検出サブフィールドＳＦｏの初期化期間Ｐｉａｏ、ｙ座標検出サブフィールドＳＦｙの初期化期間Ｐｉｂｙ、およびｘ座標検出サブフィールドＳＦｘの初期化期間Ｐｉａｘ、の各期間に発生する下り傾斜波形電圧）を発生する。 Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63. Then, by applying a constant voltage to the input terminal IN63 (giving a constant voltage difference between two circles shown as the input terminal IN63), a downward ramp waveform voltage (gradiently decreasing toward the voltage Vi4 ( Initialization periods Pia1, Pib2 to Pib8 of subfields SF1 to SF8 which are image display subfields, initialization period Piao of timing detection subfield SFo, initialization period Piby of y coordinate detection subfield SFy, and x coordinate detection sub A downward ramp waveform voltage generated in each period of the initialization period Piax of the field SFx).
　なお、スイッチング素子Ｑ６９は分離スイッチであり、走査電極駆動回路３３を構成するスイッチング素子の寄生ダイオード等を介して電流が逆流するのを防止する。 Note that the switching element Q69 is a separation switch, and prevents a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 33.
　なお、これらのスイッチング素子およびトランジスタは、ＭＯＳＦＥＴやＩＧＢＴ等の一般に知られた半導体素子を用いて構成することができる。また、これらのスイッチング素子およびトランジスタは、タイミング発生回路３５で発生したそれぞれのスイッチング素子およびトランジスタに対応するタイミング信号により制御される。 Note that these switching elements and transistors can be configured using generally known semiconductor elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the respective switching elements and transistors generated by the timing generation circuit 35.
　図７は、本発明の実施の形態におけるプラズマディスプレイ装置３０の維持電極駆動回路３４の一構成例を概略的に示す回路図である。 FIG. 7 is a circuit diagram schematically showing a configuration example of the sustain electrode drive circuit 34 of the plasma display device 30 according to the embodiment of the present invention.
　維持電極駆動回路３４は、維持パルス発生回路８０と、一定電圧発生回路８５とを備えている。なお、各回路ブロックは、タイミング発生回路３５から供給されるタイミング信号にもとづき動作するが、図７では、タイミング信号の経路の詳細は省略する。 The sustain electrode driving circuit 34 includes a sustain pulse generating circuit 80 and a constant voltage generating circuit 85. Each circuit block operates based on the timing signal supplied from the timing generation circuit 35, but details of the timing signal path are omitted in FIG.
　維持パルス発生回路８０は、電力回収回路８１と、スイッチング素子Ｑ８３と、スイッチング素子Ｑ８４とを有する。電力回収回路８１は、電力回収用のコンデンサＣ２０、スイッチング素子Ｑ２１、スイッチング素子Ｑ２２、逆流防止用のダイオードＤｉ２１、ダイオードＤｉ２２、共振用のインダクタＬ２１、インダクタＬ２２を有する。 Sustain pulse generation circuit 80 has a power recovery circuit 81, a switching element Q83, and a switching element Q84. The power recovery circuit 81 includes a power recovery capacitor C20, a switching element Q21, a switching element Q22, a backflow prevention diode Di21, a diode Di22, a resonance inductor L21, and an inductor L22.
　電力回収回路８１は、パネル１０に蓄えられた電力を、パネル１０の電極間容量とインダクタＬ２２とをＬＣ共振させてパネル１０から回収し、コンデンサＣ２０に蓄える。そして、回収した電力を、パネル１０の電極間容量とインダクタＬ２１とをＬＣ共振させてコンデンサＣ２０からパネル１０に再度供給し、維持電極ＳＵ１～ＳＵｎを駆動するときの電力として再利用する。 The power recovery circuit 81 recovers the power stored in the panel 10 from the panel 10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor L22, and stores it in the capacitor C20. Then, the recovered power is supplied to the panel 10 again from the capacitor C20 by LC resonance between the interelectrode capacitance of the panel 10 and the inductor L21, and is reused as power when driving the sustain electrodes SU1 to SUn.
　スイッチング素子Ｑ８３は維持電極ＳＵ１～ＳＵｎを電圧Ｖｓにクランプし、スイッチング素子Ｑ８４は維持電極ＳＵ１～ＳＵｎを電圧０（Ｖ）にクランプする。 Switching element Q83 clamps sustain electrodes SU1 to SUn to voltage Vs, and switching element Q84 clamps sustain electrodes SU1 to SUn to voltage 0 (V).
　このようにして、維持パルス発生回路８０は、電圧Ｖｓの維持パルスを発生し、維持電極ＳＵ１～ＳＵｎに印加する。また、タイミング検出サブフィールドＳＦｏのタイミング検出期間Ｐｏではタイミング検出パルスＶ２、Ｖ４を維持電極ＳＵ１～ＳＵｎに印加する。 Thus, sustain pulse generating circuit 80 generates a sustain pulse of voltage Vs and applies it to sustain electrodes SU1 to SUn. In the timing detection period Po of the timing detection subfield SFo, the timing detection pulses V2 and V4 are applied to the sustain electrodes SU1 to SUn.
　一定電圧発生回路８５は、スイッチング素子Ｑ８６、スイッチング素子Ｑ８７を有する。そして、一定電圧発生回路８５は、画像表示サブフィールドであるサブフィールドＳＦ１～ＳＦ８の各初期化期間Ｐｉａ１、Ｐｉｂ２～Ｐｉｂ８と各書込み期間Ｐｗ１～Ｐｗ８、タイミング検出サブフィールドＳＦｏの初期化期間Ｐｉａｏと書込み期間Ｐｗｏ、ｙ座標検出サブフィールドＳＦｙの初期化期間Ｐｉｂｙとｙ座標検出期間Ｐｙ、およびｘ座標検出サブフィールドＳＦｘの初期化期間Ｐｉａｘとｘ座標検出期間Ｐｘに、維持電極ＳＵ１～ＳＵｎに電圧Ｖｅを印加する。 The constant voltage generation circuit 85 includes a switching element Q86 and a switching element Q87. The constant voltage generation circuit 85 writes the initialization periods Pia1, Pib2 to Pib8 and the writing periods Pw1 to Pw8 of the subfields SF1 to SF8, which are image display subfields, and the initialization period Pioo of the timing detection subfield SFo. During the period Pwo, the initialization period Piby and y coordinate detection period Py of the y coordinate detection subfield SFy, and the initialization period Piax and x coordinate detection period Px of the x coordinate detection subfield SFx, the voltage Ve is applied to the sustain electrodes SU1 to SUn. Apply.
　なお、これらのスイッチング素子は、ＭＯＳＦＥＴやＩＧＢＴ等の一般に知られた素子を用いて構成することができる。またこれらのスイッチング素子は、タイミング発生回路３５で発生したそれぞれのスイッチング素子に対応するタイミング信号により制御される。 In addition, these switching elements can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements are controlled by timing signals corresponding to the respective switching elements generated by the timing generation circuit 35.
　図８は、本発明の実施の形態におけるプラズマディスプレイ装置３０のデータ電極駆動回路３２の一構成例を概略的に示す回路図である。 FIG. 8 is a circuit diagram schematically showing a configuration example of the data electrode driving circuit 32 of the plasma display device 30 according to the embodiment of the present invention.
　なお、データ電極駆動回路３２は、画像信号処理回路３１から供給される画像データおよびタイミング発生回路３５から供給されるタイミング信号にもとづき動作するが、図８では、それらの信号の経路の詳細は省略する。 The data electrode drive circuit 32 operates based on the image data supplied from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35. In FIG. 8, details of the paths of these signals are omitted. To do.
　データ電極駆動回路３２は、スイッチング素子Ｑ９１Ｈ１～Ｑ９１Ｈｍ、スイッチング素子Ｑ９１Ｌ１～Ｑ９１Ｌｍを有する。そして、スイッチング素子Ｑ９１Ｌｊをオンにすることでデータ電極Ｄｊに電圧０（Ｖ）を印加し、スイッチング素子Ｑ９１Ｈｊをオンにすることでデータ電極Ｄｊに電圧Ｖｄを印加する。こうしてデータ電極駆動回路３２は、画像表示サブフィールドであるサブフィールドＳＦ１～ＳＦ８の各書込み期間Ｐｗ１～Ｐｗ８では電圧Ｖｄの書込みパルスを、タイミング検出サブフィールドＳＦｏの書込み期間Ｐｗｏでは電圧Ｖｄの書込みパルスを、ｙ座標検出サブフィールドＳＦｙのｙ座標検出期間Ｐｙではｙ座標検出電圧Ｖｄｙ（＝電圧Ｖｄ）を、ｘ座標検出サブフィールドＳＦｘのｘ座標検出期間Ｐｘでは電圧Ｖｄｘ（＝電圧Ｖｄ）のｘ座標検出パルスを、各データ電極Ｄ１～Ｄｍに印加する。 The data electrode drive circuit 32 includes switching elements Q91H1 to Q91Hm and switching elements Q91L1 to Q91Lm. Then, voltage 0 (V) is applied to data electrode Dj by turning on switching element Q91Lj, and voltage Vd is applied to data electrode Dj by turning on switching element Q91Hj. In this way, the data electrode driving circuit 32 generates an address pulse of the voltage Vd in the address periods Pw1 to Pw8 of the subfields SF1 to SF8 that are image display subfields, and an address pulse of the voltage Vd in the address period Pwo of the timing detection subfield SFo. , Y coordinate detection voltage Vdy (= voltage Vd) in the y coordinate detection period Py of the y coordinate detection subfield SFy, and x coordinate detection of the voltage Vdx (= voltage Vd) in the x coordinate detection period Px of the x coordinate detection subfield SFx. A pulse is applied to each data electrode D1-Dm.
　次に、本実施の形態における画像表示システムの一例であるプラズマディスプレイシステム１００の動作について説明する。 Next, the operation of the plasma display system 100 which is an example of the image display system in the present embodiment will be described.
　図９は、本発明の実施の形態におけるプラズマディスプレイシステム１００においてライトペン５０の位置座標を検出するときの動作の一例を概略的に示す図である。なお、図９では画像表示領域を破線で示しているが、この破線が実際にパネル１０に表示されるわけではない。 FIG. 9 is a diagram schematically showing an example of the operation when detecting the position coordinates of the light pen 50 in the plasma display system 100 according to the embodiment of the present invention. In FIG. 9, the image display area is indicated by a broken line, but this broken line is not actually displayed on the panel 10.
　図１０は、本発明の実施の形態におけるプラズマディスプレイシステム１００においてライトペン５０の位置座標を検出するときの駆動電圧波形の一例を概略的に示す図である。 FIG. 10 is a diagram schematically showing an example of a drive voltage waveform when the position coordinate of the light pen 50 is detected in the plasma display system 100 according to the embodiment of the present invention.
　図１０には、画像表示サブフィールドであるサブフィールドＳＦ８に続くタイミング検出サブフィールドＳＦｏ、ｙ座標検出サブフィールドＳＦｙおよびｘ座標検出サブフィールドＳＦｘにおいて、走査電極ＳＣ１、走査電極ＳＣｎ、データ電極Ｄ１、データ電極Ｄｍのそれぞれに印加する駆動電圧波形、座標算出回路５６に入力される座標基準信号、および受光素子５２から出力される受光信号を示す。なお、図１０では、維持電極ＳＵ１～ＳＵｎに印加する駆動電圧波形は省略するが、図１０に示す駆動電圧波形は、図３、図４に示した駆動電圧波形と同じものである。 FIG. 10 shows scan electrode SC1, scan electrode SCn, data electrode D1, and data in timing detection subfield SFo, y-coordinate detection subfield SFy, and x-coordinate detection subfield SFx following image display subfield SF8. A driving voltage waveform applied to each of the electrodes Dm, a coordinate reference signal input to the coordinate calculation circuit 56, and a light reception signal output from the light receiving element 52 are shown. In FIG. 10, the drive voltage waveforms applied to sustain electrodes SU1 to SUn are omitted, but the drive voltage waveforms shown in FIG. 10 are the same as the drive voltage waveforms shown in FIGS.
　本実施の形態におけるプラズマディスプレイ装置３０では、時刻ｔｏ１から時刻ｔｙ０までの時間Ｔｏｙはあらかじめ定められており、時刻ｔｏ１から時刻ｔｘ０までの時間Ｔｏｘはあらかじめ定められている。 In the plasma display device 30 in the present embodiment, the time Toy from the time to1 to the time ty0 is determined in advance, and the time Tox from the time to1 to the time tx0 is predetermined.
　したがって、タイミング検出回路５４は、時刻ｔｏ１を特定できれば、図１０に示すように、時刻ｔｙ０と時刻ｔｘ０とのそれぞれに立上りエッジがある座標基準信号を発生し、座標算出回路５６に出力することができる。 Therefore, when the time to1 can be specified, the timing detection circuit 54 can generate a coordinate reference signal having rising edges at each of the time ty0 and the time tx0 and output it to the coordinate calculation circuit 56 as shown in FIG. it can.
　時刻ｔｏ１は、上述したように、タイミング検出回路５４が、発光の間隔が順に時間Ｔｏ０、時間Ｔｏ１、時間Ｔｏ２、時間Ｔｏ３となる連続する５回の発光（これらの発光にもとづき受光素子５２から出力される受光信号）を検出することで、特定される。 At time to1, as described above, the timing detection circuit 54 emits light of five consecutive times in which the intervals of light emission are time To0, time To1, time To2, and time To3 (output from the light receiving element 52 based on these light emission). Is detected by detecting the received light signal).
　ｙ座標検出サブフィールドＳＦｙのｙ座標検出期間Ｐｙにおいては、第１の方向（行方向）に延長した線状の発光が第２の方向（列方向）に順次移動するｙ座標検出パターンをパネル１０に表示する。これにより、パネル１０の画像表示領域には、図９に示したように、画像表示領域の上端部（１行目）から下端部（ｎ行目）まで順次移動する１本の横線Ｌｙが表示される。 In the y-coordinate detection period Py of the y-coordinate detection subfield SFy, a y-coordinate detection pattern in which linear light emission extended in the first direction (row direction) sequentially moves in the second direction (column direction) is displayed on the panel 10. To display. Accordingly, as shown in FIG. 9, one horizontal line Ly that sequentially moves from the upper end (first row) to the lower end (nth row) of the image display region is displayed in the image display region of the panel 10. Is done.
　ライトペン５０の先端部がパネル１０の画像表示面の「座標（ｘ、ｙ）」に接触（または近接）していれば、横線Ｌｙが座標（ｘ、ｙ）を通過する時刻ｔｙｙにおいて、ライトペン５０の受光素子５２は横線Ｌｙの発光を受光する。これにより、ライトペン５０は、図１０に示すように、受光素子５２が横線Ｌｙの発光を受光したことを示す受光信号を時刻ｔｙｙにおいて出力する。 If the tip of the light pen 50 is in contact with (or close to) the “coordinates (x, y)” of the image display surface of the panel 10, at the time tyy when the horizontal line Ly passes the coordinates (x, y), the light The light receiving element 52 of the pen 50 receives the light emission of the horizontal line Ly. Thereby, as shown in FIG. 10, the light pen 50 outputs a light reception signal indicating that the light receiving element 52 has received the light emission of the horizontal line Ly at time tyy.
　続くｘ座標検出サブフィールドＳＦｘのｘ座標検出期間Ｐｘにおいては、第２の方向（列方向）に延長した線状の発光が第１の方向（行方向）に順次移動するｘ座標検出パターンをパネル１０に表示する。これにより、パネル１０の画像表示領域には、図９に示したように、画像表示領域の左端部（１列目の画素列）から右端部（ｍ／３列目の画素列）まで順次移動する１本の縦線Ｌｘが表示される。 In the subsequent x-coordinate detection period Px of the x-coordinate detection subfield SFx, an x-coordinate detection pattern in which linear light emission extended in the second direction (column direction) sequentially moves in the first direction (row direction) is displayed on the panel. 10 is displayed. Accordingly, as shown in FIG. 9, the image display area of the panel 10 is sequentially moved from the left end portion (first pixel column) to the right end portion (m / 3 pixel row) of the image display area. One vertical line Lx is displayed.
　ライトペン５０の先端部がパネル１０の画像表示面の「座標（ｘ、ｙ）」に接触（または近接）していれば、縦線Ｌｘが座標（ｘ、ｙ）を通過する時刻ｔｘｘにおいて、ライトペン５０の受光素子５２は縦線Ｌｘの発光を受光する。これにより、ライトペン５０は、図１０に示すように、受光素子５２が縦線Ｌｘの発光を受光したことを示す受光信号を時刻ｔｘｘにおいて出力する。 If the tip of the light pen 50 is in contact with (or close to) the “coordinate (x, y)” of the image display surface of the panel 10, at the time txx when the vertical line Lx passes the coordinate (x, y), The light receiving element 52 of the light pen 50 receives the light emission of the vertical line Lx. Accordingly, as shown in FIG. 10, the light pen 50 outputs a light reception signal indicating that the light receiving element 52 has received the light emission of the vertical line Lx at time txx.
　図５に示した座標算出回路５６は、ｙ座標検出サブフィールドＳＦｙのｙ座標検出期間Ｐｙにおいてタイミング検出回路５４から出力される座標基準信号と、受光素子５２から出力される受光信号にもとづき、内部に備えたカウンタを用いて時刻ｔｙ０から時刻ｔｙｙまでの時間Ｔｙｙを測定する。そして、内部に備えた演算回路において、時間Ｔｙｙを時間Ｔｙ１で除算する。この除算結果が画像表示領域におけるライトペン５０の位置のｙ座標となる。 The coordinate calculation circuit 56 shown in FIG. 5 is based on the coordinate reference signal output from the timing detection circuit 54 and the light reception signal output from the light receiving element 52 in the y coordinate detection period Py of the y coordinate detection subfield SFy. The time Tyy from the time ty0 to the time tyy is measured using the counter provided for. The time Tyy is divided by the time Ty1 in the arithmetic circuit provided inside. The division result is the y coordinate of the position of the light pen 50 in the image display area.
　また、座標算出回路５６は、ｘ座標検出サブフィールドＳＦｘのｘ座標検出期間Ｐｘにおいてタイミング検出回路５４から出力される座標基準信号と、受光素子５２から出力される受光信号にもとづき、内部に備えたカウンタを用いて時刻ｔｘ０から時刻ｔｘｘまでの時間Ｔｘｘを測定する。そして、内部に備えた演算回路において、時間Ｔｘｘを時間Ｔｘ１で除算する。この除算結果が画像表示領域におけるライトペン５０の位置のｘ座標となる。 The coordinate calculation circuit 56 is provided internally based on the coordinate reference signal output from the timing detection circuit 54 and the light reception signal output from the light receiving element 52 in the x coordinate detection period Px of the x coordinate detection subfield SFx. A time Txx from time tx0 to time txx is measured using a counter. Then, the time Txx is divided by the time Tx1 in the arithmetic circuit provided inside. This division result is the x coordinate of the position of the light pen 50 in the image display area.
　本実施の形態における座標算出回路５６は、このようにして、画像表示領域におけるライトペン５０の位置（座標（ｘ、ｙ））を算出する。 In this way, the coordinate calculation circuit 56 in the present embodiment calculates the position (coordinates (x, y)) of the light pen 50 in the image display area.
　図１１は、本発明の実施の形態におけるプラズマディスプレイシステム１００のフィルタ回路４４の一構成例を概略的に示すブロック図である。フィルタ回路４４は、係数算出部１６０、ｘ座標フィルタ１７０、およびｙ座標フィルタ１８０を有する。 FIG. 11 is a block diagram schematically showing a configuration example of the filter circuit 44 of the plasma display system 100 in the embodiment of the present invention. The filter circuit 44 includes a coefficient calculation unit 160, an x coordinate filter 170, and a y coordinate filter 180.
　ｘ座標フィルタ１７０は、乗算器１７２、１７６、加算器１７４、および遅延器１７５を有するＩＩＲ（Ｉｎｆｉｎｉｔｅ　Ｉｍｐｕｌｓｅ　Ｒｅｓｐｏｎｓｅ）フィルタである。 The x coordinate filter 170 is an IIR (Infinite Impulse Response) filter having multipliers 172 and 176, an adder 174, and a delay unit 175.
　乗算器１７２は、入力されたｘ座標Ｘ（ｔ）にフィルタ係数Ｋｘ（ｔ）を乗算して出力する。加算器１７４は、乗算器１７２から出力される信号（Ｘ（ｔ）×Ｋｘ（ｔ））に乗算器１７６から出力される信号を加算して出力する。この出力信号がフィルタ処理後のｘ座標ＦＸ（ｔ）となる。 The multiplier 172 multiplies the input x coordinate X (t) by the filter coefficient Kx (t) and outputs the result. The adder 174 adds the signal output from the multiplier 176 to the signal (X (t) × Kx (t)) output from the multiplier 172, and outputs the result. This output signal becomes the x-coordinate FX (t) after filtering.
　遅延器１７５は、フィルタ処理後のｘ座標ＦＸ（ｔ）を１フィールド（画像信号の１フィールドに等しい時間）遅延する。乗算器１７６は、１フィールド遅延後のｘ座標ＦＸ（ｔ－１）に巡回係数（１－Ｋｘ（ｔ））を乗算して出力する。 The delay unit 175 delays the filtered x-coordinate FX (t) by one field (a time equal to one field of the image signal). The multiplier 176 multiplies the x coordinate FX (t−1) after one field delay by the cyclic coefficient (1−Kx (t)) and outputs the result.
　このように、ｘ座標フィルタ１７０は、ｘ座標Ｘ（ｔ）をフィルタ係数Ｋｘ（ｔ）のＩＩＲフィルタに通してｘ座標ＦＸ（ｔ）にし、出力する。 Thus, the x-coordinate filter 170 passes the x-coordinate X (t) through the IIR filter with the filter coefficient Kx (t) to the x-coordinate FX (t) and outputs it.
　フィルタ係数Ｋｘ（ｔ）は「０」以上、「１」以下の数値である。そして、ｘ座標フィルタ１７０は、フィルタ係数Ｋｘ（ｔ）が小さくなるほど巡回係数（１－Ｋｘ（ｔ））が大きくなって強いローパスフィルタとなり、フィルタ係数Ｋｘ（ｔ）が大きくなるほど巡回係数（１－Ｋｘ（ｔ））が小さくなって弱いローパスフィルタとなる。例えば、フィルタ係数Ｋｘ（ｔ）＝「１」のときには巡回係数が「０」となってｘ座標フィルタ１７０はローパスフィルタとして機能せず、ｘ座標ＦＸ（ｔ）＝ｘ座標Ｘ（ｔ）となる。 The filter coefficient Kx (t) is a numerical value between “0” and “1”. Then, the x-coordinate filter 170 becomes a strong low-pass filter as the filter coefficient Kx (t) becomes smaller and the cyclic coefficient (1-Kx (t)) becomes larger, and as the filter coefficient Kx (t) becomes larger, the cyclic coefficient (1− Kx (t)) becomes small and becomes a weak low-pass filter. For example, when the filter coefficient Kx (t) = “1”, the cyclic coefficient is “0”, and the x-coordinate filter 170 does not function as a low-pass filter, and x-coordinate FX (t) = x-coordinate X (t). .
　ｙ座標フィルタ１８０は、乗算器１８２、１８６、加算器１８４、および遅延器１８５を有するｘ座標フィルタ１７０と同様のＩＩＲフィルタである。 Y coordinate filter 180 is an IIR filter similar to x coordinate filter 170 having multipliers 182 and 186, adder 184, and delay unit 185.
　乗算器１８２は、入力されたｙ座標Ｙ（ｔ）にフィルタ係数Ｋｙ（ｔ）を乗算して出力する。加算器１８４は、乗算器１８２から出力される信号（Ｙ（ｔ）×Ｋｙ（ｔ））に乗算器１８６から出力される信号を加算して出力する。この出力信号がフィルタ処理後のｙ座標ＦＹ（ｔ）となる。 The multiplier 182 multiplies the input y coordinate Y (t) by the filter coefficient Ky (t) and outputs the result. The adder 184 adds the signal output from the multiplier 186 to the signal (Y (t) × Ky (t)) output from the multiplier 182 and outputs the result. This output signal becomes the y coordinate FY (t) after the filter processing.
　遅延器１８５は、フィルタ処理後のｙ座標ＦＹ（ｔ）を１フィールド（画像信号の１フィールドに等しい時間）遅延する。乗算器１８６は、１フィールド遅延後のｙ座標ＦＹ（ｔ－１）に巡回係数（１－Ｋｙ（ｔ））を乗算して出力する。 The delay unit 185 delays the y coordinate FY (t) after the filtering process by one field (a time equal to one field of the image signal). The multiplier 186 multiplies the y coordinate FY (t−1) after one field delay by the cyclic coefficient (1−Ky (t)) and outputs the result.
　このように、ｙ座標フィルタ１８０は、ｙ座標Ｙ（ｔ）をフィルタ係数Ｋｙ（ｔ）のＩＩＲフィルタに通してｙ座標ＦＹ（ｔ）にし、出力する。 Thus, the y-coordinate filter 180 passes the y-coordinate Y (t) through the IIR filter having the filter coefficient Ky (t) to make the y-coordinate FY (t) and outputs it.
　フィルタ係数Ｋｙ（ｔ）は「０」以上、「１」以下の数値である。そして、ｙ座標フィルタ１８０は、フィルタ係数Ｋｙ（ｔ）が小さくなるほど巡回係数（１－Ｋｙ（ｔ））が大きくなって強いローパスフィルタとなり、フィルタ係数Ｋｙ（ｔ）が大きくなるほど巡回係数（１－Ｋｙ（ｔ））が小さくなって弱いローパスフィルタとなる。例えば、フィルタ係数Ｋｙ（ｔ）＝「１」のときには巡回係数が「０」となってｙ座標フィルタ１８０はローパスフィルタとして機能せず、ｙ座標ＦＹ（ｔ）＝ｙ座標Ｙ（ｔ）となる。 The filter coefficient Ky (t) is a numerical value between “0” and “1”. The y-coordinate filter 180 becomes a strong low-pass filter as the filter coefficient Ky (t) becomes smaller and the cyclic coefficient (1-Ky (t)) becomes larger. As the filter coefficient Ky (t) becomes larger, the cyclic coefficient (1− Ky (t)) becomes small and a low-pass filter is weak. For example, when the filter coefficient Ky (t) = “1”, the cyclic coefficient is “0”, and the y-coordinate filter 180 does not function as a low-pass filter, and y-coordinate FY (t) = y-coordinate Y (t). .
　係数算出部１６０は、遅延器１６２、１６４、および係数演算部１６６を有する。 The coefficient calculation unit 160 includes delay units 162 and 164 and a coefficient calculation unit 166.
　遅延器１６２は、入力されたｘ座標Ｘ（ｔ）を１フィールド遅延してｘ座標Ｘ（ｔ－１）を出力する。遅延器１６４は、入力されたｙ座標Ｙ（ｔ）を１フィールド遅延してｙ座標Ｙ（ｔ－１）を出力する。 The delay unit 162 delays the input x coordinate X (t) by one field and outputs the x coordinate X (t−1). The delay unit 164 delays the input y coordinate Y (t) by one field and outputs the y coordinate Y (t−1).
　係数演算部１６６は、ライトペン５０がパネル１０上を移動するときの速度を算出する速度算出部１６７を有しており、ｘ座標Ｘ（ｔ）、ｙ座標Ｙ（ｔ）、ｘ座標Ｘ（ｔ－１）、ｙ座標Ｙ（ｔ－１）、および状態Ｓ（ｔ）にもとづき、フィルタ係数Ｋｘ（ｔ）とフィルタ係数Ｋｙ（ｔ）を算出する。 The coefficient calculation unit 166 includes a speed calculation unit 167 that calculates a speed at which the light pen 50 moves on the panel 10. The coefficient calculation unit 166 includes an x coordinate X (t), a y coordinate Y (t), and an x coordinate X ( The filter coefficient Kx (t) and the filter coefficient Ky (t) are calculated based on the t-1), the y coordinate Y (t-1), and the state S (t).
　本実施の形態においては、フィルタ係数Ｋｘ（ｔ）とフィルタ係数Ｋｙ（ｔ）を以下の計算式にもとづき算出する。
Ｋｘ（ｔ）＝ｍｉｎ（Ｒｘ（ｔ）×γ（Ｓ（ｔ））、１）
Ｋｙ（ｔ）＝ｍｉｎ（Ｒｙ（ｔ）×γ（Ｓ（ｔ））、１）
なお、ｍｉｎ（ａ、ｂ）は、「ａ」と「ｂ」のいずれか小さい方を出力する関数である。また、γ（Ｓ（ｔ））は、状態Ｓ（ｔ）によって設定される変数であり、本実施の形態では、例えば、以下のように設定する。
γ（１）＝１
γ（０）＝２．８
　上述の計算式に用いるＲｘ（ｔ）、Ｒｙ（ｔ）は、ライトペン５０の移動速度（パネル１０の画像表示面における位置座標の移動速度）を近似的に表すものであり、速度算出部１６７が以下の計算式にもとづき算出する。なお、αｘ、βｘ、αｙ、βｙのぞれぞれは、あらかじめ設定された定数である。
Ｒｘ（ｔ）＝αｘ×（Ｘ（ｔ）－Ｘ（ｔ－１））＾２＋βｘ×（Ｙ（ｔ）－Ｙ（ｔ－１））＾２
Ｒｙ（ｔ）＝αｙ×（Ｘ（ｔ）－Ｘ（ｔ－１））＾２＋βｙ×（Ｙ（ｔ）－Ｙ（ｔ－１））＾２
記号「＾」はべき乗を表す。 In the present embodiment, the filter coefficient Kx (t) and the filter coefficient Ky (t) are calculated based on the following calculation formula.
Kx (t) = min (Rx (t) × γ (S (t)), 1)
Ky (t) = min (Ry (t) × γ (S (t)), 1)
Note that min (a, b) is a function that outputs the smaller one of “a” and “b”. Further, γ (S (t)) is a variable set by the state S (t). In the present embodiment, for example, it is set as follows.
γ (1) = 1
γ (0) = 2.8
Rx (t) and Ry (t) used in the above calculation formula approximately represent the moving speed of the light pen 50 (moving speed of the position coordinates on the image display surface of the panel 10), and the speed calculating unit 167. Is calculated based on the following formula. Note that each of αx, βx, αy, and βy is a preset constant.
Rx (t) = αx × (X (t) −X (t−1)) ^ 2 + βx × (Y (t) −Y (t−1)) ^ 2
Ry (t) = αy × (X (t) −X (t−1)) ^ 2 + βy × (Y (t) −Y (t−1)) ^ 2
The symbol “^” represents a power.
　上述の式に示すように、Ｒｘ（ｔ）、Ｒｙ（ｔ）は、位置座標（Ｘ（ｔ）、Ｙ（ｔ））と、１フィールド前に入力された位置座標（Ｘ（ｔ－１）、Ｙ（ｔ－１））との差分の大きさに応じて変化する変数であり、ライトペン５０がパネル１０の上を素早く動き位置座標の変化量が大きくなると大きくなり、ライトペン５０がパネル１０の上を緩やかに動き位置座標の変化量が小さくなると小さくなる。係数演算部１６６が有する速度算出部１６７は、このようにして、ライトペン５０がパネル１０上を移動するときの速度を算出する。 As shown in the above equation, Rx (t) and Ry (t) are the position coordinates (X (t), Y (t)) and the position coordinates (X (t−1)) input one field before. , Y (t-1)) is a variable that changes according to the magnitude of the difference between the light pen 50 and the light pen 50 quickly moves on the panel 10 and increases as the amount of change in position coordinates increases. 10 gradually decreases when the amount of change in the position coordinate is small. In this way, the speed calculation unit 167 included in the coefficient calculation unit 166 calculates the speed when the light pen 50 moves on the panel 10.
　そして、Ｒｘ（ｔ）、Ｒｙ（ｔ）が大きくなるとフィルタ係数Ｋｘ（ｔ）、Ｋｙ（ｔ）は大きくなってＩＩＲフィルタは弱いローパスフィルタとなり、Ｒｘ（ｔ）、Ｒｙ（ｔ）が小さくなるとフィルタ係数Ｋｘ（ｔ）、Ｋｙ（ｔ）は小さくなってＩＩＲフィルタは強いローパスフィルタとなる。 When Rx (t) and Ry (t) become large, the filter coefficients Kx (t) and Ky (t) become large and the IIR filter becomes a weak low-pass filter, and when Rx (t) and Ry (t) become small, the filter The coefficients Kx (t) and Ky (t) become smaller and the IIR filter becomes a strong low-pass filter.
　すなわち、本実施の形態におけるフィルタ回路４４は、ライトペン５０がパネル１０の上を素早く動くときには弱いローパスフィルタになり、ライトペン５０がパネル１０の上をゆっくり動くときには強いローパスフィルタになる。 That is, the filter circuit 44 in the present embodiment becomes a weak low-pass filter when the light pen 50 moves on the panel 10 quickly, and becomes a strong low-pass filter when the light pen 50 moves slowly on the panel 10.
　ライトペン５０の座標算出回路５６が算出するライトペン５０の位置座標（Ｘ（ｔ）、Ｙ（ｔ））には、放電のばらつきやノイズ等に起因して発生する誤差が含まれる。この誤差は時間的に変化するため、ライトペン５０が静止していても、座標算出回路５６が算出する位置座標（Ｘ（ｔ）、Ｙ（ｔ））に時間的な変動が生じることがある。そして、この誤差が生じると、描画信号（例えば、パネル１０に表示されるライトペン５０の位置を示すカーソル等）に、誤差に起因する揺れが生じる。 The position coordinates (X (t), Y (t)) of the light pen 50 calculated by the coordinate calculation circuit 56 of the light pen 50 include errors caused by variations in discharge, noise, and the like. Since this error changes with time, even if the light pen 50 is stationary, the position coordinates (X (t), Y (t)) calculated by the coordinate calculation circuit 56 may vary with time. . When this error occurs, the drawing signal (for example, a cursor indicating the position of the light pen 50 displayed on the panel 10) sways due to the error.
　そして、フィルタ回路４４は、このような時間的に変動する誤差を、ローパスフィルタによって時間的に平滑化し、誤差に起因して生じる描画信号の揺れを見えにくくする。なお、この誤差は、ライトペン５０がパネル１０の上を素早く動くときには比較的目立ちにくく、ライトペン５０がパネル１０の上をゆっくり動くとき、あるいは静止しているときには比較的目立ちやすい。また、強いローパスフィルタは、誤差を強く平滑化し、誤差に起因して生じる描画信号の揺れを目立ちにくくするが、一方で、描画回路４６において作成する描画信号の、ライトペン５０の移動に対する応答性を低下させる。例えば、ライトペン５０がパネル１０の上を素早く動くときに強いローパスフィルタがかかると、パネル１０に表示されるカーソル等のライトペン５０への追従性が悪くなる。 The filter circuit 44 smoothes such a temporally varying error with a low-pass filter so as to make it difficult to see the fluctuation of the drawing signal caused by the error. This error is relatively inconspicuous when the light pen 50 moves quickly over the panel 10, and is relatively conspicuous when the light pen 50 moves slowly over the panel 10 or is stationary. The strong low-pass filter strongly smoothes the error and makes the fluctuation of the drawing signal caused by the error less noticeable. On the other hand, the response of the drawing signal created in the drawing circuit 46 to the movement of the light pen 50. Reduce. For example, if a strong low-pass filter is applied when the light pen 50 moves quickly on the panel 10, the followability of the cursor or the like displayed on the panel 10 to the light pen 50 is deteriorated.
　しかしながら、上述したように、本実施の形態におけるフィルタ回路４４は、ライトペン５０がパネル１０の上を素早く動くときには弱いローパスフィルタになり、ライトペン５０がパネル１０の上をゆっくり動くときには強いローパスフィルタになる。したがって、ライトペン５０がパネル１０の上をゆっくり動くとき、あるいは静止しているときには、誤差が相対的に強く平滑化され、誤差に起因して生じる描画信号（例えば、ライトペン５０の位置を示すカーソル等）の揺れは目立ちにくくなる。また、ライトペン５０がパネル１０の上を素早く動くときには、描画回路４６において作成する描画信号のライトペン５０への追従性を良好に保つことができる。 However, as described above, the filter circuit 44 in the present embodiment is a weak low-pass filter when the light pen 50 moves quickly over the panel 10 and a strong low-pass filter when the light pen 50 moves slowly over the panel 10. become. Therefore, when the light pen 50 moves slowly on the panel 10 or is stationary, the error is relatively strongly smoothed, and a drawing signal (for example, the position of the light pen 50 indicating the position of the light pen 50 is generated due to the error). The shaking of the cursor etc. is less noticeable. Further, when the light pen 50 moves quickly on the panel 10, the followability of the drawing signal created in the drawing circuit 46 to the light pen 50 can be kept good.
　なお、上述したように、γ（Ｓ（ｔ））は、状態Ｓ（ｔ）＝「１」のときには相対的に小さい値（例えば、「１」）であり、状態Ｓ（ｔ）＝「０」のときには相対的に大きい値（例えば、「２．８」）である。 As described above, γ (S (t)) is a relatively small value (for example, “1”) when the state S (t) = “1”, and the state S (t) = “0”. "Is a relatively large value (for example," 2.8 ").
　したがって、フィルタ回路４４では、ライトペン５０の先端部がパネル１０に接触しているとき（接触スイッチ５３がオンのとき）にはローパスフィルタが強くなり、ライトペン５０の先端部がパネル１０に接触していないとき（接触スイッチ５３がオフのとき）にはローパスフィルタが弱くなる。 Therefore, in the filter circuit 44, when the tip of the light pen 50 is in contact with the panel 10 (when the contact switch 53 is on), the low-pass filter becomes strong, and the tip of the light pen 50 contacts the panel 10. When not (when the contact switch 53 is off), the low-pass filter is weak.
　したがって、使用者が描画を行うためにライトペン５０の先端部をパネル１０に接触しているときには、誤差が相対的に強く平滑化され、誤差に起因して生じる描画信号（例えば、ライトペン５０の位置を示すカーソル等）の揺れは目立ちにくくなる。また、ライトペン５０の先端部がパネル１０に接触していないときには、描画回路４６において作成する描画信号のライトペン５０への追従性を良好に保つことができる。 Therefore, when the user is touching the front end of the light pen 50 to the panel 10 for drawing, the error is relatively strongly smoothed, and a drawing signal (for example, the light pen 50 caused by the error) is generated. The shaking of the cursor indicating the position of the position becomes inconspicuous. In addition, when the tip of the light pen 50 is not in contact with the panel 10, it is possible to maintain good followability of the drawing signal created in the drawing circuit 46 to the light pen 50.
　なお、本実施の形態では、状態Ｓ（ｔ）＝「１」のときには、位置座標の移動速度がパネル１０の画像表示面で１４（ｃｍ／ｓｅｃ）以上のときにフィルタ係数Ｋｘ（ｔ）＝「１」およびフィルタ係数Ｋｙ（ｔ）＝「１」になるように、状態Ｓ（ｔ）＝「０」のときには、位置座標の移動速度がパネル１０の画像表示面で９（ｃｍ／ｓｅｃ）以上のときにフィルタ係数Ｋｘ（ｔ）＝「１」およびフィルタ係数Ｋｙ（ｔ）＝「１」になるように、各数値を設定する。しかし、本発明は何らこれらの数値に限定されるものではなく、各数値は、プラズマディスプレイシステム１００の仕様やパネル１０のサイズ等に応じて最適に設定することが望ましい。 In the present embodiment, when the state S (t) = “1”, the filter coefficient Kx (t) = when the moving speed of the position coordinates is 14 (cm / sec) or more on the image display surface of the panel 10. When the state S (t) = “0” so that “1” and the filter coefficient Ky (t) = “1”, the moving speed of the position coordinates is 9 (cm / sec) on the image display surface of the panel 10. Each numerical value is set so that the filter coefficient Kx (t) = “1” and the filter coefficient Ky (t) = “1” at the above time. However, the present invention is not limited to these numerical values, and each numerical value is desirably set optimally according to the specifications of the plasma display system 100, the size of the panel 10, and the like.
　なお、上述のαｘ、βｘ、αｙ、βｙの各定数は、パネル１０の画像表示面における位置座標の移動速度を近似的に算出できるように、例えば、パネル１０の大きさ、時刻（ｔ）と時刻（ｔ－１）との時間差等に応じて設定する。 The constants αx, βx, αy, and βy described above are, for example, the size of the panel 10, the time (t), and the like so that the moving speed of the position coordinates on the image display surface of the panel 10 can be approximately calculated. It is set according to the time difference from the time (t-1).
　なお、フィルタ回路４４は、内部に遅延器を有し（図１１には示さず）、ｘ座標ＦＸ（ｔ）、ｙ座標ＦＹ（ｔ）のフィルタ処理に要した時間に応じた時間遅延を状態Ｓ（ｔ）に施して状態ＦＳ（ｔ）とし、描画回路４６に出力する。 Note that the filter circuit 44 has a delay device inside (not shown in FIG. 11), and has a time delay corresponding to the time required for the filter processing of the x coordinate FX (t) and the y coordinate FY (t). A state FS (t) is applied to S (t) and output to the drawing circuit 46.
　図１２Ａは、本発明の実施の形態におけるプラズマディスプレイシステム１００においてライトペン５０による手書き入力を行うときの動作の一例を概略的に示す図である。図１２Ｂは、本発明の実施の形態におけるプラズマディスプレイシステム１００においてライトペン５０による手書き入力を行うときの動作の他の一例を概略的に示す図である。なお、図１２Ａ、図１２Ｂでは画像表示領域を破線で示しているが、この破線が実際にパネル１０に表示されるわけではない。 FIG. 12A is a diagram schematically showing an example of an operation when performing handwriting input with the light pen 50 in the plasma display system 100 according to the embodiment of the present invention. FIG. 12B is a diagram schematically showing another example of the operation when performing handwritten input with the light pen 50 in the plasma display system 100 according to the embodiment of the present invention. In FIG. 12A and FIG. 12B, the image display area is indicated by a broken line, but this broken line is not actually displayed on the panel 10.
　描画回路４６は、フィルタ回路４４から出力されるｘ座標ＦＸ（ｔ）、ｙ座標ＦＹ（ｔ）に対応する画素を中心に、所定の色および大きさの描画パターン（例えば、白色の丸等のパターン、以下、「カーソル１０１」と記す）の描画信号を発生する。この描画信号は描画回路４６の画像メモリ４７に順次書込まれ、状態ＦＳ（ｔ）＝１の期間（ライトペン５０がパネル１０に接触している期間）の描画信号は画像メモリ４７に蓄積される。そして、プラズマディスプレイ装置３０は、描画回路４６の画像メモリ４７に蓄積された描画信号にもとづく画像をパネル１０に表示する。 The drawing circuit 46 has a drawing pattern of a predetermined color and size (for example, a white circle or the like) around the pixel corresponding to the x coordinate FX (t) and y coordinate FY (t) output from the filter circuit 44. A drawing signal of a pattern (hereinafter referred to as “cursor 101”) is generated. The drawing signals are sequentially written in the image memory 47 of the drawing circuit 46, and the drawing signals in the period of the state FS (t) = 1 (the period in which the light pen 50 is in contact with the panel 10) are accumulated in the image memory 47. The Then, the plasma display device 30 displays an image based on the drawing signal stored in the image memory 47 of the drawing circuit 46 on the panel 10.
　したがって、例えば図１２Ａに示すように、使用者がライトペン５０の先端部をパネル１０に接触させたまま位置Ａから位置Ｂに移動させると、その移動の軌跡を示す図柄がパネル１０に表示される。こうして、パネル１０には、ライトペン５０を用いて手書き入力された図画が表示される。 Therefore, for example, as shown in FIG. 12A, when the user moves the tip of the light pen 50 from the position A to the position B while being in contact with the panel 10, a symbol indicating the movement trajectory is displayed on the panel 10. The Thus, the panel 10 displays a graphic input by handwriting using the light pen 50.
　また、状態ＦＳ（ｔ）＝０（接触スイッチ５３がオフ）の期間は、現時点の描画信号（ｘ座標ＦＸ（ｔ）、ｙ座標ＦＹ（ｔ）にもとづく描画信号）は画像メモリ４７に書き込まれ、１フィールド前の描画信号（ｘ座標ＦＸ（ｔ－１）、ｙ座標ＦＹ（ｔ－１）にもとづく描画信号）は画像メモリ４７から消去される。 Further, during the period in which the state FS (t) = 0 (the contact switch 53 is OFF), the current drawing signal (drawing signal based on the x-coordinate FX (t) and y-coordinate FY (t)) is written in the image memory 47. The drawing signal one field before (the drawing signal based on the x coordinate FX (t−1) and the y coordinate FY (t−1)) is deleted from the image memory 47.
　したがって、例えば図１２Ｂに示すように、使用者がライトペン５０の先端部をパネル１０から離して位置Ｂから位置Ｃに移動させると、その間の移動の軌跡はパネル１０に表示されず、ライトペン５０の先端部が位置Ｃにあることを示すカーソル１０１が、位置Ａから位置Ｂまでの軌跡と共に、パネル１０に表示される。 Therefore, for example, as shown in FIG. 12B, when the user moves the tip of the light pen 50 away from the panel 10 and moves the position from the position B to the position C, the trajectory of the movement is not displayed on the panel 10 and the light pen is not displayed. A cursor 101 indicating that the tip of 50 is at position C is displayed on the panel 10 together with a locus from position A to position B.
　このように、本実施の形態では、ライトペン５０の先端部がパネル１０に接触していなくても、受光素子５２がパネル１０の発光を受光できれば、パネル１０にはライトペン５０の位置座標を示すカーソル１０１が表示される。したがって、ライトペン５０をポインタとして用いることも可能である。さらに、ライトペン５０の先端部にレンズを装着する等して、ライトペン５０がパネル１０からより離れた位置にあっても受光素子５２がパネル１０の発光を受光できるように構成すれば、より離れた位置からライトペン５０をポインタとして用いることもできる。 Thus, in this embodiment, even if the tip of the light pen 50 is not in contact with the panel 10, if the light receiving element 52 can receive the light emitted from the panel 10, the position coordinates of the light pen 50 are displayed on the panel 10. A cursor 101 is displayed. Therefore, it is possible to use the light pen 50 as a pointer. Further, if the light receiving element 52 can receive the light emitted from the panel 10 even if the light pen 50 is located farther from the panel 10 by attaching a lens to the tip of the light pen 50, the light pen 50 can be received. The light pen 50 can also be used as a pointer from a distant position.
　なお、ライトペン５０の受光素子５２がパネル１０の発光を受光できないときには、パネル１０にカーソル１０１を表示しない、あるいは、受光素子５２がパネル１０の発光を最後に受光したときの座標位置にカーソル１０１を表示する、等、適切に設定すればよい。 When the light receiving element 52 of the light pen 50 cannot receive the light emission of the panel 10, the cursor 101 is not displayed on the panel 10, or the cursor 101 is positioned at the coordinate position when the light receiving element 52 last received the light emission of the panel 10. It may be set appropriately such as displaying.
　なお、本実施の形態では説明しなかったが、位置座標の検出に関係しない発光を遮断するためのマスキング信号として、座標基準信号を使用することもできる。例えば、図１０に示したように、タイミング検出回路５４が作成した座標基準信号の立下りタイミングを、ｙ座標検出期間Ｐｙの終了時刻、およびｘ座標検出期間Ｐｘの終了時刻に設定することにより、座標基準信号が「１」の期間のみ座標算出回路５６が受光信号を受信する構成としてもよい。 Although not described in this embodiment, a coordinate reference signal can also be used as a masking signal for blocking light emission not related to position coordinate detection. For example, as shown in FIG. 10, by setting the falling timing of the coordinate reference signal created by the timing detection circuit 54 to the end time of the y coordinate detection period Py and the end time of the x coordinate detection period Px, The coordinate calculation circuit 56 may receive the light reception signal only during the period when the coordinate reference signal is “1”.
　なお、本実施の形態では、接触スイッチ５３をライトペン５０の先端部に取付ける構成を説明したが、例えば、接触スイッチ５３に相当する手動スイッチをライトペン５０の側面等に設け、使用者がスイッチのオン・オフを操作できるように構成してもよい。あるいは、ライトペン５０に接触スイッチ５３と手動スイッチの両方を備える構成であってもよい。あるいは、接触スイッチ５３を手書き入力のスイッチとして用い、手動スイッチをカーソルの表示・非表示の切り替えに用いるなど、各スイッチに異なる機能を持たせてもよい。 In the present embodiment, the configuration in which the contact switch 53 is attached to the tip of the light pen 50 has been described. For example, a manual switch corresponding to the contact switch 53 is provided on the side surface of the light pen 50, and the user switches the switch. You may comprise so that operation of ON / OFF of can be operated. Alternatively, the light pen 50 may include both the contact switch 53 and the manual switch. Alternatively, each switch may have a different function, such as using the contact switch 53 as a handwriting input switch and using a manual switch for switching between display and non-display of the cursor.
　なお、本実施の形態では、タイミング検出サブフィールドＳＦｏにおいて、あらかじめ定められた所定の時間間隔（例えば、時間Ｔｏ１、時間Ｔｏ２、時間Ｔｏ３）で、タイミング検出放電を４回発生させる例を説明したが、タイミング検出放電の回数は２回以上であればよい。 In the present embodiment, an example has been described in which the timing detection discharge is generated four times at predetermined time intervals (for example, time To1, time To2, and time To3) in the timing detection subfield SFo. The number of timing detection discharges may be two or more.
　なお、本実施の形態では、最初のタイミング検出放電を容易に特定できるようにするために、タイミング検出放電を複数回発生させるときの時間間隔は互いに異なる時間に設定することが望ましい。 In the present embodiment, it is desirable to set the time intervals for generating the timing detection discharge a plurality of times in order to easily identify the first timing detection discharge.
　なお、本実施の形態では、各フィールドにタイミング検出サブフィールドＳＦｏ、ｙ座標検出サブフィールドＳＦｙ、ｘ座標検出サブフィールドＳＦｘを設ける構成を説明したが、本発明は何らこの構成に限定されるものではない。例えば、複数フィールドに１回の割合でそれらのサブフィールドを発生する構成であってもよい。 In the present embodiment, the configuration in which the timing detection subfield SFo, the y coordinate detection subfield SFy, and the x coordinate detection subfield SFx are provided in each field has been described. However, the present invention is not limited to this configuration. Absent. For example, the configuration may be such that those subfields are generated at a rate of once in a plurality of fields.
　なお、本実施の形態では、描画装置とライトペンとの間で無線通信を行う例を説明したが、本発明は何らこの構成に限定されない。例えば、描画装置とライトペンとの間を電気ケーブル等によって電気的に接続し、その電気ケーブルを介してライトペンと描画装置との間で信号の送受信を行う構成であってもよい。また、その場合には、タイミング検出サブフィールドＳＦｏを設けなくても良い。 In the present embodiment, the example in which wireless communication is performed between the drawing apparatus and the light pen has been described, but the present invention is not limited to this configuration. For example, the drawing device and the light pen may be electrically connected by an electric cable or the like, and a signal may be transmitted and received between the light pen and the drawing device via the electric cable. In that case, the timing detection subfield SFo may not be provided.
　なお、本発明の実施の形態では、各サブフィールドの発生順が何ら実施の形態に示した順番に限定されるものではない。例えば、１フィールドにおいて、ｘ座標検出サブフィールドＳＦｘの後にｙ座標検出サブフィールドＳＦｙを発生してもよい。あるいは、１フィールドにおいて、ｙ座標検出サブフィールドＳＦｙとｘ座標検出サブフィールドＳＦｘの後に画像表示サブフィールドを発生してもよい。あるいは、１フィールドにおいて、ｙ座標検出サブフィールドＳＦｙとｘ座標検出サブフィールドＳＦｘの間にタイミング検出サブフィールドＳＦｏを発生してもよく、ｘ座標検出サブフィールドＳＦｘの後にタイミング検出サブフィールドＳＦｏを発生してもよい。 In the embodiment of the present invention, the generation order of each subfield is not limited to the order shown in the embodiment. For example, in one field, the y coordinate detection subfield SFy may be generated after the x coordinate detection subfield SFx. Alternatively, in one field, an image display subfield may be generated after the y coordinate detection subfield SFy and the x coordinate detection subfield SFx. Alternatively, in one field, the timing detection subfield SFo may be generated between the y coordinate detection subfield SFy and the x coordinate detection subfield SFx, and the timing detection subfield SFo is generated after the x coordinate detection subfield SFx. May be.
　なお、本発明の実施の形態では、画像表示部にプラズマディスプレイパネルを用いたプラズマディスプレイ装置を画像表示装置の一例として挙げて、各動作を説明した。しかし、本発明は、何ら画像表示装置がプラズマディスプレイ装置に限定されるものではない。例えば、液晶パネル、有機ＥＬパネル、ＬＥＤパネル等を用いた画像表示装置においても、上述した構成と同様の構成を適用することで、上述した効果と同様の効果を得ることができる。 In the embodiment of the present invention, each operation has been described by taking a plasma display device using a plasma display panel as an image display unit as an example of the image display device. However, in the present invention, the image display device is not limited to the plasma display device. For example, even in an image display device using a liquid crystal panel, an organic EL panel, an LED panel, or the like, the same effect as that described above can be obtained by applying the same configuration as that described above.
　なお、本発明の実施の形態では、１フィールドに、複数の画像表示サブフィールドと位置座標を検出するためのサブフィールドとを有する構成を説明したが、本発明は何らこの構成に限定されるものではない。例えば、使用者がライトペンを使用しないときは、１フィールドを複数の画像表示サブフィールドだけで構成してもよい。 In the embodiment of the present invention, a configuration in which one field has a plurality of image display subfields and a subfield for detecting position coordinates has been described. However, the present invention is not limited to this configuration. is not. For example, when the user does not use the light pen, one field may be composed of only a plurality of image display subfields.
　なお、本発明の実施の形態では、強制初期化動作を、パネルの画像表示領域内にある全ての放電セルに強制的に初期化放電を発生する初期化動作として説明したが、本発明は何らこの構成に限定されない。本発明の実施の形態では、パネルの画像表示領域内にある一部の放電セルにのみ強制初期化波形を印加してその放電セルにのみ強制的に初期化放電を発生する動作も、強制初期化動作に含めるものとする。 In the embodiment of the present invention, the forced initializing operation has been described as an initializing operation that forcibly generates initializing discharge in all the discharge cells in the image display area of the panel. It is not limited to this configuration. In the embodiment of the present invention, the forced initializing waveform is applied only to some discharge cells in the image display area of the panel and the initializing discharge is forcibly generated only in the discharge cells. It shall be included in the conversion operation.
　なお、本発明の実施の形態では、描画装置４０をプラズマディスプレイ装置と独立に備えた構成を示したが、この構成の一例としては、例えば、プラズマディスプレイ装置に接続したコンピュータに描画装置４０に相当する機能を持たせ、そのコンピュータを用いて描画信号を作成する構成等がある。しかし、本発明は何らこの構成に限定されるものではなく、例えば、描画装置４０を単独の機器として設けてもよく、あるいは描画装置４０をプラズマディスプレイ装置３０に備える構成であってもよい。 In the embodiment of the present invention, a configuration in which the drawing device 40 is provided independently of the plasma display device has been described. As an example of this configuration, for example, a computer connected to the plasma display device corresponds to the drawing device 40. There is a configuration in which a rendering signal is created using the computer. However, the present invention is not limited to this configuration. For example, the drawing device 40 may be provided as a single device, or the drawing device 40 may be provided in the plasma display device 30.
　なお、図３、図４、図１０に示した駆動電圧波形は本発明の実施の形態における一例を示したものに過ぎず、本発明は何らこの駆動電圧波形に限定されるものではない。 The drive voltage waveforms shown in FIGS. 3, 4, and 10 are merely examples in the embodiment of the present invention, and the present invention is not limited to these drive voltage waveforms.
　また、図５、図６、図７、図８、図１１に示した回路構成も本発明の実施の形態における一例を示したものに過ぎず、本発明は何らこれらの回路構成に限定されるものではない。 Further, the circuit configurations shown in FIGS. 5, 6, 7, 8, and 11 are merely examples in the embodiment of the present invention, and the present invention is not limited to these circuit configurations. It is not a thing.
　なお、本発明における実施の形態に示した各回路ブロックは、実施の形態に示した各動作を行う電気回路として構成されてもよく、あるいは、実施の形態に示した各動作と実質的に同じ動作をするようにプログラミングされたマイクロコンピュータやコンピュータ等を用いて構成されてもよい。 Each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or substantially the same as each operation shown in the embodiment. A microcomputer or a computer programmed to operate may be used.
　なお、本発明の実施の形態において示した具体的な数値は、画面サイズが５０インチ、表示電極対１４の数が１０２４のパネル１０の特性にもとづき設定したものであって、単に実施の形態における一例を示したものに過ぎない。本発明はこれらの数値に何ら限定されるものではなく、各数値はパネルの仕様やパネルの特性やプラズマディスプレイ装置の仕様等にあわせて最適に設定することが望ましい。また、これらの各数値は、上述した効果を得られる範囲でのばらつきを許容するものとする。 The specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 14 of 1024. It is just an example. The present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with panel specifications, panel characteristics, plasma display device specifications, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.
　本発明は、ライトペンを用いて画像表示部に手書き入力する際に、ノイズ等によって発生する位置座標の揺れを抑えることができるので、画像表示システムとして有用である。 The present invention is useful as an image display system because it can suppress fluctuations in position coordinates caused by noise or the like when handwritten input to the image display unit using a light pen.
　１０　　パネル
　１１　　前面基板
　１２　　走査電極
　１３　　維持電極
　１４　　表示電極対
　１５，２３　　誘電体層
　１６　　保護層
　２１　　背面基板
　２２　　データ電極
　２４　　隔壁
　２５，２５Ｒ，２５Ｇ，２５Ｂ　　蛍光体層
　３０　　プラズマディスプレイ装置
　３１　　画像信号処理回路
　３２　　データ電極駆動回路
　３３　　走査電極駆動回路
　３４　　維持電極駆動回路
　３５　　タイミング発生回路
　４０　　描画装置
　４２　　受信回路
　４４　　フィルタ回路
　４６　　描画回路
　４７　　画像メモリ
　５０　　ライトペン
　５１，８１　　電力回収回路
　５２　　受光素子
　５３　　接触スイッチ
　５４　　タイミング検出回路
　５５，８０　　維持パルス発生回路
　５６　　座標算出回路
　５８　　送信回路
　６０　　傾斜波形電圧発生回路
　６１，６２，６３　　ミラー積分回路
　７０　　走査パルス発生回路
　８５　　一定電圧発生回路
　１００　　プラズマディスプレイシステム
　１０１　　カーソル
　１６０　　係数算出部
　１６２，１６４，１７５，１８５　　遅延器
　１６６　　係数演算部
　１６７　　速度算出部　１７０　　ｘ座標フィルタ
　１８０　　ｙ座標フィルタ
　１７２，１７６，１８２，１８６　　乗算器
　１７４，１８４　　加算器
　Ｌｘ　　縦線
　Ｌｙ　　横線
　Ｄｉ１１，Ｄｉ１２，Ｄｉ２１，Ｄｉ２２，Ｄｉ６２　　ダイオード
　Ｌ１１，Ｌ１２，Ｌ２１，Ｌ２２　　インダクタ
　Ｑ１１，Ｑ１２，Ｑ２１，Ｑ２２，Ｑ５５，Ｑ５６，Ｑ５９，Ｑ６９，Ｑ７２，Ｑ８３，Ｑ８４，Ｑ８６，Ｑ８７，Ｑ７１Ｈ１～Ｑ７１Ｈｎ，Ｑ７１Ｌ１～Ｑ７１Ｌｎ，Ｑ９１Ｈ１～Ｑ９１Ｈｍ，Ｑ９１Ｌ１～Ｑ９１Ｌｍ　　スイッチング素子
　Ｃ１０，Ｃ２０，Ｃ６１，Ｃ６２，Ｃ６３　　コンデンサ
　Ｒ６１，Ｒ６２，Ｒ６３　　抵抗
　Ｑ６１，Ｑ６２，Ｑ６３　　トランジスタ
　ＩＮ６１，ＩＮ６２，ＩＮ６３　　入力端子
　Ｅ７１　　電源
　ＳＦｘ　　ｘ座標検出サブフィールド
　ＳＦｙ　　ｙ座標検出サブフィールド
　ＳＦｏ　　タイミング検出サブフィールド
　ＳＦ１～ＳＦ８　　画像表示サブフィールド DESCRIPTION OF SYMBOLS 10 Panel 11 Front substrate 12 Scan electrode 13 Sustain electrode 14 Display electrode pair 15, 23 Dielectric layer 16 Protective layer 21 Back substrate 22 Data electrode 24 Partition 25, 25R, 25G, 25B Phosphor layer 30 Plasma display device 31 Image signal processing Circuit 32 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35 Timing generation circuit 40 Drawing device 42 Reception circuit 44 Filter circuit 46 Drawing circuit 47 Image memory 50 Light pen 51, 81 Power recovery circuit 52 Light receiving element 53 Contact switch 54 timing detection circuit 55, 80 sustain pulse generation circuit 56 coordinate calculation circuit 58 transmission circuit 60 ramp waveform voltage generation circuit 61, 62, 63 Miller integration circuit 70 scan pulse generation circuit 85 constant voltage generation circuit 10 Plasma display system 101 Cursor 160 Coefficient calculation unit 162, 164, 175, 185 Delay unit 166 Coefficient calculation unit 167 Speed calculation unit 170 x coordinate filter 180 y coordinate filter 172, 176, 182, 186 multiplier 174, 184 adder Lx vertical Line Ly Horizontal line Di11, Di12, Di21, Di22, Di62 Diodes L11, L12, L21, L22 Inductors Q11, Q12, Q21, Q22, Q55, Q56, Q59, Q69, Q72, Q83, Q84, Q86, Q87, Q71H1 to Q71Hn , Q71L1 to Q71Ln, Q91H1 to Q91Hm, Q91L1 to Q91Lm Switching elements C10, C20, C61, C62, C63 Capacitors R61, R62, R63 Resistance Q61 Q62, Q63 transistors IN61, IN62, IN63 input terminal E71 power SFx x-coordinate detection subfield SFy y-coordinate detection subfield SFo timing detection subfield SF1 ~ SF8 image display subfield

Claims (7)

  1. 水平方向であるｘ座標方向および垂直方向であるｙ座標方向にそれぞれ複数の電極を有する画像表示部を備えた画像表示装置と、受光素子とスイッチとを有するライトペンと、座標算出回路と、フィルタ回路と、描画回路とを備えた画像表示システムであって、
    前記画像表示装置の前記画像表示部は、ｙ座標検出サブフィールドおよびｘ座標検出サブフィールドにおいて発光し、
    前記ライトペンは、前記ｙ座標検出サブフィールドおよび前記ｘ座標検出サブフィールドにおいて前記画像表示部に生じる発光を受光して受光信号を生成し、
    前記座標算出回路は、前記受光信号にもとづき、前記ライトペンが受光する発光の前記画像表示部上の位置を表す第１のｙ座標信号、および第１のｘ座標信号を出力し、
    前記フィルタ回路は、前記第１のｘ座標信号および前記第１のｙ座標信号にローパスフィルタをかけて第２のｘ座標信号および第２のｙ座標信号を出力し、
    前記描画回路は、前記フィルタ回路から出力される前記第２のｘ座標信号および前記第２のｙ座標信号にもとづく描画信号を作成し、
    前記画像表示装置は、前記描画信号にもとづく画像を前記画像表示部に表示し、
    前記フィルタ回路は、前記ライトペンの前記スイッチの状態に応じて前記ローパスフィルタの強さが異なる
    ことを特徴とする画像表示システム。     An image display device having an image display unit having a plurality of electrodes in the horizontal x-coordinate direction and the vertical y-coordinate direction, a light pen having a light receiving element and a switch, a coordinate calculation circuit, and a filter An image display system including a circuit and a drawing circuit,
    The image display unit of the image display device emits light in a y-coordinate detection subfield and an x-coordinate detection subfield,
    The light pen receives light emitted from the image display unit in the y coordinate detection subfield and the x coordinate detection subfield to generate a light reception signal,
    The coordinate calculation circuit outputs, based on the light reception signal, a first y coordinate signal indicating a position on the image display unit of light emission received by the light pen, and a first x coordinate signal,
    The filter circuit applies a low-pass filter to the first x coordinate signal and the first y coordinate signal to output a second x coordinate signal and a second y coordinate signal,
    The drawing circuit creates a drawing signal based on the second x-coordinate signal and the second y-coordinate signal output from the filter circuit;
    The image display device displays an image based on the drawing signal on the image display unit,
    The image display system, wherein the filter circuit has different strengths of the low-pass filter depending on a state of the switch of the light pen.
  2. 前記スイッチは、前記ライトペンが前記画像表示部に接触しているときにオン状態になり接触していないときにオフ状態になる接触スイッチである
    ことを特徴とする請求項１に記載の画像表示システム。     The image display according to claim 1, wherein the switch is a contact switch that is turned on when the light pen is in contact with the image display unit and is turned off when the light pen is not in contact. system.
  3. 前記スイッチは、手動によりオン・オフを切り替える手動スイッチである
    ことを特徴とする請求項１に記載の画像表示システム。     The image display system according to claim 1, wherein the switch is a manual switch that is manually turned on and off.
  4. 前記フィルタはＩＩＲフィルタであり、
    前記スイッチがオンのときには、前記スイッチがオフのときよりも巡回係数が大きくなる
    ことを特徴とする請求項１に記載の画像表示システム。     The filter is an IIR filter;
    The image display system according to claim 1, wherein when the switch is on, the cyclic coefficient is larger than when the switch is off.
  5. 前記フィルタ回路は、前記ライトペンが前記画像表示部を移動するときの速度を算出する速度算出部を有し、前記速度が相対的に遅いときには、前記速度が相対的に速いときよりも強いローパスフィルタを前記第１のｘ座標信号および前記第１のｙ座標信号にかける
    ことを特徴とする請求項１に記載の画像表示システム。     The filter circuit includes a speed calculation unit that calculates a speed when the light pen moves the image display unit, and when the speed is relatively low, the low-pass is stronger than when the speed is relatively fast The image display system according to claim 1, wherein a filter is applied to the first x-coordinate signal and the first y-coordinate signal.
  6. 前記描画回路は、前記フィルタ回路から出力される前記ｘ座標および前記ｙ座標によって表される前記画像表示部上の位置にカーソルを表示し、かつ前記スイッチがオフの期間の前記ｘ座標、前記ｙ座標の変化の軌跡は前記画像表示部に表示せず前記スイッチがオンの期間の前記ｘ座標、前記ｙ座標の変化の軌跡を前記画像表示部に表示する描画信号を作成する
    ことを特徴とする請求項１に記載の画像表示システム。     The drawing circuit displays a cursor at a position on the image display unit represented by the x-coordinate and y-coordinate output from the filter circuit, and the x-coordinate during a period in which the switch is off, y A coordinate change trajectory is not displayed on the image display unit, and a drawing signal is generated to display the x coordinate and y coordinate change trajectory on the image display unit while the switch is on. The image display system according to claim 1.
  7. 前記描画回路は、画像メモリを有し、前記スイッチがオンの期間の前記ｘ座標、前記ｙ座標の情報を前記画像メモリに蓄積し、前記スイッチがオフの期間は現在の前記ｘ座標、前記ｙ座標を除き前記ｘ座標、前記ｙ座標の情報を前記画像メモリに蓄積しない
    ことを特徴とする請求項１に記載の画像表示システム。     The drawing circuit has an image memory, stores information on the x-coordinate and y-coordinate in a period when the switch is on, and stores the current x-coordinate and y in the period when the switch is off. The image display system according to claim 1, wherein information on the x-coordinate and the y-coordinate is not stored in the image memory except for coordinates.
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Publication number Priority date Publication date Assignee Title
JPH01234921A (en) * 1988-03-16 1989-09-20 Fujitsu Ltd Write pen position detector
JPH09222871A (en) * 1996-02-16 1997-08-26 Pioneer Electron Corp Driving device of plasma display panel
JP2001318765A (en) * 2000-05-10 2001-11-16 Nec Corp Coordinate position detector and coordinate position detection method for plasma display panel
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