WO2013078636A1 - 多相位时钟信号发生电路 - Google Patents
多相位时钟信号发生电路 Download PDFInfo
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- WO2013078636A1 WO2013078636A1 PCT/CN2011/083212 CN2011083212W WO2013078636A1 WO 2013078636 A1 WO2013078636 A1 WO 2013078636A1 CN 2011083212 W CN2011083212 W CN 2011083212W WO 2013078636 A1 WO2013078636 A1 WO 2013078636A1
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- clock signal
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
- H03K5/15073—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using a plurality of comparators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
- H03K5/1508—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using a plurality of delay lines
Definitions
- the present technology relates to electronic circuits, and in particular to a multi-phase clock signal generating circuit. Background technique
- Multi-phase clock signal generators are widely used in integrated circuits.
- Multiphase clock generators are an important part of multiphase charge pumps.
- the prior art mainly combines the generation of a multi-phase clock signal by the delay of the clock signal.
- Prior art multi-phase clock generators vary greatly in characteristics of components such as MOS transistors and resistors in the clock generator due to variations in integration process, operating voltage, or operating temperature, depending on the clock phase of these components. Some phases may even overlap in advance or delay.
- the solid line is the normal waveform of the clock signals CLK1 and CLK2
- the dashed line is the possible change of the waveforms of CLK1 and CLK2 when the integrated process, operating voltage or operating temperature changes. It can be clearly seen from Figure 7.
- the phases have overlapped. Especially when the prior art multi-phase clock generator is applied to a multi-phase charge pump, the efficiency of the multi-phase charge pump is greatly reduced when the integration process, operating voltage or operating temperature fluctuates. Summary of the invention
- a third transistor and a fourth transistor of the second channel type wherein sources of the first transistor and the second transistor are grounded, and a drain of the first transistor is coupled to a source of the third transistor and a gate of the fourth transistor
- the drain of the second transistor is coupled to the source of the fourth transistor and the gate of the third transistor, and the drains of the third transistor and the fourth transistor are connected to a power supply;
- a first delay unit the input end receives a clock signal, the output end is coupled to the gate of the first transistor; the second delay unit, the input end receives the inverted clock signal of the clock signal, and the output end is coupled to the The gate of the second transistor;
- a fifth transistor and a sixth transistor of the first channel type respectively receiving the inverted clock signal and the clock signal; a seventh transistor and an eighth transistor of the second channel type, wherein the sources of the fifth transistor and the sixth transistor are grounded, the drain of the fifth transistor is coupled to the source of the seventh transistor, and the drain of the sixth transistor And a drain of the seventh transistor and the eighth transistor are connected to the power supply; a third delay unit, the input end is coupled to the drain of the fifth transistor and the seventh transistor a node between the sources, the output end coupled to the gate of the eighth transistor;
- the input end is coupled to a node between the drain of the sixth transistor and the source of the eighth transistor, and the output end is coupled to the gate of the seventh transistor;
- the node between the drain of the second transistor and the source of the fourth transistor outputs a first clock signal
- the node between the drain of the fifth transistor and the source of the seventh transistor outputs a second clock signal
- first A node between the drain of the transistor and the source of the third transistor outputs a third clock signal
- a node between the drain of the sixth transistor and the source of the eighth transistor outputs a fourth clock signal.
- the delay times of the first delay unit, the second delay unit, the third delay unit, and the fourth delay unit are all adjustable.
- each of the first delay unit, the second delay unit, the third delay unit, and the fourth delay unit includes: serially connected to the first inverter and the second inverter And a capacitor connected at one end to a node between the first inverter and the second inverter, the other end of the capacitor being grounded.
- the capacitor is an adjustable capacitor.
- the delay times of the first delay unit and the second delay unit are substantially equal, and the delay times of the third delay unit and the fourth delay unit are substantially equal.
- the first channel type is an N type and the second channel type is a P type.
- the first channel type is a P type and the second channel type is an N type.
- the circuit further includes:
- the input end is coupled to a node between a drain of the first transistor and a source of the third transistor, and the output end outputs a buffered third clock signal
- the input end is coupled to a node between the drain of the second transistor and the source of the fourth transistor, and the output end outputs the buffered first clock signal
- the input end is coupled to a node between the drain of the fifth transistor and the source of the seventh transistor, and the output end outputs the buffered second clock signal
- the fourth buffer has an input coupled to a node between a drain of the sixth transistor and a source of the eighth transistor, and the output outputs a buffered fourth clock signal.
- the circuit further includes an inverter that converts the input clock signal into an inverted clock signal.
- a dual phase clock signal generating circuit includes: a first transistor and a second transistor of a first channel type
- a third transistor and a fourth transistor of the second channel type wherein sources of the first transistor and the second transistor are grounded, and a drain of the first transistor is coupled to a source of the third transistor and a gate of the fourth transistor
- the drain of the second transistor is coupled to the source of the fourth transistor and the gate of the third transistor, and the drains of the third transistor and the fourth transistor are connected to a power supply;
- a first delay unit the input end receives a clock signal, the output end is coupled to the gate of the first transistor; the second delay unit, the input end receives the inverted clock signal of the clock signal, and the output end is coupled to the The gate of the second transistor;
- the node between the drain of the second transistor and the source of the fourth transistor outputs a first clock signal
- the node between the drain of the first transistor and the source of the third transistor outputs a third clock signal
- a dual phase clock signal generating circuit includes: a first transistor and a second transistor of a first channel type, respectively receiving a clock signal and an inverted clock signal of the clock signal;
- the drains of the third transistor and the fourth transistor are connected to the power supply;
- the first delay unit the input end is coupled to the drain of the first transistor and the third transistor a node between the sources, the output end coupled to the gate of the fourth transistor;
- the input end is coupled to a node between the drain of the second transistor and the source of the fourth transistor, and the output end is coupled to the gate of the third transistor;
- the node between the drain of the first transistor and the source of the third transistor outputs a first clock signal
- the node between the drain of the second transistor and the source of the fourth transistor outputs a second clock signal
- phase relationship between the clock signals of the respective phases generated by the multi-phase clock signal generating circuit according to the embodiment is relatively independent of the integrated process, operating voltage or operating temperature of the circuit, so that the efficiency of the multi-phase charge pump can be ensured.
- phase delay of each phase clock signal generated by the multi-phase clock signal generating circuit according to the embodiment is adjustable.
- power consumption of the multi-phase clock signal generating circuit according to the embodiment is low.
- FIG. 1 shows a schematic diagram of a circuit configuration of a multi-phase clock signal generator in accordance with an embodiment of the present technology
- FIG. 2 is a circuit diagram showing the structure of a delay unit in a multi-phase clock signal generator according to an embodiment of the present technology
- FIG. 3 is a diagram showing a relative timing relationship of respective phase signals output by a multi-phase clock signal generator in accordance with an embodiment of the present technology
- FIG. 4 is a circuit diagram showing a circuit configuration of a dual phase clock signal generator according to another embodiment of the present technology
- FIG. 5 is a block diagram showing a circuit configuration of a dual phase clock signal generator according to still another embodiment of the present technology
- FIG. 6 is a circuit diagram showing a circuit configuration of a four-phase clock signal generator according to still another embodiment of the present technology
- Fig. 7 shows the relationship between multiphase clocks generated by the multiphase clock generating circuit according to the prior art. detailed description
- FIG. 1 shows a schematic diagram of a circuit configuration of a multi-phase clock signal generator in accordance with an embodiment of the present technology.
- the four-phase clock signal generator shown in Figure 1 includes two circuit blocks MD1 and MD2.
- the circuit includes two circuit modules, each of which includes a cross-coupling structure and a delay unit, wherein delays D1 and D2 are adjustable delay units.
- the circuit module MD1 includes NMOS transistors MN1, MN2 and PMOS transistors MP1, MP2 and two delay units D1 and D2.
- the circuit module MD2 includes NMOS transistors MN3, MN4 and PMOS transistors MP3, MP4 and two delay units D3 and D4.
- the input of the delay unit D1 receives the input clock signal CLK.
- the clock signal after the delay of delay unit D1 is output at its output.
- the output of the delay unit is coupled to the gate of the NMOS transistor MN1.
- the input of delay unit D2 receives the inverted clock signal CLKB.
- the clock signal after the delay of delay unit D2 is output at its output.
- the output of the delay unit is coupled to the gate of the NMOS transistor MN2.
- the source of the NMOS transistor MN1 and the source of the NMOS transistor MN2 are grounded, and their drains are respectively coupled to the source of the PMOS transistor MP1 and the source of the PMOS transistor MP2.
- a node between the drain of the NMOS transistor MN2 and the source of the PMOS transistor MP2 is coupled to the gate of the PMOS transistor MP1 as a phase signal output node of the four-phase clock signal generator according to the embodiment.
- a node between the drain of the NMOS transistor MN1 and the source of the PMOS transistor MP1 is coupled to the gate of the PMOS transistor MP2, which serves as another phase signal output node of the four-phase clock signal generator according to the embodiment.
- the drains of the PMOS transistors MP1 and MP2 are connected to the power supply.
- the gate of the NMOS transistor MN3 receives the inverted input clock signal CLKB, and the gate of the NMS transistor MN4 receives the input clock signal CLK.
- the source of the NMOS transistor MN3 is connected to the source of the NMOS transistor MN4. Ground, their drains are respectively coupled to the source of the PMOS transistor MP3 and the source of the PMOS transistor MP4.
- the node between the drain of the NMOS transistor MN4 and the source of the PMOS transistor MP4 is coupled to the gate of the PMOS transistor MP3 through the fourth delay unit D4, which is another one of the four-phase clock signal generator according to the embodiment. Phase signal output node.
- the node between the drain of the NMOS transistor MN3 and the source of the PMOS transistor MP3 is coupled to the gate of the PMOS transistor MP4 through the fourth delay unit D4, which serves as another of the four-phase clock signal generator according to the embodiment. Phase signal output node.
- the drains of the PMOS transistors MP3 and MP4 are connected to a power supply.
- the clock signal B1 outputted from the node between the drain of the NMOS transistor MN1 and the source of the PMOS transistor MP1 is buffered by the buffer BF1, and the clock signal CLK3 is output.
- the clock signal A1 outputted from the node between the drain of the NMOS transistor MN2 and the source of the PMOS transistor MP2 is buffered by the buffer BF2, and the clock signal CLK1 is output.
- the clock signal B2 outputted from the node between the drain of the NMOS transistor MN3 and the source of the PMOS transistor MP3 is buffered by the buffer BF3, and the clock signal CLK2 is output.
- the clock signal A2 outputted from the node between the drain of the NMOS transistor MN4 and the source of the PMOS transistor MP4 is buffered by the buffer BF4, and the clock signal CLK4 is output.
- the different channel type MOS transistors in the above embodiments are not intended to be limiting. Instead, one of ordinary skill in the art can make various changes to it.
- the channel type of the upper two MOS transistors in the cross-coupling structure may be N-type
- the channel type of the lower two MOS transistors may be P-type.
- the sources of the NMOS transistors MN1 and B MN2 are grounded, and the drains of the PMOS transistors MP1 and MP2 are connected to the power supply.
- the power configuration of the cross-coupling structure can be adjusted according to requirements for voltage/current or heat dissipation.
- the delay amount of each of the delay units D1 to D4 described above is adjustable.
- the delay amounts of the delay units D1 ⁇ D2 are substantially equal, and the delay amounts of the delay units D3 ⁇ D4 are substantially equal.
- 2 is a circuit diagram showing the structure of a delay unit in a multi-phase clock signal generator in accordance with an embodiment of the present technology.
- the delay unit shown in Figure 2 includes two inverters NT1, NT2 and one capacitor connected in series. .
- One end of the capacitor C is coupled to the node between the inverters, and the other end is grounded.
- those skilled in the art can set a larger number of inverters to implement the delay or use other methods to delay, for example, using a delay line.
- the capacitance of the capacitor C in the delay units D1 and D2 is adjustable.
- the capacitor C is an adjustable capacitor.
- FIG. 3 is a diagram showing the relative timing relationship of signals of respective phases output by a multi-phase clock signal generator in accordance with an embodiment of the present technology.
- the input clock signals CLK and CLKB are a pair of opposite phase clock signals.
- CLKd and CLKBd are the signals generated by CLK and CLKB after delay units D1 and D2.
- CLK1, CLK2, CLK3, and CLK4 are phase clock signals outputted according to the clock signals output from the four-phase clock signal generating circuit shown in FIG. 1 and buffered by the buffers BF2, BF3, BF1, and BF4, respectively.
- tl time I the falling edge of the input clock signal CLK comes.
- PMOS transistor MP4 turns signal A2 high and clock signal CLK4 goes low.
- clock signal B1 pulls clock signal A1 high through the cross-coupled PMOS transistors MP1 and MP2, while clock signal CLK1 goes high.
- clock signal A2 pulls the clock signal B2 high through the cross-coupled PMOS transistors MP3 and MP4, and the clock signal CLK2 goes high.
- clock signal A1 pulls clock signal B1 high through the cross-coupled PMOS transistors MP1 and MP2, while clock signal CLK3 goes high.
- clock signal B2 pulls clock signal A2 high through the cross-coupled PMOS transistors MP3 and MP4, while clock signal CLK4 goes high.
- Fig. 4 is a circuit diagram showing the structure of a dual phase clock signal generator in accordance with another embodiment of the present technology.
- the two-phase clock signal generator according to the present embodiment employs the circuit block MD1 of the four-phase clock signal generator shown in Fig. 1 and the corresponding buffers BF1 and BF2.
- the two-phase clock signal generator according to the present embodiment generates clock signals CLK3 and CLK1.
- FIG. 5 shows a circuit configuration diagram of a dual phase clock signal generator in accordance with still another embodiment of the present technology.
- the bi-phase clock signal generator shown in Fig. 5 employs the circuit block MD2 of the four-phase clock signal generator shown in Fig. 1 and the corresponding buffers BF3 and BF4. Biphasic time according to the present embodiment
- the clock signal generator generates clock signals CLK2 and CLK4.
- the input clock signal is passed through the pass-through transistor structure as an additional clock signal to produce a three-phase or five-phase clock signal.
- an additional two-phase clock signal generating circuit is added and an additional delay unit is added to the additional bidirectional clock signal generating circuit, for example, FIG. 4 or Each delay unit in 5 is replaced by two delay units.
- a single clock signal is divided and then the clock generation circuit described above is used to generate a desired number of phase clock signals.
- Fig. 6 is a circuit diagram showing the structure of a four-phase clock signal generator in accordance with still another embodiment of the present technology.
- an external clock signal CLK is input, and an inverter NT is provided inside the circuit to convert the clock signal into an inverted clock signal CLKB.
- the delay unit shown in Fig. 2 is used instead of the delay unit in the circuit shown in Fig. 1, but the value of the capacitor C can be adjusted according to different needs.
- the phase relationship between the clock signals of each phase generated by the circuit structure of each embodiment in the present technology has a strict sequence trigger relationship and a timing constraint relationship, and no phase overlap occurs, that is, with the integration process,
- the operating voltage or operating temperature is relatively independent.
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Abstract
公开了一种多相时钟信号发生电路。该电路包括两个电路模块,每个电路模块都包括交叉耦合结构和两个延时单元,其中延时单元和是可调延时单元。电路模块MD1包括两个NMOS管、两个PMOS管以及两个延时单元。电路模块MD2包括两个NMOS管、两个PMOS管以及两个延时单元。根据实施例的多相位时钟信号发生电路所产生的各相时钟信号之间的相位关系与该电路的集成工艺,工作电压和工作温度相对无关,因此能够保证多相位电荷泵的效率。
Description
多相位时钟信号发生电路 技术领域
本技术涉及电子电路, 具体涉及一种多相位时钟信号发生电路。 背景技术
多相位时钟信号发生器广泛应用于集成电路中。 多相位时钟发生器是多相 位电荷泵的重要组成部分。现有技术主要通过时钟信号的延时来组合生成多相位 时钟信号。现有技术的多相位时钟发生器由于在集成工艺、工作电压或工作温度 变化时, 时钟发生器中的元件如 MOS管、 电阻的特性变化很大, 依赖于这些元 件的时钟相位可能会随之提前或者延后,某些相位甚至会发生重叠。如图 7所示, 实线为时钟信号 CLK1和 CLK2的正常波形, 虚线为集成工艺、工作电压或工作 温度变化时 CLK1和 CLK2的波形可能的变化,从图 7中可以很清楚的看到他们 的相位发生了重叠。特别是当现有技术的多相位时钟发生器应用于多相位电荷泵 时, 在集成工艺、 工作电压或工作温度波动时会大大降低多相位电荷泵的效率。 发明内容
考虑到现有技术中的一个或多个问题, 提出了一种多相位时钟信号发生电 路。
根据实施例的多相位时钟信号发生电路包括:
第一沟道类型的第一晶体管和第二晶体管;
第二沟道类型的第三晶体管和第四晶体管, 其中, 第一晶体管和第二晶体 管的源极接地, 第一晶体管的漏极耦接至第三晶体管的源极和第四晶体管的栅 极,第二晶体管的漏极耦接至第四晶体管的源极和第三晶体管的栅极,所述第三 晶体管和第四晶体管的漏极接供电电源;
第一延时单元, 输入端接收一时钟信号, 输出端耦接至第一晶体管的栅极; 第二延时单元, 输入端接收所述时钟信号的反相时钟信号, 输出端耦接至 第二晶体管的栅极;
第一沟道类型的第五晶体管和第六晶体管, 分别接收所述反相的时钟信号 和所述时钟信号;
第二沟道类型的第七晶体管和第八晶体管, 其中, 第五晶体管和第六晶体 管的源极接地,第五晶体管的漏极耦接至第七晶体管的源极,第六晶体管的漏极 耦接至第八晶体管的源极, 所述第七晶体管和第八晶体管的漏极接供电电源; 第三延时单元, 输入端耦接至所述第五晶体管的漏极和第七晶体管的源极 之间的节点, 输出端耦接至第八晶体管的栅极;
第四延时单元, 输入端耦接至所述第六晶体管的漏极和第八晶体管的源极 之间的节点, 输出端耦接至所述第七晶体管的栅极;
其中, 第二晶体管的漏极和第四晶体管的源极之间的节点输出第一时钟信 号,第五晶体管的漏极和第七晶体管的源极之间的节点输出第二时钟信号,第一 晶体管的漏极和第三晶体管的源极之间的节点输出第三时钟信号,第六晶体管的 漏极和第八晶体管的源极之间的节点输出第四时钟信号。
根据本技术的实施例, 第一延时单元、 第二延时单元、 第三延时单元和第 四延时单元的延时时间都是可调的。
根据本技术的实施例, 第一延时单元、 第二延时单元、 第三延时单元和第 四延时单元的每一个都包括: 串联连接到第一反相器和第二反相器, 以及一端连 接到第一反相器和第二反相器之间的节点的电容器, 电容器的另一端接地。
根据本技术的实施例, 所述电容器是可调电容器。
根据本技术的实施例, 第一延时单元和第二延时单元的延时时间基本上相 等, 第三延时单元和第四延时单元的延时时间基本上相等。
根据本技术的实施例, 所述第一沟道类型是 N型, 第二沟道类型是 P型。 根据本技术的实施例, 第一沟道类型是 P型, 第二沟道类型是 N型。
根据本技术的实施例, 所述的电路还包括:
第一缓冲器, 输入端耦接至第一晶体管的漏极和第三晶体管的源极之间的 节点, 输出端输出缓冲的第三时钟信号,
第二缓冲器, 输入端耦接至第二晶体管的漏极和第四晶体管的源极之间的 节点, 输出端输出缓冲的第一时钟信号,
第三缓冲器, 输入端耦接至第五晶体管的漏极和第七晶体管的源极之间的 节点, 输出端输出缓冲的第二时钟信号,
第四缓冲器, 输入端耦接至第六晶体管的漏极和第八晶体管的源极之间的 节点, 输出端输出缓冲的第四时钟信号。
根据本技术的实施例, 所述的电路还包括反相器, 将所输入的时钟信号转 换成反相的时钟信号。
根据本技术的另一实施例, 一种双相位时钟信号发生电路, 包括: 第一沟道类型的第一晶体管和第二晶体管;
第二沟道类型的第三晶体管和第四晶体管, 其中, 第一晶体管和第二晶体 管的源极接地, 第一晶体管的漏极耦接至第三晶体管的源极和第四晶体管的栅 极,第二晶体管的漏极耦接至第四晶体管的源极和第三晶体管的栅极,所述第三 晶体管和第四晶体管的漏极接供电电源;
第一延时单元, 输入端接收一时钟信号, 输出端耦接至第一晶体管的栅极; 第二延时单元, 输入端接收所述时钟信号的反相时钟信号, 输出端耦接至 第二晶体管的栅极;
其中, 第二晶体管的漏极和第四晶体管的源极之间的节点输出第一时钟信 号, 第一晶体管的漏极和第三晶体管的源极之间的节点输出第三时钟信号。
根据本技术的又一实施例, 一种双相位时钟信号发生电路, 包括: 第一沟道类型的第一晶体管和第二晶体管, 分别接收一时钟信号和所述时 钟信号的反相时钟信号;
第二沟道类型的第三晶体管和第四晶体管, 其中, 第一晶体管和第二晶体 管的源极接地,第一晶体管的漏极耦接至第三晶体管的源极,第二晶体管的漏极 耦接至第四晶体管的源极, 所述第三晶体管和第四晶体管的漏极接供电电源; 第一延时单元, 输入端耦接至所述第一晶体管的漏极和第三晶体管的源极 之间的节点, 输出端耦接至第四晶体管的栅极;
第二延时单元, 输入端耦接至所述第二晶体管的漏极和第四晶体管的源极 之间的节点, 输出端耦接至所述第三晶体管的栅极;
其中, 第一晶体管的漏极和第三晶体管的源极之间的节点输出第一时钟信 号, 第二晶体管的漏极和第四晶体管的源极之间的节点输出第二时钟信号。
根据实施例的多相位时钟信号发生电路所产生的各相时钟信号之间的相位 关系与该电路的集成工艺、工作电压或工作温度相对无关, 因此能够保证多相位 电荷泵的效率。
此外, 根据实施例的多相位时钟信号发生电路所产生的各相时钟信号的相 位延时是可调的。 另外, 根据实施例的多相位时钟信号发生电路的功耗低。
附图说明
通过结合附图对本技术的优选实施例进行详细描述, 本技术的上述和其他 目的、 特性和优点将会变得更加清楚, 其中:
图 1 示出了根据本技术的实施例的多相位时钟信号发生器的电路结构示意 图;
图 2示出了根据本技术的实施例的多相位时钟信号发生器中的延时单元的 电路结构示意图;
图 3示出了根据本技术的实施例的多相位时钟信号发生器输出的各相信号 的相对时序关系示意图;
图 4示出了根据本技术的另一实施例的双相位时钟信号发生器的电路结构 示意图;
图 5示出了根据本技术的又一实施例的双相位时钟信号发生器的电路结构 示意图;
图 6示出了根据本技术的再一实施例的四相位时钟信号发生器的电路结构 示意图; 以及
图 7示出了根据现有技术的多相时钟发生电路产生的多相时钟之间的关系。 具体实施方式
将在下文中结合附图对本技术的实施例进行详细描述。 虽然结合实施例进 行阐述, 但应理解为这并非意指将本技术限定于这些实施例中。相反, 本技术意 在涵盖由所附权利要求所界定的本技术精神和范围内所定义的各种可选方案、修 改方案和等同方案。
此外, 为了更好的理解本技术, 在下面的描述中, 阐述了大量具体的细节, 比如具体的电路、 器件、 连接关系等。 然而, 本技术的领域的普通技术人员应该 理解, 没有这些具体的细节, 本技术依然可以实施。 在其他的一些实施例中, 为 了便于凸显本技术的主旨, 对于熟知的技术未作详细的描述。
在下文所述的特定实施例代表本技术的示例性实施例,并且本质上仅为 示例说明而非限制。 在说明书中, 提及"一个实施例"或者"实施例 "意味着结 合该实施例所描述的特定特征、 结构或者特性包括在本技术的至少一个实施
例中。 术语"在一个实施例中"在说明书中各个位置出现并不全部涉及相同的 实施例, 也不是相互排除其他实施例或者可变实施例。 本说明书中公开的所 有特征, 或公开的所有方法或过程中的步骤, 除了互相排斥的特征和 /或步骤 以外, 均可以以任何方式组合。 此外, 本领域普通技术人员应当理解, 在此提 供的示图都是为了说明的目的, 并且示图不一定是按比例绘制的。应当理解, 当 称"元件" "连接到"或"耦接"到另一元件时, 它可以是直接连接或耦接到另一元件 或者可以存在中间元件。 相反, 当称元件"直接连接到"或"直接耦接到"另一元件 时, 不存在中间元件。相同的附图标记指示相同的元件。这里使用的术语"和 /或" 包括一个或多个相关列出的项目的任何和所有组合。
图 1 示出了根据本技术的实施例的多相位时钟信号发生器的电路结构示意 图。如图 1所示的四相位时钟信号发生器包括两个电路模块 MD1和 MD2。该电 路包括两个电路模块,每个电路模块都包括交叉耦合结构和延时单元,其中延时 D1和 D2是可调延时单元。
如图 1所示, 电路模块 MD1包括 NMOS管 MN1, MN2和 PMOS管 MP1 , MP2以及两个延时单元 D1和 D2。 电路模块 MD2包括 NMOS管 MN3, MN4 禾口 PMOS管 MP3, MP4以及两个延时单元 D3和 D4。
延时单元 D1的输入端接收输入的时钟信号 CLK。经过延时单元 D1延时后 的时钟信号在其输出端输出。该延时单元的输出端耦接至 NMOS管 MN1的栅极。
延时单元 D2的输入端接收反相的时钟信号 CLKB。 经过延时单元 D2延时 后的时钟信号在其输出端输出。该延时单元的输出端耦接至 NMOS管 MN2的栅 极。
NMOS管 MN1的源极与 NMOS管 MN2的源极接地,它们的漏极分别耦接 到 PMOS管 MP1的源极和 PMOS管 MP2的源极。 NMOS管 MN2的漏极与 PMOS 管 MP2的源极之间的节点耦接至 PMOS管 MP1的栅极, 该节点作为根据实施 例的四相时钟信号发生器的一个相位信号输出节点。 NMOS 管 MN1 的漏极与 PMOS管 MP1的源极之间的节点耦接至 PMOS管 MP2的栅极,该节点作为根据 实施例的四相时钟信号发生器的另一相位信号输出节点。 PMOS管 MP1和 MP2 的漏极连接到供电电源。
NMOS管 MN3的栅极接收反相的输入时钟信号 CLKB, NMS管 MN4的栅 极接收输入的时钟信号 CLK。NMOS管 MN3的源极与 NMOS管 MN4的源极接
地,它们的漏极分别耦接到 PMOS管 MP3的源极和 PMOS管 MP4的源极。 NMOS 管 MN4的漏极与 PMOS管 MP4的源极之间的节点通过第四延时单元 D4耦接至 PMOS管 MP3的栅极, 该节点作为根据实施例的四相时钟信号发生器的再一个 相位信号输出节点。 NMOS管 MN3的漏极与 PMOS管 MP3的源极之间的节点 通过第四延时单元 D4耦接至 PMOS管 MP4的栅极, 该节点作为根据实施例的 四相时钟信号发生器的另一相位信号输出节点。 PMOS管 MP3和 MP4的漏极连 接到供电电源。
在 NMOS管 MN1的漏极和 PMOS管 MP1的源极之间的节点输出的时钟信 号 B1经过缓冲器 BF1缓冲后, 输出时钟信号 CLK3。 在 NMOS管 MN2的漏极 和 PMOS管 MP2的源极之间的节点输出的时钟信号 A1经过缓冲器 BF2缓冲后, 输出时钟信号 CLK1。 在 NMOS管 MN3的漏极和 PMOS管 MP3的源极之间的 节点输出的时钟信号 B2经过缓冲器 BF3缓冲后,输出时钟信号 CLK2。在 NMOS 管 MN4的漏极和 PMOS管 MP4的源极之间的节点输出的时钟信号 A2经过缓冲 器 BF4缓冲后, 输出时钟信号 CLK4。
本领域的技术人员应该意识到,上述实施例中的不同沟道类型的 MOS管并 不是要限定性的。相反,本领域的普通技术人员可以对其做出不同的变化。例如, 交叉耦合结构中的上部两个 MOS管的沟道类型可以为 N型,同时下部两个 MOS 管的沟道类型可以为 P型。
另夕卜, 在上述实施例中, NMOS管 MN1禾 B MN2的源极接地, PMOS管 MP1和 MP2的漏极接供电电源。本领域的技术人员应该意识到这仅仅是实施例, 在不同的应用情况下, 可以根据对电压 /电流或者散热等方面的要求来调整交叉 耦合结构的电源配置。
根据本技术的另一实施例, 上述的延时单元 D1~D4的每一个的延时量都是 可调的。例如, 延时单元 D1~D2的延时量基本上相等, 延时单元 D3~D4的延时 量基本上相等。图 2示出了根据本技术的实施例的多相位时钟信号发生器中的延 时单元的电路结构示意图。
如图 2所示的延时单元包括两个串联连接的反相器 NT1、 NT2和一个电容 器。。 电容器 C的一端耦接至反相器之间的节点, 另一端接地。根据本技术的另 一实施例,本领域的技术人员可以设置更多数目的反相器来实现延时或者采用其 他的方式来进行延时, 例如采用延时线。
根据本技术的一个实施例,上述延时单元 D1和 D2中的电容器 C的电容是 可调的。 例如, 该电容器 C是可调电容器。
图 3示出了根据本技术的实施例的多相位时钟信号发生器输出的各相信号 的相对时序关系示意图。
如图 3所示, 输入时钟信号 CLK和 CLKB是一对相位相反的时钟信号。 CLKd和 CLKBd是 CLK和 CLKB经过延时单元 D1和 D2后产生的信号。 CLK1、 CLK2、 CLK3和 CLK4是根据如图 1所示的四相时钟信号发生电路输出的时钟 信号分别经过缓冲器 BF2、 BF3、 BF1和 BF4缓冲后输出的各相时钟信号。 在 tl 时亥 I」, 输入时钟信号 CLK的下降沿到来。 在 t2时刻, PMOS管 MP4将信号 A2 变为高电平, 同时时钟信号 CLK4变为低电平。 在 t3时刻, 时钟信号 CLKd的 下降沿到来, 并通过 MN1管将时钟信号 B1下拉为低电平, 同时时钟信号 CLK3 变为低电平。 在 t4时刻, 时钟信号 B1通过交叉耦合的 PMOS管 MP1和 MP2 将时钟信号 A1上拉为高电平, 同时时钟信号 CLK1变为高电平。在 t5时亥 I」, 时 钟信号 A2通过交叉耦合的 PMOS管 MP3和 MP4将时钟信号 B2上拉为高电平, 同时时钟信号 CLK2变为高电平。
在 t6时亥 I」, 输入时钟信号 CLK的上升沿到来。 在 t7时亥 lj, NMOS管 MN3 管将时钟信号 B2下拉为低电平, 同时时钟信号 CLK2变为低电平。 在 t8时刻, 时钟信号 CLKBd的下降沿到来, 并通过 NMOS管 MN2将时钟信号 A1下拉为 低电平, 同时时钟信号 CLK1变为低电平。在 t9时刻, 时钟信号 A1通过交叉耦 合的 PMOS管 MP1和 MP2将时钟信号 B1上拉为高电平, 同时时钟信号 CLK3 变为高电平。 在 tlO时刻, 时钟信号 B2通过交叉耦合的 PMOS管 MP3和 MP4 将时钟信号 A2上拉为高电平, 同时时钟信号 CLK4变为高电平。
以上描述的是四相时钟信号发生电路, 本领域的技术人员也可以利用其中 的两相结构产生两相时钟信号。图 4示出了根据本技术的另一实施例的双相位时 钟信号发生器的电路结构示意图。如图 4所示,根据本实施例的双相位时钟信号 发生器采用了图 1所示的四相时钟信号发生器的电路模块 MD1和相应的缓冲器 BF1和 BF2。根据本实施例的双相时钟信号发生器产生时钟信号 CLK3和 CLK1。
此外, 图 5示出了根据本技术的又一实施例的双相位时钟信号发生器的电 路结构示意图。图 5所示的双相位时钟信号发生器采用了图 1所示的四相时钟信 号发生器的电路模块 MD2和相应的缓冲器 BF3和 BF4。根据本实施例的双相时
钟信号发生器产生时钟信号 CLK2和 CLK4。
虽然以上描述的是双相时钟信号和四相时钟信号的产生, 但是本领域的普 通技术人员可以利用以上的实施例产生其他数目相位的时钟信号。例如,将输入 时钟信号通过一直通晶体管结构作为额外的时钟信号,从而产生三相或者五相时 钟信号。再如, 在图 1所示的四相时钟信号产生电路的基础上, 增加额外的双相 时钟信号产生电路并且给该额外的双向时钟信号产生电路增加额外的延时单元, 例如将图 4或者 5中的每个延时单元用两个延时单元代替。或者,对单一时钟信 号进行分频后再采用上述的时钟发生电路来产生想要数目相位的时钟信号。
虽然以上描述的是时钟产生电路接收外部的输入时钟和反相的输入时钟, 但是上述的电路也可以接收单一的外部输入时钟或者内置的时钟源并且设置一 个反相器进行反相操作,产生反相的时钟信号。 图 6示出了根据本技术的再一实 施例的四相位时钟信号发生器的电路结构示意图。
如图 6所示, 外部输入一个时钟信号 CLK, 在电路内部设置反相器 NT来 将时钟信号转换成反相的时钟信号 CLKB。 另外, 在图 6所示的电路中, 用如图 2所示的延时单元代替如图 1所示电路中的各个延时单元,但是电容器 C的值可 以按照不同的需要进行调节。
如上述工作过程描述, 本技术中各个实施例的电路结构产生的各相位的时 钟信号之间的相位关系具有严格的先后触发关系及时序约束关系,不会产生相位 的重叠, 即与集成工艺、 工作电压或工作温度相对无关。
以上对本技术的示出示例的描述, 包括摘要中所描述的, 并不希望是穷尽 的或者是对所公开的精确形式的限制。尽管出于说明性目的在此描述了本技术的 特定实施例和示例,但是在不偏离本技术的更宽的精神和范围的情况下,各种等 同修改是可以的。 实际上, 应当理解, 特定信号、 电流、 频率、 功率范围值、 时 间等被提供用于说明目的,并且其他值也可以用在根据本技术教导的其他实施例 和示例中。
Claims
1、 一种多相位时钟信号发生电路, 包括:
第一沟道类型的第一晶体管和第二晶体管;
第二沟道类型的第三晶体管和第四晶体管,其中,第一晶体管和第二晶体 管的源极接地, 第一晶体管的漏极耦接至第三晶体管的源极和第四晶体管的栅 极,第二晶体管的漏极耦接至第四晶体管的源极和第三晶体管的栅极,所述第三 晶体管和第四晶体管的漏极接供电电源;
第一延时单元,输入端接收一时钟信号,输出端耦接至第一晶体管的栅极; 第二延时单元,输入端接收所述时钟信号的反相时钟信号,输出端耦接至 第二晶体管的栅极;
第一沟道类型的第五晶体管和第六晶体管,分别接收所述反相的时钟信号 和所述时钟信号;
第二沟道类型的第七晶体管和第八晶体管,其中,第五晶体管和第六晶体 管的源极接地,第五晶体管的漏极耦接至第七晶体管的源极,第六晶体管的漏极 耦接至第八晶体管的源极, 所述第七晶体管和第八晶体管的漏极接供电电源; 第三延时单元,输入端耦接至所述第五晶体管的漏极和第七晶体管的源极 之间的节点, 输出端耦接至第八晶体管的栅极;
第四延时单元,输入端耦接至所述第六晶体管的漏极和第八晶体管的源极 之间的节点, 输出端耦接至所述第七晶体管的栅极;
其中,第二晶体管的漏极和第四晶体管的源极之间的节点输出第一时钟信 号,第五晶体管的漏极和第七晶体管的源极之间的节点输出第二时钟信号,第一 晶体管的漏极和第三晶体管的源极之间的节点输出第三时钟信号,第六晶体管的 漏极和第八晶体管的源极之间的节点输出第四时钟信号。
2、 如权利要求 1所述的电路, 其中第一延时单元、 第二延时单元、 第三延 时单元和第四延时单元的延时时间都是可调的。
3、 如权利要求 1所述的电路, 其中第一延时单元、 第二延时单元、 第三延 时单元和第四延时单元的每一个都包括: 串联连接到第一反相器和第二反相器, 以及一端连接到第一反相器和第二反相器之间的节点的电容器,电容器的另一端 接地。
4、 如权利要求 3所述的电路, 其中所述电容器是可调电容器。
5、如权利要求 1所述的电路,其中第一延时单元和第二延时单元的延时时 间基本上相等, 第三延时单元和第四延时单元的延时时间基本上相等。
6、 如权利要求 1所述的电路, 其中所述第一沟道类型是 N型, 第二沟道类 型是 P型。
7、 如权利要求 1所述的电路, 其中第一沟道类型是 P型, 第二沟道类型是
N型。
8、 如权利要求 1所述的电路, 还包括:
第一缓冲器,输入端耦接至第一晶体管的漏极和第三晶体管的源极之间的 节点, 输出端输出缓冲的第三时钟信号,
第二缓冲器,输入端耦接至第二晶体管的漏极和第四晶体管的源极之间的 节点, 输出端输出缓冲的第一时钟信号,
第三缓冲器,输入端耦接至第五晶体管的漏极和第七晶体管的源极之间的 节点, 输出端输出缓冲的第二时钟信号,
第四缓冲器,输入端耦接至第六晶体管的漏极和第八晶体管的源极之间的 节点, 输出端输出缓冲的第四时钟信号。
9、如权利要求 1所述的电路, 还包括反相器, 将所输入的时钟信号转换成 反相的时钟信号。
10、 一种多相位时钟信号发生电路, 包括:
第一沟道类型的第一晶体管和第二晶体管;
第二沟道类型的第三晶体管和第四晶体管,其中,第一晶体管和第二晶体 管的源极接地, 第一晶体管的漏极耦接至第三晶体管的源极和第四晶体管的栅 极,第二晶体管的漏极耦接至第四晶体管的源极和第三晶体管的栅极,所述第三 晶体管和第四晶体管的漏极接供电电源;
第一延时单元,输入端接收一时钟信号,输出端耦接至第一晶体管的栅极; 第二延时单元,输入端接收所述时钟信号的反相时钟信号,输出端耦接至 第二晶体管的栅极;
其中,第二晶体管的漏极和第四晶体管的源极之间的节点输出第一时钟信 号, 第一晶体管的漏极和第三晶体管的源极之间的节点输出第三时钟信号。
11、如权利要求 10所述的电路,其中第一延时单元和第二延时单元的每一 个都包括: 串联连接到第一反相器和第二反相器, 以及一端连接到第一反相器和 第二反相器之间的节点的电容器, 电容器的另一端接地。
12、 如权利要求 11所述的电路, 其中所述电容器是可调电容器。
13、 一种多相位时钟信号发生电路, 包括:
第一沟道类型的第一晶体管和第二晶体管,分别接收一时钟信号和所述时 钟信号的反相时钟信号;
第二沟道类型的第三晶体管和第四晶体管,其中,第一晶体管和第二晶体 管的源极接地,第一晶体管的漏极耦接至第三晶体管的源极,第二晶体管的漏极 耦接至第四晶体管的源极, 所述第三晶体管和第四晶体管的漏极接供电电源; 第一延时单元,输入端耦接至所述第一晶体管的漏极和第三晶体管的源极 之间的节点, 输出端耦接至第四晶体管的栅极;
第二延时单元,输入端耦接至所述第二晶体管的漏极和第四晶体管的源极 之间的节点, 输出端耦接至所述第三晶体管的栅极;
其中,第一晶体管的漏极和第三晶体管的源极之间的节点输出第一时钟信 号, 第二晶体管的漏极和第四晶体管的源极之间的节点输出第二时钟信号。
14、如权利要求 13所述的电路,其中第一延时单元和第二延时单元的每一 个都包括: 串联连接到第一反相器和第二反相器, 以及一端连接到第一反相器和 第二反相器之间的节点的电容器, 电容器的另一端接地。
15、 如权利要求 14所述的电路, 其中所述电容器是可调电容器。
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US6052010A (en) * | 1997-10-24 | 2000-04-18 | Cypress Semiconductor Corp. | Circuit, apparatus and method for generating signals phase-separated by ninety degrees |
JP2006014352A (ja) * | 2005-07-08 | 2006-01-12 | Renesas Technology Corp | 周波数可変発振回路並びにそれを用いた位相同期回路及びクロック同期回路 |
CN101572546A (zh) * | 2009-06-09 | 2009-11-04 | 中国人民解放军国防科学技术大学 | 用于单粒子瞬变(set)加固的差分压控振荡器(vco)电路结构 |
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