WO2013035189A1 - Solid-state image pickup device - Google Patents

Solid-state image pickup device Download PDF

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Publication number
WO2013035189A1
WO2013035189A1 PCT/JP2011/070534 JP2011070534W WO2013035189A1 WO 2013035189 A1 WO2013035189 A1 WO 2013035189A1 JP 2011070534 W JP2011070534 W JP 2011070534W WO 2013035189 A1 WO2013035189 A1 WO 2013035189A1
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Prior art keywords
island
conductor layer
region
semiconductor
layer
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PCT/JP2011/070534
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French (fr)
Japanese (ja)
Inventor
舛岡　富士雄
原田　望
Original Assignee
ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
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Application filed by ユニサンティス エレクトロニクス シンガポール プライベート リミテッド filed Critical ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
Priority to KR1020137005981A priority Critical patent/KR20130061723A/en
Priority to CN2011800431859A priority patent/CN103119719A/en
Priority to JP2013511423A priority patent/JP5281215B1/en
Priority to PCT/JP2011/070534 priority patent/WO2013035189A1/en
Priority to TW101131985A priority patent/TW201312736A/en
Priority to US13/606,823 priority patent/US8564034B2/en
Publication of WO2013035189A1 publication Critical patent/WO2013035189A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures

Definitions

  • the present invention relates to a solid-state imaging device including an SGT (Surround Gate Transistor) in which a channel region is formed in a semiconductor having an island-shaped semiconductor structure, and to a solid-state imaging device having a pixel and a drive output circuit.
  • SGT Square Gate Transistor
  • CMOS solid-state imaging devices are widely used for video cameras, still cameras, and the like. These solid-state imaging devices are composed of a pixel and a drive output circuit connected to the pixel. Further, there is a constant demand for performance improvements such as higher pixel density, higher resolution, lower color mixing in color imaging, and higher sensitivity in solid-state imaging devices. On the other hand, technological innovations such as higher pixel density have been performed in order to achieve higher resolution of solid-state imaging devices.
  • FIG. 8A to 8D show a conventional solid-state imaging device.
  • FIG. 8A shows a cross-sectional structure diagram of a solid-state imaging device in which one pixel is configured in one island-like semiconductor 100 according to the conventional example (see, for example, Patent Document 1).
  • N + region a signal line N + region 102
  • N + region is a semiconductor region containing a lot of donor impurities on a substrate 101. .
  • a P region 103 (hereinafter, a semiconductor region containing an acceptor impurity is referred to as a “P region”) is formed on the signal line N + region 102, and an insulating layer 104 is formed on the outer periphery of the P region 103.
  • a gate conductor layer 105 is formed with the insulating layer 104 interposed therebetween.
  • An N region (hereinafter, a semiconductor region containing donor impurities is referred to as an “N region”) 106 is formed on the outer peripheral portion of the P region 103 in the upper portion of the gate conductor layer 105.
  • a P + region (hereinafter, a semiconductor region containing a lot of acceptor impurities is referred to as a “P + region”) 107 is formed on the island-shaped semiconductor 100.
  • the P + region 107 is connected to the pixel selection line conductor layer 108.
  • the insulating layers 104 described above are connected to each other so as to surround the outer periphery of the island-shaped semiconductor 100.
  • the gate conductor layers 105 are connected to each other so as to surround the outer periphery of the island-shaped semiconductor 100.
  • incident light is irradiated from the P + region 107 side on the upper surface of the island-shaped semiconductor 100.
  • a photodiode region including a P region 103 and an N region 106 is formed in the island-like semiconductor 100.
  • signal charges here, free electrons
  • This signal charge is accumulated in the N region 106 of the photodiode region.
  • a junction transistor is configured with the N region 106 as a gate, the P + region 107 as a source, and the P region 103 near the signal line N + region 102 as a drain.
  • the drain-source current (output signal) of the junction transistor changes corresponding to the amount of signal charge accumulated in the N region 106, and is extracted from the signal line N + region 102 and read out.
  • the N region 106 of the photodiode region is the source
  • the gate conductor layer 105 is the reset gate
  • the signal line N + region 102 is the drain
  • the P between the N region 106 and the signal line N + region 102 is the P between the N region 106 and the signal line N + region 102.
  • a reset MOS transistor using the region 103 as a channel is formed (hereinafter, this gate conductor layer is referred to as “reset gate conductor layer”).
  • the signal charge accumulated in the N region 106 is removed to the signal line N + region 102 by applying a plus-on voltage to the reset gate conductor layer 105 of the reset MOS transistor.
  • the imaging operation of this solid-state imaging device includes the following operations. That is, in a state where the ground voltage (0 V) is applied to the signal line N + region 102, the reset gate conductor layer 105, and the P + region 107, the photoelectric conversion region (photographing region) is irradiated by irradiation of light incident from the upper surface of the island-shaped semiconductor 100.
  • FIG. 8B is a schematic diagram of a solid-state imaging device having a drive output circuit around a pixel region in which island-shaped semiconductors P11 to P33 (corresponding to the island-shaped semiconductor 100 of FIG. 8A) constituting pixels are arranged two-dimensionally. A plan view is shown (see, for example, Patent Document 2). As shown in FIG. 8B, island-like semiconductors P11 to P33 constituting pixels are formed on the signal line N + regions 102a, 102b, and 102c (corresponding to 102 in FIG. 8A). Pixel selection line conductor layers 108a, 108b, and 108c (corresponding to 108 in FIG.
  • the reset gate conductor layers 105a, 105b, and 105c are connected to each horizontal column of the island-shaped semiconductors P11 to P33 constituting the pixel, and the pixel region It is connected to a reset line vertical scanning circuit 112 provided in the periphery.
  • This reset line vertical scanning circuit 112 includes CMOS inverter circuits 113a, 113b, 113c made of SGT connected to the respective reset gate conductor layers 105a, 105b, 105c, and a shift register 114 connected to the CMOS inverter circuits 113a, 113b, 113c.
  • the CMOS inverter circuits 113a, 113b, and 113c are configured using, for example, two P-channel SGTs and one N-channel SGT.
  • CMOS inverter circuit 113a, 113b the low-level voltage to the input terminal of the shift register 114 of 113c is applied, the reset-on voltage V RH from the output terminal is reset gate conductor layer 105a, 105b, while being applied to 105c , when the high level voltage is applied, the reset-off voltage V RL is reset gate conductor layer 105a, 105b, is applied to 105c from the output terminal.
  • the lower part of each signal line N + region 102a, 102b, 102c is connected to the switches SGT 115a, 115b, 115c, and the gate of each switch SGT 115a, 115b, 115c is connected to the signal line horizontal scanning circuit 116.
  • SGT Short Gate Transistor
  • SGT refers to a transistor having a structure in which a gate conductor layer is formed on the outer periphery of a silicon pillar via a gate insulating layer.
  • the signal line N + regions 102a, 102b, and 102c are applied with an off voltage from the signal line horizontal scanning circuit 116 to the gates of the switches SGTs 115a, 115b, and 115c, and the switch circuits 118a, 118b, and 118c by becoming the ground voltage side, condition that the ground voltage, the reset gate conductor layer 105a, 105b, a state in which the reset-off voltage V RL is applied to 105c, the pixel selection line conductor layers 108a, 108b, a ground voltage to 108c In a state where is applied.
  • a reset / off voltage VRL is applied to the reset gate conductor layers 105a, 105b, and 105c, a high-level voltage is applied to the pixel selection line conductor layers 108a, 108b, and 108c of the pixel to be read, and reading is performed.
  • An ON voltage is applied to the gates of the switches SGT 115a, 115b, and 115c connected to the pixel signal line N + regions 102a, 102b, and 102c, the output terminals of the switch circuits 118a, 118b, and 118c are floating, and the input terminal of the output circuit 117 is low.
  • the output circuit 117 takes in the source / drain current of the junction transistor of the pixel to be read out.
  • the signal charge removal operation the pixel-like semiconductors P11 to P11 for removing the accumulated signal charge are removed in a state where all the pixel selection line conductor layers 108a, 108b, and 108c are at the ground voltage and all the switches SGT115a, 115b, and 115c are off.
  • reset gate conductor layer 105a connected to the P33, 105b, reset-on voltage is applied to 105c, the switch circuits 118a, 118b, an output terminal of 118c is performed by going reset voltage V RD.
  • FIG. 8C shows a schematic plan view of a region A surrounded by a two-dot chain line in FIG. 8B.
  • the island-shaped semiconductor P11 constituting the pixel is formed on the signal line N + region 102a
  • the island-shaped semiconductor 119a constituting the N-channel SGT of the CMOS inverter circuit 113a is formed on the first semiconductor layer 120a
  • the P-channel SGT Are formed on the second semiconductor layer 120b.
  • a P well region 121a is formed above the first semiconductor layer 120a so as to be connected to a lower portion of the island-shaped semiconductor 119a constituting the N channel SGT (overlapping in the drawing).
  • An N well region 121b is formed above the second semiconductor layer 120b so as to be connected to the lower portion of the island-shaped semiconductors 119b and 119c constituting the P channel SGT (overlapping in the drawing).
  • a lower portion of the island-shaped semiconductor 119a constituting the N channel SGT and an N + region 122a connected to the lower portion are formed.
  • the N well region 121b lower portions of the island-shaped semiconductors 119b and 119c constituting the P channel SGT and a P + region 122b connected thereto are formed.
  • Drain N + region 123a of the N-channel SGT is formed on top of the island-like semiconductor 119a for N-channel, the drain N + region 123a via a contact hole 124a, the reset-off voltage V RL is applied It is connected to the first metal wiring layer 125a (shown with a one-dot chain line).
  • the drain P + regions 123b and 123c of the P channel SGT are formed on the island-shaped semiconductors 119b and 119c for the P channel, and the drain P + regions 123b and 123c are reset via the contact holes 124b and 124c. It is connected to the first-layer metal wiring layer 125b (denoted by a one-dot chain line) to which the on-voltage VRH is applied.
  • N-channel SGT and P-channel SGT gate conductor layer 126 are formed so as to be connected, and first-layer metal wiring layer 125c (denoted by an alternate long and short dash line) in which this gate conductor layer 126 is connected to shift register circuit 114 through contact hole 127a It is connected to the.
  • the reset gate conductor layer 105a of the island-shaped semiconductor P11 and the drain P + region 122b of the P-channel SGT constituting the pixel are first-layer metal wiring layers 125e (shown by alternate long and short dash lines) through contact holes 127e and 127f. It is connected.
  • the source P + region 122b of the P channel SGT and the drain N + region 122a of the N channel SGT are connected to each other by a first layer metal wiring layer 125b (shown by a one-dot chain line) via contact holes 127b and 127d. ing.
  • the P well region 121a is connected to a second metal wiring layer 128a (shown by a dotted line) located above the first metal wiring layers 125a, 125b, 125c, 125d, and 125e through a contact hole 127c. Yes.
  • the N well region 121b is connected to a second metal wiring layer 128b (shown by a dotted line) located above the first metal wiring layers 125a, 125b, 125c, 125d, and 125e through a contact hole 127e.
  • a second metal wiring layer 128a shown by a dotted line
  • FIG. 8D shows a cross-sectional structure diagram taken along the line BB ′ of FIG. 8C.
  • the cross-sectional structure of the island-shaped semiconductor P11 constituting the pixel is the same as that shown in FIG. 8A.
  • a pixel signal line N + region 102a, a first semiconductor layer 120a, and a second semiconductor layer 120b are formed on a substrate 100 (for example, a SiO 2 layer).
  • the island-shaped semiconductor P11 that forms the pixel is formed on the signal line N + region 102a, and the island-shaped semiconductor 119a that forms the N-channel SGT is formed on the first semiconductor layer 120a, and the island-shaped semiconductor that forms the P-channel SGT Semiconductors 119b and 119c are formed on the second semiconductor layer 120b.
  • a P well region 121a is formed above the first semiconductor layer 120a, and an N well region 121b is formed above the second semiconductor layer 120b.
  • a source N + region 122a is formed above the P-well region 121a and below the island-shaped semiconductor 119a constituting the N-channel SGT.
  • a source P + region 122b is formed above the N well region 121b and below the island-shaped semiconductors 119b and 119c constituting the P channel SGT.
  • a drain N + region 123a is formed on the island-shaped semiconductor 119a constituting the N channel SGT. Then, drain P + regions 123b and 123c are formed above the island-shaped semiconductors 119b and 119c constituting the P channel SGT.
  • the channel of the N-channel SGT is the P region 131a, and the source / drain of the island-shaped semiconductor constituting the P-channel SGT Between the P + regions 122b and 123b, 123c, the channels of the P channel SGT are the N regions 131b, 131c.
  • An N-channel SGT gate insulating layer 129a is formed on the outer periphery of the island-shaped semiconductor 119a constituting the N-channel SGT, and an insulating layer 132a is formed on the outer periphery of the first semiconductor layer 120a so as to be connected to the N-channel SGT gate insulating layer 129a. Is formed.
  • P-channel SGT gate insulating layers 129b and 129c are formed on the outer peripheral portions of the island-shaped semiconductors 119a and 119c constituting the P-channel SGT, and the second connected to the gate insulating layers 129b and 129c constituting the P-channel SGT.
  • An insulating layer 132b is formed on the outer periphery of the semiconductor layer 120b.
  • the reset gate conductor layer 105a of the reset MOS transistor connected to the outer periphery of the island-shaped semiconductor P11 constituting the pixel is connected to the first-layer metal wiring layer 125e through the contact hole 127f, and this first-layer metal wiring layer 125e is connected to the source P + region 122b connected to the lower part of the island-shaped semiconductors 119b and 119c constituting the P-channel SGT through the contact hole 127b.
  • the N-channel SGT and the P-channel SGT gate conductor layer 126 are formed between the island-shaped semiconductor 119a constituting the N-channel SGT and the island-shaped semiconductors 119b and 119c constituting the P-channel SGT, and between the gate insulating layers 129b and 129c.
  • the first metal wiring layer 125c is connected to the outer periphery and connected to the shift register circuit through the contact hole 127a.
  • the drain N + region 123a is connected to the first metal wiring layer 125a to which the reset / off voltage VRL is applied via the contact hole 124a.
  • the drain P + regions 123b and 123c of the P channel SGT are connected to the first metal wiring layer 125b to which the reset-on voltage VRH is applied via the contact holes 124b and 124c.
  • the first interlayer insulating layer 130a, the second interlayer insulating layer 130b, the third interlayer insulating layer 130c, the fourth interlayer insulating layer 130d, and the fifth interlayer insulating layer 130e are formed between the semiconductor P11 and on the substrate 100. Is formed.
  • the pixel reset gate conductor layer 105a is wired on the first interlayer insulating layer 130a, the P-channel / N-channel SGT gate conductor layer 126 is wired on the second interlayer insulating layer 130b, and the third interlayer insulating layer 130d.
  • the pixel selection line conductor layer 108a is wired thereon, the first metal wiring layers 125a, 125b, 125c, 125e are formed on the fourth interlayer insulating layer 130d, and the P-well is formed on the fifth interlayer insulating layer 130e.
  • a second metal wiring layer 128a connected to region 121a and a second metal wiring layer 128b connected to N well region 121b are formed.
  • the reset gate conductor layer 105a of the reset MOS transistor in the island-shaped semiconductor P11 constituting the pixel is at the bottom of the island-shaped semiconductor P11 constituting the pixel, whereas the CMOS inverter
  • the SGT gate conductor layer 126 of the circuit 113a is at the bottom of the island-shaped semiconductors 119a, 119b, and 119c constituting the SGT on the first and second semiconductor layers 120a and 120b.
  • the photodiode region of the island-shaped semiconductor P11 constituting the pixel has a height of 2.5 to 3 ⁇ m in order to efficiently absorb light incident from the upper surface of the island-shaped semiconductor P11 constituting the pixel. Necessary (see Non-Patent Document 1).
  • the height of the reset gate conductor layer 105a and the SGT gate conductor layer 126 may be about 0.1 ⁇ m or less.
  • semiconductor layers 120a and 120b having the same thickness as the sum of the signal line N + region 102a and the island-shaped semiconductor P11 constituting the pixel are formed in the drive output circuit region including the CMOS inverter circuit 113a. Thereafter, island-shaped semiconductors P11 and 119b that form SGT and island-shaped semiconductors P11 that form pixels are formed.
  • the height difference between the reset gate conductor layer 105a of the island-shaped semiconductor P11 constituting the pixel and the height direction of the SGT gate conductor layer 126 inevitably differs in the height of the island-shaped semiconductor P11 constituting the pixel. Occurs. Since the reset gate conductor layer 105a is formed on the first interlayer insulating layer 130a and the SGT gate conductor layer 126 is formed on the second interlayer insulating layer 130b, the reset gate conductor layer 105a and the SGT gate are formed. The conductor layer 126 must be formed separately. Similarly, the signal line N + region 102a and the source N + region 122a of the N channel SGT must be formed separately.
  • this solid-state imaging device requires a step of forming an SGT that constitutes the drive output circuit in addition to the step of forming the structure of the island-shaped semiconductor P11 that constitutes the pixel. This leads to a decrease in yield and an increase in cost of the solid-state imaging device.
  • a P well region 121a and an N well region 121b are formed above the first and second semiconductor layers 120a and 120b. Due to the presence of the P well region 121a and the N well region 121b, for example, current generated by leakage light incident on the first and second semiconductor layers 120a and 120b causes the source N + region 122a of the N channel SGT and the source of the P channel SGT. This prevents the CMOS inverter circuit 113a from malfunctioning by preventing it from flowing into the P + region 122b.
  • the CMOS inverter circuit 113a can be made more stable. It can be operated.
  • the N channel / P channel SGT is a drive output circuit other than the CMOS inverter circuit 113a, which is a shift register 114 of the reset line vertical scanning circuit 112, a pixel selection scanning circuit 110, a horizontal scanning circuit 116, an output circuit 117, a switch SGT 115a, 115b and 115c and switch circuits 118a, 118b, and 118c are also formed, resulting in a problem that leads to a decrease in yield and an increase in cost of the solid-state imaging device described above.
  • the reset gate conductor layer 105a of the reset MOS transistor in the island-shaped semiconductor P11 constituting the pixel is at the bottom of the island-shaped semiconductor P11 constituting the pixel, whereas in the drive output circuit
  • the SGT gate conductor layer 126 is located on the island-shaped semiconductors 119a and 119b constituting the SGT on the first and second semiconductor layers 120a and 120b, which are substantially at the same height as the upper surface of the island-shaped semiconductor P11 constituting the pixel.
  • the difference in height between the reset gate conductor layer 105a of the reset MOS transistor and the SGT gate conductor layer 126 in the drive output circuit is as large as 2.5 to 3 ⁇ m necessary for the photodiode region of the island-shaped semiconductor P11 constituting the pixel.
  • the reset gate conductor layer 105a of the reset MOS transistor and the SGT gate conductor layer 126 in the drive output circuit are formed on different interlayer insulating layers 130a and 130b. Therefore, inevitably, the reset gate conductor layer 105a of the reset MOS transistor and the SGT gate conductor layer 126 in the drive output circuit must be formed separately. Similarly, the signal line N + region 102a and the source N + region 122a of the N channel SGT must be formed separately.
  • the step of forming the SGT in the drive output circuit is required.
  • a solid-state imaging device in which the island-shaped semiconductor P11 that constitutes the pixel and the SGT that constitutes the drive output circuit are formed on the same substrate 100, a solid-state imaging device that can suppress a decrease in yield and an increase in cost is desired. It is done.
  • the present invention has been made in view of the above circumstances, and an object thereof is to realize a solid-state imaging device capable of suppressing a decrease in yield and an increase in cost.
  • the solid-state imaging device of the present invention includes: In a solid-state imaging device having two-dimensionally arranged pixels, and a drive output circuit that drives the pixels and reads signals from the pixels,
  • the pixel has a first island-shaped semiconductor formed on a substrate,
  • the drive output circuit has at least one second island-shaped semiconductor formed on the substrate to have the same height as the first island-shaped semiconductor,
  • the first island-shaped semiconductor is A first semiconductor region formed at the bottom of the first island-shaped semiconductor;
  • a second semiconductor region formed on the first semiconductor region and made of a semiconductor having a conductivity type opposite to that of the first semiconductor region or an intrinsic type;
  • a first gate insulating layer formed at a lower portion and an outer periphery of the second semiconductor region;
  • a first gate conductor layer formed so as to surround the first gate insulating layer;
  • a third semiconductor region formed on the outer periphery of the second semiconductor region adjacent to the first gate conductor layer and made of a semiconductor having the same conductivity type as the first semiconductor region;
  • the height of the first gate conductor layer and the second gate conductor layer may be the same.
  • a third gate conductor layer formed so as to surround a part of the second island-shaped semiconductors among the plurality of second island-shaped semiconductors; Among the two island-shaped semiconductors, the third gate conductor layer is formed so as to surround the second island-shaped semiconductor different from the second island-shaped semiconductor surrounded by the third gate conductor layer, And a fourth gate conductor layer made of a different material.
  • the heights of the third gate conductor layer and the fourth gate conductor layer may be different from each other.
  • the height of the third gate conductor layer and the fourth gate conductor layer may be the same.
  • the seventh semiconductor region is formed on the sixth semiconductor region, and a conductor layer made of a silicide layer or a metal layer is formed on the seventh semiconductor region. It can be said.
  • a metal layer may be provided so as to surround the sixth semiconductor region.
  • a conductor layer formed inside the third island-shaped semiconductor is connected to at least one of the first semiconductor region and the fifth semiconductor region at a lower portion of the third island-shaped semiconductor. It can be said that.
  • FIG. 3 is a cross-sectional structure diagram for explaining a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. It is a cross-section figure for demonstrating the manufacturing method of the pixel and CMOS inverter circuit of the solid-state imaging device which concern on the 2nd Embodiment of this invention.
  • FIG. 1 It is a cross-sectional structure figure of the pixel and CMOS inverter circuit of the solid-state imaging device concerning a 2nd embodiment. It is a cross-section figure for demonstrating the manufacturing method of the pixel and CMOS inverter circuit of the solid-state imaging device which concern on the 3rd Embodiment of this invention. It is sectional structure drawing for demonstrating the manufacturing method of the pixel and CMOS inverter circuit of the solid-state imaging device which concern on 3rd Embodiment. It is sectional structure drawing for demonstrating the manufacturing method of the pixel and CMOS inverter circuit of the solid-state imaging device which concern on 3rd Embodiment. FIG.
  • FIG. 6 is a cross-sectional structure diagram of a pixel and a CMOS inverter circuit of a solid-state imaging device according to a third embodiment. It is a cross-section figure of a pixel and CMOS inverter circuit of a solid imaging device concerning a 4th embodiment of the present invention. It is a cross-sectional structure figure of the pixel and CMOS inverter circuit of the solid-state imaging device which concern on the 5th Embodiment of this invention. It is a cross-section figure for demonstrating the manufacturing method of the pixel of the solid-state imaging device which concerns on the 6th Embodiment of this invention, and a CMOS inverter circuit.
  • FIG. 1A shows a schematic circuit diagram of a region A surrounded by a two-dot chain line in the schematic plan view of the solid-state imaging device shown in FIG. 8B.
  • the reset gate conductor layer 105 a is connected to a CMOS inverter circuit 113 a composed of two P-channel SGTs 4 aa and 4 bb and one N-channel SGT 4 cc.
  • the CMOS inverter circuit 113 a is connected to the shift register 114.
  • the reset-on voltage V RH is applied to the reset gate conductor layer 105a from the output terminal, the input terminal of the CMOS inverter circuit 113a
  • the reset-off voltage VRL is applied from the output terminal to the reset gate conductor layer 105a.
  • FIG. 1B shows a schematic plan view of FIG. 1A.
  • the signal line N + region 102a in the pixel region, the source plate N + region 3a of the N channel SGT4cc in the CMOS inverter circuit 113a region, and the source plate of the P channels SGT4aa and 4bb A shaped P + region 3b is formed.
  • an island-shaped semiconductor P11 that constitutes a pixel is formed on the signal line N + region 102a, and an island-like semiconductor 4a that constitutes an N-channel SGT4cc is formed on the source plate-like N + region 3a, and the P-channel SGT4aa, Island-like semiconductors 4b and 4c constituting P-channel SGTs 4aa and 4bb are formed on the 4bb source plate-like P + region 3b.
  • a continuous gate conductor layer 7a is formed so as to surround the island-shaped semiconductor constituting the N-channel SGT4cc and the island-shaped semiconductor constituting the P-channel SGT4aa, 4bb, and surrounds the island-shaped semiconductor P11 constituting the pixel in the horizontal direction.
  • a connected reset gate conductor layer 105a is formed.
  • a contact hole 9a is formed on the gate conductor layer 7a, and the gate conductor layer 7a is connected to the first metal wiring layer 12a (one-dot chain line) connected to the shift register 114 via the contact hole 9a.
  • a contact hole 9b is formed on the reset gate conductor layer 105a, and the reset gate conductor layer 105a is connected to the first metal wiring layer 12e (one-dot chain line) through the contact hole 9b.
  • a contact hole 9c is formed on the boundary between the source plate N + region 3a of the N channel SGT4cc and the source plate P + region 3b of the P channels SGT4aa and 4bb, and the N channel SGT4cc of the N channel SGT4cc is formed via the contact hole 9c.
  • the source plate N + region 3a and the source plate P + regions 3b of the P channels SGT4aa and 4bb are connected to the first metal wiring layer 12e (one-dot chain line).
  • Drain N + region 8b of the drain N + region on 8a at the top of the island-like semiconductor 4a constituting the N-channel SGT4cc to form a contact hole 11a, the top of the island-like semiconductor 4b constituting P-channel SGT4aa, the 4bb, Contact holes 11b and 11c are formed on 8c.
  • the drain N + region 8a is connected to the first metal wiring layer 12b (one-dot chain line) to which the reset low level voltage VRL is applied via the contact hole 11a, and the drain P + regions 8b and 8c are in contact with each other.
  • the holes are connected to the first metal wiring layers 12c and 12d (one-dot chain lines) to which the reset high level voltage VRH is applied through the holes 11b and 11c.
  • the first metal wiring layers 12c and 12d are connected to the second metal wiring layer 14 (dotted line) to which the reset on voltage VRH is applied.
  • FIG. 1C shows a cross-sectional structure diagram along line AA ′ of FIG. 1B.
  • the cross-sectional structure of the island-shaped semiconductor P11 constituting the pixel is the same as that shown in FIG. 8D.
  • a signal line N + region 102a of a pixel, a source N + region 3a of an N channel SGT 4cc, and a source P + region 3b of P channels SGT 4aa and 4bb are formed on the substrate 1 (for example, SiO 2 layer).
  • the island-shaped semiconductor P11 constituting the pixel is formed on the signal line N + region 102a, and the island-shaped semiconductor 4a constituting the N-channel SGT4cc is formed on the source semiconductor layer N + region 3a to constitute the P-channel SGT4aa and 4bb. Insulating semiconductors 4a and 4b are formed on the source P + region 3b.
  • the source N + region 3a is connected to the lower portion of the island-shaped semiconductor 4a constituting the N-channel SGT4cc
  • the source P + region 3b is connected to the lower portion of the island-shaped semiconductors 4b and 4c constituting the P-channel SGT4aa and 4bb. .
  • the channel P region 5a of the N channel SGT4cc is connected to the source N + region 3a, the channel N regions 5b and 5c of the P channels SGT4aa and 4bb are connected to the source P + region 3b, and the signal line N + region 2 of the pixel is connected. It is connected to the channel of the reset MOS transistor and the P region which becomes the drain of the junction transistor (the channel semiconductor regions 5a, 5b and 5c, and the P region 5d region of the island-shaped semiconductor P11 constituting the pixel may be an intrinsic type. ).
  • a gate insulating layer 6a of the N-channel SGT4cc is formed on the outer periphery of the island-shaped semiconductor 4a constituting the N-channel SGT4cc connected to the source N + region 3a, and P-channel SGT4aa and 4bb connected to the source P + region 3b are formed.
  • Gate insulating layers 6b and 6c of P-channel SGTs 4aa and 4bb are formed on the outer periphery of the island-shaped semiconductors 4b and 4c.
  • a reset MOS gate insulating film 6d is formed on the outer periphery of the island-shaped semiconductor P11 constituting the pixel connected to the signal line N + region 102a of the pixel.
  • the outer periphery of the gate insulating layer 6a of the N-channel SGT4cc and the gate insulating layers 6b and 6c of the P-channel SGT4aa and 4bb is connected to the first interlayer insulating layer 14a formed on the substrate 1 and connected to the N-channel P Gate conductor layers 7a of channels SGT4aa, 4bb, 4cc are formed.
  • the reset gate conductor layer 105a of the pixel includes the outer periphery of the gate insulating film 6d of the reset MOS, and is connected to the first interlayer insulating layer 14a.
  • a drain N + region 8a is formed in the island-like semiconductor 4a constituting the N-channel SGT4cc adjacent to the upper portion of the N-channel SGT4cc gate conductor layer 7a.
  • Drain P + regions 8b and 8c are formed in the island-like semiconductors 4b and 4c constituting the channels SGT4aa and 4bb.
  • a photodiode region composed of a P region 5d and an N region 8d formed so as to surround the P region 5d is formed in the island-shaped semiconductor P11 constituting the pixel adjacent to the upper portion of the reset gate conductor layer 105a of the pixel.
  • the drain N + region 8a of the N channel SGT4cc and the drain P + regions 8b, 8c of the P channels SGT4aa, 4bb are formed so as to be connected to the top surfaces of the island-like semiconductors 4a, 4b, 4c constituting the SGT.
  • the pixel selection P + region 10 is formed on the upper surface of the island-shaped semiconductor P11 constituting the pixel.
  • the pixel selection P + region 10 is connected to a pixel selection line conductor layer 108a formed on the third interlayer insulating layer 14c on the second interlayer insulating layer 14b.
  • N-channel / P-channel SGT4aa, 4bb, 4cc gate conductor layer 7a is formed on fourth interlayer insulating layer 14d through contact hole 9a, and is connected to first-layer metal interconnection layer 12a connected to the shift register. ing.
  • the drain N + region 8a above the island-shaped semiconductor 4a constituting the N channel SGT4cc is connected to the first metal wiring layer 12b to which the reset off voltage VRL is applied via the contact hole 11a.
  • the drain P + regions 8b and 8c above the island-shaped semiconductors 4b and 4c constituting the P-channel SGT are applied to the first layer metal to which the reset-on voltage VRH is applied via the contact holes 11b and 11c.
  • the wiring layers 12c and 12d are connected.
  • the reset gate conductor layer 105a of the pixel is electrically connected to the source N + region 3a of the N channel SGT4cc and the source P + region 3b of the P channels SGT4aa and 4bb on the fourth interlayer insulating layer 14d through the contact hole 9b. Is connected to the first-layer metal wiring layer 12e.
  • the first-layer metal wiring layers 12c and 12d are formed on the fifth interlayer insulating layer 14e through the contact holes 15a and 15b, and the second-layer metal wiring to which the reset-on voltage VRH is applied. Connected to layer 16.
  • the solid-state imaging device of this embodiment has the following structural features.
  • the first feature is that a semiconductor containing donor or acceptor impurities of the source N + region 3a, the P + region 3b, and the signal line N + region 102a of the N channel / P channel SGT4aa, 4bb, 4cc directly on the substrate 1. Regions are formed and they are formed in the same layer.
  • the second feature is that an N-channel / P-channel SGT4aa, 4bb, 4cc gate conductor layer 7a and a pixel reset gate conductor layer 105a are formed on the same first interlayer insulating layer 14a, and each island-shaped It is formed on the outer periphery of the gate insulating films 6a, 6b, 6c, 6d connected to the bottoms of the semiconductors 4a, 4b, 4c, P11, and is formed in the same layer.
  • the third feature is that the SGT channel P region 5a or N regions 5b and 5c and the pixel reset MOS channel P region 5d are formed in the same layer.
  • the fourth feature is that the drain N + region 8a of the N-channel SGT4cc and the drain P + regions 8b, 8c of the P-channel SGT4aa, 4bb are arranged on the island-shaped semiconductors 4a, 4b, 4c constituting the SGT.
  • the N region 8d and the selective P + region 10 constituting the photodiode are formed in the same layer.
  • the present embodiment has the following advantages.
  • the first advantage is that in the solid-state imaging device of the conventional example (FIG. 8D), the island-shaped semiconductors 119a, 119b, and 119c constituting the SGT and the island-shaped semiconductor P11 constituting the pixel are individually formed.
  • the island-shaped semiconductors 4a, 4b, and 4c constituting the SGT and the island-shaped semiconductor P11 constituting the pixel can be formed in the same process.
  • the second advantage is that the N + region 3a of the N channel SGT4cc and the source P + region 3b of the P channels SGT4aa and 4bb are formed directly on the substrate 1, so that the conventional solid state imaging device (FIG. 8D) is used.
  • a third advantage is that the N + region 3a of the N-channel SGT4cc formed individually in the conventional solid-state imaging device (see FIG. 8D) can be formed in the same process as the pixel signal line N + region 102a. It is.
  • the fourth advantage is that in the conventional solid-state imaging device (see FIG. 8D), the N-channel / P-channel SGT4aa, 4bb, 4cc gate conductor layer 7a and the pixel reset gate conductor layer 105a are formed in the same process. This is a possible point.
  • a fifth advantage is that contact holes 9a and 9b formed on the gate conductor layers 7a and 105a, which are individually formed in the solid-state imaging device of the conventional example (see FIG. 8D), can be formed in the same process.
  • the solid-state imaging device of the present invention can be manufactured with a smaller number of processes than the conventional solid-state imaging device. Thereby, cost reduction of a solid-state imaging device is implement
  • a manufacturing method for forming the solid-state imaging device according to the first embodiment of the present invention will be described with reference to FIGS. 2A to 2Q, and AA ′ in the plan view of the pixel portion and CMOS inverter circuit portion in FIG. 1B.
  • the manufacturing method which forms the cross-sectional structure along a line is shown.
  • a single crystal semiconductor silicon layer (hereinafter simply referred to as “Si layer”) 22 is formed on a SiO 2 substrate 21.
  • the SiO 2 layer 23 formed by oxidizing the Si layer 22 surface, and the silicon nitride layer on the SiO 2 layer 23 (which is hereafter written as SiN layer) 24, CVD (Chemical Vapor Deposition ) method using SiO 2 layer 25 Form.
  • the SiO 2 layer 25 by the CVD method serves as an etching mask in etching the Si layer 22 by the RIE (Reactive Ion Etching) method.
  • the SiN layer 24 serves as a stopper layer in planarizing a CMP (Chemical Mechanical Polishing) SiO 2 film in a later process.
  • the SiO 2 layer 23 on the Si layer 22 serves as a buffer layer for stress relaxation between the Si layer 22 and the SiN layer 24.
  • the silicon layer constituting the N channel SGT is etched by etching the Si layer 22 of the N channel SGT part, the P channel SGT part, and the pixel part using the SiO 2 layer 25 as an etching mask.
  • Si pillar will be referred to as “Si pillar”.
  • 26a, Si pillars 26b and 26c constituting the P channel SGT, and Si pillar 26d constituting the pixel are formed, and a plate-like Si is formed at the bottom of the Si layer 22.
  • the layers 22a and 22b are left.
  • etching plate Si layer 22a, the Si layer 22 of 22b region to SiO 2 substrate 21 surface, then Si pillars 26a, 26b, 26c, by forming 26d form the structure of FIG. 2B.
  • SiO 2 layers 27a, 27b, 27c, and 27d are formed on the outer periphery of the Si pillars 26a, 26b, 26c, and 26d and the plate-like Si layers 225a and 22b.
  • polycrystalline Si layers 28a, 28b, 28c, and 28d are formed surrounding the SiO 2 layers 27a, 27b, 27c, and 27d of the Si pillars 26a, 26b, 26c, and 26d, and a photoresist layer is formed except for the P-channel SGT portion.
  • the polycrystalline Si layers 28a, 28b, 28c, 28d are stopper layers for preventing boron ions from being implanted into the Si pillars 26a, 26b, 26c, 26d when boron ions are implanted.
  • the photoresist layer 29 is removed, and the plate-like Si layer 22a and the pixel-like plate-like Si layer 22b in the N-channel SGT portion are formed by the same photolithography technique and donor impurity phosphorus (P) or arsenic (As) ion implantation. N + regions are formed.
  • the polycrystalline Si layers 28a, 28b, 28c, 28d are removed and heat treatment is performed, so that the Si pillars 26a, 26b, 26c, N + regions 31a, 31c, and P + regions 31b connected to the lower portion of 26d are formed.
  • a photoresist layer 32 is formed by photolithography so as to cover the Si pillars 26b and 26c constituting the P channel SGT, and ion implantation of acceptor impurities such as boron (B) is further performed. Then, P regions 33a and 33d are formed in the Si pillar 26a constituting the N channel SGT and the Si pillar 26d constituting the pixel. Thereafter, the photo resist layer 32 is removed.
  • a photoresist layer is formed by photolithography so as to cover the Si pillar 26a constituting the N channel SGT and the Si pillar 26d constituting the pixel, and arsenic (As), phosphorus (P).
  • As arsenic
  • P phosphorus
  • N regions 33b and 33c are formed in the Si pillars 26b and 26c constituting the P channel SGT by performing ion implantation of donor impurities such as the above and further removing the photo resist layer and performing heat treatment.
  • the first interlayer insulating layer 34a is formed, and the SiO 2 layers 27a, 27b, 27c, 27d are removed (at the same time, the SiO 2 layers 25a, 25b, 25c, 25d are removed).
  • the gate insulating layers 35a, 35b, 35c, and 35d made of a high dielectric constant insulating material such as SiO 2 and hafnium oxide (HfO 2 ) are formed on the outer periphery of the Si pillars 26a, 26b, 26c, and 26d.
  • polycrystalline Si, tungsten (W), cobalt (Co), platinum (Pt), silicide material by CVD (Chemical Vapor Deposition) method so as to surround the Si pillars 26a, 26b, 26c, and 26d on the interlayer insulating layer 34a Is formed on the gate region of the N channel / P channel SGT, and the photo resist layer 37a is formed on the pixel reset gate region.
  • CVD Chemical Vapor Deposition
  • the first interlayer insulating layer 34a is formed by depositing a SiO 2 film to a position higher than the Si pillars 26a, 26b, 26c, and 26d by the CVD method, and forming the Si pillars 26a, 26b, 26c, and 26d by the CMP (Chemical Mechanical Polishing) method. It is formed by polishing and flattening to a height and then performing etching by RIE (hereinafter referred to as etch back).
  • etch back etch back
  • the SiN so as to surround the plate-like N + regions 31a and 31c, the plate-like P + region 31b, and the Si pillars 26a, 26b, 26c, and 26d on the SiO 2 substrate 1.
  • a film may be deposited and the SiN film surrounding the Si pillars 26a, 26b, 26c, and 26d may be removed after the SiO 2 film is etched back.
  • the SiN film serves as a protective film for preventing the Si pillars 26a, 26b, 26c, and 26d from being etched during the etch back.
  • the conductor layer 36 is etched using the photoresist layers 37a and 37b as a mask. Thereafter, the photoresist layers 37a and 37b are removed. Subsequently, as shown in FIG. 2H, a second interlayer insulating layer 34b is formed. Similarly to the first interlayer insulating film 34a, the second interlayer insulating layer 34b is also formed by SiO 2 film deposition by the CVD method, SiO 2 film polishing by the CMP method, and etch back by the RIE method.
  • the gate conductor layers 36aa and 36bb exposed so as to surround the Si pillars 26a, 26b, 26c and 26d without being covered with the second interlayer insulating layer 34b are etched.
  • an N-channel / P-channel SGT gate conductor layer 36a and a pixel reset gate conductor layer 36b are formed.
  • the N-channel / P-channel SGT gate conductor layer 36a is formed so as to surround the outer periphery of the lower portion of the Si pillars 26a, 26b, and 26c constituting the SGT and to be connected to the first interlayer insulating layer 34a.
  • an SiN layer 38 is formed on the second interlayer insulating layer 34b, and an SiO 2 layer 39 formed by CVD is formed so as to cover the second interlayer insulating layer 34b and the Si pillar.
  • a SiN layer 40 is formed on the formed and planarized SiO 2 layer 39, and a photoresist layer 41 in which holes are formed in the Si pillars 26b and 26c constituting the P channel SGT is formed using a photolithography technique.
  • SiN layer 38 plays a role of etch quenching stopper layer of the SiO 2 layer 39
  • SiN layer 40 on the SiO 2 layer 39 serves as an etching mask layer of SiO 2 layer 39.
  • the SiN layer 40 on the Si pillars 26b and 26c constituting the P-channel SGT is etched using the photoresist layer 41 as a mask, and after removing the photoresist layer 41, an SiO 2 layer is formed using the SiN layer 40 as an etching mask. 39 is etched to the surface of the SiN layer 38 by RIE. Thereafter, the gate insulating layers 35b and 35c on the outer periphery of the Si pillars 26b and 26c are removed.
  • a SiO 2 layer 42b containing an acceptor impurity such as boron (B) is formed by a CVD method.
  • the SiO 2 layer 42b containing the acceptor impurity is first deposited up to the SiN layer 40, and then polished to the SiN layer 40 by CMP to form a flat surface.
  • the SiN layer 40 is removed, a new SiN layer 43 is deposited, and a hole is formed on the Si pillar 26a constituting the N channel SGT of the SiN layer 43 by forming a resist layer by photolithography and SiN etching. To do.
  • the SiN layer 43 as an etching mask, the SiO 2 layer 39 is etched to the surface of the SiN layer 36.
  • a SiO2 layer 42a containing donor impurities such as phosphorus (P) and arsenic (As) is formed.
  • donor impurities and acceptor impurities are diffused from the SiO 2 layers 42a and 42b formed by the CVD method in the Si pillars 26a, 26b, and 26c, and N + in the Si pillars 26a, 26b, and 26c.
  • Region 37a and P + regions 37b and 37c are formed.
  • the SiON containing donor impurities is formed on the SiN layer 38 in the Si pillar 26d region constituting the pixel.
  • a two- layer 42c is formed, and an N region 43 is formed on the outer periphery of the Si pillar 26d by heat treatment.
  • the amount of donor impurities contained in the SiO 2 layer 42c is less than that of the SiO 2 layer 42a for forming the N + region 37a.
  • the SiO 2 layers 39, 42a, 42b, and 42c are removed.
  • the surfaces of the Si pillars 26a, 26b, 26c, and 26d where the Si surface is exposed are oxidized to form SiO 2 layers 45a, 45b, 45c, and 45d.
  • the SiN layers 24a, 24b, 24c, 24d, and 38 are removed to form a third interlayer insulating layer 34c. Boron (B) using the photolithography technique and the photoresist layer formed thereby as a mask.
  • the P + region 47 is formed on the Si pillar 26d constituting the pixel by ion implantation of acceptor impurities such as.
  • Si pillars 26a, 26b, 26c, the SiO 2 layer 23a on the 26 d, 2b, 23c, and 23d, the SiO 2 layer at the top than the third interlayer insulating layer 34c is removed.
  • a pixel selection line conductor layer 48 such as aluminum (Al), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN) is formed, and a fourth interlayer insulating layer 34d is formed thereon, and a gate A contact hole 50a is formed on the conductor layer 36a, contact holes 50b, 50c and 50d are formed on the Si pillars 26a, 26b and 26c constituting the SGT, and a contact hole 50e is formed on the pixel reset gate conductor layer 36b.
  • the SGT gate conductor layer 36a and the first metal wiring layer 51a Si pillar 26a constituting the SGT, 26b, 26c of N + regions 37a, P + regions 37b, 37c and the first layer metal interconnection layers 51b, 51c, 51d and the reset gate conductor layer 36b and the first layer metal Connection to the wiring layer 51e is performed.
  • a fifth interlayer insulating layer 34e is formed, contact holes 51a and 51b are formed, and the first metal wiring layers 51c and 51d are formed through the contact holes 51a and 51b. Are connected to the second metal wiring layer 52.
  • FIG. 3E shows a cross-sectional structure of the solid-state imaging device according to the present embodiment
  • FIGS. 3A to 3D show a manufacturing method leading to this
  • 3A to 3E show a cross-sectional structure along the line AA ′ in the plan view of the pixel portion and CMOS inverter circuit portion in FIG. 1B, as in FIGS. 2A to 2Q.
  • the N-channel / P-channel SGT gate conductor layer 7a is formed by being connected with the same material, whereas in the solid-state imaging device of the present embodiment, a plurality of gates formed with different materials. It is characterized by being composed of a conductor layer.
  • the technical idea of the present invention is applied to a solid-state imaging device in which an N-channel SGT and a pixel gate conductor layer are formed of the same material and a P-channel SGT gate conductor layer is formed of different materials.
  • the gate insulating layers 35a, 35b, and 35c made of a high dielectric constant insulating material such as SiO 2 and hafnium oxide (HfO 2 ) are disposed on the outer periphery of the Si pillars 26a, 26b, 26c, and 26d. , 35d and surrounding the Si pillars 26a, 26b, 26c, 26d on the first interlayer insulating layer 34a, for example, polycrystalline Si, tungsten (W), cobalt (Co) by CVD (Chemical Vapor Deposition) method Then, a conductor layer 36 of platinum (Pt) and a silicide material is formed.
  • a high dielectric constant insulating material such as SiO 2 and hafnium oxide (HfO 2 )
  • a SiN layer 55 is deposited on the entire surface.
  • the photoresist layers 56a.. are covered by photolithography so as to cover the N channel SGT portion and the pixel portion. 56b is formed.
  • the SiN layer 55 and the conductor layer 36 are etched using the photoresist layers 56a and 56b as a mask.
  • the SiN layers 55a and 55b are formed by etching so as to be side-etched inside the regions covered with the photoresist layers 56a and 56b.
  • the photoresist layers 56a and 56b are removed.
  • an N channel SGT part conductor layer 57a covering the N channel SGT part and a pixel part conductor layer 57b covering the pixel part are formed.
  • a second conductor layer 58 is formed so as to cover the entire structure.
  • a photoresist layer 59 is formed by using a photolithography technique so as to cover the P channel SGT portion.
  • the second conductor layer 58 is etched to form a P-channel SGT portion conductor layer 58a.
  • the photoresist layer 59 is removed.
  • the SiN layers 55a and 55b here serve as etching protective films for the N-channel SGT portion conductor layer 57a and the pixel portion conductor layer 57b in the etching of the conductor layer 58.
  • the SiN layers 55a and 55b are removed.
  • N channel SGT part conductor layer 57a, P channel SGT part conductor layer 58a, and pixel part conductor layer 57b are etched using first interlayer insulating layer 34a as a mask to form N channel SGT part gate conductor layer 57aa and P channel SGT.
  • the part gate conductor layer 58bb and the pixel part reset gate conductor layer 57bb are formed.
  • the N channel SGT gate conductor layer 57aa, the P channel SGT gate conductor layer 58bb, and the pixel portion reset gate conductor layer 57bb are connected to the gate insulating layer 35a on the outer periphery of the Si pillar 26a constituting the N channel SGT and the P channel SGT.
  • 3F is the same as FIG. 2Q except that the P-channel SGT part gate conductor layer 58bb is different from the N-channel SGT part gate conductor layer 57aa and the pixel part gate conductor layer 57bb.
  • the second embodiment of the present invention has the same features as the first embodiment.
  • the P region 33aa of the Si pillar 26a constituting the N channel SGT, the Si pillar 26bb constituting the P channel SGT, the N regions 33b and 33c of 26cc, and the P region 33d of the Si pillar constituting the pixel are intrinsic types. Also good.
  • the threshold voltages of the N channel / P channel SGT and the pixel reset transistor are set according to the work functions of the gate conductor layers 57aa, 58bb, and 57bb.
  • the photolithography process for forming the P regions 33a and 33d and the N regions 33b and 33c described with reference to FIGS. 2E and 2F in the first embodiment, and the ion implantation process of acceptor impurities and donor impurities are performed. It becomes unnecessary.
  • FIG. 4D shows a cross-sectional structure of the solid-state imaging device according to the present embodiment
  • FIGS. 4A to 4C show a manufacturing method leading to FIG. 4D
  • 4A to 4D show the pixel portion of FIG. 1B and the cross-sectional structure along the line AA ′ in the plan view of the CMOS inverter circuit portion, as in FIGS. 2A to 2Q.
  • FIG. 4D shows a cross-sectional structure of the solid-state imaging device according to the present embodiment
  • FIGS. 4A to 4C show a manufacturing method leading to FIG. 4D
  • 4A to 4D show the pixel portion of FIG. 1B and the cross-sectional structure along the line AA ′ in the plan view of the CMOS inverter circuit portion, as in FIGS. 2A to 2Q.
  • the N + region 8a which is the drain of the N channel SGT and the P + region 8b which is the drain of the P channel SGT above the Si pillars 4a, 4b and 4c constituting the SGT.
  • 8c are connected to the first metal wiring layers 12b, 12c, 12d through the contact holes 11a, 11b, 11c from the upper surfaces of the Si pillars 4a, 4b, 4c.
  • the drain resistance of the N channel / P channel SGT is determined by the resistance values of the N + region 8a and the P + regions 8b and 8c. The smaller the resistance value, the better.
  • the present embodiment is characterized in that the electrical resistance value is reduced by forming the upper portion of the N + region 8a and the P + regions 8b and 8c as a silicide layer.
  • FIG. 4A the process before the SiN layer 38 in FIG. 2M is formed on the first interlayer insulating layer 34a is formed in the same process as in FIGS. 2A to 2L, and a new SiN layer 38a is formed in the first interlayer insulating layer 34a.
  • the N + region 37a and the Si pillars 26b and 26c constituting the P channel SGT are formed on the insulating layer 34a and formed on the Si pillar 26a constituting the N channel SGT through the same process as shown in FIGS. 2M and 2N.
  • P + regions 26b and 26c are formed on the upper portion, an N region 43 is formed on the outer periphery of the upper portion of the Si pillar 26d constituting the pixel, and a P + region 47 is formed on the upper surface of the Si pillar 26d constituting the pixel.
  • 26c, and 26d the cross-sectional structure in the case where the insulating layers 45a, 45b, 35c, and 45d are formed on the outer peripheral portion is shown.
  • the insulating layers 45a, 45b, 45c on the outer periphery of the Si pillars 26a, 26b, 26c constituting the N-channel / P-channel SGT are removed.
  • the entire structure is covered with, for example, tungsten (W), platinum (Pt), nickel (Ni), cobalt (Co), or a metal layer 54 containing these, and heat treatment is performed.
  • the silicide layers 55a, 55b, and 55c are formed on the Si pillars 26a, 26b, and 26c constituting the N channel / P channel SGT.
  • N + regions 56a and P + regions 56b and 56c are formed below the silicide layers 55a, 55b and 55c. It is formed. Thereafter, the metal layer 54 is removed.
  • the N + region 56a and the P + regions 56b and 56c become the drains of the N channel / P channel SGT, and the N + region 56a, the P + regions 56b and 56c, and the first metal wiring layers 51b, 51c and 51d. Is performed through silicide layers 55a, 55b, and 55c having lower electrical resistance values.
  • tungsten (W), platinum (Pt), nickel (Ni), and cobalt (N) are enclosed so as to surround the N + region 55 a, the P + region 55 b, and the P + region 55 c.
  • Co or metal layers 56a, 56b and 56c containing them.
  • the SiO 2 layer 45d formed on the outer periphery of the Si pillar 26d constituting the pixel is connected to the P + region on the upper surface of the Si pillar 26d constituting the pixel at the same time.
  • the pixel selection line metal layer 56d surrounding the pixel selection line, it is not necessary to separately form the pixel selection line conductor layer 108a in FIG. 1C.
  • the pixel selection line conductor layer 108a is formed so as to surround the N region 43 of the photodiode portion which is a photoelectric conversion region, so that light incident on the Si pillar 26d constituting the pixel from an oblique direction can be obtained.
  • the pixel selection line conductor layer 108a is formed so as to surround the N region 43 of the photodiode portion which is a photoelectric conversion region, so that light incident on the Si pillar 26d constituting the pixel from an oblique direction can be obtained.
  • silicide layers 55a, 55b, and 55c are provided on the drain N + region 56a in the N channel SGT and the drain P + regions 56b and 56c in the P channel SGT.
  • the electrical resistance values between the drain N + region 56a and P + regions 56b and 56c and the first metal wiring layers 51b, 51c and 51d are lowered.
  • the present embodiment is characterized in that copper (Cu) metal layers 58a, 58b, and 58c are formed in place of the silicide layers 55a, 55b, and 55c, as shown in FIG.
  • the electrical resistance value between the drain N + region 56a and P + regions 56b and 56c and the first metal wiring layers 51b, 51c and 51d can be further reduced.
  • the Cu metal layers 58a, 58b, and 58c are formed by the damascene technique, the N + regions 56a and P + are interposed between the Cu metal layers 58a, 58b, and 58c and the insulating layers 57a, 57b, and 57c.
  • a material layer such as TiN, TaN, or Cu for preventing reaction / diffusion with the Cu metal layers 58a, 58b, 58c and maintaining adhesion of the Cu metal layers 58a, 58b, 58c on the upper surfaces of the regions 56b, 56c.
  • barrier seed layers 59a, 59b and 59c are formed.
  • FIG. 7C shows a cross-sectional structure diagram of the solid-state imaging device of the present embodiment
  • FIGS. 7A and 7B show a manufacturing method leading to that.
  • the N-channel / P-channel SGT gate conductor layer 7a and the reset gate conductor layer 105a of the pixel are connected to the first metal wiring layer 12a, deep contact holes 9a, 9b. 12e.
  • These contact holes 9a and 9e are formed by etching the N-channel / P-channel SGT gate conductor layer 7a and the first, second and third interlayer insulating layers 14a, 14b and 14c on the reset gate conductor layer 105a of the pixel. To do. In this case, it is necessary to stop the etching of the deep contact holes 9a and 9b on the N-channel / P-channel SGT gate conductor layer 7a and the pixel reset gate conductor layer 105a with good control. Further, the N channel / P channel SGT gate conductor layer 7a and the pixel reset gate conductor layer 105a and the pixel reset gate conductor layer 7b are not removed by the overetching at this time. It is necessary to increase the thickness. This embodiment can further improve such manufacturing difficulties.
  • insulating layers 35e and 35f are formed on the outer peripheral portions of the Si pillars 26e and 26f constituting the gate conductor layer contact.
  • the first interlayer insulating layer 34a is formed, and the SGT gate conductor layer 36aa is formed so as to surround the Si pillars 26a, 26b, 26c constituting the SGT and the Si pillar 26e constituting the gate conductor layer contact.
  • the pixel reset gate conductor layer 36bb is formed so as to surround the Si pillar 26d constituting the pixel and the Si pillar 26f constituting the gate conductor layer contact.
  • the gate conductor layer 36aa and the reset gate conductor layer 36bb are wired on the first interlayer insulating layer 34a, and the second interlayer insulating layer 34b so as to surround the Si pillars 26a, 26b, 26c, 26d, 26e, and 26f. Formed at the same height.
  • the previous steps are basically the same as those shown in FIGS. 2A to 2I.
  • the silicide layers 55a, 55b, and 55c and the drain N + regions 56a and P + regions 56b and 56c in the SGT are formed on the Si pillars 26a, 26b, and 26c constituting the SGT. Then, the silicide layers 55a, 55b, and 55c are removed. Thereby, as shown in FIG. 7B, holes 60a, 60b, and 60c are formed on the drain N + region 56a and the P + regions 56b and 56c of the Si pillars 26a, 26b, and 26c constituting the SGT.
  • the Si layers 33e and 33f of the Si pillars 26e and 26f constituting the gate conductor layer contact are etched to a position lower than the upper end positions of the gate conductor layer 36aa and the pixel reset gate conductor layer 36bb.
  • the SiO 2 layers 35e and 35f exposed by this etching are removed to form holes 60d and 60e.
  • a conductive material layer such as TiN, TaN, or Cu for preventing the reaction / diffusion with Cu and maintaining the adhesion of the Cu metal layer 62, which is necessary for the formation of the Cu layer 62 by the damascene technology.
  • the barrier seed layer 61 is formed on the inner surfaces of the holes 60a, 60b, 60c, 60d, 60e and the fourth interlayer insulating layer 34d. Then, a Cu layer 62 is formed in the holes 60a, 60b, 60c, 60d, and 60e and on the fourth interlayer insulating layer 34d by plating. As a result, the SGT gate conductor layer 33aa and the pixel reset gate conductor layer 36bb are electrically connected to the Cu layer 62 via the barrier / seed layer 61 which is a conductor material layer.
  • the Cu layer 62 and the barrier / seed layer 61 are etched to form first metal wiring layers 62a, 62b, 62c, 62d, and 62e.
  • the entire structure is covered with the fifth interlayer insulating layer 34e, contact holes 63a and 63b are formed on the P-channel SGT first-layer metal wiring layers 62c and 62d, and the P-channel SGT first-layer is formed.
  • the metal wiring layers 62c and 62d are connected to the second metal wiring layer 64 formed on the fifth interlayer insulating layer 34e through contact holes 63a and 63b.
  • the etching of the Si layers 33e and 33f of the Si pillars 26e and 26f constituting the gate conductor layer contact is performed to a position lower than the upper end positions of the gate conductor layer 36aa and the pixel reset gate conductor layer 36bb. may be etched, it may be etched until the SiO 2 substrate 21 upper surface. For this reason, this etching process becomes easy. Further, in this etching, since the SGT gate conductor layer 36aa and the reset gate conductor layer 36bb are protected by the SiO 2 layers 35e and 35f, as shown in FIG. 1C, the gate conductor layer 36aa, the pixel reset gate It is not necessary to increase the thickness of the conductor layer 36bb.
  • the SGT gate conductor layer 36aa and the pixel reset gate conductor layer 36bb surround the Si pillars 26e and 26f constituting the gate conductor layer contact, the Si pillar 26d constituting the pixel, and the Si pillars 26a, 26b and 26c constituting the SGT. , Simultaneously and at the same height. This facilitates the manufacturing process as described above.
  • the silicide layers 55a, 55b, and 55c are all removed. However, some silicide on the drain N + region 56a and the P + regions 56b and 56c may remain. . Further, the silicide layers 55a, 55b, and 55c may be replaced with N + regions 8a and P + regions 8b and 8c as shown in FIG. 1C. Further, the metal material formed inside the holes 60a, 60b, 60c, 60d, and 60e may be a conductive material layer containing W, Co, Ni, Ti, or these substances instead of Cu.
  • the island-shaped semiconductors P11 to P33 constituting the pixel are present in the pixel region, and the SGT is present in the drive output circuit.
  • the SGT is present in the pixel region. Needless to say, the technical idea of the present invention can be applied even when the SGTs are formed adjacent to each other.
  • the N regions 8d and 43 constituting the photodiode are formed on the outer surface of the Si pillar P11 constituting the island-like semiconductor constituting the pixel.
  • the charge on the surface of the Si pillar P11 that forms the pixel on the outer periphery of the N regions 8d and 43 is opposite to the signal charge (free electrons). It is also possible to form a P + region that accumulates (holes).
  • the pixel reset gate conductor layers 7b, 36b, and 36bb formed at the same height as the SGT gate conductor layers 7a, 36a, and 36aa are connected to the signal line N + regions 2 and 31c of the signal charges accumulated in the photodiode. It may be provided as a light shielding layer instead of removing the light.
  • the SGT gate conductor layer 36aa and the pixel reset gate conductor layer 36bb are connected to the first layer via the Cu layer 62 formed on the Si pillars 26e and 26f constituting the gate conductor layer contact.
  • the case where the metal wiring layers 62a and 62e are connected has been described.
  • the pixel reset gate conductor layer 7b (gate conductor layer 36bb in FIG. 7C) and the SGT source N + region 3a (in FIG. 7C).
  • N + region 31a) and P + region 3b (P + region 31bb in FIG. 7C) are connected to each other via contact hole 9 and first metal wiring layer 12e. Can be applied.
  • a Si pillar constituting a contact is formed on the contact hole 9 and the pixel reset gate conductor layer 7b (the gate conductor layer 36bb in FIG. 7C) and the SGT source are formed in the same manner as in FIGS. 7A to 7C. Connection to the N + region 3a (N + region 31a in FIG. 7C) and the P + region 3b (P + region 31bb in FIG. 7C) can be made.
  • the present invention can be widely applied to semiconductor devices in which circuit elements are formed in columnar semiconductors such as solid-state imaging devices and SGTs.

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Abstract

In this solid-state image pickup device, a pixel has a first island-like semiconductor section (P11) formed on a substrate (1), and a drive output circuit has second island-like semiconductor sections (4a-4c), which are formed on the substrate with a height same as that of the first island-like semiconductor section (P11). The first island-like semiconductor section (P11) has a first gate insulating layer (6b) formed on the outer circumference of the first island-like semiconductor section, and a first gate conductor layer (105a) that surrounds the first gate insulating layer (6b). The second island-like semiconductor sections (4a-4c) have a second gate insulating layer (6a) formed on the outer circumference of the second island-like semiconductor sections, and a second gate conductor layer (7a) that surrounds the second gate insulating layer (6a). The first gate conductor layer (105a) and the second gate conductor layer (7a) have respective bottom portions positioned on a same plane.

Description

固体撮像装置Solid-state imaging device
　本発明は、島状半導体構造を有する半導体内にチャネル領域が形成されているＳＧＴ（Surround Gate Transistor）を備える固体撮像装置に関し、画素と駆動出力回路を有する固体撮像装置に関する。 The present invention relates to a solid-state imaging device including an SGT (Surround Gate Transistor) in which a channel region is formed in a semiconductor having an island-shaped semiconductor structure, and to a solid-state imaging device having a pixel and a drive output circuit.
　現在、ＣＭＯＳ固体撮像装置は、ビデオカメラ、スチールカメラなどに広く用いられている。これら固体撮像装置は、画素と、画素に繋がった駆動出力回路から構成されている。そして、固体撮像装置の高画素密度化、高解像度化、カラー撮像における低混色化、高感度化などの性能向上が常に求められている。これに対し、固体撮像装置の高解像度化を実現するために画素高密度化などによる技術革新が行われてきた。 Currently, CMOS solid-state imaging devices are widely used for video cameras, still cameras, and the like. These solid-state imaging devices are composed of a pixel and a drive output circuit connected to the pixel. Further, there is a constant demand for performance improvements such as higher pixel density, higher resolution, lower color mixing in color imaging, and higher sensitivity in solid-state imaging devices. On the other hand, technological innovations such as higher pixel density have been performed in order to achieve higher resolution of solid-state imaging devices.
　図８Ａ～図８Ｄに従来例の固体撮像装置を示す。
　図８Ａに、従来例に係る、１個の島状半導体１００に、１個の画素が構成されている固体撮像装置の断面構造図を示す（例えば、特許文献１を参照）。
　図８Ａに示すように、この画素を構成する島状半導体１００においては、基板１０１上に、信号線Ｎ＋領域１０２（以下、「Ｎ＋領域」をドナー不純物が多く含まれた半導体領域とする。）が形成されている。この信号線Ｎ＋領域１０２上にＰ領域１０３（以下、アクセプタ不純物が含まれた半導体領域を「Ｐ領域」とする。）が形成され、このＰ領域１０３の外周部に絶縁層１０４が形成され、この絶縁層１０４を介在させてゲート導体層１０５が形成されている。このゲート導体層１０５の上方部位におけるＰ領域１０３の外周部に、Ｎ領域（以下、ドナー不純物が含まれた半導体領域を「Ｎ領域」とする。）１０６が形成されている。このＮ領域１０６及びＰ領域１０３上において、島状半導体１００の上部にＰ＋領域（以下、アクセプタ不純物が多く含まれた半導体領域を「Ｐ＋領域」とする。）１０７が形成されている。このＰ＋領域１０７は、画素選択線導体層１０８に接続されている。上述した絶縁層１０４は、島状半導体１００の外周部を囲んだ状態で互いに繋がっている。同様に、ゲート導体層１０５も、島状半導体１００の外周部を囲んだ状態で互いに繋がっている。 8A to 8D show a conventional solid-state imaging device.
FIG. 8A shows a cross-sectional structure diagram of a solid-state imaging device in which one pixel is configured in one island-like semiconductor 100 according to the conventional example (see, for example, Patent Document 1).
As shown in FIG. 8A, in an island-shaped semiconductor 100 constituting this pixel, a signal line N + region 102 (hereinafter referred to as “N + region”) is a semiconductor region containing a lot of donor impurities on a substrate 101. .) Is formed. A P region 103 (hereinafter, a semiconductor region containing an acceptor impurity is referred to as a “P region”) is formed on the signal line N + region 102, and an insulating layer 104 is formed on the outer periphery of the P region 103. A gate conductor layer 105 is formed with the insulating layer 104 interposed therebetween. An N region (hereinafter, a semiconductor region containing donor impurities is referred to as an “N region”) 106 is formed on the outer peripheral portion of the P region 103 in the upper portion of the gate conductor layer 105. On the N region 106 and the P region 103, a P + region (hereinafter, a semiconductor region containing a lot of acceptor impurities is referred to as a “P + region”) 107 is formed on the island-shaped semiconductor 100. The P + region 107 is connected to the pixel selection line conductor layer 108. The insulating layers 104 described above are connected to each other so as to surround the outer periphery of the island-shaped semiconductor 100. Similarly, the gate conductor layers 105 are connected to each other so as to surround the outer periphery of the island-shaped semiconductor 100.
　本固体撮像装置では、入射光が、島状半導体１００の上面にあるＰ＋領域１０７側から照射される。島状半導体１００内において、Ｐ領域１０３とＮ領域１０６とからなるフォトダイオード領域が形成されており、この光照射によって、当該フォトダイオード領域における光電変換領域にて信号電荷（ここでは、自由電子）が発生する。そして、この信号電荷は、フォトダイオード領域のＮ領域１０６に蓄積される。また、島状半導体１００内において、このＮ領域１０６をゲート、Ｐ＋領域１０７をソースとし、信号線Ｎ＋領域１０２近傍のＰ領域１０３をドレインとした接合トランジスタが構成されている。そして、接合トランジスタのドレイン・ソース間電流（出力信号）が、Ｎ領域１０６に蓄積された信号電荷量に対応して変化し、信号線Ｎ＋領域１０２から外部に取り出され、読み出される。さらに、島状半導体１００内には、フォトダイオード領域のＮ領域１０６をソース、ゲート導体層１０５をリセットゲート、信号線Ｎ＋領域１０２をドレイン、Ｎ領域１０６と信号線Ｎ＋領域１０２間のＰ領域１０３をチヤネルとしたリセットＭＯＳトランジスタが形成されている（以後、このゲート導体層を「リセットゲート導体層」と称する。）。そして、このＮ領域１０６に蓄積された信号電荷は、リセットＭＯＳトランジスタのリセットゲート導体層１０５にプラス・オン電圧が印加されることによって、信号線Ｎ＋領域１０２に除去される。 In the solid-state imaging device, incident light is irradiated from the P + region 107 side on the upper surface of the island-shaped semiconductor 100. In the island-like semiconductor 100, a photodiode region including a P region 103 and an N region 106 is formed. By this light irradiation, signal charges (here, free electrons) are generated in the photoelectric conversion region in the photodiode region. Will occur. This signal charge is accumulated in the N region 106 of the photodiode region. Further, in the island-shaped semiconductor 100, a junction transistor is configured with the N region 106 as a gate, the P + region 107 as a source, and the P region 103 near the signal line N + region 102 as a drain. Then, the drain-source current (output signal) of the junction transistor changes corresponding to the amount of signal charge accumulated in the N region 106, and is extracted from the signal line N + region 102 and read out. Further, in the island-shaped semiconductor 100, the N region 106 of the photodiode region is the source, the gate conductor layer 105 is the reset gate, the signal line N + region 102 is the drain, and the P between the N region 106 and the signal line N + region 102. A reset MOS transistor using the region 103 as a channel is formed (hereinafter, this gate conductor layer is referred to as “reset gate conductor layer”). The signal charge accumulated in the N region 106 is removed to the signal line N + region 102 by applying a plus-on voltage to the reset gate conductor layer 105 of the reset MOS transistor.
　この固体撮像装置の撮像動作は、以下の動作から構成される。即ち、信号線Ｎ＋領域１０２、リセットゲート導体層１０５、Ｐ＋領域１０７にグランド電圧（０Ｖ）が印加された状態で、島状半導体１００の上面から入射した光線の照射によって光電変換領域（フォトダイオード領域）に発生した信号電荷をＮ領域１０６に蓄積する信号電荷蓄積動作と、信号線Ｎ＋領域１０２及びリセットゲート導体層１０５にグランド電圧が印加されるとともに、Ｐ＋領域１０７にプラス電圧が印加された状態で、蓄積信号電荷量に応じて変化したＮ領域１０６の電位により変調された接合トランジスタのソース・ドレイン電流を信号電流として読み出す信号電荷読み出し動作と、この信号電荷読み出し動作の後に、Ｐ＋領域１０７にグランド電圧が印加されるとともに、リセットゲート導体層１０５及び信号線Ｎ＋領域１０２にプラス電圧が印加された状態で、Ｎ領域１０６に蓄積されている信号電荷を信号線Ｎ＋領域１０２に除去するリセット動作と、から構成される。 The imaging operation of this solid-state imaging device includes the following operations. That is, in a state where the ground voltage (0 V) is applied to the signal line N + region 102, the reset gate conductor layer 105, and the P + region 107, the photoelectric conversion region (photographing region) is irradiated by irradiation of light incident from the upper surface of the island-shaped semiconductor 100. A signal charge accumulation operation for accumulating signal charges generated in the diode region) in the N region 106, a ground voltage is applied to the signal line N + region 102 and the reset gate conductor layer 105, and a positive voltage is applied to the P + region 107. In the applied state, after the signal charge read operation for reading the source / drain current of the junction transistor modulated by the potential of the N region 106 changed according to the accumulated signal charge amount as the signal current, and after this signal charge read operation, with the ground voltage is applied to the P + region 107, reset gate conductor layer 105 and the signal line + In the region 102 in a state where positive voltage is applied, a reset operation for removing the signal charges accumulated in the N region 106 to the signal line N + region 102, and a.
　図８Ｂに、画素を構成する島状半導体Ｐ１１～Ｐ３３（図８Ａの島状半導体１００に対応する。）が２次元状に配列された画素領域の周辺に駆動出力回路を有する固体撮像装置の模式平面図を示す（例えば、特許文献２を参照）。
　図８Ｂに示すように、信号線Ｎ＋領域１０２ａ，１０２ｂ，１０２ｃ（図８Ａの１０２に対応する。）上に画素を構成する島状半導体Ｐ１１～Ｐ３３が形成されている。画素島状半導体Ｐ１１～Ｐ３３の水平列毎に画素選択線導体層１０８ａ，１０８ｂ，１０８ｃ（図８Ａの１０８に対応する。）が繋がって形成され、画素領域の周辺に設けられた画素選択線垂直走査回路１１０に接続されている。同様に、画素を構成する島状半導体Ｐ１１～Ｐ３３の水平列毎にリセットゲート導体層１０５ａ，１０５ｂ，１０５ｃ（図８Ａに示すゲート導体層１０５に対応する。）が繋がって形成され、画素領域の周辺に設けられたリセット線垂直走査回路１１２に接続されている。このリセット線垂直走査回路１１２は、各リセットゲート導体層１０５ａ，１０５ｂ，１０５ｃに繋がるＳＧＴからなるＣＭＯＳインバータ回路１１３ａ，１１３ｂ，１１３ｃと、このＣＭＯＳインバータ回路１１３ａ，１１３ｂ，１１３ｃに繋がるシフトレジスタ１１４とからなる。そして、このＣＭＯＳインバータ回路１１３ａ，１１３ｂ，１１３ｃは、例えば２個のＰチャネルＳＧＴと１個のＮチャネルＳＧＴを使用した構成になっている。ＣＭＯＳインバータ回路１１３ａ，１１３ｂ，１１３ｃの入力端子にシフトレジスタ１１４から低レベル電圧が印加されると、出力端子からリセット・オン電圧ＶＲＨがリセットゲート導体層１０５ａ，１０５ｂ，１０５ｃに印加される一方で、高レベル電圧が印加されると、出力端子からリセット・オフ電圧ＶＲＬがリセットゲート導体層１０５ａ，１０５ｂ，１０５ｃに印加される。各信号線Ｎ＋領域１０２ａ，１０２ｂ，１０２ｃの下方部位はスイッチＳＧＴ１１５ａ，１１５ｂ，１１５ｃに接続され、各スイッチＳＧＴ１１５ａ，１１５ｂ，１１５ｃのゲートは信号線水平走査回路１１６に接続されている。そして、各スイッチＳＧＴ１１５ａ，１１５ｂ，１１５ｃのドレインは出力回路１１７に接続されている。信号電荷蓄積動作時にはグランド電圧（＝０Ｖ）、信号電荷読出し動作時にはフローティング、信号電荷除去動作時にはリセット電圧ＶＲＤが印加されるスイッチ回路１１８ａ，１１８ｂ，１１８ｃが、各信号線Ｎ＋領域１０２ａ，１０２ｂ，１０２ｃの上部に繋がるように形成されている。
　ここで、ＳＧＴ（Surrounding Gate Transistor）とは、シリコン柱の外周にゲート絶縁層を介してゲート導体層を形成した構造のトランジスタをいう。 FIG. 8B is a schematic diagram of a solid-state imaging device having a drive output circuit around a pixel region in which island-shaped semiconductors P11 to P33 (corresponding to the island-shaped semiconductor 100 of FIG. 8A) constituting pixels are arranged two-dimensionally. A plan view is shown (see, for example, Patent Document 2).
As shown in FIG. 8B, island-like semiconductors P11 to P33 constituting pixels are formed on the signal line N + regions 102a, 102b, and 102c (corresponding to 102 in FIG. 8A). Pixel selection line conductor layers 108a, 108b, and 108c (corresponding to 108 in FIG. 8A) are connected to each horizontal column of the pixel island-shaped semiconductors P11 to P33, and the pixel selection line vertical provided in the periphery of the pixel region is formed. It is connected to the scanning circuit 110. Similarly, the reset gate conductor layers 105a, 105b, and 105c (corresponding to the gate conductor layer 105 shown in FIG. 8A) are connected to each horizontal column of the island-shaped semiconductors P11 to P33 constituting the pixel, and the pixel region It is connected to a reset line vertical scanning circuit 112 provided in the periphery. This reset line vertical scanning circuit 112 includes CMOS inverter circuits 113a, 113b, 113c made of SGT connected to the respective reset gate conductor layers 105a, 105b, 105c, and a shift register 114 connected to the CMOS inverter circuits 113a, 113b, 113c. Become. The CMOS inverter circuits 113a, 113b, and 113c are configured using, for example, two P-channel SGTs and one N-channel SGT. CMOS inverter circuit 113a, 113b, the low-level voltage to the input terminal of the shift register 114 of 113c is applied, the reset-on voltage V RH from the output terminal is reset gate conductor layer 105a, 105b, while being applied to 105c , when the high level voltage is applied, the reset-off voltage V RL is reset gate conductor layer 105a, 105b, is applied to 105c from the output terminal. The lower part of each signal line N + region 102a, 102b, 102c is connected to the switches SGT 115a, 115b, 115c, and the gate of each switch SGT 115a, 115b, 115c is connected to the signal line horizontal scanning circuit 116. The drains of the switches SGT115a, 115b, and 115c are connected to the output circuit 117. The switch circuits 118a, 118b, and 118c to which the ground voltage (= 0V) is applied during the signal charge accumulation operation, the floating operation is performed during the signal charge read operation, and the reset voltage VRD is applied during the signal charge removal operation are the signal lines N + regions 102a and 102b. , 102c.
Here, SGT (Surrounding Gate Transistor) refers to a transistor having a structure in which a gate conductor layer is formed on the outer periphery of a silicon pillar via a gate insulating layer.
　信号電荷蓄積動作は、信号線Ｎ＋領域１０２ａ，１０２ｂ，１０２ｃが、スイッチＳＧＴ１１５ａ，１１５ｂ，１１５ｃのゲートに信号線水平走査回路１１６からオフ電圧が印加され、かつ、スイッチ回路１１８ａ，１１８ｂ，１１８ｃがグランド電圧側になることで、グランド電圧となった状態、リセットゲート導体層１０５ａ，１０５ｂ，１０５ｃにリセット・オフ電圧ＶＲＬが印加された状態、画素選択線導体層１０８ａ，１０８ｂ，１０８ｃにグランド電圧が印加されている状態、において行われる。
　信号電荷読出し動作は、リセットゲート導体層１０５ａ，１０５ｂ，１０５ｃにリセット・オフ電圧ＶＲＬが印加され、読み出す画素の画素選択線導体層１０８ａ，１０８ｂ，１０８ｃに高レベル電圧が印加され、かつ、読み出す画素の信号線Ｎ＋領域１０２ａ，１０２ｂ，１０２ｃに繋がるスイッチＳＧＴ１１５ａ，１１５ｂ，１１５ｃのゲートにオン電圧が印加され、スイッチ回路１１８ａ，１１８ｂ，１１８ｃの出力端子がフローティング、出力回路１１７の入力端子が低レベル電圧の状態において、読み出す画素の接合トランジスタのソース・ドレイン電流が出力回路１１７に取り込まれることによって行われる。
　信号電荷除去動作は、全画素選択線導体層１０８ａ，１０８ｂ，１０８ｃがグランド電圧、全スイッチＳＧＴ１１５ａ，１１５ｂ，１１５ｃがオフになっている状態において、蓄積信号電荷を除去する画素の島状半導体Ｐ１１～Ｐ３３に繋がるリセットゲート導体層１０５ａ，１０５ｂ，１０５ｃにリセット・オン電圧が印加され、スイッチ回路１１８ａ，１１８ｂ，１１８ｃの出力端子がリセット電圧ＶＲＤになることによって行われる。 In the signal charge accumulation operation, the signal line N + regions 102a, 102b, and 102c are applied with an off voltage from the signal line horizontal scanning circuit 116 to the gates of the switches SGTs 115a, 115b, and 115c, and the switch circuits 118a, 118b, and 118c by becoming the ground voltage side, condition that the ground voltage, the reset gate conductor layer 105a, 105b, a state in which the reset-off voltage V RL is applied to 105c, the pixel selection line conductor layers 108a, 108b, a ground voltage to 108c In a state where is applied.
In the signal charge reading operation, a reset / off voltage VRL is applied to the reset gate conductor layers 105a, 105b, and 105c, a high-level voltage is applied to the pixel selection line conductor layers 108a, 108b, and 108c of the pixel to be read, and reading is performed. An ON voltage is applied to the gates of the switches SGT 115a, 115b, and 115c connected to the pixel signal line N + regions 102a, 102b, and 102c, the output terminals of the switch circuits 118a, 118b, and 118c are floating, and the input terminal of the output circuit 117 is low. In the level voltage state, the output circuit 117 takes in the source / drain current of the junction transistor of the pixel to be read out.
In the signal charge removal operation, the pixel-like semiconductors P11 to P11 for removing the accumulated signal charge are removed in a state where all the pixel selection line conductor layers 108a, 108b, and 108c are at the ground voltage and all the switches SGT115a, 115b, and 115c are off. reset gate conductor layer 105a connected to the P33, 105b, reset-on voltage is applied to 105c, the switch circuits 118a, 118b, an output terminal of 118c is performed by going reset voltage V RD.
　図８Ｃに、図８Ｂにおいて２点鎖線で囲まれた領域Ａにおける模式平面図を示す。画素を構成する島状半導体Ｐ１１は信号線Ｎ＋領域１０２ａ上に形成され、ＣＭＯＳインバータ回路１１３ａのＮチャネルＳＧＴを構成する島状半導体１１９ａは第１の半導体層１２０ａ上に形成され、ＰチャネルＳＧＴを構成する島状半導体１１９ｂ，１１９ｃは第２の半導体層１２０ｂ上に形成されている。ＮチャネルＳＧＴを構成する島状半導体１１９ａの下方部位に繋がるように、第１の半導体層１２０ａの上部にＰウエル領域１２１ａが形成されている（図面では重なっている）。そして、ＰチャネルＳＧＴを構成する島状半導体１１９ｂ、１１９ｃの下方部位に繋がるように、第２の半導体層１２０ｂの上部にＮウエル領域１２１ｂが形成されている（図面では重なっている）。Ｐウエル領域１２１ａ内にあって、ＮチャネルＳＧＴを構成する島状半導体１１９ａの下方部位と、これに繋がるＮ＋領域１２２ａが形成されている。そして、Ｎウエル領域１２１ｂ内にあって、ＰチャネルＳＧＴを構成する島状半導体１１９ｂ、１１９ｃの下方部位と、これに繋がったＰ＋領域１２２ｂが形成されている。ＮチャネルＳＧＴのドレインＮ＋領域１２３ａがＮチャネルのための島状半導体１１９ａの上部に形成され、このドレインＮ＋領域１２３ａがコンタクトホール１２４ａを介して、リセット・オフ電圧ＶＲＬが印加された第１層目金属配線層１２５ａ（一点鎖線で記載）に接続されている。 FIG. 8C shows a schematic plan view of a region A surrounded by a two-dot chain line in FIG. 8B. The island-shaped semiconductor P11 constituting the pixel is formed on the signal line N + region 102a, the island-shaped semiconductor 119a constituting the N-channel SGT of the CMOS inverter circuit 113a is formed on the first semiconductor layer 120a, and the P-channel SGT Are formed on the second semiconductor layer 120b. A P well region 121a is formed above the first semiconductor layer 120a so as to be connected to a lower portion of the island-shaped semiconductor 119a constituting the N channel SGT (overlapping in the drawing). An N well region 121b is formed above the second semiconductor layer 120b so as to be connected to the lower portion of the island-shaped semiconductors 119b and 119c constituting the P channel SGT (overlapping in the drawing). In the P well region 121a, a lower portion of the island-shaped semiconductor 119a constituting the N channel SGT and an N + region 122a connected to the lower portion are formed. In the N well region 121b, lower portions of the island-shaped semiconductors 119b and 119c constituting the P channel SGT and a P + region 122b connected thereto are formed. Drain N + region 123a of the N-channel SGT is formed on top of the island-like semiconductor 119a for N-channel, the drain N + region 123a via a contact hole 124a, the reset-off voltage V RL is applied It is connected to the first metal wiring layer 125a (shown with a one-dot chain line).
　そして、ＰチャネルＳＧＴのドレインＰ＋領域１２３ｂ，１２３ｃがＰチャネルのための島状半導体１１９ｂ，１１９ｃの上部に形成され、このドレインＰ＋領域１２３ｂ，１２３ｃがコンタクトホール１２４ｂ，１２４ｃを介して、リセット・オン電圧ＶＲＨが印加された第１層目金属配線層１２５ｂ（一点鎖線で記載）に接続されている。ＮチャネルＳＧＴとＰチャネルＳＧＴゲート導体層１２６が繋がるように形成され、このゲート導体層１２６がコンタクトホール１２７ａを介してシフトレジスタ回路１１４に繋がる第１層目金属配線層１２５ｃ（一点鎖線で記載）に接続されている。画素を構成する島状半導体Ｐ１１のリセットゲート導体層１０５ａとＰチャネルＳＧＴのドレインＰ＋領域１２２ｂとは、コンタクトホール１２７ｅ，１２７ｆを介して第１層目金属配線層１２５ｅ（一点鎖線で記載）で接続されている。そして、ＰチャネルＳＧＴのソースＰ＋領域１２２ｂとＮチャネルＳＧＴのドレインＮ＋領域１２２ａとは、コンタクトホール１２７ｂ，１２７ｄを介して、第１層目金属配線層１２５ｂ（一点鎖線で記載）で接続されている。Ｐウエル領域１２１ａは、コンタクトホール１２７ｃを介して、第１層目金属配線層１２５ａ,１２５ｂ，１２５ｃ，１２５ｄ，１２５ｅの上部にある第２層目金属配線層１２８ａ（点線で記載）に接続されている。そして、Ｎウエル領域１２１ｂは、コンタクトホール１２７ｅを介して、第１層目金属配線層１２５ａ,１２５ｂ,１２５ｃ，１２５ｄ，１２５ｅの上部にある第２層目金属配線層１２８ｂ（点線で記載）に接続されている。 The drain P + regions 123b and 123c of the P channel SGT are formed on the island-shaped semiconductors 119b and 119c for the P channel, and the drain P + regions 123b and 123c are reset via the contact holes 124b and 124c. It is connected to the first-layer metal wiring layer 125b (denoted by a one-dot chain line) to which the on-voltage VRH is applied. N-channel SGT and P-channel SGT gate conductor layer 126 are formed so as to be connected, and first-layer metal wiring layer 125c (denoted by an alternate long and short dash line) in which this gate conductor layer 126 is connected to shift register circuit 114 through contact hole 127a It is connected to the. The reset gate conductor layer 105a of the island-shaped semiconductor P11 and the drain P + region 122b of the P-channel SGT constituting the pixel are first-layer metal wiring layers 125e (shown by alternate long and short dash lines) through contact holes 127e and 127f. It is connected. The source P + region 122b of the P channel SGT and the drain N + region 122a of the N channel SGT are connected to each other by a first layer metal wiring layer 125b (shown by a one-dot chain line) via contact holes 127b and 127d. ing. The P well region 121a is connected to a second metal wiring layer 128a (shown by a dotted line) located above the first metal wiring layers 125a, 125b, 125c, 125d, and 125e through a contact hole 127c. Yes. The N well region 121b is connected to a second metal wiring layer 128b (shown by a dotted line) located above the first metal wiring layers 125a, 125b, 125c, 125d, and 125e through a contact hole 127e. Has been.
　図８Ｄに、図８ＣのＢ－Ｂ’線に沿った断面構造図を示す。画素を構成する島状半導体Ｐ１１の断面構造は、図８Ａに示したものと同じである。基板１００（例えばＳｉＯ２層）上に、画素の信号線Ｎ＋領域１０２ａと、第１の半導体層１２０ａと、第２の半導体層１２０ｂと、が形成されている。画素を構成する島状半導体Ｐ１１が信号線Ｎ＋領域１０２ａ上に形成され、ＮチャネルＳＧＴを構成する島状半導体１１９ａが第１の半導体層上１２０ａに形成され、ＰチャネルＳＧＴを構成する島状半導体１１９ｂ、１１９ｃが第２の半導体層１２０ｂ上に形成されている。第１の半導体層１２０ａの上部にＰウエル領域１２１ａが形成され、第２の半導体層１２０ｂの上部にＮウエル領域１２１ｂが形成されている。Ｐウエル領域１２１ａ上部であって、ＮチャネルＳＧＴを構成する島状半導体１１９ａの下方部位には、ソースＮ＋領域１２２ａが形成されている。そして、Ｎウエル領域１２１ｂの上部であって、ＰチャネルＳＧＴを構成する島状半導体１１９ｂ、１１９ｃの下方部位には、ソースＰ＋領域１２２ｂが形成されている。ＮチャネルＳＧＴを構成する島状半導体１１９ａの上部にはドレインＮ＋領域１２３ａが形成されている。そして、ＰチャネルＳＧＴを構成する島状半導体１１９ｂ、１１９ｃの上部にはドレインＰ＋領域１２３ｂ、１２３ｃが形成されている。ＮチャネルＳＧＴを構成する島状半導体１１９ａのソース・ドレインＮ＋領域１２２ａ，１２３ａの間においては、ＮチャネルＳＧＴのチャネルはＰ領域１３１ａであり、ＰチャネルＳＧＴを構成する島状半導体のソース・ドレインＰ＋領域１２２ｂと１２３ｂ，１２３ｃとの間においては、ＰチャネルＳＧＴのチャネルはＮ領域１３１ｂ，１３１ｃである。ＮチャネルＳＧＴを構成する島状半導体１１９ａの外周部に、ＮチャネルＳＧＴゲート絶縁層１２９ａが形成され、このＮチャネルＳＧＴゲート絶縁層１２９ａに繋がるように第１の半導体層１２０ａ外周に絶縁層１３２ａが形成されている。 FIG. 8D shows a cross-sectional structure diagram taken along the line BB ′ of FIG. 8C. The cross-sectional structure of the island-shaped semiconductor P11 constituting the pixel is the same as that shown in FIG. 8A. A pixel signal line N + region 102a, a first semiconductor layer 120a, and a second semiconductor layer 120b are formed on a substrate 100 (for example, a SiO 2 layer). The island-shaped semiconductor P11 that forms the pixel is formed on the signal line N + region 102a, and the island-shaped semiconductor 119a that forms the N-channel SGT is formed on the first semiconductor layer 120a, and the island-shaped semiconductor that forms the P- channel SGT Semiconductors 119b and 119c are formed on the second semiconductor layer 120b. A P well region 121a is formed above the first semiconductor layer 120a, and an N well region 121b is formed above the second semiconductor layer 120b. A source N + region 122a is formed above the P-well region 121a and below the island-shaped semiconductor 119a constituting the N-channel SGT. A source P + region 122b is formed above the N well region 121b and below the island-shaped semiconductors 119b and 119c constituting the P channel SGT. A drain N + region 123a is formed on the island-shaped semiconductor 119a constituting the N channel SGT. Then, drain P + regions 123b and 123c are formed above the island-shaped semiconductors 119b and 119c constituting the P channel SGT. Between the source / drain N + regions 122a and 123a of the island-shaped semiconductor 119a constituting the N-channel SGT, the channel of the N-channel SGT is the P region 131a, and the source / drain of the island-shaped semiconductor constituting the P-channel SGT Between the P + regions 122b and 123b, 123c, the channels of the P channel SGT are the N regions 131b, 131c. An N-channel SGT gate insulating layer 129a is formed on the outer periphery of the island-shaped semiconductor 119a constituting the N-channel SGT, and an insulating layer 132a is formed on the outer periphery of the first semiconductor layer 120a so as to be connected to the N-channel SGT gate insulating layer 129a. Is formed.
　そして、ＰチャネルＳＧＴを構成する島状半導体１１９ａ，１１９ｃの外周部に、ＰチャネルＳＧＴゲート絶縁層１２９ｂ，１２９ｃが形成され、このＰチャネルＳＧＴを構成するゲート絶縁層１２９ｂ，１２９ｃに繋がった第２の半導体層１２０ｂの外周部に絶縁層１３２ｂが形成されている。画素を構成する島状半導体Ｐ１１の外周部に繋がったリセットＭＯＳトランジスタのリセットゲート導体層１０５ａはコンタクトホール１２７ｆを介して第１層目金属配線層１２５ｅに接続され、この第１層目金属配線層１２５ｅはコンタクトホール１２７ｂを介して、ＰチャネルＳＧＴを構成する島状半導体１１９ｂ、１１９ｃの下方部位に繋がるソースＰ＋領域１２２ｂに接続されている。ＮチャネルＳＧＴとＰチャネルＳＧＴゲート導体層１２６が、ＮチャネルＳＧＴを構成する島状半導体１１９ａとＰチャネルＳＧＴを構成する島状半導体１１９ｂ、１１９ｃとの間と、それらのゲート絶縁層１２９ｂ，１２９ｃの外周に繋がり、コンタクトホール１２７ａを介してシフトレジスタ回路に繋がる第１層目金属配線層１２５ｃに接続されている。 Then, P-channel SGT gate insulating layers 129b and 129c are formed on the outer peripheral portions of the island-shaped semiconductors 119a and 119c constituting the P-channel SGT, and the second connected to the gate insulating layers 129b and 129c constituting the P-channel SGT. An insulating layer 132b is formed on the outer periphery of the semiconductor layer 120b. The reset gate conductor layer 105a of the reset MOS transistor connected to the outer periphery of the island-shaped semiconductor P11 constituting the pixel is connected to the first-layer metal wiring layer 125e through the contact hole 127f, and this first-layer metal wiring layer 125e is connected to the source P + region 122b connected to the lower part of the island-shaped semiconductors 119b and 119c constituting the P-channel SGT through the contact hole 127b. The N-channel SGT and the P-channel SGT gate conductor layer 126 are formed between the island-shaped semiconductor 119a constituting the N-channel SGT and the island-shaped semiconductors 119b and 119c constituting the P-channel SGT, and between the gate insulating layers 129b and 129c. The first metal wiring layer 125c is connected to the outer periphery and connected to the shift register circuit through the contact hole 127a.
　ドレインＮ＋領域１２３ａがコンタクトホール１２４ａを介して、リセット・オフ電圧ＶＲＬが印加された第１層目金属配線層１２５ａに接続されている。そして、ＰチャネルＳＧＴのドレインＰ＋領域１２３ｂ、１２３ｃがコンタクトホール１２４ｂ、１２４ｃを介して、リセット・オン電圧ＶＲＨが印加された第１層目金属配線層１２５ｂに接続されている。第１の半導体層１２０ａ、第２の半導体層１２０ｂ、信号線Ｎ＋領域１０２ａ、ＮチャネルＳＧＴを構成する島状半導体１１９ａ、ＰチャネルＳＧＴを構成する島状半導体１１９ｂ，１１９ｃ、画素を構成する島状半導体Ｐ１１の間と、基板１００上に第１の層間絶縁層１３０ａ、第２の層間絶縁層１３０ｂ、第３の層間絶縁層１３０ｃ、第４の層間絶縁層１３０ｄ、第５の層間絶縁層１３０ｅが形成されている。第１の層間絶縁層１３０ａ上に画素のリセットゲート導体層１０５ａが配線され、第２の層間絶縁層１３０ｂ上にＰチャネル・ＮチャネルＳＧＴゲート導体層１２６が配線され、第３の層間絶縁層１３０ｄ上に画素選択線導体層１０８ａが配線され、第４の層間絶縁層１３０ｄ上に第１層目金属配線層１２５ａ，１２５ｂ，１２５ｃ，１２５ｅが形成され、第５の層間絶縁層１３０ｅ上にＰウエル領域１２１ａに接続された第２層目金属配線層１２８ａと、Ｎウエル領域１２１ｂに接続された第２層目金属配線層１２８ｂとが形成されている。 The drain N + region 123a is connected to the first metal wiring layer 125a to which the reset / off voltage VRL is applied via the contact hole 124a. The drain P + regions 123b and 123c of the P channel SGT are connected to the first metal wiring layer 125b to which the reset-on voltage VRH is applied via the contact holes 124b and 124c. First semiconductor layer 120a, second semiconductor layer 120b, signal line N + region 102a, island-shaped semiconductor 119a constituting N-channel SGT, island-shaped semiconductors 119b and 119c constituting P-channel SGT, island constituting pixels The first interlayer insulating layer 130a, the second interlayer insulating layer 130b, the third interlayer insulating layer 130c, the fourth interlayer insulating layer 130d, and the fifth interlayer insulating layer 130e are formed between the semiconductor P11 and on the substrate 100. Is formed. The pixel reset gate conductor layer 105a is wired on the first interlayer insulating layer 130a, the P-channel / N-channel SGT gate conductor layer 126 is wired on the second interlayer insulating layer 130b, and the third interlayer insulating layer 130d. The pixel selection line conductor layer 108a is wired thereon, the first metal wiring layers 125a, 125b, 125c, 125e are formed on the fourth interlayer insulating layer 130d, and the P-well is formed on the fifth interlayer insulating layer 130e. A second metal wiring layer 128a connected to region 121a and a second metal wiring layer 128b connected to N well region 121b are formed.
　図８Ｄの断面構造図に示すように、画素を構成する島状半導体Ｐ１１におけるリセットＭＯＳトランジスタのリセットゲート導体層１０５ａが、画素を構成する島状半導体Ｐ１１の底部にあるのに対して、ＣＭＯＳインバータ回路１１３ａのＳＧＴゲート導体層１２６は、第１・第２の半導体層１２０ａ，１２０ｂ上のＳＧＴを構成する島状半導体１１９ａ，１１９ｂ，１１９ｃの底部にある。画素を構成する島状半導体Ｐ１１のフォトダイオード領域は、画素を構成する島状半導体Ｐ１１の上面より入射した光をこのフォトダイオード領域で効率良く吸収するために、２．５～３μｍの高さが必要である（非特許文献１を参照）。
　これに対して、リセットゲート導体層１０５ａとＳＧＴゲート導体層１２６の高さは０．１μｍ程度、またはそれ以下であっても良い。通常、最初に信号線Ｎ＋領域１０２ａに画素を構成する島状半導体Ｐ１１を加えた厚さと、同じ厚さの半導体層１２０ａ，１２０ｂを、ＣＭＯＳインバータ回路１１３ａを含む駆動出力回路領域に形成し、その後に画素を構成する島状半導体Ｐ１１とＳＧＴを構成する島状半導体１１９ａ，１１９ｂを形成する。このため、画素を構成する島状半導体Ｐ１１のリセットゲート導体層１０５ａと、ＳＧＴゲート導体層１２６の高さ方向の位置に、必然的に、ほぼ画素を構成する島状半導体Ｐ１１の高さの違いが生じる。そして、リセットゲート導体層１０５ａは第１の層間絶縁層１３０ａ上に形成されており、ＳＧＴゲート導体層１２６は第２の層間絶縁層１３０ｂ上に形成されるため、リセットゲート導体層１０５ａとＳＧＴゲート導体層１２６は、必然的に、別々に形成しなければいけない。同様に、信号線Ｎ＋領域１０２ａとＮチャネルＳＧＴのソースＮ＋領域１２２ａは別々に形成しなければいけない。このため、この固体撮像装置の製造は、画素を構成する島状半導体Ｐ１１の構造を形成する工程に加えて、駆動出力回路を構成するＳＧＴを形成する工程が必要になる。これは、本固体撮像装置の歩留り低下、コスト増加に繋がる。 8D, the reset gate conductor layer 105a of the reset MOS transistor in the island-shaped semiconductor P11 constituting the pixel is at the bottom of the island-shaped semiconductor P11 constituting the pixel, whereas the CMOS inverter The SGT gate conductor layer 126 of the circuit 113a is at the bottom of the island-shaped semiconductors 119a, 119b, and 119c constituting the SGT on the first and second semiconductor layers 120a and 120b. The photodiode region of the island-shaped semiconductor P11 constituting the pixel has a height of 2.5 to 3 μm in order to efficiently absorb light incident from the upper surface of the island-shaped semiconductor P11 constituting the pixel. Necessary (see Non-Patent Document 1).
On the other hand, the height of the reset gate conductor layer 105a and the SGT gate conductor layer 126 may be about 0.1 μm or less. Usually, semiconductor layers 120a and 120b having the same thickness as the sum of the signal line N + region 102a and the island-shaped semiconductor P11 constituting the pixel are formed in the drive output circuit region including the CMOS inverter circuit 113a. Thereafter, island-shaped semiconductors P11 and 119b that form SGT and island-shaped semiconductors P11 that form pixels are formed. For this reason, the height difference between the reset gate conductor layer 105a of the island-shaped semiconductor P11 constituting the pixel and the height direction of the SGT gate conductor layer 126 inevitably differs in the height of the island-shaped semiconductor P11 constituting the pixel. Occurs. Since the reset gate conductor layer 105a is formed on the first interlayer insulating layer 130a and the SGT gate conductor layer 126 is formed on the second interlayer insulating layer 130b, the reset gate conductor layer 105a and the SGT gate are formed. The conductor layer 126 must be formed separately. Similarly, the signal line N + region 102a and the source N + region 122a of the N channel SGT must be formed separately. For this reason, the manufacture of this solid-state imaging device requires a step of forming an SGT that constitutes the drive output circuit in addition to the step of forming the structure of the island-shaped semiconductor P11 that constitutes the pixel. This leads to a decrease in yield and an increase in cost of the solid-state imaging device.
　なお、図８Ｃ、図８Ｄでは、第１・第２の半導体層１２０ａ，１２０ｂの上部にＰウエル領域１２１ａ、Ｎウエル領域１２１ｂを形成されている。Ｐウエル領域１２１ａとＮウエル領域１２１ｂの存在によって、例えば第１・第２の半導体層１２０ａ、１２０ｂに入射した漏洩光により発生する電流がＮチャネルＳＧＴのソースＮ＋領域１２２ａ及びＰチャネルＳＧＴのソースＰ＋領域１２２ｂに流入することを防止して、ＣＭＯＳインバータ回路１１３ａの誤動作が発生しづらくなっている。また、Ｐウエル領域１２１ａとＮウエル領域１２１ｂと、コンタクトホール１２７ｃ，１２７ｅを介して接続された第２層目金属配線層１２８ａ、１２８ｂを、例えばグランド電圧に印加しておくことにより、ＮチャネルＳＧＴのソースＮ＋領域１２２ａ及びＰチャネルＳＧＴのソースＰ＋領域１２２ｂを、電気的に浮遊している第１・第２の半導体層１２０ａ，１２０ｂから分離することにより、ＣＭＯＳインバータ回路１１３ａをより安定に動作させることができる。 8C and 8D, a P well region 121a and an N well region 121b are formed above the first and second semiconductor layers 120a and 120b. Due to the presence of the P well region 121a and the N well region 121b, for example, current generated by leakage light incident on the first and second semiconductor layers 120a and 120b causes the source N + region 122a of the N channel SGT and the source of the P channel SGT. This prevents the CMOS inverter circuit 113a from malfunctioning by preventing it from flowing into the P + region 122b. Further, by applying the second-layer metal wiring layers 128a and 128b connected to the P well region 121a and the N well region 121b through the contact holes 127c and 127e, for example, to the ground voltage, the N channel SGT By separating the source N + region 122a of the P and the source P + region 122b of the P-channel SGT from the first and second semiconductor layers 120a and 120b that are electrically floating, the CMOS inverter circuit 113a can be made more stable. It can be operated.
　Ｎチャネル・ＰチャネルＳＧＴは、このＣＭＯＳインバータ回路１１３ａ以外の駆動出力回路である、リセット線垂直走査回路１１２のシフトレジスタ１１４、画素選択走査回路１１０、水平走査回路１１６、出力回路１１７、スイッチＳＧＴ１１５ａ，１１５ｂ，１１５ｃ、スイッチ回路１１８ａ，１１８ｂ，１１８ｃにも形成されるので、上述の本固体撮像装置の歩留り低下、コスト増加に繋がる問題を生じる。 The N channel / P channel SGT is a drive output circuit other than the CMOS inverter circuit 113a, which is a shift register 114 of the reset line vertical scanning circuit 112, a pixel selection scanning circuit 110, a horizontal scanning circuit 116, an output circuit 117, a switch SGT 115a, 115b and 115c and switch circuits 118a, 118b, and 118c are also formed, resulting in a problem that leads to a decrease in yield and an increase in cost of the solid-state imaging device described above.
国際公開第２００９／０３４６２３号International Publication No. 2009/034623 特開２００９－１８２３１７号公報JP 2009-182317 A
　従来例の固体撮像装置においては、画素を構成する島状半導体Ｐ１１におけるリセットＭＯＳトランジスタのリセットゲート導体層１０５ａが、画素を構成する島状半導体Ｐ１１の底部にあるのに対して、駆動出力回路におけるＳＧＴゲート導体層１２６が、画素を構成する島状半導体Ｐ１１上面とほぼ同じ高さにある、第１・第２の半導体層１２０ａ，１２０ｂ上のＳＧＴを構成する島状半導体１１９ａ，１１９ｂにある。リセットＭＯＳトランジスタのリセットゲート導体層１０５ａと駆動出力回路におけるＳＧＴゲート導体層１２６の高さの差は、画素を構成する島状半導体Ｐ１１のフォトダイオード領域として必要な２．５～３μｍと大きい。そして、リセットＭＯＳトランジスタのリセットゲート導体層１０５ａと駆動出力回路におけるＳＧＴゲート導体層１２６が異なる層間絶縁層１３０ａ，１３０ｂ上に形成される。このため、必然的に、リセットＭＯＳトランジスタのリセットゲート導体層１０５ａと駆動出力回路におけるＳＧＴゲート導体層１２６は、別々に形成しなければいけない。同様に、信号線Ｎ＋領域１０２ａとＮチャネルＳＧＴのソースＮ＋領域１２２ａも、別々に形成する必要がある。このため、固体撮像装置の製造において、画素を構成する島状半導体Ｐ１１の構造を形成する工程に加えて、駆動出力回路におけるＳＧＴを形成する工程が必要になる。これは、本固体撮像装置の歩留り低下、コスト増加に繋がる。これに対し、画素を構成する島状半導体Ｐ１１と駆動出力回路を構成するＳＧＴとを同一の基板１００上に形成する固体撮像装置において、歩留まり低下、およびコスト増加を抑制しうる固体撮像装置が求められる。
　本発明は、上記の事情を鑑みてなされたものであり、歩留まり低下、およびコスト増加を抑制しうる固体撮像装置を実現することを目的とする。 In the solid-state imaging device of the conventional example, the reset gate conductor layer 105a of the reset MOS transistor in the island-shaped semiconductor P11 constituting the pixel is at the bottom of the island-shaped semiconductor P11 constituting the pixel, whereas in the drive output circuit The SGT gate conductor layer 126 is located on the island-shaped semiconductors 119a and 119b constituting the SGT on the first and second semiconductor layers 120a and 120b, which are substantially at the same height as the upper surface of the island-shaped semiconductor P11 constituting the pixel. The difference in height between the reset gate conductor layer 105a of the reset MOS transistor and the SGT gate conductor layer 126 in the drive output circuit is as large as 2.5 to 3 μm necessary for the photodiode region of the island-shaped semiconductor P11 constituting the pixel. The reset gate conductor layer 105a of the reset MOS transistor and the SGT gate conductor layer 126 in the drive output circuit are formed on different interlayer insulating layers 130a and 130b. Therefore, inevitably, the reset gate conductor layer 105a of the reset MOS transistor and the SGT gate conductor layer 126 in the drive output circuit must be formed separately. Similarly, the signal line N + region 102a and the source N + region 122a of the N channel SGT must be formed separately. For this reason, in the manufacture of the solid-state imaging device, in addition to the step of forming the structure of the island-shaped semiconductor P11 constituting the pixel, the step of forming the SGT in the drive output circuit is required. This leads to a decrease in yield and an increase in cost of the solid-state imaging device. In contrast, in a solid-state imaging device in which the island-shaped semiconductor P11 that constitutes the pixel and the SGT that constitutes the drive output circuit are formed on the same substrate 100, a solid-state imaging device that can suppress a decrease in yield and an increase in cost is desired. It is done.
The present invention has been made in view of the above circumstances, and an object thereof is to realize a solid-state imaging device capable of suppressing a decrease in yield and an increase in cost.
　上記目的を達成するため、本発明の固体撮像装置は、
　２次元状に配置された画素と、前記画素を駆動するとともに、前記画素からの信号を読み出す駆動出力回路と、を有する固体撮像装置において、
　前記画素は、基板上に形成された第１の島状半導体を有し、
　前記駆動出力回路は、前記基板上に、前記第１の島状半導体と同じ高さになるように形成された少なくとも１つの第２の島状半導体を有し、
　前記第１の島状半導体は、
　前記第１の島状半導体の底部に形成された第１の半導体領域と、
　前記第１の半導体領域上に形成され、前記第１の半導体領域と反対導電型、または真性型の半導体からなる第２の半導体領域と、
　前記第２の半導体領域の下部、かつ、外周に形成された第１のゲート絶縁層と、
　前記第１のゲート絶縁層を囲むように形成された第１のゲート導体層と、
　前記第１のゲート導体層に隣接する前記第２の半導体領域の外周部に形成され、前記第１の半導体領域と同じ導電型の半導体からなる第３の半導体領域と、
　前記第３の半導体領域及び前記第２の半導体領域上に形成され、前記第１の半導体領域と反対の導電型の半導体からなる第４の半導体領域とを、有し、
　前記第２の島状半導体は、
　前記第２の島状半導体の下部に形成された第５の半導体領域と、
　前記第５の半導体領域上に形成され、前記第５の半導体領域と反対導電型、または真性型の半導体からなる第６の半導体領域と、
　前記第６の半導体領域の外周に形成された第２のゲート絶縁層を囲むように形成された第２のゲート導体層と、
　前記第６の半導体領域上に、前記第２のゲート導体層に隣接するように、かつ、前記第２の半導体領域の上方に位置するように形成された第７の半導体領域とを、有し、
　前記第１のゲート導体層及び前記第２のゲート導体層は、それぞれの底部が同じ面上に位置している、
　ことを特徴とする。 In order to achieve the above object, the solid-state imaging device of the present invention includes:
In a solid-state imaging device having two-dimensionally arranged pixels, and a drive output circuit that drives the pixels and reads signals from the pixels,
The pixel has a first island-shaped semiconductor formed on a substrate,
The drive output circuit has at least one second island-shaped semiconductor formed on the substrate to have the same height as the first island-shaped semiconductor,
The first island-shaped semiconductor is
A first semiconductor region formed at the bottom of the first island-shaped semiconductor;
A second semiconductor region formed on the first semiconductor region and made of a semiconductor having a conductivity type opposite to that of the first semiconductor region or an intrinsic type;
A first gate insulating layer formed at a lower portion and an outer periphery of the second semiconductor region;
A first gate conductor layer formed so as to surround the first gate insulating layer;
A third semiconductor region formed on the outer periphery of the second semiconductor region adjacent to the first gate conductor layer and made of a semiconductor having the same conductivity type as the first semiconductor region;
A fourth semiconductor region formed on the third semiconductor region and the second semiconductor region and made of a semiconductor having a conductivity type opposite to the first semiconductor region;
The second island-shaped semiconductor is
A fifth semiconductor region formed under the second island-shaped semiconductor;
A sixth semiconductor region formed on the fifth semiconductor region and made of a semiconductor having a conductivity type opposite to that of the fifth semiconductor region or an intrinsic type;
A second gate conductor layer formed so as to surround a second gate insulating layer formed on the outer periphery of the sixth semiconductor region;
A seventh semiconductor region formed on the sixth semiconductor region so as to be adjacent to the second gate conductor layer and to be positioned above the second semiconductor region; ,
The first gate conductor layer and the second gate conductor layer have their bottoms located on the same plane,
It is characterized by that.
　前記第１のゲート導体層及び前記第２のゲート導体層の高さが互いに同じである、とすることができる。 The height of the first gate conductor layer and the second gate conductor layer may be the same.
　前記第２のゲート導体層が、複数の前記第２の島状半導体の内の一部の前記第２の島状半導体を囲むように形成された第３のゲート導体層と、複数の前記第２の島状半導体の内において、前記第３のゲート導体層が囲む前記第２の島状半導体とは異なる前記第２の島状半導体を囲むように形成され、前記第３のゲート導体層と異なる材料からなる第４のゲート導体層と、から構成されている、とすることができる。 A third gate conductor layer formed so as to surround a part of the second island-shaped semiconductors among the plurality of second island-shaped semiconductors; Among the two island-shaped semiconductors, the third gate conductor layer is formed so as to surround the second island-shaped semiconductor different from the second island-shaped semiconductor surrounded by the third gate conductor layer, And a fourth gate conductor layer made of a different material.
　前記第３のゲート導体層及び前記第４のゲート導体層の高さが互いに異なる、とすることができる。 The heights of the third gate conductor layer and the fourth gate conductor layer may be different from each other.
　前記第３のゲート導体層及び前記第４のゲート導体層の高さが互いに同じである、とすることができる。 The height of the third gate conductor layer and the fourth gate conductor layer may be the same.
　前記第２の島状半導体において、前記第６の半導体領域上に、前記第７の半導体領域が形成され、前記第７の半導体領域上に、シリサイド層又は金属層からなる導体層が形成されている、とすることができる。 In the second island-shaped semiconductor, the seventh semiconductor region is formed on the sixth semiconductor region, and a conductor layer made of a silicide layer or a metal layer is formed on the seventh semiconductor region. It can be said.
　前記第２の島状半導体において、前記第６の半導体領域を囲むように金属層が設けられている、とすることができる。 In the second island-shaped semiconductor, a metal layer may be provided so as to surround the sixth semiconductor region.
　前記第１の島状半導体及び前記第２の島状半導体と、当該第１及び第２の島状半導体と同じ高さに形成された第３の島状半導体と、を有し、
　前記第１の島状半導体を囲むように形成された前記第１のゲート導体層と、前記第２の島状半導体を囲むように形成された前記第２のゲート導体層の内の少なくとも一方が、前記第３の島状半導体を囲むように延在しており、
　前記第１のゲート導体層及び前記第２のゲート導体層の内の少なくとも一方が、前記第３の島状半導体の内部に形成された導体層と、前記第３の島状半導体の下方部位で電気的に接続されている、とすることができる。 The first island-shaped semiconductor and the second island-shaped semiconductor, and a third island-shaped semiconductor formed at the same height as the first and second island-shaped semiconductor,
At least one of the first gate conductor layer formed so as to surround the first island-shaped semiconductor and the second gate conductor layer formed so as to surround the second island-shaped semiconductor; , Extending around the third island-shaped semiconductor,
At least one of the first gate conductor layer and the second gate conductor layer is a conductor layer formed inside the third island-shaped semiconductor, and a lower portion of the third island-shaped semiconductor. It can be electrically connected.
　前記第３の島状半導体の内部に形成された導体層が、前記第１の半導体領域及び前記第５の半導体領域の内の少なくとも一方と、前記第３の島状半導体の下方部位で接続されている、とすることができる。 A conductor layer formed inside the third island-shaped semiconductor is connected to at least one of the first semiconductor region and the fifth semiconductor region at a lower portion of the third island-shaped semiconductor. It can be said that.
　本発明によれば、画素高集積化、高感度化、低コスト化を可能にする固体撮像装置を提供することができる。 According to the present invention, it is possible to provide a solid-state imaging device that enables high pixel integration, high sensitivity, and low cost.
本発明の第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路について説明するための模式回路図である。It is a schematic circuit diagram for demonstrating the pixel and CMOS inverter circuit of the solid-state imaging device which concern on the 1st Embodiment of this invention. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路について説明するための模式平面図である。It is a schematic plan view for demonstrating the pixel and CMOS inverter circuit of the solid-state imaging device which concern on 1st Embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路について説明するための断面構造図である。FIG. 3 is a cross-sectional structure diagram for explaining a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 第１の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. 本発明の第２の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。It is a cross-section figure for demonstrating the manufacturing method of the pixel and CMOS inverter circuit of the solid-state imaging device which concern on the 2nd Embodiment of this invention. 第２の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。It is a cross-section figure for demonstrating the manufacturing method of the pixel of the solid-state imaging device which concerns on 2nd Embodiment, and a CMOS inverter circuit. 第２の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。It is a cross-section figure for demonstrating the manufacturing method of the pixel of the solid-state imaging device which concerns on 2nd Embodiment, and a CMOS inverter circuit. 第２の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。It is a cross-section figure for demonstrating the manufacturing method of the pixel of the solid-state imaging device which concerns on 2nd Embodiment, and a CMOS inverter circuit. 第２の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。It is a cross-section figure for demonstrating the manufacturing method of the pixel of the solid-state imaging device which concerns on 2nd Embodiment, and a CMOS inverter circuit. 第２の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の断面構造図である。It is a cross-sectional structure figure of the pixel and CMOS inverter circuit of the solid-state imaging device concerning a 2nd embodiment. 本発明の第３の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。It is a cross-section figure for demonstrating the manufacturing method of the pixel and CMOS inverter circuit of the solid-state imaging device which concern on the 3rd Embodiment of this invention. 第３の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。It is sectional structure drawing for demonstrating the manufacturing method of the pixel and CMOS inverter circuit of the solid-state imaging device which concern on 3rd Embodiment. 第３の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。It is sectional structure drawing for demonstrating the manufacturing method of the pixel and CMOS inverter circuit of the solid-state imaging device which concern on 3rd Embodiment. 第３の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の断面構造図である。FIG. 6 is a cross-sectional structure diagram of a pixel and a CMOS inverter circuit of a solid-state imaging device according to a third embodiment. 本発明の第４の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の断面構造図である。It is a cross-section figure of a pixel and CMOS inverter circuit of a solid imaging device concerning a 4th embodiment of the present invention. 本発明の第５の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の断面構造図である。It is a cross-sectional structure figure of the pixel and CMOS inverter circuit of the solid-state imaging device which concern on the 5th Embodiment of this invention. 本発明の第６の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。It is a cross-section figure for demonstrating the manufacturing method of the pixel of the solid-state imaging device which concerns on the 6th Embodiment of this invention, and a CMOS inverter circuit. 第６の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の製造方法について説明するための断面構造図である。It is sectional structure drawing for demonstrating the manufacturing method of the pixel of the solid-state imaging device which concerns on 6th Embodiment, and a CMOS inverter circuit. 第６の実施形態に係る固体撮像装置の画素とＣＭＯＳインバータ回路の断面構造図である。It is a sectional structure figure of a pixel of a solid-state imaging device concerning a 6th embodiment, and a CMOS inverter circuit. 従来例の固体撮像装置の画素断面構造図である。It is a pixel cross-section figure of the solid-state imaging device of a prior art example. 従来例の固体撮像装置の模式平面図である。It is a model top view of the solid-state imaging device of a prior art example. 従来例の固体撮像装置における画素とＣＭＯＳインバータ回路の模式平面図である。It is a schematic top view of the pixel and CMOS inverter circuit in the solid-state imaging device of a prior art example. 従来例の固体撮像装置における画素とＣＭＯＳインバータ回路の断面構造図である。It is sectional drawing of the pixel and CMOS inverter circuit in the solid-state imaging device of a prior art example.
　以下に、本発明の第実施形態に係る固体撮像装置について図面を参照して説明する。 Hereinafter, a solid-state imaging device according to a second embodiment of the present invention will be described with reference to the drawings.
（第１の実施形態）
　以下、図１Ａ～図１Ｃを参照しながら、本発明の第１の実施形態に係る固体撮像装置について説明する。 (First embodiment)
The solid-state imaging device according to the first embodiment of the present invention will be described below with reference to FIGS. 1A to 1C.
　本実施形態に係る固体撮像装置の模式平面図は、図８Ｂに示すものと同じである。図１Ａに、図８Ｂに示す固体撮像装置の模式平面図の２点鎖線で囲まれた領域Ａの、模式回路図を示す。リセットゲート導体層１０５ａは、２個のＰチャネルＳＧＴ４ａａ、４ｂｂと１個のＮチャネルＳＧＴ４ｃｃからなるＣＭＯＳインバータ回路１１３ａに接続され、このＣＭＯＳインバータ回路１１３ａはシフトレジスタ１１４に接続されている。
　そして、このＣＭＯＳインバータ回路１１３ａの入力端子にシフトレジスタ１１４から低レベル電圧が印加されると、出力端子からリセット・オン電圧ＶＲＨがリセットゲート導体層１０５ａに印加され、ＣＭＯＳインバータ回路１１３ａの入力端子にシフトレジスタ１１４から高レベル電圧が印加されると、出力端子からリセット・オフ電圧ＶＲＬがリセットゲート導体層１０５ａに印加される。 The schematic plan view of the solid-state imaging device according to this embodiment is the same as that shown in FIG. 8B. FIG. 1A shows a schematic circuit diagram of a region A surrounded by a two-dot chain line in the schematic plan view of the solid-state imaging device shown in FIG. 8B. The reset gate conductor layer 105 a is connected to a CMOS inverter circuit 113 a composed of two P-channel SGTs 4 aa and 4 bb and one N-channel SGT 4 cc. The CMOS inverter circuit 113 a is connected to the shift register 114.
When the low-level voltage from the shift register 114 to the input terminal of the CMOS inverter circuit 113a is applied, the reset-on voltage V RH is applied to the reset gate conductor layer 105a from the output terminal, the input terminal of the CMOS inverter circuit 113a When a high level voltage is applied from the shift register 114, the reset-off voltage VRL is applied from the output terminal to the reset gate conductor layer 105a.
　図１Ｂに、図１Ａの模式平面図を示す。酸化シリコン基板（ＳｉＯ２基板）１上に、画素領域における信号線Ｎ＋領域１０２ａとＣＭＯＳインバータ回路１１３ａ領域のＮチャネルＳＧＴ４ｃｃのソース用板状Ｎ＋領域３ａとＰチャネルＳＧＴ４ａａ，４ｂｂのソース用板状Ｐ＋領域３ｂが形成されている。また、信号線Ｎ＋領域１０２ａ上に画素を構成する島状半導体Ｐ１１が形成され、ソース用板状Ｎ＋領域３ａ上にＮチャネルＳＧＴ４ｃｃを構成する島状半導体４ａが形成され、ＰチャネルＳＧＴ４ａａ，４ｂｂのソース用板状Ｐ＋領域３ｂ上にＰチャネルＳＧＴ４ａａ，４ｂｂを構成する島状半導体４ｂ，４ｃが形成されている。ＮチャネルＳＧＴ４ｃｃを構成する島状半導体とＰチャネルＳＧＴ４ａａ，４ｂｂを構成する島状半導体を囲むように、連続したゲート導体層７ａが形成され、画素を構成する島状半導体Ｐ１１を囲み、水平方向に繋がったリセットゲート導体層１０５ａが形成されている。 FIG. 1B shows a schematic plan view of FIG. 1A. On the silicon oxide substrate (SiO 2 substrate) 1, the signal line N + region 102a in the pixel region, the source plate N + region 3a of the N channel SGT4cc in the CMOS inverter circuit 113a region, and the source plate of the P channels SGT4aa and 4bb A shaped P + region 3b is formed. Further, an island-shaped semiconductor P11 that constitutes a pixel is formed on the signal line N + region 102a, and an island-like semiconductor 4a that constitutes an N-channel SGT4cc is formed on the source plate-like N + region 3a, and the P-channel SGT4aa, Island- like semiconductors 4b and 4c constituting P-channel SGTs 4aa and 4bb are formed on the 4bb source plate-like P + region 3b. A continuous gate conductor layer 7a is formed so as to surround the island-shaped semiconductor constituting the N-channel SGT4cc and the island-shaped semiconductor constituting the P-channel SGT4aa, 4bb, and surrounds the island-shaped semiconductor P11 constituting the pixel in the horizontal direction. A connected reset gate conductor layer 105a is formed.
　ゲート導体層７ａ上にコンタクトホール９ａが形成され、ゲート導体層７ａはこのコンタクトホール９ａを介してシフトレジスタ１１４に繋がる第１層目金属配線層１２ａ（一点鎖線）に繋がっている。そして、リセットゲート導体層１０５ａ上にコンタクトホール９ｂが形成され、リセットゲート導体層１０５ａはコンタクトホール９ｂを介して第１層目金属配線層１２ｅ（一点鎖線）に接続されている。ＮチャネルＳＧＴ４ｃｃのソース用板状Ｎ＋領域３ａとＰチャネルＳＧＴ４ａａ，４ｂｂのソース用板状Ｐ＋領域３ｂの境界上にコンタクトホール９ｃが形成され、このコンタクトホール９ｃを介して、ＮチャネルＳＧＴ４ｃｃのソース用板状Ｎ＋領域３ａとＰチャネルＳＧＴ４ａａ，４ｂｂのソース用板状Ｐ＋領域３ｂが第１層目金属配線層１２ｅ（一点鎖線）に接続されている。ＮチャネルＳＧＴ４ｃｃを構成する島状半導体４ａの上部にあるドレインＮ＋領域８ａ上にコンタクトホール１１ａを形成し、ＰチャネルＳＧＴ４ａａ，４ｂｂを構成する島状半導体４ｂの上部にあるドレインＮ＋領域８ｂ、８ｃ上にコンタクトホール１１ｂ、１１ｃを形成している。そして、ドレインＮ＋領域８ａはコンタクトホール１１ａを介してリセット低レベル電圧ＶＲＬが印加されている第１層目金属配線層１２ｂ（一点鎖線）に接続され、ドレインＰ＋領域８ｂ、８ｃはコンタクトホール１１ｂ、１１ｃを介してリセット高レベル電圧ＶＲＨが印加されている第１層目金属配線層１２ｃ、１２ｄ（一点鎖線）に接続されている。これら第１層目金属配線層１２ｃ、１２ｄはリセットオン電圧ＶＲＨが印加されている第２層目金属配線層１４（点線）に接続されている。 A contact hole 9a is formed on the gate conductor layer 7a, and the gate conductor layer 7a is connected to the first metal wiring layer 12a (one-dot chain line) connected to the shift register 114 via the contact hole 9a. A contact hole 9b is formed on the reset gate conductor layer 105a, and the reset gate conductor layer 105a is connected to the first metal wiring layer 12e (one-dot chain line) through the contact hole 9b. A contact hole 9c is formed on the boundary between the source plate N + region 3a of the N channel SGT4cc and the source plate P + region 3b of the P channels SGT4aa and 4bb, and the N channel SGT4cc of the N channel SGT4cc is formed via the contact hole 9c. The source plate N + region 3a and the source plate P + regions 3b of the P channels SGT4aa and 4bb are connected to the first metal wiring layer 12e (one-dot chain line). Drain N + region 8b of the drain N + region on 8a at the top of the island-like semiconductor 4a constituting the N-channel SGT4cc to form a contact hole 11a, the top of the island-like semiconductor 4b constituting P-channel SGT4aa, the 4bb, Contact holes 11b and 11c are formed on 8c. The drain N + region 8a is connected to the first metal wiring layer 12b (one-dot chain line) to which the reset low level voltage VRL is applied via the contact hole 11a, and the drain P + regions 8b and 8c are in contact with each other. The holes are connected to the first metal wiring layers 12c and 12d (one-dot chain lines) to which the reset high level voltage VRH is applied through the holes 11b and 11c. The first metal wiring layers 12c and 12d are connected to the second metal wiring layer 14 (dotted line) to which the reset on voltage VRH is applied.
　図１Ｃに、図１ＢのＡ－Ａ’線に沿った断面構造図を示す。画素を構成する島状半導体Ｐ１１の断面構造は、図８Ｄに示したものと同じである。基板１（例えばＳｉＯ２層）上に、画素の信号線Ｎ＋領域１０２ａと、ＮチャネルＳＧＴ４ｃｃのソースＮ＋領域３ａと、ＰチャネルＳＧＴ４ａａ，４ｂｂのソースＰ＋領域３ｂが形成されている。画素を構成する島状半導体Ｐ１１が信号線Ｎ＋領域１０２ａ上に形成され、ＮチャネルＳＧＴ４ｃｃを構成する島状半導体４ａがソース半導体層Ｎ＋領域３ａ上に形成され、ＰチャネルＳＧＴ４ａａ，４ｂｂを構成する島状半導体４ａ，４ｂがソースＰ＋領域３ｂ上に形成されている。ＮチャネルＳＧＴ４ｃｃを構成する島状半導体４ａの下方部位にソースＮ＋領域３ａが繋がるとともに、ＰチャネルＳＧＴ４ａａ，４ｂｂを構成する島状半導体４ｂ、４ｃの下方部位にソースＰ＋領域３ｂが繋がっている。ソースＮ＋領域３ａ上にＮチャネルＳＧＴ４ｃｃのチャネルＰ領域５ａが繋がり、ソースＰ＋領域３ｂ上にＰチャネルＳＧＴ４ａａ，４ｂｂのチャネルＮ領域５ｂ、５ｃが繋がり、画素の信号線Ｎ＋領域２上にリセットＭＯＳトランジスタのチャネル、接合トランジスタのドレインとなるＰ領域に繋がっている（これらチャネル半導体領域５ａ、５ｂ、５ｃ、画素を構成する島状半導体Ｐ１１のＰ領５ｄ域は真性型であっても良い）。ソースＮ＋領域３ａに繋がったＮチャネルＳＧＴ４ｃｃを構成する島状半導体４ａの外周部に、ＮチャネルＳＧＴ４ｃｃのゲート絶縁層６ａが形成され、ソースＰ＋領域３ｂに繋がったＰチャネルＳＧＴ４ａａ，４ｂｂを構成する島状半導体４ｂ，４ｃの外周部に、ＰチャネルＳＧＴ４ａａ，４ｂｂのゲート絶縁層６ｂ、６ｃが形成されている。また、画素の信号線Ｎ＋領域１０２ａに繋がる画素を構成する島状半導体Ｐ１１の外周部にリセットＭＯＳゲート絶縁膜６ｄが形成されている。 FIG. 1C shows a cross-sectional structure diagram along line AA ′ of FIG. 1B. The cross-sectional structure of the island-shaped semiconductor P11 constituting the pixel is the same as that shown in FIG. 8D. A signal line N + region 102a of a pixel, a source N + region 3a of an N channel SGT 4cc, and a source P + region 3b of P channels SGT 4aa and 4bb are formed on the substrate 1 (for example, SiO 2 layer). The island-shaped semiconductor P11 constituting the pixel is formed on the signal line N + region 102a, and the island-shaped semiconductor 4a constituting the N-channel SGT4cc is formed on the source semiconductor layer N + region 3a to constitute the P-channel SGT4aa and 4bb. Insulating semiconductors 4a and 4b are formed on the source P + region 3b. The source N + region 3a is connected to the lower portion of the island-shaped semiconductor 4a constituting the N-channel SGT4cc, and the source P + region 3b is connected to the lower portion of the island-shaped semiconductors 4b and 4c constituting the P-channel SGT4aa and 4bb. . The channel P region 5a of the N channel SGT4cc is connected to the source N + region 3a, the channel N regions 5b and 5c of the P channels SGT4aa and 4bb are connected to the source P + region 3b, and the signal line N + region 2 of the pixel is connected. It is connected to the channel of the reset MOS transistor and the P region which becomes the drain of the junction transistor (the channel semiconductor regions 5a, 5b and 5c, and the P region 5d region of the island-shaped semiconductor P11 constituting the pixel may be an intrinsic type. ). A gate insulating layer 6a of the N-channel SGT4cc is formed on the outer periphery of the island-shaped semiconductor 4a constituting the N-channel SGT4cc connected to the source N + region 3a, and P-channel SGT4aa and 4bb connected to the source P + region 3b are formed. Gate insulating layers 6b and 6c of P-channel SGTs 4aa and 4bb are formed on the outer periphery of the island-shaped semiconductors 4b and 4c. Further, a reset MOS gate insulating film 6d is formed on the outer periphery of the island-shaped semiconductor P11 constituting the pixel connected to the signal line N + region 102a of the pixel.
　ＮチャネルＳＧＴ４ｃｃのゲート絶縁層６ａとＰチャネルＳＧＴ４ａａ，４ｂｂのゲート絶縁層６ｂ、６ｃの外周部を含み、基板１上に形成された第１の層間絶縁層１４ａ上に、繋がってＮチャネル・ＰチャネルＳＧＴ４ａａ，４ｂｂ、４ｃｃのゲート導体層７ａが形成されている。同じく、画素のリセットゲート導体層１０５ａがリセットＭＯＳのゲート絶縁膜６ｄの外周部を含み、第１の層間絶縁層１４ａ上に、繋がって形成されている。ＮチャネルＳＧＴ４ｃｃゲート導体層７ａの上部に隣接したＮチャネルＳＧＴ４ｃｃを構成する島状半導体４ａ内にドレインＮ＋領域８ａが形成され、同じく、ＰチャネルＳＧＴ４ａａ，４ｂｂゲート導体層７ａに上部に隣接したＰチャネルＳＧＴ４ａａ，４ｂｂを構成する島状半導体４ｂ、４ｃ内にドレインＰ＋領域８ｂ、８ｃが形成されている。また、画素のリセットゲート導体層１０５ａに上部に隣接した画素を構成する島状半導体Ｐ１１内に、Ｐ領域５ｄと、このＰ領域５ｄを囲んで形成されたＮ領域８ｄよりなるフォトダイオード領域が形成されている。ＮチャネルＳＧＴ４ｃｃのドレインＮ＋領域８ａ、ＰチャネルＳＧＴ４ａａ，４ｂｂのドレインＰ＋領域８ｂ、８ｃは、ＳＧＴを構成する島状半導体４ａ，４ｂ，４ｃの上面まで繋がるように形成されている。また、画素を構成する島状半導体Ｐ１１の上面に画素選択Ｐ＋領域１０が形成されている。この画素選択Ｐ＋領域１０は、第２の層間絶縁層１４ｂ上にある第３の層間絶縁層１４ｃ上に形成された画素選択線導体層１０８ａに接続されている。 The outer periphery of the gate insulating layer 6a of the N-channel SGT4cc and the gate insulating layers 6b and 6c of the P-channel SGT4aa and 4bb is connected to the first interlayer insulating layer 14a formed on the substrate 1 and connected to the N-channel P Gate conductor layers 7a of channels SGT4aa, 4bb, 4cc are formed. Similarly, the reset gate conductor layer 105a of the pixel includes the outer periphery of the gate insulating film 6d of the reset MOS, and is connected to the first interlayer insulating layer 14a. A drain N + region 8a is formed in the island-like semiconductor 4a constituting the N-channel SGT4cc adjacent to the upper portion of the N-channel SGT4cc gate conductor layer 7a. Similarly, the P-channel SGT4aa, Pbb adjacent to the Pbb SGT4aa and 4bb gate conductor layers 7a Drain P + regions 8b and 8c are formed in the island- like semiconductors 4b and 4c constituting the channels SGT4aa and 4bb. In addition, a photodiode region composed of a P region 5d and an N region 8d formed so as to surround the P region 5d is formed in the island-shaped semiconductor P11 constituting the pixel adjacent to the upper portion of the reset gate conductor layer 105a of the pixel. Has been. The drain N + region 8a of the N channel SGT4cc and the drain P + regions 8b, 8c of the P channels SGT4aa, 4bb are formed so as to be connected to the top surfaces of the island- like semiconductors 4a, 4b, 4c constituting the SGT. Further, the pixel selection P + region 10 is formed on the upper surface of the island-shaped semiconductor P11 constituting the pixel. The pixel selection P + region 10 is connected to a pixel selection line conductor layer 108a formed on the third interlayer insulating layer 14c on the second interlayer insulating layer 14b.
　Ｎチャネル・ＰチャネルＳＧＴ４ａａ，４ｂｂ，４ｃｃのゲート導体層７ａはコンタクトホール９ａを介して、第４の層間絶縁層１４ｄ上に形成され、シフトレジスタに繋がる第１層目金属配線層１２ａに接続されている。ＮチャネルＳＧＴ４ｃｃを構成する島状半導体４ａの上部にあるドレインＮ＋領域８ａは、コンタクトホール１１ａを介してリセットオフ電圧ＶＲＬが印加されている第１層目金属配線層１２ｂに接続されている。また、ＰチャネルＳＧＴを構成する島状半導体４ｂ，４ｃの上部にあるドレインＰ＋領域８ｂ，８ｃは、コンタクトホール１１ｂ、１１ｃを介してリセットオン電圧ＶＲＨが印加されている第１層目金属配線層１２ｃ、１２ｄに接続されている。画素のリセットゲート導体層１０５ａはコンタクトホール９ｂを介して、第４の層間絶縁層１４ｄ上にある、ＮチャネルＳＧＴ４ｃｃのソースＮ＋領域３ａ、ＰチャネルＳＧＴ４ａａ，４ｂｂのソースＰ＋領域３ｂと電気的に接続された第１層目金属配線層１２ｅに接続されている。また、第１層目金属配線層１２ｃ、１２ｄはコンタクトホール１５ａ，１５ｂを介して、第５の層間絶縁層１４ｅ上に形成された、リセットオン電圧ＶＲＨが印加された第２層目金属配線層１６に接続されている。 N-channel / P-channel SGT4aa, 4bb, 4cc gate conductor layer 7a is formed on fourth interlayer insulating layer 14d through contact hole 9a, and is connected to first-layer metal interconnection layer 12a connected to the shift register. ing. The drain N + region 8a above the island-shaped semiconductor 4a constituting the N channel SGT4cc is connected to the first metal wiring layer 12b to which the reset off voltage VRL is applied via the contact hole 11a. . The drain P + regions 8b and 8c above the island-shaped semiconductors 4b and 4c constituting the P-channel SGT are applied to the first layer metal to which the reset-on voltage VRH is applied via the contact holes 11b and 11c. The wiring layers 12c and 12d are connected. The reset gate conductor layer 105a of the pixel is electrically connected to the source N + region 3a of the N channel SGT4cc and the source P + region 3b of the P channels SGT4aa and 4bb on the fourth interlayer insulating layer 14d through the contact hole 9b. Is connected to the first-layer metal wiring layer 12e. The first-layer metal wiring layers 12c and 12d are formed on the fifth interlayer insulating layer 14e through the contact holes 15a and 15b, and the second-layer metal wiring to which the reset-on voltage VRH is applied. Connected to layer 16.
　図１Ｃの断面構造図に示されるように、本実施形態の固体撮像装置においては、以下のような構造的特徴を有する。
　第１の特徴は、基板１上に直接に、Ｎチャネル・ＰチャネルＳＧＴ４ａａ，４ｂｂ，４ｃｃのソースＮ＋領域３ａ、Ｐ＋領域３ｂ、信号線Ｎ＋領域１０２ａのドナー又はアクセプタ不純物を含んだ半導体領域が形成され、それらが同層に形成されている点である。
　第２の特徴は、Ｎチャネル・ＰチャネルＳＧＴ４ａａ，４ｂｂ，４ｃｃのゲート導体層７ａと画素のリセットゲート導体層１０５ａとが、同じ第１の層間絶縁層１４ａ上に形成されると共に、各島状半導体４ａ，４ｂ，４ｃ，Ｐ１１の底部に繋がる、ゲート絶縁膜６ａ，６ｂ，６ｃ，６ｄの外周に形成され、互いに同層に形成されている点である。
　第３の特徴は、ＳＧＴのチャネルＰ領域５ａまたはＮ領域５ｂ，５ｃと、画素のリセットＭＯＳチャネルのＰ領域５ｄと、が互いに同層に形成されている点である。
　第４の特徴は、ＳＧＴを構成する島状半導体４ａ，４ｂ，４ｃの上部において、ＮチャネルＳＧＴ４ｃｃのドレインＮ＋領域８ａと、ＰチャネルＳＧＴ４ａａ，４ｂｂのドレインＰ＋領域８ｂ，８ｃとが、画素の島状半導体Ｐ１１の上部において、フォトダイオードを構成するＮ領域８ｄと選択Ｐ＋領域１０とが、互いに同層に形成されている。 As shown in the cross-sectional structure diagram of FIG. 1C, the solid-state imaging device of this embodiment has the following structural features.
The first feature is that a semiconductor containing donor or acceptor impurities of the source N + region 3a, the P + region 3b, and the signal line N + region 102a of the N channel / P channel SGT4aa, 4bb, 4cc directly on the substrate 1. Regions are formed and they are formed in the same layer.
The second feature is that an N-channel / P-channel SGT4aa, 4bb, 4cc gate conductor layer 7a and a pixel reset gate conductor layer 105a are formed on the same first interlayer insulating layer 14a, and each island-shaped It is formed on the outer periphery of the gate insulating films 6a, 6b, 6c, 6d connected to the bottoms of the semiconductors 4a, 4b, 4c, P11, and is formed in the same layer.
The third feature is that the SGT channel P region 5a or N regions 5b and 5c and the pixel reset MOS channel P region 5d are formed in the same layer.
The fourth feature is that the drain N + region 8a of the N-channel SGT4cc and the drain P + regions 8b, 8c of the P-channel SGT4aa, 4bb are arranged on the island-shaped semiconductors 4a, 4b, 4c constituting the SGT. In the upper part of the island-shaped semiconductor P11, the N region 8d and the selective P + region 10 constituting the photodiode are formed in the same layer.
　これらの構造的な特徴によって本実施形態は、以下のような利点を有する。
　第１の利点は、従来例の固体撮像装置（図８Ｄ）では、ＳＧＴを構成する島状半導体１１９ａ，１１９ｂ，１１９ｃと画素を構成する島状半導体Ｐ１１とを個別に形成していたのに対して、本実施形態においては、ＳＧＴを構成する島状半導体４ａ，４ｂ，４ｃと画素を構成する島状半導体Ｐ１１とを同じ工程で形成することができる点である。
　第２の利点は、ＮチャネルＳＧＴ４ｃｃのＮ＋領域３ａ、ＰチャネルＳＧＴ４ａａ，４ｂｂのソースＰ＋領域３ｂが、基板１上に直接形成されるため、従来例の固体撮像装置（図８Ｄ）のようなＮウエル層１２１ｂや、Ｐウエル層１２１ａを必要としない点である。
　第３の利点は、従来例の固体撮像装置（図８Ｄ参照）では個別に形成した、ＮチャネルＳＧＴ４ｃｃのＮ＋領域３ａを、画素信号線Ｎ＋領域１０２ａと同じ工程で形成することができる点である。
　第４の利点は、従来例の固体撮像装置（図８Ｄ参照）では個別に形成したＮチャネル・ＰチャネルＳＧＴ４ａａ，４ｂｂ，４ｃｃのゲート導体層７ａ、画素のリセットゲート導体層１０５ａを同じ工程で形成できる点である。
　第５の利点は、従来例の固体撮像装置（図８Ｄ参照）では個別に形成した、これらゲート導体層７ａ，１０５ａ上に形成するコンタクトホール９ａ，９ｂを同じ工程で形成できる点である。 Due to these structural features, the present embodiment has the following advantages.
The first advantage is that in the solid-state imaging device of the conventional example (FIG. 8D), the island-shaped semiconductors 119a, 119b, and 119c constituting the SGT and the island-shaped semiconductor P11 constituting the pixel are individually formed. In the present embodiment, the island-shaped semiconductors 4a, 4b, and 4c constituting the SGT and the island-shaped semiconductor P11 constituting the pixel can be formed in the same process.
The second advantage is that the N + region 3a of the N channel SGT4cc and the source P + region 3b of the P channels SGT4aa and 4bb are formed directly on the substrate 1, so that the conventional solid state imaging device (FIG. 8D) is used. The N well layer 121b and the P well layer 121a are not required.
A third advantage is that the N + region 3a of the N-channel SGT4cc formed individually in the conventional solid-state imaging device (see FIG. 8D) can be formed in the same process as the pixel signal line N + region 102a. It is.
The fourth advantage is that in the conventional solid-state imaging device (see FIG. 8D), the N-channel / P-channel SGT4aa, 4bb, 4cc gate conductor layer 7a and the pixel reset gate conductor layer 105a are formed in the same process. This is a possible point.
A fifth advantage is that contact holes 9a and 9b formed on the gate conductor layers 7a and 105a, which are individually formed in the solid-state imaging device of the conventional example (see FIG. 8D), can be formed in the same process.
　これらの利点は、従来例の固体撮像装置と比べて、本発明の固体撮像装置を少ない工程数で製作できることを意味している。これにより、固体撮像装置の低コスト化が実現される。 These advantages mean that the solid-state imaging device of the present invention can be manufactured with a smaller number of processes than the conventional solid-state imaging device. Thereby, cost reduction of a solid-state imaging device is implement | achieved.
　図２Ａ～図２Ｑを参照しながら、本発明の第１の実施形態に係る固体撮像装置を形成するための製造方法を示し、図１Ｂの画素部とＣＭＯＳインバータ回路部平面図のＡ－Ａ’線に沿った断面構造を形成する製造方法を示す。 A manufacturing method for forming the solid-state imaging device according to the first embodiment of the present invention will be described with reference to FIGS. 2A to 2Q, and AA ′ in the plan view of the pixel portion and CMOS inverter circuit portion in FIG. 1B. The manufacturing method which forms the cross-sectional structure along a line is shown.
　図２Ａに示すように、ＳｉＯ２基板２１上に単結晶半導体シリコン層（以下、単に「Ｓｉ層」とする。）２２を形成している。このＳｉ層２２表面を酸化してＳｉＯ２層２３を形成し、このＳｉＯ２層２３上にシリコン窒化層（以後ＳｉＮ層と記載する）２４と、ＣＶＤ（Chemical Vapor Deposition）法によるＳｉＯ２層２５を形成する。
　ここで、ＣＶＤ法によるＳｉＯ２層２５はＳｉ層２２をＲＩＥ（Reactive Ion Etching）法によるエッチングにおけるエッチングマスクの役割をする。ＳｉＮ層２４は、後工程におけるＣＭＰ（Chemical Mechanical Polishing）ＳｉＯ２膜平坦化におけるストッパ層の役割をする。また、Ｓｉ層２２上のＳｉＯ２層２３は、Ｓｉ層２２とＳｉＮ層２４との応力緩和のためのバッファ層となる。 As shown in FIG. 2A, a single crystal semiconductor silicon layer (hereinafter simply referred to as “Si layer”) 22 is formed on a SiO 2 substrate 21. The SiO 2 layer 23 formed by oxidizing the Si layer 22 surface, and the silicon nitride layer on the SiO 2 layer 23 (which is hereafter written as SiN layer) 24, CVD (Chemical Vapor Deposition ) method using SiO 2 layer 25 Form.
Here, the SiO 2 layer 25 by the CVD method serves as an etching mask in etching the Si layer 22 by the RIE (Reactive Ion Etching) method. The SiN layer 24 serves as a stopper layer in planarizing a CMP (Chemical Mechanical Polishing) SiO 2 film in a later process. The SiO 2 layer 23 on the Si layer 22 serves as a buffer layer for stress relaxation between the Si layer 22 and the SiN layer 24.
　次に、図２Ｂに示すように、ＮチャネルＳＧＴ部、ＰチャネルＳＧＴ部、画素部のＳｉ層２２を、ＳｉＯ２層２５をエッチングマスクにして、エッチングして、ＮチャネルＳＧＴを構成するシリコン柱（以下、「シリコン柱」を「Ｓｉ柱」とする。）２６ａ、ＰチャネルＳＧＴを構成するＳｉ柱２６ｂ，２６ｃ、画素を構成するＳｉ柱２６ｄを形成し、Ｓｉ層２２の底部に板状Ｓｉ層２２ａ，２２ｂを残存させる。
　ここでは、板状Ｓｉ層２２ａ，２２ｂ領域のＳｉ層２２をＳｉＯ２基板２１表面までエッチングして、次にＳｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄを形成することによって図２Ｂの構造を形成する。 Next, as shown in FIG. 2B, the silicon layer constituting the N channel SGT is etched by etching the Si layer 22 of the N channel SGT part, the P channel SGT part, and the pixel part using the SiO 2 layer 25 as an etching mask. (Hereinafter, the “silicon pillar” will be referred to as “Si pillar”.) 26a, Si pillars 26b and 26c constituting the P channel SGT, and Si pillar 26d constituting the pixel are formed, and a plate-like Si is formed at the bottom of the Si layer 22. The layers 22a and 22b are left.
Here, etching plate Si layer 22a, the Si layer 22 of 22b region to SiO 2 substrate 21 surface, then Si pillars 26a, 26b, 26c, by forming 26d form the structure of FIG. 2B.
　続いて、図２Ｃに示すように、Ｓｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄと板状Ｓｉ層２２５ａ，２２ｂの外周にＳｉＯ２層２７ａ，２７ｂ，２７ｃ，２７ｄを形成する。続いて、Ｓｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄのＳｉＯ２層２７ａ，２７ｂ，２７ｃ，２７ｄを囲んで多結晶Ｓｉ層２８ａ，２８ｂ，２８ｃ，２８ｄを形成し、ＰチャネルＳＧＴ部以外をフォトレジスト層２９で覆い、この上からアクセプタ不純物のボロン（Ｂ）イオン注入を行い、板状Ｓｉ層２５ａにＰ＋領域３０を形成する。なお、フォトレジスト層２９の形成は、フォトリソグラフィ（photolithography）技術を用いて行う。ここで、多結晶Ｓｉ層２８ａ，２８ｂ，２８ｃ，２８ｄはボロンイオン注入のとき、Ｓｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄ内にボロンイオンを注入させないためのストッパ層である。
　その後、フォトレジスト層２９を除去し、同様なフォトリソグラフィ技術とドナー不純物リン（Ｐ）または砒素（Ａｓ）イオン注入により、ＮチャネルＳＧＴ部の板状Ｓｉ層２２ａと画素用板状Ｓｉ層２２ｂにＮ＋領域を形成する。 Subsequently, as shown in FIG. 2C, SiO 2 layers 27a, 27b, 27c, and 27d are formed on the outer periphery of the Si pillars 26a, 26b, 26c, and 26d and the plate-like Si layers 225a and 22b. Subsequently, polycrystalline Si layers 28a, 28b, 28c, and 28d are formed surrounding the SiO 2 layers 27a, 27b, 27c, and 27d of the Si pillars 26a, 26b, 26c, and 26d, and a photoresist layer is formed except for the P-channel SGT portion. Then, boron (B) ions of acceptor impurities are implanted from above, and a P + region 30 is formed in the plate-like Si layer 25a. The formation of the photoresist layer 29 is performed using a photolithography technique. Here, the polycrystalline Si layers 28a, 28b, 28c, 28d are stopper layers for preventing boron ions from being implanted into the Si pillars 26a, 26b, 26c, 26d when boron ions are implanted.
Thereafter, the photoresist layer 29 is removed, and the plate-like Si layer 22a and the pixel-like plate-like Si layer 22b in the N-channel SGT portion are formed by the same photolithography technique and donor impurity phosphorus (P) or arsenic (As) ion implantation. N + regions are formed.
　次に、図２Ｄに示すように、多結晶Ｓｉ層２８ａ，２８ｂ，２８ｃ，２８ｄを除去し、熱処理を行うことにより、熱拡散により板状Ｓｉ層２５ａ，２５ｂからＳｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄの下方部位に繋がったＮ＋領域３１ａ，３１ｃ，Ｐ＋領域３１ｂが形成される。 Next, as shown in FIG. 2D, the polycrystalline Si layers 28a, 28b, 28c, 28d are removed and heat treatment is performed, so that the Si pillars 26a, 26b, 26c, N + regions 31a, 31c, and P + regions 31b connected to the lower portion of 26d are formed.
　続いて、図２Ｅに示すように、ＰチャネルＳＧＴを構成するＳｉ柱２６ｂ，２６ｃを覆うようにフォトレシスト層３２をフォトリソグラフィ技術で形成し、さらにボロン（Ｂ）などのアクセプタ不純物のイオン注入を行い、ＮチャネルＳＧＴを構成するＳｉ柱２６ａ、画素を構成するＳｉ柱２６ｄに、Ｐ領域３３ａ，３３ｄを形成する。その後、フォトレシスト層３２を除去する。 Subsequently, as shown in FIG. 2E, a photoresist layer 32 is formed by photolithography so as to cover the Si pillars 26b and 26c constituting the P channel SGT, and ion implantation of acceptor impurities such as boron (B) is further performed. Then, P regions 33a and 33d are formed in the Si pillar 26a constituting the N channel SGT and the Si pillar 26d constituting the pixel. Thereafter, the photo resist layer 32 is removed.
　続いて、これと同様にして、ＮチャネルＳＧＴを構成するＳｉ柱２６ａ、画素を構成するＳｉ柱２６ｄを覆うようにフォトリソグラフィ技術によりフォトレシスト層を形成し、砒素（Ａｓ)，リン（Ｐ）などのドナー不純物のイオン注入を行い、さらにフォトレシスト層を除去し熱処理することにより、図２Ｆに示すように、ＰチャネルＳＧＴを構成するＳｉ柱２６ｂ，２６ｃにＮ領域３３ｂ、３３ｃを形成する。 Subsequently, in the same manner, a photoresist layer is formed by photolithography so as to cover the Si pillar 26a constituting the N channel SGT and the Si pillar 26d constituting the pixel, and arsenic (As), phosphorus (P). As shown in FIG. 2F, N regions 33b and 33c are formed in the Si pillars 26b and 26c constituting the P channel SGT by performing ion implantation of donor impurities such as the above and further removing the photo resist layer and performing heat treatment.
　続いて、図２Ｇに示すように、第１の層間絶縁層３４ａを形成し、ＳｉＯ２層２７ａ，２７ｂ，２７ｃ，２７ｄを除去し（このとき同時にＳｉＯ２層２５ａ，２５ｂ，２５ｃ，２５ｄが除去される）、Ｓｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄの外周にＳｉＯ２、酸化ハフニウム（ＨｆＯ2)などの高誘電率絶縁材料によるゲート絶縁層３５ａ，３５ｂ，３５ｃ，３５ｄを形成し、第１の層間絶縁層３４ａ上、Ｓｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄを囲むように、例えばＣＶＤ（Chemical Vapor Deposition）法による多結晶Ｓｉ、タングステン（Ｗ）、コバルト（Ｃｏ）、白金（Ｐｔ）、シリサイド材料による導体層３６を形成し、Ｎチャネル・ＰチャネルＳＧＴのゲート領域上にフォトレシスト層３７ａ、画素リセットゲート領域にフォトレジスト層３７ｂを形成する。
　第１の層間絶縁層３４ａは、ＣＶＤ法でＳｉＯ２膜をＳｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄより高い位置まで堆積し、ＣＭＰ（Chemical Mechanical Polishing）法によりＳｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄの高さまで研磨・平坦化して、そのあとＲＩＥ法によるエッチング（以後、エッチバックと記載する）を行うことで形成する。ここでは、ＣＶＤ法によるＳｉＯ２膜の堆積前に、ＳｉＯ２基板１上、板状Ｎ＋領域３１ａ，３１ｃ、板状Ｐ＋領域３１ｂ、Ｓｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄを囲むようにＳｉＮ膜を堆積し、ＳｉＯ２膜のエッチバック後にＳｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄを囲むＳｉＮ膜を除去してもよい。この場合、このＳｉＮ膜はエッチバック時においてＳｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄがエッチングされないための保護膜の役割を果たす。 Subsequently, as shown in FIG. 2G, the first interlayer insulating layer 34a is formed, and the SiO 2 layers 27a, 27b, 27c, 27d are removed (at the same time, the SiO 2 layers 25a, 25b, 25c, 25d are removed). The gate insulating layers 35a, 35b, 35c, and 35d made of a high dielectric constant insulating material such as SiO 2 and hafnium oxide (HfO 2 ) are formed on the outer periphery of the Si pillars 26a, 26b, 26c, and 26d. For example, polycrystalline Si, tungsten (W), cobalt (Co), platinum (Pt), silicide material by CVD (Chemical Vapor Deposition) method so as to surround the Si pillars 26a, 26b, 26c, and 26d on the interlayer insulating layer 34a Is formed on the gate region of the N channel / P channel SGT, and the photo resist layer 37a is formed on the pixel reset gate region. To form a layer 37b.
The first interlayer insulating layer 34a is formed by depositing a SiO 2 film to a position higher than the Si pillars 26a, 26b, 26c, and 26d by the CVD method, and forming the Si pillars 26a, 26b, 26c, and 26d by the CMP (Chemical Mechanical Polishing) method. It is formed by polishing and flattening to a height and then performing etching by RIE (hereinafter referred to as etch back). Here, before the SiO 2 film is deposited by the CVD method, the SiN so as to surround the plate-like N + regions 31a and 31c, the plate-like P + region 31b, and the Si pillars 26a, 26b, 26c, and 26d on the SiO 2 substrate 1. A film may be deposited and the SiN film surrounding the Si pillars 26a, 26b, 26c, and 26d may be removed after the SiO 2 film is etched back. In this case, the SiN film serves as a protective film for preventing the Si pillars 26a, 26b, 26c, and 26d from being etched during the etch back.
　続いて、フォトレジスト層３７ａ，３７ｂをマスクとして、導体層３６をエッチングする。その後、フォトレジスト層３７ａ，３７ｂを除去する。
　続いて、図２Ｈに示すように、第２の層間絶縁層３４ｂを形成する。この第２の層間絶縁層３４ｂも、第１の層間絶縁膜３４ａと同様に、ＣＶＤ法によるＳｉＯ２膜堆積、ＣＭＰ法によるＳｉＯ２膜研磨、ＲＩＥ法によるエッチバックにより形成する。 Subsequently, the conductor layer 36 is etched using the photoresist layers 37a and 37b as a mask. Thereafter, the photoresist layers 37a and 37b are removed.
Subsequently, as shown in FIG. 2H, a second interlayer insulating layer 34b is formed. Similarly to the first interlayer insulating film 34a, the second interlayer insulating layer 34b is also formed by SiO 2 film deposition by the CVD method, SiO 2 film polishing by the CMP method, and etch back by the RIE method.
　続いて、図２Ｉに示すように、第２の層間絶縁層３４ｂで覆われることなくＳｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄを囲むように露出しているゲート導体層３６ａａ，３６ｂｂをエッチングする。これによって、Ｎチャネル・ＰチャネルＳＧＴゲート導体層３６ａと画素リセットゲート導体層３６ｂが形成される。
　ここでは、Ｎチャネル・ＰチャネルＳＧＴゲート導体層３６ａは、ＳＧＴを構成するＳｉ柱２６ａ，２６ｂ，２６ｃの下方部位の外周を囲み、第１の層間絶縁層３４ａ上に繋がって形成される。 Subsequently, as shown in FIG. 2I, the gate conductor layers 36aa and 36bb exposed so as to surround the Si pillars 26a, 26b, 26c and 26d without being covered with the second interlayer insulating layer 34b are etched. As a result, an N-channel / P-channel SGT gate conductor layer 36a and a pixel reset gate conductor layer 36b are formed.
Here, the N-channel / P-channel SGT gate conductor layer 36a is formed so as to surround the outer periphery of the lower portion of the Si pillars 26a, 26b, and 26c constituting the SGT and to be connected to the first interlayer insulating layer 34a.
　続いて、図２Ｊに示すように、第２の層間絶縁層３４ｂ上にＳｉＮ層３８を形成し、この第２の層間絶縁層３４ｂとＳｉ柱とを覆うようにＣＶＤ法によるＳｉＯ２層３９を形成し、平坦化したＳｉＯ２層３９上にＳｉＮ層４０を形成し、さらにフォトリソグラフィ技術を用いてＰチャネルＳＧＴを構成するＳｉ柱２６ｂ，２６ｃに孔を形成したフォトレジスト層４１を形成する。
　ここでは、ＳｉＮ層３８は、ＳｉＯ２層３９のエッチチング・ストッパ層の役割を果たし、ＳｉＯ２層３９上のＳｉＮ層４０は、ＳｉＯ２層３９のエッチングマスク層の役割を果たす。 Subsequently, as shown in FIG. 2J, an SiN layer 38 is formed on the second interlayer insulating layer 34b, and an SiO 2 layer 39 formed by CVD is formed so as to cover the second interlayer insulating layer 34b and the Si pillar. A SiN layer 40 is formed on the formed and planarized SiO 2 layer 39, and a photoresist layer 41 in which holes are formed in the Si pillars 26b and 26c constituting the P channel SGT is formed using a photolithography technique.
Here, SiN layer 38 plays a role of etch quenching stopper layer of the SiO 2 layer 39, SiN layer 40 on the SiO 2 layer 39 serves as an etching mask layer of SiO 2 layer 39.
　続いて、フォトレシスト層４１をマスクにＰチャネルＳＧＴを構成するＳｉ柱２６ｂ，２６ｃ上のＳｉＮ層４０をエッチングし、フォトレジスト層４１を除去した後に、ＳｉＮ層４０をエッチングマスクにしてＳｉＯ２層３９をＳｉＮ層３８表面までＲＩＥ法エッチングする。その後に、Ｓｉ柱２６ｂ，２６ｃの外周にあるゲート絶縁層３５ｂ，３５ｃを除去する。
　続いて、図２Ｋに示すように、ＣＶＤ法によってボロン（Ｂ）などのアクセプタ不純物を含んだＳｉＯ２層４２ｂを形成する。
　ここでは、アクセプタ不純物を含んだＳｉＯ２層４２ｂは、最初ＳｉＮ層４０上まで堆積した後、ＣＭＰ法によってＳｉＮ層４０まで研磨し、平坦にして形成する。 Subsequently, the SiN layer 40 on the Si pillars 26b and 26c constituting the P-channel SGT is etched using the photoresist layer 41 as a mask, and after removing the photoresist layer 41, an SiO 2 layer is formed using the SiN layer 40 as an etching mask. 39 is etched to the surface of the SiN layer 38 by RIE. Thereafter, the gate insulating layers 35b and 35c on the outer periphery of the Si pillars 26b and 26c are removed.
Subsequently, as shown in FIG. 2K, a SiO 2 layer 42b containing an acceptor impurity such as boron (B) is formed by a CVD method.
Here, the SiO 2 layer 42b containing the acceptor impurity is first deposited up to the SiN layer 40, and then polished to the SiN layer 40 by CMP to form a flat surface.
　続いて、ＳｉＮ層４０を除去し、新たなＳｉＮ層４３を堆積し、フォトリソグラフィ法でのレジスト層形成とＳｉＮエッチングにより、ＳｉＮ層４３のＮチャネルＳＧＴを構成するＳｉ柱２６ａ上に孔を形成する。このＳｉＮ層４３をエッチングマスクにしてＳｉＯ２層３９をＳｉＮ層３６の表面までエッチングする。
　続いて、図２Ｌに示すように、Ｓｉ柱のゲート絶縁膜３５ａを除去した後、リン（Ｐ）、砒素（Ａｓ）などのドナー不純物を含んだＳｉＯ２層４２ａを形成する。
　続いて、熱処理を行うことにより、Ｓｉ柱２６ａ，２６ｂ，２６ｃ内にＣＶＤ法で形成したＳｉＯ２層４２ａ、４２ｂからドナー不純物とアクセプタ不純物を拡散し、Ｓｉ柱２６ａ，２６ｂ，２６ｃ内にＮ＋領域３７ａと、Ｐ＋領域３７ｂ，３７ｃを形成する。 Subsequently, the SiN layer 40 is removed, a new SiN layer 43 is deposited, and a hole is formed on the Si pillar 26a constituting the N channel SGT of the SiN layer 43 by forming a resist layer by photolithography and SiN etching. To do. Using the SiN layer 43 as an etching mask, the SiO 2 layer 39 is etched to the surface of the SiN layer 36.
Subsequently, as shown in FIG. 2L, after removing the Si pillar gate insulating film 35a, a SiO2 layer 42a containing donor impurities such as phosphorus (P) and arsenic (As) is formed.
Subsequently, by performing heat treatment, donor impurities and acceptor impurities are diffused from the SiO 2 layers 42a and 42b formed by the CVD method in the Si pillars 26a, 26b, and 26c, and N + in the Si pillars 26a, 26b, and 26c. Region 37a and P + regions 37b and 37c are formed.
　続いて、図２Ｍに示すように、Ｎ＋領域３７ａ、Ｐ＋領域３７ｂ，３７ｃを形成する方法と同様に、画素を構成するＳｉ柱２６ｄ領域のＳｉＮ層３８上に、ドナー不純物を含んだＳｉＯ２層４２ｃを形成し、熱処理により、Ｓｉ柱２６ｄの外周部にＮ領域４３を形成する。
　ここでは、ＳｉＯ２層４２ｃに含まれたドナー不純物の量は、Ｎ＋領域３７ａを形成するためのＳｉＯ２層４２ａより少ない。 Subsequently, as shown in FIG. 2M, in a manner similar to the method of forming the N + region 37a and the P + regions 37b and 37c, the SiON containing donor impurities is formed on the SiN layer 38 in the Si pillar 26d region constituting the pixel. A two- layer 42c is formed, and an N region 43 is formed on the outer periphery of the Si pillar 26d by heat treatment.
Here, the amount of donor impurities contained in the SiO 2 layer 42c is less than that of the SiO 2 layer 42a for forming the N + region 37a.
　続いて、ＳｉＯ２層３９，４２ａ，４２ｂ，４２ｃを除去する。次に、図２Ｎに示すように、Ｓｉ面が露出したＳｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄの表面を酸化してＳｉＯ２層４５ａ，４５ｂ，４５ｃ，４５ｄを形成する。
　続いて、ＳｉＮ層２４ａ，２４ｂ，２４ｃ，２４ｄ，３８を除去し、第３の層間絶縁層３４ｃを形成し、フォトリソグラフィ技術と、これにより形成したフォトレジスト層をマスクにしてのボロン（Ｂ）などのアクセプタ不純物のイオン注入により、画素を構成するＳｉ柱２６ｄの上部にＰ＋領域４７を形成する。 Subsequently, the SiO 2 layers 39, 42a, 42b, and 42c are removed. Next, as shown in FIG. 2N, the surfaces of the Si pillars 26a, 26b, 26c, and 26d where the Si surface is exposed are oxidized to form SiO 2 layers 45a, 45b, 45c, and 45d.
Subsequently, the SiN layers 24a, 24b, 24c, 24d, and 38 are removed to form a third interlayer insulating layer 34c. Boron (B) using the photolithography technique and the photoresist layer formed thereby as a mask. The P + region 47 is formed on the Si pillar 26d constituting the pixel by ion implantation of acceptor impurities such as.
　続いて、図２Ｐに示すように、Ｓｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄ上のＳｉＯ２層２３ａ，２ｂ，２３ｃ，２３ｄと、第３の層間絶縁層３４ｃよりも上部にあるＳｉＯ２層を除去し、アルミニウム（Ａｌ）、タングステン（Ｗ）、窒化チタン（ＴｉＮ）、窒化タンタル（ＴａＮ）などの画素選択線導体層４８を形成し、その上に第４の層間絶縁層３４ｄを形成し、ゲート導体層３６ａ上にコンタクトホール５０ａを形成し、ＳＧＴを構成するＳｉ柱２６ａ，２６ｂ，２６ｃ上にコンタクトホール５０ｂ，５０ｃ，５０ｄを形成し、画素リセットゲート導体層３６ｂ上にコンタクトホール５０ｅを形成し、これらコンタクトホール５０ａ,５０ｂ，５０ｃ，５０ｄ，５０ｅを介して、ＳＧＴゲート導体層３６ａと第１層目金属配線層５１ａ、ＳＧＴを構成するＳｉ柱２６ａ，２６ｂ，２６ｃのＮ＋領域３７ａ、Ｐ＋領域３７ｂ，３７ｃと、第１層目金属配線層５１ｂ，５１ｃ，５１ｄと、リセットゲート導体層３６ｂと第１層目金属配線層５１ｅとの接続を行う。 Subsequently, as shown in FIG. 2P, Si pillars 26a, 26b, 26c, the SiO 2 layer 23a on the 26 d, 2b, 23c, and 23d, the SiO 2 layer at the top than the third interlayer insulating layer 34c is removed Then, a pixel selection line conductor layer 48 such as aluminum (Al), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN) is formed, and a fourth interlayer insulating layer 34d is formed thereon, and a gate A contact hole 50a is formed on the conductor layer 36a, contact holes 50b, 50c and 50d are formed on the Si pillars 26a, 26b and 26c constituting the SGT, and a contact hole 50e is formed on the pixel reset gate conductor layer 36b. Through the contact holes 50a, 50b, 50c, 50d, and 50e, the SGT gate conductor layer 36a and the first metal wiring layer 51a Si pillar 26a constituting the SGT, 26b, 26c of N + regions 37a, P + regions 37b, 37c and the first layer metal interconnection layers 51b, 51c, 51d and the reset gate conductor layer 36b and the first layer metal Connection to the wiring layer 51e is performed.
　続いて、図２Ｑに示すように、第５の層間絶縁層３４ｅを形成し、コンタクトホール５１ａ，５１ｂを形成し、このコンタクトホール５１ａ，５１ｂを介して、第１層目金属配線層５１ｃ、５１ｄと第２層目金属配線層５２とを接続する。 Subsequently, as shown in FIG. 2Q, a fifth interlayer insulating layer 34e is formed, contact holes 51a and 51b are formed, and the first metal wiring layers 51c and 51d are formed through the contact holes 51a and 51b. Are connected to the second metal wiring layer 52.
（第２の実施形態）
　以下、図３Ａ～図３Ｅを参照しながら、本発明の第２の実施形態に係る固体撮像装置について説明する。
　図３Ｅに、本実施形態に係る固体撮像装置の断面構造を示し、図３Ａ～図３Ｄに、これに至る製造方法を示す。また、図３Ａ～３Ｅは、図２Ａ～図２Ｑと同じく、図１Ｂの画素部とＣＭＯＳインバータ回路部平面図のＡ－Ａ’線に沿った断面構造を示す。第1の実施形態では、Ｎチャネル・ＰチャネルＳＧＴゲート導体層７ａが、同じ材料で繋がって形成されていたのに対し、本実施形態の固体撮像装置では、異なる材料で形成された複数のゲート導体層で構成されているという特徴を有する。例えば、ＮチャネルＳＧＴと画素のゲート導体層を同じ材料で形成し、ＰチャネルＳＧＴゲート導体層を異なる材料で形成される固体撮像装置に本発明の技術思想を適用したものである。 (Second Embodiment)
Hereinafter, a solid-state imaging device according to the second embodiment of the present invention will be described with reference to FIGS. 3A to 3E.
FIG. 3E shows a cross-sectional structure of the solid-state imaging device according to the present embodiment, and FIGS. 3A to 3D show a manufacturing method leading to this. 3A to 3E show a cross-sectional structure along the line AA ′ in the plan view of the pixel portion and CMOS inverter circuit portion in FIG. 1B, as in FIGS. 2A to 2Q. In the first embodiment, the N-channel / P-channel SGT gate conductor layer 7a is formed by being connected with the same material, whereas in the solid-state imaging device of the present embodiment, a plurality of gates formed with different materials. It is characterized by being composed of a conductor layer. For example, the technical idea of the present invention is applied to a solid-state imaging device in which an N-channel SGT and a pixel gate conductor layer are formed of the same material and a P-channel SGT gate conductor layer is formed of different materials.
　図３Ａは、図２Ｇにおける場合と同様に、Ｓｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄの外周部にＳｉＯ２、酸化ハフニウム（ＨｆＯ2)などの高誘電率絶縁材料によるゲート絶縁層３５ａ，３５ｂ，３５ｃ，３５ｄを形成し、第１の層間絶縁層３４ａ上のＳｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄを囲んで、例えばＣＶＤ（Chemical Vapor Deposition）法による多結晶Ｓｉ、タングステン（Ｗ）、コバルト（Ｃｏ）、白金（Ｐｔ）、シリサイド材料による導体層３６を形成する。それ以前の工程は、図２Ａ～図２Ｆで説明した工程と同じである。そして、全体にＳｉＮ層５５を堆積する。その後、ＮチャネルＳＧＴ部と画素部を覆うように、フォトリソグラフィ技術を用いてフォトレジスト層５６ａ．５６ｂを形成する。 In FIG. 3A, as in the case of FIG. 2G, the gate insulating layers 35a, 35b, and 35c made of a high dielectric constant insulating material such as SiO 2 and hafnium oxide (HfO 2 ) are disposed on the outer periphery of the Si pillars 26a, 26b, 26c, and 26d. , 35d and surrounding the Si pillars 26a, 26b, 26c, 26d on the first interlayer insulating layer 34a, for example, polycrystalline Si, tungsten (W), cobalt (Co) by CVD (Chemical Vapor Deposition) method Then, a conductor layer 36 of platinum (Pt) and a silicide material is formed. The previous steps are the same as those described with reference to FIGS. 2A to 2F. Then, a SiN layer 55 is deposited on the entire surface. Thereafter, the photoresist layers 56a.. Are covered by photolithography so as to cover the N channel SGT portion and the pixel portion. 56b is formed.
　次に、図３Ｂに示すように、フォトレジスト層５６ａ，５６ｂをマスクにしてＳｉＮ層５５と導体層３６をエッチングする。この場合、ＳｉＮ層５５のエッチングでは、フォトレジスト層５６ａ，５６ｂの覆われている領域より内側にサイドエッチングされるようにエッチングしてＳｉＮ層５５ａ，５５ｂを形成する。
　続いて、フォトレジスト層５６ａ，５６ｂを除去する。これによって、ＮチャネルＳＧＴ部を覆うＮチャネルＳＧＴ部導体層５７ａと、画素部を覆う画素部導体層５７ｂとを形成する。 Next, as shown in FIG. 3B, the SiN layer 55 and the conductor layer 36 are etched using the photoresist layers 56a and 56b as a mask. In this case, in the etching of the SiN layer 55, the SiN layers 55a and 55b are formed by etching so as to be side-etched inside the regions covered with the photoresist layers 56a and 56b.
Subsequently, the photoresist layers 56a and 56b are removed. Thus, an N channel SGT part conductor layer 57a covering the N channel SGT part and a pixel part conductor layer 57b covering the pixel part are formed.
　続いて、図３Ｃに示すように、構造物の全体を覆うように第２の導体層５８を形成する。 Subsequently, as shown in FIG. 3C, a second conductor layer 58 is formed so as to cover the entire structure.
　続いて、図３Ｄに示すように、ＰチャネルＳＧＴ部を覆うように、フォトリソグラフィ技術を用いてフォトレジスト層５９を形成する。
　続いて、このフォトレジスト層５９をマスクに、第２の導体層５８をエッチングして、ＰチャネルＳＧＴ部導体層５８ａを形成する。その後、フォトレジスト層５９を除去する。ここでのＳｉＮ層５５ａ，５５ｂは、導体層５８のエッチングにおけるＮチャネルＳＧＴ部導体層５７ａと画素部導体層５７ｂのエッチング保護膜の役割を果たしている。 Subsequently, as shown in FIG. 3D, a photoresist layer 59 is formed by using a photolithography technique so as to cover the P channel SGT portion.
Subsequently, with the photoresist layer 59 as a mask, the second conductor layer 58 is etched to form a P-channel SGT portion conductor layer 58a. Thereafter, the photoresist layer 59 is removed. The SiN layers 55a and 55b here serve as etching protective films for the N-channel SGT portion conductor layer 57a and the pixel portion conductor layer 57b in the etching of the conductor layer 58.
　これによって、図３Ｅに示すように、ＮチャネルＳＧＴ部を覆うＮチャネルＳＧＴ部導体層５７ａと、ＰチャネルＳＧＴ部を覆うＰチャネルＳＧＴ部導体層５８ａと、画素部を覆う画素部導体層５７ｂとが形成される。ＮチャネルＳＧＴ部導体層５７ａとＰチャネルＳＧＴ部導体層５８ａとは、この２つの導体層５７ａ，５８ａとの境界部６０において、互いに重なり、かつ電気的に接続される。続いて、ＳｉＮ層５５ａ，５５ｂを除去する。 As a result, as shown in FIG. 3E, an N-channel SGT portion conductor layer 57a covering the N-channel SGT portion, a P-channel SGT portion conductor layer 58a covering the P-channel SGT portion, and a pixel portion conductor layer 57b covering the pixel portion. Is formed. The N channel SGT part conductor layer 57a and the P channel SGT part conductor layer 58a overlap each other and are electrically connected at a boundary part 60 between the two conductor layers 57a and 58a. Subsequently, the SiN layers 55a and 55b are removed.
　それ以後、図２Ｈ～図２Ｑに示す工程と同じ工程を経ることにより、図３Ｆに示す断面構造が形成される。第１の層間絶縁層３４ａをマスクにしてＮチャネルＳＧＴ部導体層５７ａと、ＰチャネルＳＧＴ部導体層５８ａと、画素部導体層５７ｂをエッチングしてＮチャネルＳＧＴ部ゲート導体層５７ａａ、ＰチャネルＳＧＴ部ゲート導体層５８ｂｂ、画素部リセットゲート導体層５７ｂｂを形成する。これによって、ＮチャネルＳＧＴゲート導体層５７ａａ、ＰチャネルＳＧＴゲート導体層５８ｂｂ、画素部リセットゲート導体層５７ｂｂが、ＮチャネルＳＧＴを構成するＳｉ柱２６ａの外周のゲート絶縁層３５ａと、ＰャネルＳＧＴを構成するＳｉ柱２６ｂ，２６ｃの外周のゲート絶縁層３５ｂ，３５ｃと、画素を構成するＳｉ柱の外周のゲート絶縁層３５ｄと、を囲み、同じ第１の層間絶縁層３４ａ上に配線されて形成される。 Thereafter, through the same steps as those shown in FIGS. 2H to 2Q, the cross-sectional structure shown in FIG. 3F is formed. N channel SGT part conductor layer 57a, P channel SGT part conductor layer 58a, and pixel part conductor layer 57b are etched using first interlayer insulating layer 34a as a mask to form N channel SGT part gate conductor layer 57aa and P channel SGT. The part gate conductor layer 58bb and the pixel part reset gate conductor layer 57bb are formed. As a result, the N channel SGT gate conductor layer 57aa, the P channel SGT gate conductor layer 58bb, and the pixel portion reset gate conductor layer 57bb are connected to the gate insulating layer 35a on the outer periphery of the Si pillar 26a constituting the N channel SGT and the P channel SGT. Surrounding the gate insulating layers 35b and 35c on the outer periphery of the Si pillars 26b and 26c constituting and the gate insulating layer 35d on the outer periphery of the Si pillar constituting the pixel, and formed by wiring on the same first interlayer insulating layer 34a Is done.
　図３Ｆの断面構造図は、図２Ｑのそれに対して、ＰチャネルＳＧＴ部ゲート導体層５８ｂｂが、ＮチャネルＳＧＴ部ゲート導体層５７ａａ、画素部ゲート導体層５７ｂｂと材料が異なる以外は同じである。これによって、本発明の第２の実施形態は、第１の実施形態と同じ特徴を有する。 3F is the same as FIG. 2Q except that the P-channel SGT part gate conductor layer 58bb is different from the N-channel SGT part gate conductor layer 57aa and the pixel part gate conductor layer 57bb. Thus, the second embodiment of the present invention has the same features as the first embodiment.
　また、ＮチャネルＳＧＴを構成するＳｉ柱２６ａのＰ領域３３ａａ、ＰチャネルＳＧＴを構成するＳｉ柱２６ｂｂ，２６ｃｃのＮ領域３３ｂ，３３ｃ、画素を構成するＳｉ柱のＰ領域３３ｄは真性型であってもよい。この場合、Ｎチャネル・ＰチャネルＳＧＴ、画素リセットトランジスタの閾値電圧をゲート導体層５７ａａ，５８ｂｂ，５７ｂｂの仕事関数の違いにより設定する。ここでは、第１の実施形態における図２Ｅ、図２Ｆによって説明した、Ｐ領域３３ａ，３３ｄ、Ｎ領域３３ｂ，３３ｃを形成するためのフォトリソグラフィ工程と、アクセプタ不純物とドナー不純物のイオン注入工程とが不要となる。 In addition, the P region 33aa of the Si pillar 26a constituting the N channel SGT, the Si pillar 26bb constituting the P channel SGT, the N regions 33b and 33c of 26cc, and the P region 33d of the Si pillar constituting the pixel are intrinsic types. Also good. In this case, the threshold voltages of the N channel / P channel SGT and the pixel reset transistor are set according to the work functions of the gate conductor layers 57aa, 58bb, and 57bb. Here, the photolithography process for forming the P regions 33a and 33d and the N regions 33b and 33c described with reference to FIGS. 2E and 2F in the first embodiment, and the ion implantation process of acceptor impurities and donor impurities are performed. It becomes unnecessary.
（第３の実施形態）
　以下、図４Ａ～図４Ｄを参照しながら、本発明の第３の実施形態に係る固体撮像装置について説明する。図４Ｄに本実施形態に係る固体撮像装置の断面構造を示し、図４Ａ～図４Ｃに、図４Ｄに至る製造方法を示す。また、図４Ａ～図４Ｄは、図２Ａ～図２Ｑと同様に、図１Ｂの画素部と、ＣＭＯＳインバータ回路部平面図のＡ－Ａ’線に沿った断面構造とを示す。
　第１の実施形態を説明した図１Ｃでは、ＳＧＴを構成するＳｉ柱４ａ，４ｂ，４ｃの上部にあるＮチャネルＳＧＴのドレインであるＮ＋領域８ａ，ＰチャネルＳＧＴのドレインであるＰ＋領域８ｂ、８ｃは、Ｓｉ柱４ａ，４ｂ，４ｃの上面から、コンタクトホール１１ａ，１１ｂ，１１ｃを介して、第１層目金属配線層１２ｂ，１２ｃ，１２ｄと接続されている。この場合、Ｎチャネル・ＰチャネルＳＧＴのドレイン抵抗は、Ｎ＋領域８ａ、Ｐ＋領域８ｂ，８ｃの抵抗値により決定される。この抵抗値は、小さいほど望ましい。本実施形態は、Ｎ＋領域８ａ、Ｐ＋領域８ｂ，８ｃの上部をシリサイド層にすることで、その電気抵抗値を小さくしている特徴を有する。 (Third embodiment)
Hereinafter, a solid-state imaging device according to a third embodiment of the present invention will be described with reference to FIGS. 4A to 4D. FIG. 4D shows a cross-sectional structure of the solid-state imaging device according to the present embodiment, and FIGS. 4A to 4C show a manufacturing method leading to FIG. 4D. 4A to 4D show the pixel portion of FIG. 1B and the cross-sectional structure along the line AA ′ in the plan view of the CMOS inverter circuit portion, as in FIGS. 2A to 2Q.
In FIG. 1C illustrating the first embodiment, the N + region 8a which is the drain of the N channel SGT and the P + region 8b which is the drain of the P channel SGT above the Si pillars 4a, 4b and 4c constituting the SGT. , 8c are connected to the first metal wiring layers 12b, 12c, 12d through the contact holes 11a, 11b, 11c from the upper surfaces of the Si pillars 4a, 4b, 4c. In this case, the drain resistance of the N channel / P channel SGT is determined by the resistance values of the N + region 8a and the P + regions 8b and 8c. The smaller the resistance value, the better. The present embodiment is characterized in that the electrical resistance value is reduced by forming the upper portion of the N + region 8a and the P + regions 8b and 8c as a silicide layer.
　図４Ａに、図２ＭにおけるＳｉＮ層３８を第１の層間絶縁層３４ａ上に形成する前までの工程を、図２Ａ～図２Ｌと同じ工程で形成し、新たなＳｉＮ層３８ａを第１の層間絶縁層３４ａ上に形成し、図２Ｍ、図２Ｎに示す工程と同じ工程を経てＮチャネルＳＧＴを構成するＳｉ柱２６ａの上部にＮ＋領域３７ａ、ＰチャネルＳＧＴを構成するＳｉ柱２６ｂ、２６ｃの上部にＰ＋領域２６ｂ，２６ｃ、画素を構成するＳｉ柱２６ｄの上部の外周部にＮ領域４３、画素を構成するＳｉ柱２６ｄの上面にＰ＋領域４７をそれぞれ形成し、Ｓｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄの外周部に絶縁層４５ａ，４５ｂ，３５ｃ，４５ｄを形成した場合の断面構造を示す。 In FIG. 4A, the process before the SiN layer 38 in FIG. 2M is formed on the first interlayer insulating layer 34a is formed in the same process as in FIGS. 2A to 2L, and a new SiN layer 38a is formed in the first interlayer insulating layer 34a. The N + region 37a and the Si pillars 26b and 26c constituting the P channel SGT are formed on the insulating layer 34a and formed on the Si pillar 26a constituting the N channel SGT through the same process as shown in FIGS. 2M and 2N. P + regions 26b and 26c are formed on the upper portion, an N region 43 is formed on the outer periphery of the upper portion of the Si pillar 26d constituting the pixel, and a P + region 47 is formed on the upper surface of the Si pillar 26d constituting the pixel. , 26c, and 26d, the cross-sectional structure in the case where the insulating layers 45a, 45b, 35c, and 45d are formed on the outer peripheral portion is shown.
　次に、図４Ｂに示すように、Ｎチャネル・ＰチャネルＳＧＴを構成するＳｉ柱２６ａ，２６ｂ，２６ｃの外周にある絶縁層４５ａ，４５ｂ，４５ｃを除去する。 Next, as shown in FIG. 4B, the insulating layers 45a, 45b, 45c on the outer periphery of the Si pillars 26a, 26b, 26c constituting the N-channel / P-channel SGT are removed.
　続いて、図４Ｃに示すように、例えばタングステン（Ｗ）、白金（Ｐｔ）、ニッケル（Ｎｉ）、コバルト（Ｃｏ）、またはこれらを含む金属層５４で構造物の全体を被覆するとともに熱処理を行い、Ｎチャネル・ＰチャネルＳＧＴを構成するＳｉ柱２６ａ，２６ｂ，２６ｃにシリサイド層５５ａ，５５ｂ，５５ｃを形成する。このとき、シリサイドとＳｉでのアクセプタ・ドナー不純物の偏析係数の違いによる雪かき効果（Snow-plow effect）により、シリサイド層５５ａ，５５ｂ，５５ｃの下方にＮ＋領域５６ａ、Ｐ＋領域５６ｂ，５６ｃが形成される。その後、金属層５４を除去する。 Subsequently, as shown in FIG. 4C, the entire structure is covered with, for example, tungsten (W), platinum (Pt), nickel (Ni), cobalt (Co), or a metal layer 54 containing these, and heat treatment is performed. The silicide layers 55a, 55b, and 55c are formed on the Si pillars 26a, 26b, and 26c constituting the N channel / P channel SGT. At this time, due to the snow-plow effect due to the difference in the segregation coefficients of acceptor / donor impurities between silicide and Si, N + regions 56a and P + regions 56b and 56c are formed below the silicide layers 55a, 55b and 55c. It is formed. Thereafter, the metal layer 54 is removed.
　その後、図２Ｎ～図２Ｑに示した工程と同じ工程を経て、図４Ｄに示す断面構造が得られる。 Thereafter, the cross-sectional structure shown in FIG. 4D is obtained through the same steps as those shown in FIGS. 2N to 2Q.
　これにより、Ｎ＋領域５６ａ、Ｐ＋領域５６ｂ，５６ｃはＮチャネル・ＰチャネルＳＧＴのドレインとなり、これらＮ＋領域５６ａ、Ｐ＋領域５６ｂ，５６ｃと第１層目金属配線層５１ｂ，５１ｃ，５１ｄとの間は、電気抵抗値がより低いシリサイド層５５ａ，５５ｂ，５５ｃを介して行われる。 As a result, the N + region 56a and the P + regions 56b and 56c become the drains of the N channel / P channel SGT, and the N + region 56a, the P + regions 56b and 56c, and the first metal wiring layers 51b, 51c and 51d. Is performed through silicide layers 55a, 55b, and 55c having lower electrical resistance values.
（第４の実施形態）
　以下、図５を参照しながら、本発明の第４の実施形態に係る固体撮像装置について説明する。 (Fourth embodiment)
Hereinafter, a solid-state imaging device according to a fourth embodiment of the present invention will be described with reference to FIG.
　本実施形態では、図５に示すように、Ｎ＋領域５５ａ、Ｐ＋領域５５ｂ、及びＰ＋領域５５ｃを囲むように、例えばタングステン（Ｗ）、白金（Ｐｔ）、ニッケル（Ｎｉ）、コバルト（Ｃｏ）、またはこれらを含む金属層５６ａ，５６ｂ，５６ｃが形成されている。これによって、チャネル３３ａａ，３３ｂｂ，３３ｃｃの上端から第１層目金属配線層５１ｂ，５１ｃ，５１ｄ間の接続は、電気抵抗値がより低い金属層５６ａ，５６ｂ，５６ｃを介して行われるようになる。これにより、第４の実施形態と同じ効果が得られる。 In the present embodiment, as shown in FIG. 5, for example, tungsten (W), platinum (Pt), nickel (Ni), and cobalt (N) are enclosed so as to surround the N + region 55 a, the P + region 55 b, and the P + region 55 c. Co) or metal layers 56a, 56b and 56c containing them. As a result, the connection between the upper ends of the channels 33aa, 33bb and 33cc and the first metal wiring layers 51b, 51c and 51d is made through the metal layers 56a, 56b and 56c having lower electrical resistance values. . Thereby, the same effect as the fourth embodiment can be obtained.
　なお、金属層５６ａ，５６ｂ，５６ｃを形成するとき、同時に、画素を構成するＳｉ柱２６ｄの上面にあるＰ＋領域に接続し、画素を構成するＳｉ柱２６ｄの外周に形成したＳｉＯ２層４５ｄを囲む画素選択線金属層５６ｄを形成することで、図１Ｃにおける画素選択線導体層１０８ａを、別途形成する必要がない。さらに、ここでは、画素選択線導体層１０８ａが光電変換領域であるフォトダイオード部のＮ領域４３を囲むように形成されることにより、画素を構成するＳｉ柱２６ｄに斜め方向から入射した光線が、互いに隣接する画素を構成するＳｉ柱に入射することにより発生するカラー撮像での混色、解像度低下を防止できるという特徴がある。 Note that when forming the metal layers 56a, 56b, and 56c, the SiO 2 layer 45d formed on the outer periphery of the Si pillar 26d constituting the pixel is connected to the P + region on the upper surface of the Si pillar 26d constituting the pixel at the same time. By forming the pixel selection line metal layer 56d surrounding the pixel selection line, it is not necessary to separately form the pixel selection line conductor layer 108a in FIG. 1C. Further, here, the pixel selection line conductor layer 108a is formed so as to surround the N region 43 of the photodiode portion which is a photoelectric conversion region, so that light incident on the Si pillar 26d constituting the pixel from an oblique direction can be obtained. There is a feature that it is possible to prevent color mixing and a decrease in resolution in color imaging caused by being incident on Si pillars constituting adjacent pixels.
（第５の実施形態）
　以下、図６を参照しながら、本発明の第５の実施形態に係る固体撮像装置について説明する。 (Fifth embodiment)
Hereinafter, a solid-state imaging device according to a fifth embodiment of the present invention will be described with reference to FIG.
　図４Ｄに示す第３の実施形態においては、ＮチャネルＳＧＴにおけるドレインのＮ＋領域５６ａ、ＰチャネルＳＧＴにおけるドレインのＰ＋領域５６ｂ，５６ｃ上に、シリサイド層５５ａ，５５ｂ，５５ｃを設けることによって、ドレインのＮ＋領域５６ａ、Ｐ＋領域５６ｂ，５６ｃと第１層目金属配線層５１ｂ，５１ｃ，５１ｄ間の電気抵抗値を低くさせていた。これに対し、本実施形態では、図６に示すように、シリサイド層５５ａ，５５ｂ，５５ｃの代わりに銅（Ｃｕ)の金属層５８ａ，５８ｂ，５８ｃを形成していることを特徴としている。これによって、ドレインのＮ＋領域５６ａ、Ｐ＋領域５６ｂ，５６ｃと第１層目金属配線層５１ｂ，５１ｃ，５１ｄとの間の電気抵抗値をさらに低くすることができる。なお、Ｃｕ金属層５８ａ，５８ｂ，５８ｃをダマシン（Damascene）技術により形成する場合には、Ｃｕ金属層５８ａ，５８ｂ，５８ｃと絶縁層５７ａ，５７ｂ，５７ｃとの間、Ｎ＋領域５６ａ、Ｐ＋領域５６ｂ，５６ｃの上面に、Ｃｕ金属層５８ａ，５８ｂ，５８ｃとの反応・拡散を防止するとともに、Ｃｕ金属層５８ａ，５８ｂ，５８ｃの付着力を保つためのＴｉＮ、ＴａＮ、Ｃｕなどの材料層によるバリヤ・シード層５９ａ，５９ｂ，５９ｃが形成される。 In the third embodiment shown in FIG. 4D, silicide layers 55a, 55b, and 55c are provided on the drain N + region 56a in the N channel SGT and the drain P + regions 56b and 56c in the P channel SGT. The electrical resistance values between the drain N + region 56a and P + regions 56b and 56c and the first metal wiring layers 51b, 51c and 51d are lowered. In contrast, the present embodiment is characterized in that copper (Cu) metal layers 58a, 58b, and 58c are formed in place of the silicide layers 55a, 55b, and 55c, as shown in FIG. As a result, the electrical resistance value between the drain N + region 56a and P + regions 56b and 56c and the first metal wiring layers 51b, 51c and 51d can be further reduced. When the Cu metal layers 58a, 58b, and 58c are formed by the damascene technique, the N + regions 56a and P + are interposed between the Cu metal layers 58a, 58b, and 58c and the insulating layers 57a, 57b, and 57c. A material layer such as TiN, TaN, or Cu for preventing reaction / diffusion with the Cu metal layers 58a, 58b, 58c and maintaining adhesion of the Cu metal layers 58a, 58b, 58c on the upper surfaces of the regions 56b, 56c. Thus, barrier seed layers 59a, 59b and 59c are formed.
（第６の実施形態）
　以下、図７Ａ～図７Ｃを参照しながら、本発明の第６の実施形態に係る固体撮像装置について説明する。図７Ｃは、本実施形態の固体撮像装置の断面構造図を示し、図７Ａ、図７Ｂに、それに至る製造方法を示す。
　図１Ｃに示す第１の実施形態においては、Ｎチャネル・ＰチャネルＳＧＴゲート導体層７ａ、画素のリセットゲート導体層１０５ａが、深いコンタクトホール９ａ，９ｂを介して第１層目金属配線層１２ａ，１２ｅに接続されていた。これらコンタクトホール９ａ，９ｅは、Ｎチャネル・ＰチャネルＳＧＴゲート導体層７ａ、画素のリセットゲート導体層１０５ａ上の第１・第２・第３の層間絶縁層１４ａ，１４ｂ，１４ｃをエッチングして形成する。この場合、深いコンタクトホール９ａ，９ｂのエッチングを制御良くＮチャネル・ＰチャネルＳＧＴゲート導体層７ａ、画素のリセットゲート導体層１０５ａ上で停止する必要がある。また、このときのオーバーエッチングにＮチャネル・ＰチャネルＳＧＴゲート導体層７ａ、画素のリセットゲート導体層１０５ａが除去されないように、Ｎチャネル・ＰチャネルＳＧＴゲート導体層７ａ、画素のリセットゲート導体層７ｂの厚さを厚くする必要がある。このような製造上の困難性を、本実施形態はより改善できるものである。 (Sixth embodiment)
Hereinafter, a solid-state imaging device according to a sixth embodiment of the present invention will be described with reference to FIGS. 7A to 7C. FIG. 7C shows a cross-sectional structure diagram of the solid-state imaging device of the present embodiment, and FIGS. 7A and 7B show a manufacturing method leading to that.
In the first embodiment shown in FIG. 1C, the N-channel / P-channel SGT gate conductor layer 7a and the reset gate conductor layer 105a of the pixel are connected to the first metal wiring layer 12a, deep contact holes 9a, 9b. 12e. These contact holes 9a and 9e are formed by etching the N-channel / P-channel SGT gate conductor layer 7a and the first, second and third interlayer insulating layers 14a, 14b and 14c on the reset gate conductor layer 105a of the pixel. To do. In this case, it is necessary to stop the etching of the deep contact holes 9a and 9b on the N-channel / P-channel SGT gate conductor layer 7a and the pixel reset gate conductor layer 105a with good control. Further, the N channel / P channel SGT gate conductor layer 7a and the pixel reset gate conductor layer 105a and the pixel reset gate conductor layer 7b are not removed by the overetching at this time. It is necessary to increase the thickness. This embodiment can further improve such manufacturing difficulties.
　ＳｉＯ２基板２１上に、画素信号線Ｎ＋領域３１ｃ、ＳＧＴ部のＮ＋領域３１ａ、Ｐ＋領域３１ｂと、画素を構成するＳｉ柱２６ｄ、ＳＧＴを構成するＳｉ柱２６ａ，２６ｂ，２６ｃと、これと同時にゲート導体層コンタクトを構成するＳｉ柱３１ｄ，３１ｅとＳｉ柱２６ｅ，２６ｆとをそれぞれ形成する（ゲート導体層コンタクトを構成するＳｉ柱２６ｅ，２６ｆ内部のＳｉ層３３ｅ，３３ｆはＰ型、Ｎ型、真性型のいずれであってもよい）。
　続いて、ゲート絶縁層３５ａ，３５ｂ，３５ｃ，３５ｄと同時に、ゲート導体層コンタクトを構成するＳｉ柱２６ｅ，２６ｆの外周部に絶縁層３５ｅ，３５ｆを形成する。
　続いて、第１の層間絶縁層３４ａを形成し、ＳＧＴゲート導体層３６ａａを、ＳＧＴを構成するＳｉ柱２６ａ，２６ｂ，２６ｃとゲート導体層コンタクトを構成するＳｉ柱２６ｅとを囲むように形成し、これと同様に、画素リセットゲート導体層３６ｂｂを画素を構成するＳｉ柱２６ｄとゲート導体層コンタクトを構成するＳｉ柱２６ｆとを囲むように形成する。ゲート導体層３６ａａとリセットゲート導体層３６ｂｂとは、第１の層間絶縁層３４ａ上に配線され、Ｓｉ柱２６ａ，２６ｂ，２６ｃ，２６ｄ，２６ｅ，２６ｆを囲むように第２の層間絶縁層３４ｂと同じ高さで形成される。それ以前の工程は、図２Ａ～図２Ｉまでと基本的に同じ工程である。 On the SiO 2 substrate 21, the pixel signal line N + region 31 c, the N + region 31 a and the P + region 31 b of the SGT part, the Si pillar 26 d constituting the pixel, the Si pillars 26 a, 26 b and 26 c constituting the SGT, At the same time, Si pillars 31d and 31e and Si pillars 26e and 26f constituting the gate conductor layer contact are formed (the Si layers 33e and 33f inside the Si pillars 26e and 26f constituting the gate conductor layer contact are P-type, N-type or intrinsic type may be used).
Subsequently, simultaneously with the gate insulating layers 35a, 35b, 35c, and 35d, insulating layers 35e and 35f are formed on the outer peripheral portions of the Si pillars 26e and 26f constituting the gate conductor layer contact.
Subsequently, the first interlayer insulating layer 34a is formed, and the SGT gate conductor layer 36aa is formed so as to surround the Si pillars 26a, 26b, 26c constituting the SGT and the Si pillar 26e constituting the gate conductor layer contact. Similarly, the pixel reset gate conductor layer 36bb is formed so as to surround the Si pillar 26d constituting the pixel and the Si pillar 26f constituting the gate conductor layer contact. The gate conductor layer 36aa and the reset gate conductor layer 36bb are wired on the first interlayer insulating layer 34a, and the second interlayer insulating layer 34b so as to surround the Si pillars 26a, 26b, 26c, 26d, 26e, and 26f. Formed at the same height. The previous steps are basically the same as those shown in FIGS. 2A to 2I.
　続いて、図４Ｄに示す工程と同様の工程により、ＳＧＴを構成するＳｉ柱２６ａ，２６ｂ，２６ｃにシリサイド層５５ａ，５５ｂ，５５ｃとＳＧＴにおけるドレインのＮ＋領域５６ａ，Ｐ＋領域５６ｂ，５６ｃを形成し、さらにシリサイド層５５ａ，５５ｂ，５５ｃを除去する。
　これにより、図７Ｂに示すように、ＳＧＴを構成するＳｉ柱２６ａ，２６ｂ，２６ｃのドレインＮ＋領域５６ａ、Ｐ＋領域５６ｂ，５６ｃ上に孔６０ａ，６０ｂ，６０ｃを形成する。
　続いて、ゲート導体層コンタクトを構成するＳｉ柱２６ｅ，２６ｆのＳｉ層３３ｅ，３３ｆを、ゲート導体層３６ａａ、画素リセットゲート導体層３６ｂｂの上端位置より低い位置までエッチングする。
　そして、このエッチングにより露出したＳｉＯ２層３５ｅ，３５ｆを除去して、孔６０ｄ，６０ｅを形成する。
　その後、ダマシン（Damascene）技術によるＣｕ層６２の形成に必要となる、Ｃｕとの反応・拡散を防止し、Ｃｕ金属層６２の付着力を保つためのＴｉＮ,ＴａＮ，Ｃｕなどの導体材料層によるバリヤ・シード層６１を、孔６０ａ，６０ｂ，６０ｃ，６０ｄ，６０ｅ内部表面と第４の層間絶縁層３４ｄ上に形成する。
　そして、メッキ法によってＣｕ層６２を孔６０ａ，６０ｂ，６０ｃ，６０ｄ，６０ｅ内部と第４の層間絶縁層３４ｄ上とに形成する。これによって、ＳＧＴゲート導体層３３ａａ、画素リセットゲート導体層３６ｂｂが導体材料層であるバリヤ・シード層６１を介して、Ｃｕ層６２と電気的に接続される。 4D, the silicide layers 55a, 55b, and 55c and the drain N + regions 56a and P + regions 56b and 56c in the SGT are formed on the Si pillars 26a, 26b, and 26c constituting the SGT. Then, the silicide layers 55a, 55b, and 55c are removed.
Thereby, as shown in FIG. 7B, holes 60a, 60b, and 60c are formed on the drain N + region 56a and the P + regions 56b and 56c of the Si pillars 26a, 26b, and 26c constituting the SGT.
Subsequently, the Si layers 33e and 33f of the Si pillars 26e and 26f constituting the gate conductor layer contact are etched to a position lower than the upper end positions of the gate conductor layer 36aa and the pixel reset gate conductor layer 36bb.
Then, the SiO 2 layers 35e and 35f exposed by this etching are removed to form holes 60d and 60e.
After that, with a conductive material layer such as TiN, TaN, or Cu for preventing the reaction / diffusion with Cu and maintaining the adhesion of the Cu metal layer 62, which is necessary for the formation of the Cu layer 62 by the damascene technology. The barrier seed layer 61 is formed on the inner surfaces of the holes 60a, 60b, 60c, 60d, 60e and the fourth interlayer insulating layer 34d.
Then, a Cu layer 62 is formed in the holes 60a, 60b, 60c, 60d, and 60e and on the fourth interlayer insulating layer 34d by plating. As a result, the SGT gate conductor layer 33aa and the pixel reset gate conductor layer 36bb are electrically connected to the Cu layer 62 via the barrier / seed layer 61 which is a conductor material layer.
　次に、図７Ｃに示すように、Ｃｕ層６２とバリヤ・シード層６１をエッチングして第１層目金属配線層６２ａ，６２ｂ，６２ｃ，６２ｄ，６２ｅを形成する。
　続いて、第５の層間絶縁層３４ｅを構造物の全体に被覆し、ＰチャネルＳＧＴ第１層目金属配線層６２ｃ，６２ｄ上にコンタクトホール６３ａ，６３ｂを形成し、ＰチャネルＳＧＴ第１層目金属配線層６２ｃ，６２ｄと、第５の層間絶縁層３４ｅ上に形成する第２層目金属配線層６４と、を、コンタクトホール６３ａ，６３ｂを介して接続する。 Next, as shown in FIG. 7C, the Cu layer 62 and the barrier / seed layer 61 are etched to form first metal wiring layers 62a, 62b, 62c, 62d, and 62e.
Subsequently, the entire structure is covered with the fifth interlayer insulating layer 34e, contact holes 63a and 63b are formed on the P-channel SGT first-layer metal wiring layers 62c and 62d, and the P-channel SGT first-layer is formed. The metal wiring layers 62c and 62d are connected to the second metal wiring layer 64 formed on the fifth interlayer insulating layer 34e through contact holes 63a and 63b.
　本実施形態の固体撮像装置において、ゲート導体層コンタクトを構成するＳｉ柱２６ｅ，２６ｆのＳｉ層３３ｅ，３３ｆのエッチングについては、ゲート導体層３６ａａ、画素リセットゲート導体層３６ｂｂの上端位置より低い位置までエッチングすればよく、ＳｉＯ２基板２１上面までエッチングしてもよい。このため、このエッチング工程は容易となる。さらに、このエッチングでは、ＳＧＴゲート導体層３６ａａ、リセットゲート導体層３６ｂｂは、ＳｉＯ２層３５ｅ，３５ｆで保護されているために、図１Ｃに示す場合のように、ゲート導体層３６ａａ、画素リセットゲート導体層３６ｂｂを厚くすることが必要でない。 In the solid-state imaging device of this embodiment, the etching of the Si layers 33e and 33f of the Si pillars 26e and 26f constituting the gate conductor layer contact is performed to a position lower than the upper end positions of the gate conductor layer 36aa and the pixel reset gate conductor layer 36bb. may be etched, it may be etched until the SiO 2 substrate 21 upper surface. For this reason, this etching process becomes easy. Further, in this etching, since the SGT gate conductor layer 36aa and the reset gate conductor layer 36bb are protected by the SiO 2 layers 35e and 35f, as shown in FIG. 1C, the gate conductor layer 36aa, the pixel reset gate It is not necessary to increase the thickness of the conductor layer 36bb.
　本実施形態の特徴は、以下の諸点である。即ち、
　画素を構成するＳｉ柱２６ｄ、ＳＧＴを構成するＳｉ柱２６ａ，２６ｂ，２６ｃと同時に、画素を構成するＳｉ柱２６ｄ、ＳＧＴを構成するＳｉ柱２６ａ，２６ｂ，２６ｃと同じ高さのＳＧＴゲート導体層３６ａａ、画素のリセットゲート導体層３６ｂｂを構成するＳｉ柱２６ｅ，２６ｆが形成されている点、
　ＳＧＴゲート導体層３６ａａ，画素リセットゲート導体層３６ｂｂが、Ｓｉ柱２６ｅ，２６ｆの内部のＳｉ層３３ｅ，３３ｆに置換されて形成されたＣｕで形成された第２層目金属配線層６２ａ、６２ｅと直接に接続されている点、
　ＳＧＴゲート導体層３６ａａ，画素リセットゲート導体層３６ｂｂが、ゲート導体層コンタクトを構成するＳｉ柱２６ｅ，２６ｆ、画素を構成するＳｉ柱２６ｄ、ＳＧＴを構成するＳｉ柱２６ａ，２６ｂ，２６ｃを囲むように、同時に、かつ、同じ高さで形成されている点、である。
　これによって、上述したような、製造上の容易化が実現される。 The features of this embodiment are the following points. That is,
A SGT gate conductor layer having the same height as the Si pillars 26d and SGTs constituting the pixels and the Si pillars 26a, 26b and 26c constituting the pixels, simultaneously with the Si pillars 26d and SGTs constituting the pixels. 36aa, Si pillars 26e and 26f constituting the reset gate conductor layer 36bb of the pixel are formed,
Second metal wiring layers 62a and 62e made of Cu formed by replacing the SGT gate conductor layer 36aa and the pixel reset gate conductor layer 36bb with the Si layers 33e and 33f inside the Si pillars 26e and 26f, and Directly connected point,
The SGT gate conductor layer 36aa and the pixel reset gate conductor layer 36bb surround the Si pillars 26e and 26f constituting the gate conductor layer contact, the Si pillar 26d constituting the pixel, and the Si pillars 26a, 26b and 26c constituting the SGT. , Simultaneously and at the same height.
This facilitates the manufacturing process as described above.
　なお、図７Ａ～図７Ｃに示す工程においては、シリサイド層５５ａ，５５ｂ，５５ｃを全て除去したが、ドレインＮ＋領域５６ａ、Ｐ＋領域５６ｂ，５６ｃ上の一部のシリサイドを残存させてもよい。
　また、シリサイド層５５ａ，５５ｂ，５５ｃは、それに代えて、図１Ｃに示すようなＮ＋領域８ａ、Ｐ＋領域８ｂ，８ｃであってもよい。
　また、孔６０ａ，６０ｂ，６０ｃ，６０ｄ，６０ｅの内部に形成する金属材料は、Ｃｕに代えて、Ｗ、Ｃｏ、Ｎｉ、Ｔｉまたはこれらの物質を含む導体材料層であっても良い。 7A to 7C, the silicide layers 55a, 55b, and 55c are all removed. However, some silicide on the drain N + region 56a and the P + regions 56b and 56c may remain. .
Further, the silicide layers 55a, 55b, and 55c may be replaced with N + regions 8a and P + regions 8b and 8c as shown in FIG. 1C.
Further, the metal material formed inside the holes 60a, 60b, 60c, 60d, and 60e may be a conductive material layer containing W, Co, Ni, Ti, or these substances instead of Cu.
　なお、第１～第６の実施形態では、画素領域には画素を構成する島状半導体Ｐ１１～Ｐ３３が存在し、ＳＧＴは、駆動出力回路に存在する場合について説明したが、画素領域の画素に隣接するように、ＳＧＴが形成されている場合においても、本発明の技術思想が適用できることは言うまでもない。 In the first to sixth embodiments, the island-shaped semiconductors P11 to P33 constituting the pixel are present in the pixel region, and the SGT is present in the drive output circuit. However, the SGT is present in the pixel region. Needless to say, the technical idea of the present invention can be applied even when the SGTs are formed adjacent to each other.
　第１～第６の実施形態における画素を構成する島状半導体Ｐ１１では、画素を構成する島状半導体を構成するＳｉ柱Ｐ１１の外周部の表層にフォトダイオードを構成するＮ領域８ｄ，４３が形成されている場合としたが、暗電流・ノイズ低減のため、Ｎ領域８ｄ，４３の外周部であって画素を構成するＳｉ柱Ｐ１１の表層に、信号電荷（自由電子）と逆極性の電荷（正孔）を蓄積するＰ＋領域を形成することもできる。 In the island-like semiconductor P11 constituting the pixel in the first to sixth embodiments, the N regions 8d and 43 constituting the photodiode are formed on the outer surface of the Si pillar P11 constituting the island-like semiconductor constituting the pixel. However, in order to reduce dark current and noise, the charge on the surface of the Si pillar P11 that forms the pixel on the outer periphery of the N regions 8d and 43 is opposite to the signal charge (free electrons). It is also possible to form a P + region that accumulates (holes).
　ＳＧＴゲート導体層７ａ，３６ａ，３６ａａと同時に、かつ同じ高さで形成される画素リセットゲート導体層７ｂ，３６ｂ，３６ｂｂは、フォトダイオードに蓄積された信号電荷の信号線Ｎ＋領域２，３１ｃへの除去のためでなく、光遮蔽層として設けられているものであってもよい。 The pixel reset gate conductor layers 7b, 36b, and 36bb formed at the same height as the SGT gate conductor layers 7a, 36a, and 36aa are connected to the signal line N + regions 2 and 31c of the signal charges accumulated in the photodiode. It may be provided as a light shielding layer instead of removing the light.
　図７Ａ～図７Ｃを参照して、ＳＧＴゲート導体層３６ａａ、画素リセットゲート導体層３６ｂｂを、ゲート導体層コンタクトを構成するＳｉ柱２６ｅ，２６ｆに形成されたＣｕ層６２を介して第１層目金属配線層６２ａ，６２ｅに接続した場合について説明したが、例えば図１Ｂの模式平面図において、画素リセットゲート導体層７ｂ（図７Ｃにおけるゲート導体層３６ｂｂ）とＳＧＴソースＮ＋領域３ａ（図７ＣにおけるＮ＋領域３１ａ）、Ｐ＋領域３ｂ（図７ＣにおけるＰ＋領域３１ｂｂ）とを、コンタクトホール９と、第１層目金属配線層１２ｅとを介して接続する場合にも、本発明の技術思想を適用できる。この場合には、コンタクトホール９部上にコンタクトを構成するＳｉ柱を形成し、図７Ａ～図７Ｃと同様な方法によって、画素リセットゲート導体層７ｂ（図７Ｃにおけるゲート導体層３６ｂｂ）とＳＧＴソースＮ＋領域３ａ（図７ＣにおけるＮ＋領域３１ａ）、Ｐ＋領域３ｂ（図７ＣにおけるＰ＋領域３１ｂｂ）との接続が行なえる。 7A to 7C, the SGT gate conductor layer 36aa and the pixel reset gate conductor layer 36bb are connected to the first layer via the Cu layer 62 formed on the Si pillars 26e and 26f constituting the gate conductor layer contact. The case where the metal wiring layers 62a and 62e are connected has been described. For example, in the schematic plan view of FIG. 1B, the pixel reset gate conductor layer 7b (gate conductor layer 36bb in FIG. 7C) and the SGT source N + region 3a (in FIG. 7C). N + region 31a) and P + region 3b (P + region 31bb in FIG. 7C) are connected to each other via contact hole 9 and first metal wiring layer 12e. Can be applied. In this case, a Si pillar constituting a contact is formed on the contact hole 9 and the pixel reset gate conductor layer 7b (the gate conductor layer 36bb in FIG. 7C) and the SGT source are formed in the same manner as in FIGS. 7A to 7C. Connection to the N + region 3a (N + region 31a in FIG. 7C) and the P + region 3b (P + region 31bb in FIG. 7C) can be made.
　なお、本発明は、本発明の広義の精神と範囲を逸脱することなく、様々な実施形態及び変形が可能とされるものである。また、上述した実施形態は、本発明の一実施例を説明するためのものであり、本発明の範囲を限定するものではない。 The present invention is capable of various embodiments and modifications without departing from the broad spirit and scope of the present invention. Further, the above-described embodiment is for describing an example of the present invention, and does not limit the scope of the present invention.
　本発明は、固体撮像装置、ＳＧＴなどの柱状半導体に回路素子を形成した半導体装置に広く適用できる。 The present invention can be widely applied to semiconductor devices in which circuit elements are formed in columnar semiconductors such as solid-state imaging devices and SGTs.
　Ｐ１１～Ｐ３３、４ａ、４ｂ、４ｃ、２６ａ、２６ｂ、２６ｃ、２６ｄ　島状半導体
　１、２１　基板
　３ａ、３１ａ　ＳＧＴソースＮ＋領域（ソース用板状半導体Ｎ＋領域）
　３ｂ、３１ｂ　ＳＧＴソースＰ＋領域（ソース用板状半導体Ｐ＋領域）
　４ａａ、４ｂｂ　ＰチャネルＳＧＴ
　４ｃｃ　ＮチャネルＳＧＴ
　６ａ、６ｂ、６ｃ、６ｄ、３５ａ、３５ｂ、３５ｃ、３５ｄ　ゲート絶縁層
　７ａ、３６ａ　ゲート導体層
　８ａ　ドレインＮ＋領域
　８ｂ、８ｃ　ドレインＰ＋領域
　９ａ、９ｂ、１１ａ、１１ｂ、１１ｃ　コンタクトホール
　１０　Ｐ＋領域
　１２ａ、１２ｂ、１２ｃ、１２ｄ、１２ｅ、５１ａ、５１ｂ、５１ｃ、５１ｄ、５１ｅ　第１層目金属配線層
　１４ａ、３４ａ　第１の層間絶縁層
　１４ｂ、３４ｂ　第２の層間絶縁層
　１４ｃ、３４ｃ　第３の層間絶縁層
　１４ｄ、３４ｄ　第４の層間絶縁層
　１４ｅ、３４ｅ　第５の層間絶縁層
　１６、５２　第２層目金属配線層
　２３ａ、２３ｂ、２３ｃ、２ｄ、２５ａ、２５ｂ、２５ｃ、２５ｄ、２７ａ、２７ｂ、２７ｃ、２７ｄ、３９　ＳｉＯ２層（酸化シリコン層）
　２４ａ、２４ｂ、２４ｃ、２４ｅ、３８、４０、４３、５５、５５ａ、５５ｂ　ＳｉＮ層
　３１ｃ、１０２ａ　信号線Ｎ＋領域
　３２、３７ａ、３７ｂ、４１、５６ａ、５６ｂ　フォトレジスト層
　３３ａ、３３ｄ　Ｐ領域
　３３ｂ、３３ｃ　Ｎ領域
　３６　導体層
　３６ａ、５７ａ、５８ａ　ゲート導体層
　３６ｂ、５７ｂ　リセットゲート導体層
　４２ａ、４２ｂ、４２ｃ　ドナーまたはアクセプタ不純物を含んだＳｉＯ２層
　４３　フォトダイオードＮ領域
　５５ａ、５５ｂ、５５ｃ　シリサイド層
　５８ａ、５８ｂ、５８ｃ、６２、　Ｃｕ層
　１０５ａ、３６ｂ　リセットゲート導体層
　１０８ａ　画素選択線導体層 P11 to P33, 4a, 4b, 4c, 26a, 26b, 26c, 26d Island- like semiconductor 1, 21 Substrate 3a, 31a SGT source N + region (source plate-like semiconductor N + region)
3b, 31b SGT source P + region (source plate semiconductor P + region)
4aa, 4bb P channel SGT
4cc N channel SGT
6a, 6b, 6c, 6d, 35a, 35b, 35c, 35d Gate insulating layer 7a, 36a Gate conductor layer 8a Drain N + region 8b, 8c Drain P + region 9a, 9b, 11a, 11b, 11c Contact hole 10P + Regions 12a, 12b, 12c, 12d, 12e, 51a, 51b, 51c, 51d, 51e First-layer metal wiring layers 14a, 34a First interlayer insulating layers 14b, 34b Second interlayer insulating layers 14c, 34c Third Interlayer insulating layers 14d, 34d Fourth interlayer insulating layers 14e, 34e Fifth interlayer insulating layers 16, 52 Second metal wiring layers 23a, 23b, 23c, 2d, 25a, 25b, 25c, 25d, 27a, 27b, 27c, 27d, 39 SiO 2 layer (silicon oxide layer)
24a, 24b, 24c, 24e, 38, 40, 43, 55, 55a, 55b SiN layer 31c, 102a Signal line N + region 32, 37a, 37b, 41, 56a, 56b Photoresist layer 33a, 33d P region 33b, 33c N region 36 Conductor layer 36a, 57a, 58a Gate conductor layer 36b, 57b Reset gate conductor layer 42a, 42b, 42c SiO 2 layer containing donor or acceptor impurities 43 Photodiode N region 55a, 55b, 55c Silicide layer 58a, 58b, 58c, 62, Cu layer 105a, 36b Reset gate conductor layer 108a Pixel selection line conductor layer

Claims (9)

  1. 　２次元状に配置された画素と、前記画素を駆動するとともに、前記画素からの信号を読み出す駆動出力回路と、を有する固体撮像装置において、
    　前記画素は、基板上に形成された第１の島状半導体を有し、
    　前記駆動出力回路は、前記基板上に、前記第１の島状半導体と同じ高さになるように形成された少なくとも１つの第２の島状半導体を有し、
    　前記第１の島状半導体は、
    　前記第１の島状半導体の底部に形成された第１の半導体領域と、
    　前記第１の半導体領域上に形成され、前記第１の半導体領域と反対導電型、または真性型の半導体からなる第２の半導体領域と、
    　前記第２の半導体領域の下部、かつ、外周に形成された第１のゲート絶縁層と、
    　前記第１のゲート絶縁層を囲むように形成された第１のゲート導体層と、
    　前記第１のゲート導体層に隣接する前記第２の半導体領域の外周部に形成され、前記第１の半導体領域と同じ導電型の半導体からなる第３の半導体領域と、
    　前記第３の半導体領域及び前記第２の半導体領域上に形成され、前記第１の半導体領域と反対の導電型の半導体からなる第４の半導体領域とを、有し、
    　前記第２の島状半導体は、
    　前記第２の島状半導体の下部に形成された第５の半導体領域と、
    　前記第５の半導体領域上に形成され、前記第５の半導体領域と反対導電型、または真性型の半導体からなる第６の半導体領域と、
    　前記第６の半導体領域の外周に形成された第２のゲート絶縁層を囲むように形成された第２のゲート導体層と、
    　前記第６の半導体領域上に、前記第２のゲート導体層に隣接するように、かつ、前記第２の半導体領域の上方に位置するように形成された第７の半導体領域とを、有し、
    　前記第１のゲート導体層及び前記第２のゲート導体層は、それぞれの底部が同じ面上に位置している、
    　ことを特徴とする固体撮像装置。     In a solid-state imaging device having two-dimensionally arranged pixels, and a drive output circuit that drives the pixels and reads signals from the pixels,
    The pixel has a first island-shaped semiconductor formed on a substrate,
    The drive output circuit has at least one second island-shaped semiconductor formed on the substrate to have the same height as the first island-shaped semiconductor,
    The first island-shaped semiconductor is
    A first semiconductor region formed at the bottom of the first island-shaped semiconductor;
    A second semiconductor region formed on the first semiconductor region and made of a semiconductor having a conductivity type opposite to that of the first semiconductor region or an intrinsic type;
    A first gate insulating layer formed at a lower portion and an outer periphery of the second semiconductor region;
    A first gate conductor layer formed so as to surround the first gate insulating layer;
    A third semiconductor region formed on the outer periphery of the second semiconductor region adjacent to the first gate conductor layer and made of a semiconductor having the same conductivity type as the first semiconductor region;
    A fourth semiconductor region formed on the third semiconductor region and the second semiconductor region and made of a semiconductor having a conductivity type opposite to the first semiconductor region;
    The second island-shaped semiconductor is
    A fifth semiconductor region formed under the second island-shaped semiconductor;
    A sixth semiconductor region formed on the fifth semiconductor region and made of a semiconductor having a conductivity type opposite to that of the fifth semiconductor region or an intrinsic type;
    A second gate conductor layer formed so as to surround a second gate insulating layer formed on the outer periphery of the sixth semiconductor region;
    A seventh semiconductor region formed on the sixth semiconductor region so as to be adjacent to the second gate conductor layer and to be positioned above the second semiconductor region; ,
    The first gate conductor layer and the second gate conductor layer have their bottoms located on the same plane,
    A solid-state imaging device.
  2. 　前記第１のゲート導体層及び前記第２のゲート導体層の高さが互いに同じである、
    　ことを特徴とする請求項１に記載の固体撮像装置。     The first gate conductor layer and the second gate conductor layer have the same height;
    The solid-state imaging device according to claim 1.
  3. 　前記第２のゲート導体層が、複数の前記第２の島状半導体の内の一部の前記第２の島状半導体を囲むように形成された第３のゲート導体層と、複数の前記第２の島状半導体の内において、前記第３のゲート導体層が囲む前記第２の島状半導体とは異なる前記第２の島状半導体を囲むように形成され、前記第３のゲート導体層と異なる材料からなる第４のゲート導体層と、から構成されている、
    　ことを特徴とする請求項１に記載の固体撮像装置。     A third gate conductor layer formed so as to surround a part of the second island-shaped semiconductors among the plurality of second island-shaped semiconductors; Among the two island-shaped semiconductors, the third gate conductor layer is formed so as to surround the second island-shaped semiconductor different from the second island-shaped semiconductor surrounded by the third gate conductor layer, A fourth gate conductor layer made of a different material, and
    The solid-state imaging device according to claim 1.
  4. 　前記第３のゲート導体層及び前記第４のゲート導体層の高さが互いに異なる、
    　ことを特徴とする請求項３に記載の固体撮像装置。     The third gate conductor layer and the fourth gate conductor layer have different heights from each other;
    The solid-state imaging device according to claim 3.
  5. 　前記第３のゲート導体層及び前記第４のゲート導体層の高さが互いに同じである、
    　ことを特徴とする請求項３に記載の固体撮像装置。     The third gate conductor layer and the fourth gate conductor layer have the same height;
    The solid-state imaging device according to claim 3.
  6. 　前記第２の島状半導体において、前記第６の半導体領域上に、前記第７の半導体領域が形成され、前記第７の半導体領域上に、シリサイド層又は金属層からなる導体層が形成されている、
    　ことを特徴とする請求項１に記載の固体撮像装置。     In the second island-shaped semiconductor, the seventh semiconductor region is formed on the sixth semiconductor region, and a conductor layer made of a silicide layer or a metal layer is formed on the seventh semiconductor region. Yes,
    The solid-state imaging device according to claim 1.
  7. 　前記第２の島状半導体において、前記第６の半導体領域を囲むように金属層が設けられている、
    　ことを特徴とする請求項１に記載の固体撮像装置。     In the second island-shaped semiconductor, a metal layer is provided so as to surround the sixth semiconductor region.
    The solid-state imaging device according to claim 1.
  8. 　前記第１の島状半導体及び前記第２の島状半導体と、当該第１及び第２の島状半導体と同じ高さに形成された第３の島状半導体と、を有し、
    　前記第１の島状半導体を囲むように形成された前記第１のゲート導体層と、前記第２の島状半導体を囲むように形成された前記第２のゲート導体層の内の少なくとも一方が、前記第３の島状半導体を囲むように延在しており、
    　前記第１のゲート導体層及び前記第２のゲート導体層の内の少なくとも一方が、前記第３の島状半導体の内部に形成された導体層と、前記第３の島状半導体の下方部位で電気的に接続されている、
    　ことを特徴とする請求項１に記載の固体撮像装置。     The first island-shaped semiconductor and the second island-shaped semiconductor, and a third island-shaped semiconductor formed at the same height as the first and second island-shaped semiconductor,
    At least one of the first gate conductor layer formed so as to surround the first island-shaped semiconductor and the second gate conductor layer formed so as to surround the second island-shaped semiconductor; , Extending around the third island-shaped semiconductor,
    At least one of the first gate conductor layer and the second gate conductor layer is a conductor layer formed inside the third island-shaped semiconductor, and a lower portion of the third island-shaped semiconductor. Electrically connected,
    The solid-state imaging device according to claim 1.
  9. 　前記第３の島状半導体の内部に形成された導体層が、前記第１の半導体領域及び前記第５の半導体領域の内の少なくとも一方と、前記第３の島状半導体の下方部位で接続されている、
    　ことを特徴とする請求項１に記載の固体撮像装置。     A conductor layer formed inside the third island-shaped semiconductor is connected to at least one of the first semiconductor region and the fifth semiconductor region at a lower portion of the third island-shaped semiconductor. ing,
    The solid-state imaging device according to claim 1.
PCT/JP2011/070534 2011-09-08 2011-09-08 Solid-state image pickup device WO2013035189A1 (en)

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