WO2012132614A1 - Dispositif de conversion photoélectrique - Google Patents

Dispositif de conversion photoélectrique Download PDF

Info

Publication number
WO2012132614A1
WO2012132614A1 PCT/JP2012/053838 JP2012053838W WO2012132614A1 WO 2012132614 A1 WO2012132614 A1 WO 2012132614A1 JP 2012053838 W JP2012053838 W JP 2012053838W WO 2012132614 A1 WO2012132614 A1 WO 2012132614A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
amorphous silicon
region
type amorphous
silicon layer
Prior art date
Application number
PCT/JP2012/053838
Other languages
English (en)
Japanese (ja)
Inventor
護 有本
大樹 橋口
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Publication of WO2012132614A1 publication Critical patent/WO2012132614A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a photoelectric conversion device.
  • a so-called back junction type solar cell is proposed in which a p-type semiconductor region and an n-type semiconductor region are formed on the back side of the solar cell, and the p-side electrode and the n-side electrode are electrically separated by a separation groove ( Patent Document 1).
  • Patent Document 1 A so-called back junction type solar cell is proposed in which a p-type semiconductor region and an n-type semiconductor region are formed on the back side of the solar cell, and the p-side electrode and the n-side electrode are electrically separated by a separation groove.
  • the photoelectric conversion device includes a semiconductor substrate, a first amorphous semiconductor layer including a first conductivity type amorphous semiconductor layer formed on one surface of the semiconductor substrate, and one of the semiconductor substrates.
  • the photoelectric conversion device of the present invention it is possible to improve current extraction efficiency while preventing carrier recombination.
  • FIG. 1 is a diagram illustrating a planar shape pattern of an IN amorphous silicon layer and an IP amorphous silicon layer, omitting an n-side electrode and a p-side electrode in FIG.
  • FIG. 3 is an enlarged view of an N region in FIG. 2. It is an enlarged view of P area
  • FIG. 1 is a plan view of the photoelectric conversion device 10 as viewed from the back side.
  • the photoelectric conversion device 10 is formed on the back surface side of the photoelectric conversion unit 20 that generates carriers (electrons and holes) when light such as sunlight enters, and the photoelectric conversion unit 20.
  • An n-side electrode 40 and a p-side electrode 50 are provided. That is, the photoelectric conversion device 10 is a back surface junction type in which no electrode is present on the light receiving surface side.
  • carriers generated by the photoelectric conversion unit 20 are collected by the n-side electrode 40 and the p-side electrode 50, respectively.
  • the wiring material which is not illustrated is electrically connected to the n side electrode 40 and the p side electrode 50, and the photoelectric conversion apparatus 10 is modularized, A carrier is taken out as an electrical energy outside.
  • the “back surface” means a surface opposite to the “light receiving surface” which is a surface on which light is incident from the outside of the apparatus.
  • the surface on which the n-side electrode 40 and the p-side electrode 50 are formed is the back surface.
  • the n-side electrode 40 is an electrode that collects carriers (electrons) from the IN amorphous silicon layer 25 of the photoelectric conversion unit 20.
  • the p-side electrode 50 is an electrode that collects carriers (holes) from the IP amorphous silicon layer 26 of the photoelectric conversion unit 20.
  • Each electrode has a plurality of finger electrode portions 41 and 51 and bus bar electrode portions 42 and 52 connecting the corresponding finger electrode portions.
  • the photoelectric conversion unit 20 has an n-type single crystal silicon substrate 21 as a semiconductor substrate.
  • the semiconductor substrate for example, a crystalline silicon substrate, a gallium arsenide (GaAs) substrate, an indium phosphorus (InP) substrate, or the like can be applied.
  • the crystalline semiconductor substrate may be, for example, an n-type polycrystalline silicon substrate or a p-type single crystal or polycrystalline silicon substrate, but it is preferable to use the n-type single crystal silicon substrate 21 exemplified in this embodiment. It is.
  • the n-type single crystal silicon substrate 21 functions as a power generation layer and has a thickness of 100 to 300 ⁇ m, for example.
  • a texture structure (not shown) is preferably formed on the light receiving surface 11 of the n-type single crystal silicon substrate 21.
  • the “texture structure” is an uneven structure that suppresses surface reflection and increases the light absorption amount of the photoelectric conversion unit 20.
  • a pyramidal (quadrangular pyramid or quadrangular frustum-shaped) uneven structure obtained by performing anisotropic etching on the light receiving surface 11 having a (100) plane can be exemplified.
  • FIG. 2 is a cross-sectional view taken along line AA in FIG.
  • an i-type amorphous silicon film 22, an n-type amorphous silicon layer 23, and a protective layer 24 are sequentially formed on the light-receiving surface 11 side of the n-type single crystal silicon substrate 21.
  • the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23 function as a passivation layer.
  • the protective layer 24 protects the passivation layer and has an antireflection function.
  • the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23 are laminated, for example, over the entire region excluding the edge region of the light receiving surface 11 of the n-type single crystal silicon substrate 21.
  • the i-type amorphous silicon layer 22 is a thin film layer of intrinsic amorphous silicon and has a thickness of about 0.5 nm to 50 nm.
  • the n-type amorphous silicon layer 23 is an amorphous silicon thin film layer doped with phosphorus (P) or the like, for example, and has a thickness of about 1 nm to 50 nm.
  • the protective layer 24 is stacked on substantially the entire area on the n-type amorphous silicon layer 23.
  • the protective layer 24 is preferably made of a material having high light transmittance.
  • the protective layer 24 is preferably an insulating layer made of, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), or silicon oxynitride (SiON), and a SiN layer is particularly suitable.
  • the thickness of the protective layer 24 can be appropriately changed in consideration of antireflection characteristics and the like, but for example, about 80 nm to 1 ⁇ m is preferable.
  • an IN amorphous silicon layer 25 (hereinafter referred to as an IN layer 25) and an IP amorphous silicon layer 26 (hereinafter referred to as an IP layer) are formed on the back surface 12 side of the n-type single crystal silicon substrate 21. 26).
  • An insulating layer 31 is provided between the IN layer 25 and the IP layer 26.
  • the IN layer 25 is a thin film layer that forms an n-type amorphous semiconductor region (hereinafter referred to as an N region).
  • the IN layer 25 includes a first i-type amorphous silicon layer 27a and a second i-type amorphous silicon layer 27b stacked on the back surface 12 of the n-type single crystal silicon substrate 21, and an i-type amorphous layer.
  • a first n-type amorphous silicon layer 28a stacked on the silicon layer 27a and a second n-type amorphous silicon layer 28b stacked on the i-type amorphous silicon layer 27b are included.
  • the i-type amorphous silicon layers 27a and 27b can be formed with the same composition as that of the i-type amorphous silicon layer 22, for example.
  • the n-type amorphous silicon layers 28a and 28b can be formed with the same composition as the n-type amorphous silicon layer 23, for example, and have a thickness of about 1 nm to 50 nm.
  • the IP layer 26 is a thin film layer that forms a p-type amorphous semiconductor region (hereinafter referred to as a P region). The P region can have a larger lamination area than the N region.
  • the IP layer 26 includes an i-type amorphous silicon layer 29 stacked on the back surface 12 of the n-type single crystal silicon substrate 21 and a first p-type amorphous silicon stacked on the i-type amorphous silicon layer 29.
  • a p-type amorphous silicon layer 30b stacked on the p-type amorphous silicon layer 30a and the back surface 12 of the n-type single crystal silicon substrate 21.
  • the i-type amorphous silicon layer 29 can be formed with the same composition as the i-type amorphous silicon layer 22 and the i-type amorphous silicon layers 27a and 27b, for example.
  • the p-type amorphous silicon layers 30a and 30b are, for example, amorphous silicon thin films doped with boron (B) or the like, and have a thickness of about 1 nm to 50 nm.
  • the n-side electrode 40 is an electrode electrically connected to the IN layer 25 and is mainly formed on the IN layer 25.
  • the p-side electrode 50 is an electrode formed so as to be separated from the n-side electrode 40 and electrically connected to the IP layer 26, and is formed on the IP layer 26.
  • a separation groove 60 that separates both electrodes is formed between the n-side electrode 40 and the p-side electrode 50.
  • the laminated area of each electrode corresponds to the laminated area of the IN layer 25 and the IP layer 26, and the p-side electrode 50 has a larger laminated area than the n-side electrode 40.
  • the n-side electrode 40 and the p-side electrode 50 are each composed of a laminate of first conductive layers 43 and 53, second conductive layers 44 and 54, third conductive layers 45 and 55, and fourth conductive layers 46 and 56.
  • the first conductive layer 43, the second conductive layer 44, the third conductive layer 45, and the fourth conductive layer 46 are n-side conductive layers.
  • the fourth conductive layer 56 is a p-side conductive layer.
  • the first conductive layers 43 and 53 are constituted by a transparent conductive layer.
  • the second conductive layers 44 and 54 are composed of a metal layer, and for example, copper (Cu) is used from the viewpoint of electrical conductivity and material cost.
  • the first conductive layers 43 and 53 and the second conductive layers 44 and 54 are formed by sputtering.
  • the transparent conductive layer is, for example, at least one of metal oxides such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), and titanium oxide (TiO 2 ) having a polycrystalline structure. It is preferable that it is comprised including seeds.
  • These metal oxides contain dopants such as tin (Sn), zinc (Zn), tungsten (W), antimony (Sb), titanium (Ti), aluminum (Al), cerium (Ce), and gallium (Ga).
  • ITO in which In 2 O 3 is doped with Sn is particularly preferable.
  • the concentration of the dopant can be 0 to 20 wt%.
  • the metal layer is preferably about 50 nm to 1 ⁇ m thick, for example.
  • the metal layer is preferably made of a metal having high conductivity and high light reflectance.
  • a metal such as silver (Ag), aluminum (Al), titanium (Ti), copper (Cu), tin (Sn), or an alloy containing one or more of them can be used.
  • the second conductive layer 14 is preferably a Cu layer.
  • the first conductive layers 43 and 53 and the second conductive layers 44 and 54 function as seed layers serving as starting points when the third conductive layers 45 and 55 and the fourth conductive layers 46 and 56 are formed by plating.
  • the third conductive layers 45 and 55 are formed of a metal layer, and for example, copper (Cu) is used from the viewpoint of electrical conductivity and material cost.
  • the fourth conductive layers 46 and 56 are formed of a metal layer.
  • tin (Sn) is used to prevent corrosion of the first conductive layers 43 and 53, the second conductive layers 44 and 54, and the third conductive layers 45 and 55. ) Is used.
  • the configuration of the IN layer 25 and the IP layer 26 will be described in detail with further reference to FIGS.
  • the current extraction region 33 will be described in detail.
  • FIG. 3 shows a planar shape pattern of the IN layer 25 and the IP layer 26 (the region with cross-hatching is the overlapping region 32 where the insulating layer 31 is provided).
  • 4 is an enlarged view of an N region in FIG. 2
  • FIG. 5 is an enlarged view of a P region in FIG.
  • the IN layer 25 and the IP layer 26 have a comb-teeth shape or a stripe-like laminated form formed so as to mesh with each other.
  • the IN layers 25 and the IP layers 26 are preferably formed alternately along one direction parallel to the back surface 12 from the viewpoint of photoelectric conversion efficiency and the like.
  • the IN layer 25 and the IP layer 26 are preferably formed so as to cover a wide area on the back surface 12 of the n-type single crystal silicon substrate 21. For this reason, the edge region of the IP layer 26 is alternately stacked without a gap while overlapping the edge region of the IN layer 25. A region where the IN layer 25 and the IP layer 26 overlap will be referred to as an “overlapping region 32”.
  • the insulating layer 31 has a function of insulating the N region and the P region, and is provided between the IN layer 25 and the IP layer 26 in the overlapping region 32.
  • the insulating layer 31 for example, it can be formed with the same composition and the same thickness as the protective layer 24, and it is particularly preferable to apply a SiN layer.
  • the insulating layer 31 is not formed on the region where the IP layer 26 is not stacked. Thereby, the IN layer 25 and the n-side electrode 40 can be electrically connected while ensuring good insulation between the IN layer 25 and the IP layer 26.
  • the back surface 12 of the n-type single crystal silicon substrate 21 has a current extraction region 33 from which carriers are extracted by each electrode.
  • the current extraction region 33 is a region where each electrode is formed and a region on the back surface 12 where a layer for blocking carrier movement is not provided between each electrode.
  • the region where the amorphous silicon layer and the electrode are formed along the thickness direction of the n-type single crystal silicon substrate 21 functions as the current extraction region 33.
  • the region where the insulating layer 31 is stacked between the n-type single crystal silicon substrate 21 and the electrode (for example, the overlapping region 32). Does not function as the current extraction region 33.
  • the mobility of carriers in the amorphous silicon layer is small. That is, in the thickness direction of the n-type single crystal silicon substrate 21, the amorphous silicon layer is thin and the moving distance is short, so that carriers can sufficiently pass therethrough, but the surface direction of the amorphous silicon layer (on the back surface 12). This is because the carrier cannot move because it spreads greatly in the parallel direction.
  • a region where the insulating layer 31 is not provided becomes a current extraction region 33n from which carriers are extracted by the n-side electrode 40. That is, a region excluding the overlapping region 32 where the insulating layer 31 is provided between the IN layer 25 and the n-side electrode 40 is a current extraction region 33n.
  • An i-type amorphous silicon layer 27b and an n-type amorphous silicon layer 28b are formed in the current extraction region 33n.
  • an i-type amorphous silicon layer 27a and an n-type amorphous silicon layer 28a are formed.
  • the i-type amorphous silicon layer 27b and the n-type amorphous silicon layer 28b may be formed so as to cover the entire area on the n-type amorphous silicon layer 28a.
  • the total film thickness of the i-type amorphous silicon layer 27b and the n-type amorphous silicon layer 28b formed in the current extraction region 33n is equal to the i-type amorphous silicon layer formed in the overlapping region 32.
  • 27a and the total film thickness of the n-type amorphous silicon layer 28a is preferably made thinner than the i-type amorphous silicon layer 27a.
  • the thickness of the i-type amorphous silicon layer 27a is set from the viewpoint of passivation characteristics, and for example, about 0.5 nm to 50 nm is preferable.
  • the film thickness of the i-type amorphous silicon layer 27b is, for example, 2/3 to 1 / th of the film thickness of the i-type amorphous silicon layer 27a in consideration of passivation characteristics and current extraction efficiency. It is preferable to set it to about 3.
  • the n-type amorphous silicon layers 28 a and 28 b have a film thickness that provides necessary characteristics for the open-circuit voltage of the photoelectric conversion device 10 and the contact resistance with the n-side electrode 40.
  • the film thickness of the n-type amorphous silicon layer 28b is also made thinner than the film thickness of the n-type amorphous silicon layer 28a.
  • a region where the insulating layer 31 is not provided becomes a current extraction region 33p from which carriers are extracted by the p-side electrode 50. That is, a region excluding the overlapping region 32 where the insulating layer 31 is provided between the n-type single crystal silicon substrate 21 and the IP layer 26 becomes the current extraction region 33p.
  • a p-type amorphous silicon layer 30b is formed in the current extraction region 33p.
  • an i-type amorphous silicon layer 29 and a p-type amorphous silicon layer 30a are formed.
  • an i-type amorphous silicon layer 29, a p-type amorphous silicon layer 30a, and a p-type amorphous silicon layer 30b are sequentially stacked in part of the current extraction region 33p.
  • the p-type amorphous silicon layer 30b may be formed so as to cover the entire area on the p-type amorphous silicon layer 30a.
  • the current extraction region 33p is provided with a region where the p-type amorphous silicon layer 30b is directly stacked on the back surface 12 and the i-type amorphous silicon layer is not stacked.
  • the p-type amorphous silicon layers 30a and 30b can be formed with the same thickness, for example.
  • the film thickness of the amorphous silicon layer (p-type amorphous silicon layer 30b) in the current extraction region 33p becomes the same as that of the amorphous silicon layer (i-type amorphous silicon layer 29 and 29) formed in the overlapping region 32. It is thinner than the thickness of the p-type amorphous silicon layer 30a).
  • the film thickness of the amorphous silicon layer can be confirmed by, for example, cross-sectional observation with a scanning electron microscope (SEM) or a transmission electron microscope (TEM).
  • SEM scanning electron microscope
  • TEM transmission electron microscope
  • the film thickness of the amorphous silicon layer may be adjusted based on the maximum film thickness, for example, but is preferably adjusted based on the average film thickness.
  • FIG. 6 to 14 are diagrams showing manufacturing steps of the photoelectric conversion unit 20.
  • an i-type amorphous silicon layer 22 and an n-type amorphous silicon are formed on the light-receiving surface 11 of the n-type single crystal silicon substrate 21 by plasma enhanced chemical vapor deposition (PECVD) or sputtering.
  • PECVD plasma enhanced chemical vapor deposition
  • the layer 23 and the protective layer 24 are sequentially stacked, and the i-type amorphous silicon layer 27 a and the n-type amorphous silicon layer 28 a are sequentially stacked on the back surface 12.
  • a silane gas (SiH 4 ) diluted with hydrogen (H 2 ) can be used as a source gas.
  • phosphine (PH 3 ) added to silane (SiH 4 ) and diluted with hydrogen (H 2 ) can be used as a source gas.
  • the film quality of the i-type amorphous silicon films 22 and 27a and the n-type amorphous silicon films 23 and 28a can be changed by changing the hydrogen dilution rate of the silane gas.
  • the doping concentration of the n-type amorphous silicon films 23 and 28a can be changed by changing the mixed concentration of phosphine (PH 3 ).
  • the “texture structure” is an uneven structure that suppresses surface reflection and increases the light absorption amount of the photoelectric conversion unit 20.
  • a pyramidal (quadrangular pyramid or quadrangular pyramid-shaped) uneven structure obtained by performing anisotropic etching on the light receiving surface 11 having a (100) plane can be exemplified.
  • the texture structure can be formed, for example, by anisotropically etching the (100) plane using a potassium hydroxide (KOH) aqueous solution.
  • KOH potassium hydroxide
  • the i-type amorphous silicon layer 27a and the n-type amorphous silicon layer 28a are partially etched and removed.
  • the region to be etched is a region that becomes the current extraction region 33n and the current extraction region 33p.
  • a resist film formed by a screen printing or ink jet coating process, a photolithography process or the like is used as a mask.
  • an etchant for example, a sodium hydroxide (NaOH) aqueous solution (for example, 1 wt% NaOH aqueous solution) or the like is used.
  • the i-type amorphous silicon layer 27 b, the n-type amorphous silicon layer 28 b, and the insulating layer 31 are formed over the entire region excluding the edge region on the back surface 12 by, for example, PECVD.
  • PECVD plasma chemical vapor deposition
  • the i-type amorphous silicon layer 27b, the n-type amorphous silicon layer 28b, and the insulating layer 31 are stacked also on the n-type amorphous silicon layer 28a.
  • an i-type amorphous silicon layer 27b thinner than the i-type amorphous silicon layer 27a is formed in a region that becomes the current extraction region 33n.
  • the post-process is advanced so that the region where the i-type amorphous silicon layer 27b is directly formed on the back surface 12 becomes the current extraction region 33n.
  • the insulating layer 31, the i-type amorphous silicon layer 27b, and the n-type amorphous silicon layer 28b are partially etched and removed using the resist film 100 as a mask.
  • the region to be etched is a region that becomes the current extraction region 33p of the P region.
  • the edge layer 31 is etched using the resist film 100 as a mask.
  • the insulating layer 31 is silicon oxide (SiO 2 ), silicon nitride (SiN), or silicon oxynitride (SiON), for example, etching can be performed using an aqueous hydrogen fluoride (HF) solution.
  • HF aqueous hydrogen fluoride
  • the i-type amorphous silicon layer 27b and the n-type amorphous silicon layer 28b are etched using the patterned insulating layer 31 as a mask. By this step, patterning of the N region constituted by the IN layer 25 is completed.
  • an i-type amorphous silicon layer 29 and a p-type amorphous silicon layer 30 a are sequentially stacked over the entire region excluding the edge region on the back surface 12. That is, the i-type amorphous silicon layer 29 and the p-type amorphous silicon layer 30a are also stacked on the patterned N region via the insulating layer 31.
  • the i-type amorphous silicon layer 29 and the p-type amorphous silicon layer 30a are sequentially formed from the i-type amorphous silicon layer 29 and the p-type amorphous silicon layer 30a by PECVD or the like. It can be formed by film formation.
  • diborane (B 2 H 6 ) is used as a doping gas instead of phosphine (PH 3 ).
  • the i-type amorphous silicon layer 29 and the p-type amorphous silicon layer 30a are partially removed by etching using a resist film formed by screen printing or the like as a mask.
  • the region to be etched is, for example, a part of the region that becomes the current extraction region 33p, and the etching range can be adjusted as appropriate.
  • the IP layer 26 Since the IP layer 26 is usually harder to etch than the IN layer 25, the IP layer 26 has a higher concentration than the NaOH aqueous solution used for etching the IN layer 25 (for example, 10 wt% NaOH aqueous solution) or hydrofluoric acid (HF, HNO 3 ) (For example, 30 wt% each) is preferably used. Alternatively, it is also preferable to use an aqueous NaOH solution heated to about 70 to 90 ° C. (thermal alkali treatment).
  • the NaOH aqueous solution used for etching the IN layer 25 for example, 10 wt% NaOH aqueous solution
  • hydrofluoric acid HF, HNO 3
  • the p-type amorphous silicon layer 30 b is laminated over the entire region excluding the edge region on the back surface 12 by, for example, PECVD.
  • PECVD plasma-organic chemical vapor deposition
  • the IP layer 26 and the insulating layer 31 are partially removed by etching using a resist film formed by screen printing or the like as a mask to expose the IN layer 25.
  • the region of the IP layer 26 and the insulating layer 31 to be etched is a region on the region where the i-type amorphous silicon layer 27 b is directly formed on the back surface 12.
  • FIGS. 15 to 17 are diagrams showing the steps of forming the n-side electrode 40 and the p-side electrode 50.
  • a process of forming the third conductive layers 45 and 55 and the fourth conductive layers 46 and 56 of the respective electrodes by electrolytic plating using the second conductive layers 44 and 54 of the respective electrodes as a seed layer will be described.
  • the first conductive layer 13 and the second conductive layer 14 are sequentially formed on the IN layer 25 and the IP layer 26 by, for example, sputtering.
  • the first conductive layer 13 is stacked on substantially the entire area on the IN layer 25 and the IP layer 26.
  • the first conductive layer 13 is a layer that is patterned in a later step to become the first conductive layers 43 and 53 of each electrode.
  • the second conductive layer 14 is a layer that is patterned in a later step to become the second conductive layers 44 and 45 of each electrode.
  • the first conductive layer 13 and the second conductive layer 14 are partially etched to divide each layer, and the first conductive layers 43 and 53 and the first conductive layers 43 and 53 of each electrode separated from each other.
  • Two conductive layers 44 and 45 are formed.
  • Etching of the first conductive layer 13 and the second conductive layer 14 uses, for example, a resist film formed by screen printing or the like as a mask, and an aqueous solution containing ferric chloride (FeCl 3 ) and hydrochloric acid (HCl). To do.
  • the region to be etched is preferably a region on the overlapping region 32, for example.
  • the third conductive layers 45 and 55 are formed by electrolytic plating using the second conductive layers 44 and 45 as seed layers, respectively.
  • the fourth conductive layers 46 and 56 are formed on the third conductive layers 45 and 55 by electrolytic plating, so that the photoelectric conversion unit 20 is provided with the n-side electrode 40 and the p-side electrode 50 on the back surface side.
  • the conversion device 10 (see FIG. 2) is obtained.
  • the electroplating can be performed, for example, by flowing a current of the same magnitude through the second conductive layer 44 constituting the n-side electrode 40 and the second conductive layer 54 constituting the p-side electrode 50. In this case, a metal plating layer having the same mass is formed on the second conductive layers 44 and 54.
  • the thickness of the third conductive layer is increased. That is, the thickness of the n-side electrode 40 can be made thicker than the thickness of the p-side electrode 50 by carrying out electrolytic plating while flowing the same current.
  • the film thickness of the amorphous silicon layer formed in the current extraction region 33 is larger than the film thickness of the amorphous silicon layer formed in another region of the current extraction region 33. It is getting thinner. For this reason, in the current extraction region 33, the contact resistance can be reduced and the current extraction efficiency can be increased. In the other region of the current extraction region 33, the film thickness of the amorphous silicon layer is set to a film thickness that is suitable from the viewpoint of passivation characteristics, and carrier recombination is sufficiently prevented, and the lifetime of the carrier is reduced. Can be stretched.
  • the film thickness of the i-type amorphous silicon layer 27b in the current extraction region 33n is smaller than the film thickness of the i-type amorphous silicon layer 27a in other regions of the current extraction region 33n. . Therefore, in the current extraction region 33n, the contact resistance can be further reduced while exhibiting the passivation characteristics, and the current extraction efficiency can be further increased.
  • the photoelectric conversion device 10 can optimize the balance between the passivation characteristics and the current extraction efficiency.
  • the photoelectric conversion device 10 can increase photoelectric conversion efficiency by improving current extraction efficiency while preventing carrier recombination.
  • the film thickness of the amorphous silicon layer in the current extraction region is smaller than the film thickness of the amorphous silicon layer in other regions of the current extraction region in both the N region and the P region.
  • only one of the regions may have such a configuration.
  • the film thickness of the amorphous silicon layer in the current extraction region and other regions may be set to the same level.
  • the IP layer 26 is stacked after the IN layer 25 is stacked, but the IP layer 26 may be stacked first. In this case, a region where the i-type amorphous semiconductor layer is not provided may be formed in a part of the current extraction region 33n.

Landscapes

  • Engineering & Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Energy (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Sustainable Development (AREA)
  • Photovoltaic Devices (AREA)

Abstract

Le dispositif de conversion photoélectrique (10) de l'invention est équipé : d'un substrat de silicium monocristallin de type n (21); de couches IN (25) et de couches IP (26) formées sur une surface envers (12) située sur le substrat de silicium monocristallin de type n (21); d'une électrode côté n (40) électriquement connectée aux couches IN (25); et d'une électrode côté p (50) qui est séparée de l'électrode côté n (40), et qui est formée de manière à être électriquement connectée aux couches IP (26). Au moins une partie de l'épaisseur des couches IN (25) et des couches IP (26) qui sont formées dans une région hors courant électrique (33), est plus mince que l'épaisseur des couches IN (25) et des couches IP (26) correspondantes formées dans une autre région.
PCT/JP2012/053838 2011-03-25 2012-02-17 Dispositif de conversion photoélectrique WO2012132614A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011068441 2011-03-25
JP2011-068441 2011-03-25

Publications (1)

Publication Number Publication Date
WO2012132614A1 true WO2012132614A1 (fr) 2012-10-04

Family

ID=46930376

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/053838 WO2012132614A1 (fr) 2011-03-25 2012-02-17 Dispositif de conversion photoélectrique

Country Status (1)

Country Link
WO (1) WO2012132614A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013141232A1 (fr) * 2012-03-23 2013-09-26 三洋電機株式会社 Cellule solaire et procédé de fabrication de cette dernière
JPWO2015189878A1 (ja) * 2014-06-13 2017-04-20 国立大学法人福島大学 太陽電池及びその製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0613639A (ja) * 1992-06-24 1994-01-21 Sanyo Electric Co Ltd 光起電力装置
JP2003031831A (ja) * 2001-07-13 2003-01-31 Sanyo Electric Co Ltd 光起電力素子及びその製造方法
WO2009096539A1 (fr) * 2008-01-30 2009-08-06 Kyocera Corporation Élément de batterie solaire et procédé de fabrication d'élément de batterie solaire
WO2010104098A1 (fr) * 2009-03-10 2010-09-16 三洋電機株式会社 Procédé de fabrication d'une pile solaire, et pile solaire

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0613639A (ja) * 1992-06-24 1994-01-21 Sanyo Electric Co Ltd 光起電力装置
JP2003031831A (ja) * 2001-07-13 2003-01-31 Sanyo Electric Co Ltd 光起電力素子及びその製造方法
WO2009096539A1 (fr) * 2008-01-30 2009-08-06 Kyocera Corporation Élément de batterie solaire et procédé de fabrication d'élément de batterie solaire
WO2010104098A1 (fr) * 2009-03-10 2010-09-16 三洋電機株式会社 Procédé de fabrication d'une pile solaire, et pile solaire

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013141232A1 (fr) * 2012-03-23 2013-09-26 三洋電機株式会社 Cellule solaire et procédé de fabrication de cette dernière
JPWO2015189878A1 (ja) * 2014-06-13 2017-04-20 国立大学法人福島大学 太陽電池及びその製造方法

Similar Documents

Publication Publication Date Title
JP5879538B2 (ja) 光電変換装置及びその製造方法
JP5820988B2 (ja) 光電変換装置及びその製造方法
JP5705968B2 (ja) 光電変換装置及びその製造方法
US10134940B2 (en) Method of manufacturing solar cell
JP5891382B2 (ja) 光電変換素子の製造方法
US8877545B2 (en) Method of manufacturing solar cell
JP6179900B2 (ja) 太陽電池及びその製造方法
WO2012090643A1 (fr) Procédé de fabrication d'une cellule solaire, ainsi que cellule solaire
JP5884030B2 (ja) 光電変換装置の製造方法
US20140027875A1 (en) Photoelectric conversion device and method for producing photoelectric conversion device
JPWO2012132766A1 (ja) 光電変換装置及び光電変換装置の製造方法
WO2012132614A1 (fr) Dispositif de conversion photoélectrique
US20190207052A1 (en) Method of manufacturing solar cell, and solar cell
WO2012090650A1 (fr) Cellule solaire
US20170012164A1 (en) Method of forming electrode pattern and method of manufacturing solar cell
US10930810B2 (en) Solar cell and method of manufacturing solar cell
WO2012132834A1 (fr) Cellule solaire et procédé de production de cellule solaire
US8852982B2 (en) Photoelectric device and manufacturing method thereof
JP2015185658A (ja) 太陽電池の製造方法
WO2012132932A1 (fr) Cellule solaire et son procédé de fabrication

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12764947

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12764947

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP