WO2012132614A1 - Photoelectric converter - Google Patents

Photoelectric converter Download PDF

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Publication number
WO2012132614A1
WO2012132614A1 PCT/JP2012/053838 JP2012053838W WO2012132614A1 WO 2012132614 A1 WO2012132614 A1 WO 2012132614A1 JP 2012053838 W JP2012053838 W JP 2012053838W WO 2012132614 A1 WO2012132614 A1 WO 2012132614A1
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layer
amorphous silicon
region
type amorphous
silicon layer
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PCT/JP2012/053838
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French (fr)
Japanese (ja)
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護 有本
大樹 橋口
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三洋電機株式会社
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Publication of WO2012132614A1 publication Critical patent/WO2012132614A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a photoelectric conversion device.
  • a so-called back junction type solar cell is proposed in which a p-type semiconductor region and an n-type semiconductor region are formed on the back side of the solar cell, and the p-side electrode and the n-side electrode are electrically separated by a separation groove ( Patent Document 1).
  • Patent Document 1 A so-called back junction type solar cell is proposed in which a p-type semiconductor region and an n-type semiconductor region are formed on the back side of the solar cell, and the p-side electrode and the n-side electrode are electrically separated by a separation groove.
  • the photoelectric conversion device includes a semiconductor substrate, a first amorphous semiconductor layer including a first conductivity type amorphous semiconductor layer formed on one surface of the semiconductor substrate, and one of the semiconductor substrates.
  • the photoelectric conversion device of the present invention it is possible to improve current extraction efficiency while preventing carrier recombination.
  • FIG. 1 is a diagram illustrating a planar shape pattern of an IN amorphous silicon layer and an IP amorphous silicon layer, omitting an n-side electrode and a p-side electrode in FIG.
  • FIG. 3 is an enlarged view of an N region in FIG. 2. It is an enlarged view of P area
  • FIG. 1 is a plan view of the photoelectric conversion device 10 as viewed from the back side.
  • the photoelectric conversion device 10 is formed on the back surface side of the photoelectric conversion unit 20 that generates carriers (electrons and holes) when light such as sunlight enters, and the photoelectric conversion unit 20.
  • An n-side electrode 40 and a p-side electrode 50 are provided. That is, the photoelectric conversion device 10 is a back surface junction type in which no electrode is present on the light receiving surface side.
  • carriers generated by the photoelectric conversion unit 20 are collected by the n-side electrode 40 and the p-side electrode 50, respectively.
  • the wiring material which is not illustrated is electrically connected to the n side electrode 40 and the p side electrode 50, and the photoelectric conversion apparatus 10 is modularized, A carrier is taken out as an electrical energy outside.
  • the “back surface” means a surface opposite to the “light receiving surface” which is a surface on which light is incident from the outside of the apparatus.
  • the surface on which the n-side electrode 40 and the p-side electrode 50 are formed is the back surface.
  • the n-side electrode 40 is an electrode that collects carriers (electrons) from the IN amorphous silicon layer 25 of the photoelectric conversion unit 20.
  • the p-side electrode 50 is an electrode that collects carriers (holes) from the IP amorphous silicon layer 26 of the photoelectric conversion unit 20.
  • Each electrode has a plurality of finger electrode portions 41 and 51 and bus bar electrode portions 42 and 52 connecting the corresponding finger electrode portions.
  • the photoelectric conversion unit 20 has an n-type single crystal silicon substrate 21 as a semiconductor substrate.
  • the semiconductor substrate for example, a crystalline silicon substrate, a gallium arsenide (GaAs) substrate, an indium phosphorus (InP) substrate, or the like can be applied.
  • the crystalline semiconductor substrate may be, for example, an n-type polycrystalline silicon substrate or a p-type single crystal or polycrystalline silicon substrate, but it is preferable to use the n-type single crystal silicon substrate 21 exemplified in this embodiment. It is.
  • the n-type single crystal silicon substrate 21 functions as a power generation layer and has a thickness of 100 to 300 ⁇ m, for example.
  • a texture structure (not shown) is preferably formed on the light receiving surface 11 of the n-type single crystal silicon substrate 21.
  • the “texture structure” is an uneven structure that suppresses surface reflection and increases the light absorption amount of the photoelectric conversion unit 20.
  • a pyramidal (quadrangular pyramid or quadrangular frustum-shaped) uneven structure obtained by performing anisotropic etching on the light receiving surface 11 having a (100) plane can be exemplified.
  • FIG. 2 is a cross-sectional view taken along line AA in FIG.
  • an i-type amorphous silicon film 22, an n-type amorphous silicon layer 23, and a protective layer 24 are sequentially formed on the light-receiving surface 11 side of the n-type single crystal silicon substrate 21.
  • the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23 function as a passivation layer.
  • the protective layer 24 protects the passivation layer and has an antireflection function.
  • the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23 are laminated, for example, over the entire region excluding the edge region of the light receiving surface 11 of the n-type single crystal silicon substrate 21.
  • the i-type amorphous silicon layer 22 is a thin film layer of intrinsic amorphous silicon and has a thickness of about 0.5 nm to 50 nm.
  • the n-type amorphous silicon layer 23 is an amorphous silicon thin film layer doped with phosphorus (P) or the like, for example, and has a thickness of about 1 nm to 50 nm.
  • the protective layer 24 is stacked on substantially the entire area on the n-type amorphous silicon layer 23.
  • the protective layer 24 is preferably made of a material having high light transmittance.
  • the protective layer 24 is preferably an insulating layer made of, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), or silicon oxynitride (SiON), and a SiN layer is particularly suitable.
  • the thickness of the protective layer 24 can be appropriately changed in consideration of antireflection characteristics and the like, but for example, about 80 nm to 1 ⁇ m is preferable.
  • an IN amorphous silicon layer 25 (hereinafter referred to as an IN layer 25) and an IP amorphous silicon layer 26 (hereinafter referred to as an IP layer) are formed on the back surface 12 side of the n-type single crystal silicon substrate 21. 26).
  • An insulating layer 31 is provided between the IN layer 25 and the IP layer 26.
  • the IN layer 25 is a thin film layer that forms an n-type amorphous semiconductor region (hereinafter referred to as an N region).
  • the IN layer 25 includes a first i-type amorphous silicon layer 27a and a second i-type amorphous silicon layer 27b stacked on the back surface 12 of the n-type single crystal silicon substrate 21, and an i-type amorphous layer.
  • a first n-type amorphous silicon layer 28a stacked on the silicon layer 27a and a second n-type amorphous silicon layer 28b stacked on the i-type amorphous silicon layer 27b are included.
  • the i-type amorphous silicon layers 27a and 27b can be formed with the same composition as that of the i-type amorphous silicon layer 22, for example.
  • the n-type amorphous silicon layers 28a and 28b can be formed with the same composition as the n-type amorphous silicon layer 23, for example, and have a thickness of about 1 nm to 50 nm.
  • the IP layer 26 is a thin film layer that forms a p-type amorphous semiconductor region (hereinafter referred to as a P region). The P region can have a larger lamination area than the N region.
  • the IP layer 26 includes an i-type amorphous silicon layer 29 stacked on the back surface 12 of the n-type single crystal silicon substrate 21 and a first p-type amorphous silicon stacked on the i-type amorphous silicon layer 29.
  • a p-type amorphous silicon layer 30b stacked on the p-type amorphous silicon layer 30a and the back surface 12 of the n-type single crystal silicon substrate 21.
  • the i-type amorphous silicon layer 29 can be formed with the same composition as the i-type amorphous silicon layer 22 and the i-type amorphous silicon layers 27a and 27b, for example.
  • the p-type amorphous silicon layers 30a and 30b are, for example, amorphous silicon thin films doped with boron (B) or the like, and have a thickness of about 1 nm to 50 nm.
  • the n-side electrode 40 is an electrode electrically connected to the IN layer 25 and is mainly formed on the IN layer 25.
  • the p-side electrode 50 is an electrode formed so as to be separated from the n-side electrode 40 and electrically connected to the IP layer 26, and is formed on the IP layer 26.
  • a separation groove 60 that separates both electrodes is formed between the n-side electrode 40 and the p-side electrode 50.
  • the laminated area of each electrode corresponds to the laminated area of the IN layer 25 and the IP layer 26, and the p-side electrode 50 has a larger laminated area than the n-side electrode 40.
  • the n-side electrode 40 and the p-side electrode 50 are each composed of a laminate of first conductive layers 43 and 53, second conductive layers 44 and 54, third conductive layers 45 and 55, and fourth conductive layers 46 and 56.
  • the first conductive layer 43, the second conductive layer 44, the third conductive layer 45, and the fourth conductive layer 46 are n-side conductive layers.
  • the fourth conductive layer 56 is a p-side conductive layer.
  • the first conductive layers 43 and 53 are constituted by a transparent conductive layer.
  • the second conductive layers 44 and 54 are composed of a metal layer, and for example, copper (Cu) is used from the viewpoint of electrical conductivity and material cost.
  • the first conductive layers 43 and 53 and the second conductive layers 44 and 54 are formed by sputtering.
  • the transparent conductive layer is, for example, at least one of metal oxides such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), and titanium oxide (TiO 2 ) having a polycrystalline structure. It is preferable that it is comprised including seeds.
  • These metal oxides contain dopants such as tin (Sn), zinc (Zn), tungsten (W), antimony (Sb), titanium (Ti), aluminum (Al), cerium (Ce), and gallium (Ga).
  • ITO in which In 2 O 3 is doped with Sn is particularly preferable.
  • the concentration of the dopant can be 0 to 20 wt%.
  • the metal layer is preferably about 50 nm to 1 ⁇ m thick, for example.
  • the metal layer is preferably made of a metal having high conductivity and high light reflectance.
  • a metal such as silver (Ag), aluminum (Al), titanium (Ti), copper (Cu), tin (Sn), or an alloy containing one or more of them can be used.
  • the second conductive layer 14 is preferably a Cu layer.
  • the first conductive layers 43 and 53 and the second conductive layers 44 and 54 function as seed layers serving as starting points when the third conductive layers 45 and 55 and the fourth conductive layers 46 and 56 are formed by plating.
  • the third conductive layers 45 and 55 are formed of a metal layer, and for example, copper (Cu) is used from the viewpoint of electrical conductivity and material cost.
  • the fourth conductive layers 46 and 56 are formed of a metal layer.
  • tin (Sn) is used to prevent corrosion of the first conductive layers 43 and 53, the second conductive layers 44 and 54, and the third conductive layers 45 and 55. ) Is used.
  • the configuration of the IN layer 25 and the IP layer 26 will be described in detail with further reference to FIGS.
  • the current extraction region 33 will be described in detail.
  • FIG. 3 shows a planar shape pattern of the IN layer 25 and the IP layer 26 (the region with cross-hatching is the overlapping region 32 where the insulating layer 31 is provided).
  • 4 is an enlarged view of an N region in FIG. 2
  • FIG. 5 is an enlarged view of a P region in FIG.
  • the IN layer 25 and the IP layer 26 have a comb-teeth shape or a stripe-like laminated form formed so as to mesh with each other.
  • the IN layers 25 and the IP layers 26 are preferably formed alternately along one direction parallel to the back surface 12 from the viewpoint of photoelectric conversion efficiency and the like.
  • the IN layer 25 and the IP layer 26 are preferably formed so as to cover a wide area on the back surface 12 of the n-type single crystal silicon substrate 21. For this reason, the edge region of the IP layer 26 is alternately stacked without a gap while overlapping the edge region of the IN layer 25. A region where the IN layer 25 and the IP layer 26 overlap will be referred to as an “overlapping region 32”.
  • the insulating layer 31 has a function of insulating the N region and the P region, and is provided between the IN layer 25 and the IP layer 26 in the overlapping region 32.
  • the insulating layer 31 for example, it can be formed with the same composition and the same thickness as the protective layer 24, and it is particularly preferable to apply a SiN layer.
  • the insulating layer 31 is not formed on the region where the IP layer 26 is not stacked. Thereby, the IN layer 25 and the n-side electrode 40 can be electrically connected while ensuring good insulation between the IN layer 25 and the IP layer 26.
  • the back surface 12 of the n-type single crystal silicon substrate 21 has a current extraction region 33 from which carriers are extracted by each electrode.
  • the current extraction region 33 is a region where each electrode is formed and a region on the back surface 12 where a layer for blocking carrier movement is not provided between each electrode.
  • the region where the amorphous silicon layer and the electrode are formed along the thickness direction of the n-type single crystal silicon substrate 21 functions as the current extraction region 33.
  • the region where the insulating layer 31 is stacked between the n-type single crystal silicon substrate 21 and the electrode (for example, the overlapping region 32). Does not function as the current extraction region 33.
  • the mobility of carriers in the amorphous silicon layer is small. That is, in the thickness direction of the n-type single crystal silicon substrate 21, the amorphous silicon layer is thin and the moving distance is short, so that carriers can sufficiently pass therethrough, but the surface direction of the amorphous silicon layer (on the back surface 12). This is because the carrier cannot move because it spreads greatly in the parallel direction.
  • a region where the insulating layer 31 is not provided becomes a current extraction region 33n from which carriers are extracted by the n-side electrode 40. That is, a region excluding the overlapping region 32 where the insulating layer 31 is provided between the IN layer 25 and the n-side electrode 40 is a current extraction region 33n.
  • An i-type amorphous silicon layer 27b and an n-type amorphous silicon layer 28b are formed in the current extraction region 33n.
  • an i-type amorphous silicon layer 27a and an n-type amorphous silicon layer 28a are formed.
  • the i-type amorphous silicon layer 27b and the n-type amorphous silicon layer 28b may be formed so as to cover the entire area on the n-type amorphous silicon layer 28a.
  • the total film thickness of the i-type amorphous silicon layer 27b and the n-type amorphous silicon layer 28b formed in the current extraction region 33n is equal to the i-type amorphous silicon layer formed in the overlapping region 32.
  • 27a and the total film thickness of the n-type amorphous silicon layer 28a is preferably made thinner than the i-type amorphous silicon layer 27a.
  • the thickness of the i-type amorphous silicon layer 27a is set from the viewpoint of passivation characteristics, and for example, about 0.5 nm to 50 nm is preferable.
  • the film thickness of the i-type amorphous silicon layer 27b is, for example, 2/3 to 1 / th of the film thickness of the i-type amorphous silicon layer 27a in consideration of passivation characteristics and current extraction efficiency. It is preferable to set it to about 3.
  • the n-type amorphous silicon layers 28 a and 28 b have a film thickness that provides necessary characteristics for the open-circuit voltage of the photoelectric conversion device 10 and the contact resistance with the n-side electrode 40.
  • the film thickness of the n-type amorphous silicon layer 28b is also made thinner than the film thickness of the n-type amorphous silicon layer 28a.
  • a region where the insulating layer 31 is not provided becomes a current extraction region 33p from which carriers are extracted by the p-side electrode 50. That is, a region excluding the overlapping region 32 where the insulating layer 31 is provided between the n-type single crystal silicon substrate 21 and the IP layer 26 becomes the current extraction region 33p.
  • a p-type amorphous silicon layer 30b is formed in the current extraction region 33p.
  • an i-type amorphous silicon layer 29 and a p-type amorphous silicon layer 30a are formed.
  • an i-type amorphous silicon layer 29, a p-type amorphous silicon layer 30a, and a p-type amorphous silicon layer 30b are sequentially stacked in part of the current extraction region 33p.
  • the p-type amorphous silicon layer 30b may be formed so as to cover the entire area on the p-type amorphous silicon layer 30a.
  • the current extraction region 33p is provided with a region where the p-type amorphous silicon layer 30b is directly stacked on the back surface 12 and the i-type amorphous silicon layer is not stacked.
  • the p-type amorphous silicon layers 30a and 30b can be formed with the same thickness, for example.
  • the film thickness of the amorphous silicon layer (p-type amorphous silicon layer 30b) in the current extraction region 33p becomes the same as that of the amorphous silicon layer (i-type amorphous silicon layer 29 and 29) formed in the overlapping region 32. It is thinner than the thickness of the p-type amorphous silicon layer 30a).
  • the film thickness of the amorphous silicon layer can be confirmed by, for example, cross-sectional observation with a scanning electron microscope (SEM) or a transmission electron microscope (TEM).
  • SEM scanning electron microscope
  • TEM transmission electron microscope
  • the film thickness of the amorphous silicon layer may be adjusted based on the maximum film thickness, for example, but is preferably adjusted based on the average film thickness.
  • FIG. 6 to 14 are diagrams showing manufacturing steps of the photoelectric conversion unit 20.
  • an i-type amorphous silicon layer 22 and an n-type amorphous silicon are formed on the light-receiving surface 11 of the n-type single crystal silicon substrate 21 by plasma enhanced chemical vapor deposition (PECVD) or sputtering.
  • PECVD plasma enhanced chemical vapor deposition
  • the layer 23 and the protective layer 24 are sequentially stacked, and the i-type amorphous silicon layer 27 a and the n-type amorphous silicon layer 28 a are sequentially stacked on the back surface 12.
  • a silane gas (SiH 4 ) diluted with hydrogen (H 2 ) can be used as a source gas.
  • phosphine (PH 3 ) added to silane (SiH 4 ) and diluted with hydrogen (H 2 ) can be used as a source gas.
  • the film quality of the i-type amorphous silicon films 22 and 27a and the n-type amorphous silicon films 23 and 28a can be changed by changing the hydrogen dilution rate of the silane gas.
  • the doping concentration of the n-type amorphous silicon films 23 and 28a can be changed by changing the mixed concentration of phosphine (PH 3 ).
  • the “texture structure” is an uneven structure that suppresses surface reflection and increases the light absorption amount of the photoelectric conversion unit 20.
  • a pyramidal (quadrangular pyramid or quadrangular pyramid-shaped) uneven structure obtained by performing anisotropic etching on the light receiving surface 11 having a (100) plane can be exemplified.
  • the texture structure can be formed, for example, by anisotropically etching the (100) plane using a potassium hydroxide (KOH) aqueous solution.
  • KOH potassium hydroxide
  • the i-type amorphous silicon layer 27a and the n-type amorphous silicon layer 28a are partially etched and removed.
  • the region to be etched is a region that becomes the current extraction region 33n and the current extraction region 33p.
  • a resist film formed by a screen printing or ink jet coating process, a photolithography process or the like is used as a mask.
  • an etchant for example, a sodium hydroxide (NaOH) aqueous solution (for example, 1 wt% NaOH aqueous solution) or the like is used.
  • the i-type amorphous silicon layer 27 b, the n-type amorphous silicon layer 28 b, and the insulating layer 31 are formed over the entire region excluding the edge region on the back surface 12 by, for example, PECVD.
  • PECVD plasma chemical vapor deposition
  • the i-type amorphous silicon layer 27b, the n-type amorphous silicon layer 28b, and the insulating layer 31 are stacked also on the n-type amorphous silicon layer 28a.
  • an i-type amorphous silicon layer 27b thinner than the i-type amorphous silicon layer 27a is formed in a region that becomes the current extraction region 33n.
  • the post-process is advanced so that the region where the i-type amorphous silicon layer 27b is directly formed on the back surface 12 becomes the current extraction region 33n.
  • the insulating layer 31, the i-type amorphous silicon layer 27b, and the n-type amorphous silicon layer 28b are partially etched and removed using the resist film 100 as a mask.
  • the region to be etched is a region that becomes the current extraction region 33p of the P region.
  • the edge layer 31 is etched using the resist film 100 as a mask.
  • the insulating layer 31 is silicon oxide (SiO 2 ), silicon nitride (SiN), or silicon oxynitride (SiON), for example, etching can be performed using an aqueous hydrogen fluoride (HF) solution.
  • HF aqueous hydrogen fluoride
  • the i-type amorphous silicon layer 27b and the n-type amorphous silicon layer 28b are etched using the patterned insulating layer 31 as a mask. By this step, patterning of the N region constituted by the IN layer 25 is completed.
  • an i-type amorphous silicon layer 29 and a p-type amorphous silicon layer 30 a are sequentially stacked over the entire region excluding the edge region on the back surface 12. That is, the i-type amorphous silicon layer 29 and the p-type amorphous silicon layer 30a are also stacked on the patterned N region via the insulating layer 31.
  • the i-type amorphous silicon layer 29 and the p-type amorphous silicon layer 30a are sequentially formed from the i-type amorphous silicon layer 29 and the p-type amorphous silicon layer 30a by PECVD or the like. It can be formed by film formation.
  • diborane (B 2 H 6 ) is used as a doping gas instead of phosphine (PH 3 ).
  • the i-type amorphous silicon layer 29 and the p-type amorphous silicon layer 30a are partially removed by etching using a resist film formed by screen printing or the like as a mask.
  • the region to be etched is, for example, a part of the region that becomes the current extraction region 33p, and the etching range can be adjusted as appropriate.
  • the IP layer 26 Since the IP layer 26 is usually harder to etch than the IN layer 25, the IP layer 26 has a higher concentration than the NaOH aqueous solution used for etching the IN layer 25 (for example, 10 wt% NaOH aqueous solution) or hydrofluoric acid (HF, HNO 3 ) (For example, 30 wt% each) is preferably used. Alternatively, it is also preferable to use an aqueous NaOH solution heated to about 70 to 90 ° C. (thermal alkali treatment).
  • the NaOH aqueous solution used for etching the IN layer 25 for example, 10 wt% NaOH aqueous solution
  • hydrofluoric acid HF, HNO 3
  • the p-type amorphous silicon layer 30 b is laminated over the entire region excluding the edge region on the back surface 12 by, for example, PECVD.
  • PECVD plasma-organic chemical vapor deposition
  • the IP layer 26 and the insulating layer 31 are partially removed by etching using a resist film formed by screen printing or the like as a mask to expose the IN layer 25.
  • the region of the IP layer 26 and the insulating layer 31 to be etched is a region on the region where the i-type amorphous silicon layer 27 b is directly formed on the back surface 12.
  • FIGS. 15 to 17 are diagrams showing the steps of forming the n-side electrode 40 and the p-side electrode 50.
  • a process of forming the third conductive layers 45 and 55 and the fourth conductive layers 46 and 56 of the respective electrodes by electrolytic plating using the second conductive layers 44 and 54 of the respective electrodes as a seed layer will be described.
  • the first conductive layer 13 and the second conductive layer 14 are sequentially formed on the IN layer 25 and the IP layer 26 by, for example, sputtering.
  • the first conductive layer 13 is stacked on substantially the entire area on the IN layer 25 and the IP layer 26.
  • the first conductive layer 13 is a layer that is patterned in a later step to become the first conductive layers 43 and 53 of each electrode.
  • the second conductive layer 14 is a layer that is patterned in a later step to become the second conductive layers 44 and 45 of each electrode.
  • the first conductive layer 13 and the second conductive layer 14 are partially etched to divide each layer, and the first conductive layers 43 and 53 and the first conductive layers 43 and 53 of each electrode separated from each other.
  • Two conductive layers 44 and 45 are formed.
  • Etching of the first conductive layer 13 and the second conductive layer 14 uses, for example, a resist film formed by screen printing or the like as a mask, and an aqueous solution containing ferric chloride (FeCl 3 ) and hydrochloric acid (HCl). To do.
  • the region to be etched is preferably a region on the overlapping region 32, for example.
  • the third conductive layers 45 and 55 are formed by electrolytic plating using the second conductive layers 44 and 45 as seed layers, respectively.
  • the fourth conductive layers 46 and 56 are formed on the third conductive layers 45 and 55 by electrolytic plating, so that the photoelectric conversion unit 20 is provided with the n-side electrode 40 and the p-side electrode 50 on the back surface side.
  • the conversion device 10 (see FIG. 2) is obtained.
  • the electroplating can be performed, for example, by flowing a current of the same magnitude through the second conductive layer 44 constituting the n-side electrode 40 and the second conductive layer 54 constituting the p-side electrode 50. In this case, a metal plating layer having the same mass is formed on the second conductive layers 44 and 54.
  • the thickness of the third conductive layer is increased. That is, the thickness of the n-side electrode 40 can be made thicker than the thickness of the p-side electrode 50 by carrying out electrolytic plating while flowing the same current.
  • the film thickness of the amorphous silicon layer formed in the current extraction region 33 is larger than the film thickness of the amorphous silicon layer formed in another region of the current extraction region 33. It is getting thinner. For this reason, in the current extraction region 33, the contact resistance can be reduced and the current extraction efficiency can be increased. In the other region of the current extraction region 33, the film thickness of the amorphous silicon layer is set to a film thickness that is suitable from the viewpoint of passivation characteristics, and carrier recombination is sufficiently prevented, and the lifetime of the carrier is reduced. Can be stretched.
  • the film thickness of the i-type amorphous silicon layer 27b in the current extraction region 33n is smaller than the film thickness of the i-type amorphous silicon layer 27a in other regions of the current extraction region 33n. . Therefore, in the current extraction region 33n, the contact resistance can be further reduced while exhibiting the passivation characteristics, and the current extraction efficiency can be further increased.
  • the photoelectric conversion device 10 can optimize the balance between the passivation characteristics and the current extraction efficiency.
  • the photoelectric conversion device 10 can increase photoelectric conversion efficiency by improving current extraction efficiency while preventing carrier recombination.
  • the film thickness of the amorphous silicon layer in the current extraction region is smaller than the film thickness of the amorphous silicon layer in other regions of the current extraction region in both the N region and the P region.
  • only one of the regions may have such a configuration.
  • the film thickness of the amorphous silicon layer in the current extraction region and other regions may be set to the same level.
  • the IP layer 26 is stacked after the IN layer 25 is stacked, but the IP layer 26 may be stacked first. In this case, a region where the i-type amorphous semiconductor layer is not provided may be formed in a part of the current extraction region 33n.

Abstract

A photoelectric converter (10) is provided with an n-type monocrystalline silicon substrate (21), an IN layer (25) and an IP layer (26) formed on the rear surface (12) of the n-type monocrystalline silicon substrate (21), an n-side electrode (40) electrically connected to the IN layer (25), and a p-side electrode (50) formed so as to be separate from the n-side electrode (40) and so as to be electrically connected to the IP layer (26). The thickness of at least a portion of the IN layer (25) and the IP layer (26) formed on a current isolation region (33) is thinner than the thickness of the corresponding IN layer (25) and IP layer (26) formed on another region.

Description

光電変換装置Photoelectric conversion device
　本発明は、光電変換装置に関する。 The present invention relates to a photoelectric conversion device.
　太陽電池の裏面側にｐ型半導体領域及びｎ型半導体領域が形成され、ｐ側電極とｎ側電極とが分離溝によって電気的に分離された所謂裏面接合型の太陽電池が提案されている（特許文献１参照）。この裏面接合型の太陽電池によれば、受光面側に電極が存在しないため、光の受光効率を高めて発電効率を向上させることができる。 A so-called back junction type solar cell is proposed in which a p-type semiconductor region and an n-type semiconductor region are formed on the back side of the solar cell, and the p-side electrode and the n-side electrode are electrically separated by a separation groove ( Patent Document 1). According to this back junction solar cell, since no electrode is present on the light receiving surface side, the light receiving efficiency can be increased and the power generation efficiency can be improved.
特開２００９－２００２６７号公報JP 2009-200277 A
　裏面接合型の太陽電池では、キャリアの再結合を防止しながら、電流の取り出し効率を向上させることが重要である。 In a back junction solar cell, it is important to improve current extraction efficiency while preventing carrier recombination.
　本発明に係る光電変換装置は、半導体基板と、半導体基板の一方の面上に形成された第１導電型の非晶質半導体層を含む第１非晶質半導体層と、半導体基板の一方の面上の第１非晶質半導体層が形成されていない領域に形成された第２導電型の非晶質半導体層を含む第２非晶質半導体層と、第１非晶質半導体層と電気的に接続された第１電極と、第１電極から離間して第２非晶質半導体層と電気的に接続されるように形成された第２電極とを備え、第１及び第２電極によりキャリアが取り出される電流取り出し領域に形成された第１及び第２非晶質半導体層のうち少なくとも一部の膜厚が、他の領域に形成された対応する第１及び第２非晶質半導体層の膜厚よりも薄いことを特徴とする。 The photoelectric conversion device according to the present invention includes a semiconductor substrate, a first amorphous semiconductor layer including a first conductivity type amorphous semiconductor layer formed on one surface of the semiconductor substrate, and one of the semiconductor substrates. A second amorphous semiconductor layer including a second conductive type amorphous semiconductor layer formed in a region where the first amorphous semiconductor layer is not formed on the surface; First electrodes connected to each other and a second electrode formed so as to be electrically connected to the second amorphous semiconductor layer apart from the first electrodes, and the first and second electrodes Corresponding first and second amorphous semiconductor layers in which at least a part of the first and second amorphous semiconductor layers formed in the current extraction region from which carriers are extracted are formed in other regions. It is characterized by being thinner than the film thickness.
　本発明の光電変換装置によれば、キャリアの再結合を防止しながら、電流の取り出し効率を向上させることが可能である。 According to the photoelectric conversion device of the present invention, it is possible to improve current extraction efficiency while preventing carrier recombination.
本発明の実施形態である光電変換装置を裏面側から見た平面図である。It is the top view which looked at the photoelectric conversion apparatus which is embodiment of this invention from the back surface side. 図１のＡ‐Ａ線断面図である。It is the sectional view on the AA line of FIG. 図１において、ｎ側電極及びｐ側電極を省略し、ＩＮ非晶質シリコン層及びＩＰ非晶質シリコン層の平面形状パターンを示す図である。FIG. 1 is a diagram illustrating a planar shape pattern of an IN amorphous silicon layer and an IP amorphous silicon layer, omitting an n-side electrode and a p-side electrode in FIG. 図２のＮ領域の拡大図である。FIG. 3 is an enlarged view of an N region in FIG. 2. 図２のＰ領域の拡大図である。It is an enlarged view of P area | region of FIG. 本発明の実施形態である光電変換装置の製造方法を説明するための断面図であって、光電変換部の製造工程を示す図である。It is sectional drawing for demonstrating the manufacturing method of the photoelectric conversion apparatus which is embodiment of this invention, Comprising: It is a figure which shows the manufacturing process of a photoelectric conversion part. 本発明の実施形態である光電変換装置の製造方法を説明するための断面図であって、光電変換部の製造工程を示す図である。It is sectional drawing for demonstrating the manufacturing method of the photoelectric conversion apparatus which is embodiment of this invention, Comprising: It is a figure which shows the manufacturing process of a photoelectric conversion part. 本発明の実施形態である光電変換装置の製造方法を説明するための断面図であって、光電変換部の製造工程を示す図である。It is sectional drawing for demonstrating the manufacturing method of the photoelectric conversion apparatus which is embodiment of this invention, Comprising: It is a figure which shows the manufacturing process of a photoelectric conversion part. 本発明の実施形態である光電変換装置の製造方法を説明するための断面図であって、光電変換部の製造工程を示す図である。It is sectional drawing for demonstrating the manufacturing method of the photoelectric conversion apparatus which is embodiment of this invention, Comprising: It is a figure which shows the manufacturing process of a photoelectric conversion part. 本発明の実施形態である光電変換装置の製造方法を説明するための断面図であって、光電変換部の製造工程を示す図である。It is sectional drawing for demonstrating the manufacturing method of the photoelectric conversion apparatus which is embodiment of this invention, Comprising: It is a figure which shows the manufacturing process of a photoelectric conversion part. 本発明の実施形態である光電変換装置の製造方法を説明するための断面図であって、光電変換部の製造工程を示す図である。It is sectional drawing for demonstrating the manufacturing method of the photoelectric conversion apparatus which is embodiment of this invention, Comprising: It is a figure which shows the manufacturing process of a photoelectric conversion part. 本発明の実施形態である光電変換装置の製造方法を説明するための断面図であって、光電変換部の製造工程を示す図である。It is sectional drawing for demonstrating the manufacturing method of the photoelectric conversion apparatus which is embodiment of this invention, Comprising: It is a figure which shows the manufacturing process of a photoelectric conversion part. 本発明の実施形態である光電変換装置の製造方法を説明するための断面図であって、光電変換部の製造工程を示す図である。It is sectional drawing for demonstrating the manufacturing method of the photoelectric conversion apparatus which is embodiment of this invention, Comprising: It is a figure which shows the manufacturing process of a photoelectric conversion part. 本発明の実施形態である光電変換装置の製造方法を説明するための断面図であって、光電変換部の製造工程を示す図である。It is sectional drawing for demonstrating the manufacturing method of the photoelectric conversion apparatus which is embodiment of this invention, Comprising: It is a figure which shows the manufacturing process of a photoelectric conversion part. 本発明の他の実施形態である光電変換装置の製造方法を説明するための断面図であって、ｎ側電極及びｐ側電極の形成工程を示す図である。It is sectional drawing for demonstrating the manufacturing method of the photoelectric conversion apparatus which is other embodiment of this invention, Comprising: It is a figure which shows the formation process of an n side electrode and a p side electrode. 本発明の他の実施形態である光電変換装置の製造方法を説明するための断面図であって、ｎ側電極及びｐ側電極の形成工程を示す図である。It is sectional drawing for demonstrating the manufacturing method of the photoelectric conversion apparatus which is other embodiment of this invention, Comprising: It is a figure which shows the formation process of an n side electrode and a p side electrode. 本発明の他の実施形態である光電変換装置の製造方法を説明するための断面図であって、ｎ側電極及びｐ側電極の形成工程を示す図である。It is sectional drawing for demonstrating the manufacturing method of the photoelectric conversion apparatus which is other embodiment of this invention, Comprising: It is a figure which shows the formation process of an n side electrode and a p side electrode.
　以下、図面を用いて、本発明の実施形態を詳細に説明する。
　以下の実施形態は、単なる例示である。本発明は、以下の実施形態に限定されない。実施形態において参照する図面は、模式的に記載されたものであり、図面に描画された物体の寸法比率などは、現実の物体の寸法比率などとは異なる場合がある。具体的な物体の寸法比率等は、以下の説明を参酌して判断されるべきである。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
The following embodiments are merely illustrative. The present invention is not limited to the following embodiments. The drawings referred to in the embodiments are schematically described, and the dimensional ratios of objects drawn in the drawings may be different from the dimensional ratios of actual objects. The specific dimensional ratio of the object should be determined in consideration of the following description.
　まず初めに、図１～図５を参照して、光電変換装置１０の構成を詳細に説明する。 First, the configuration of the photoelectric conversion device 10 will be described in detail with reference to FIGS. 1 to 5.
　図１は、光電変換装置１０を裏面側から見た平面図である。図１に示すように、光電変換装置１０は、太陽光等の光が入射することでキャリア（電子及び正孔）を生成する光電変換部２０と、光電変換部２０の裏面側に形成されたｎ側電極４０及びｐ側電極５０とを備える。即ち、光電変換装置１０は、受光面側に電極が存在しない裏面接合型である。光電変換装置１０では、光電変換部２０で生成されたキャリアがｎ側電極４０及びｐ側電極５０によりそれぞれ収集される。そして、ｎ側電極４０及びｐ側電極５０に図示しない配線材を電気的に接続して光電変換装置１０をモジュール化することで、キャリアが電気エネルギーとして外部に取り出される。ここで、「裏面」とは、装置の外部から光が入射する面である「受光面」と反対側の面を意味する。換言すれば、ｎ側電極４０及びｐ側電極５０が形成される面が裏面である。また、ｎ側電極４０とは、光電変換部２０のＩＮ非晶質シリコン層２５からキャリア（電子）を収集する電極である。ｐ側電極５０とは、光電変換部２０のＩＰ非晶質シリコン層２６からキャリア（正孔）を収集する電極である。各電極は、複数のフィンガー電極部４１，５１と、対応する各フィンガー電極部を繋ぐバスバー電極部４２，５２とをそれぞれ有する。 FIG. 1 is a plan view of the photoelectric conversion device 10 as viewed from the back side. As shown in FIG. 1, the photoelectric conversion device 10 is formed on the back surface side of the photoelectric conversion unit 20 that generates carriers (electrons and holes) when light such as sunlight enters, and the photoelectric conversion unit 20. An n-side electrode 40 and a p-side electrode 50 are provided. That is, the photoelectric conversion device 10 is a back surface junction type in which no electrode is present on the light receiving surface side. In the photoelectric conversion device 10, carriers generated by the photoelectric conversion unit 20 are collected by the n-side electrode 40 and the p-side electrode 50, respectively. And the wiring material which is not illustrated is electrically connected to the n side electrode 40 and the p side electrode 50, and the photoelectric conversion apparatus 10 is modularized, A carrier is taken out as an electrical energy outside. Here, the “back surface” means a surface opposite to the “light receiving surface” which is a surface on which light is incident from the outside of the apparatus. In other words, the surface on which the n-side electrode 40 and the p-side electrode 50 are formed is the back surface. The n-side electrode 40 is an electrode that collects carriers (electrons) from the IN amorphous silicon layer 25 of the photoelectric conversion unit 20. The p-side electrode 50 is an electrode that collects carriers (holes) from the IP amorphous silicon layer 26 of the photoelectric conversion unit 20. Each electrode has a plurality of finger electrode portions 41 and 51 and bus bar electrode portions 42 and 52 connecting the corresponding finger electrode portions.
　光電変換部２０は、半導体基板としてｎ型単結晶シリコン基板２１を有する。半導体基板としては、例えば、結晶系シリコン基板、ガリウム砒素（ＧａＡｓ）基板、インジウム燐（ＩｎＰ）基板等が適用できる。結晶系半導体基板は、例えば、ｎ型多結晶シリコン基板やｐ型の単結晶又は多結晶シリコン基板であってもよいが、本実施形態で例示するｎ型単結晶シリコン基板２１を用いることが好適である。ｎ型単結晶シリコン基板２１は、発電層として機能し、例えば、１００～３００μｍの厚みを有する。ｎ型単結晶シリコン基板２１の受光面１１には、テクスチャ構造（図示せず）を形成することが好適である。ここで、「テクスチャ構造」とは、表面反射を抑制し、光電変換部２０の光吸収量を増大させる凹凸構造である。テクスチャ構造の具体例としては、（１００）面を有する受光面１１に異方性エッチングを施すことによって得られるピラミッド状（四角錐状や四角錐台状）の凹凸構造が例示できる。 The photoelectric conversion unit 20 has an n-type single crystal silicon substrate 21 as a semiconductor substrate. As the semiconductor substrate, for example, a crystalline silicon substrate, a gallium arsenide (GaAs) substrate, an indium phosphorus (InP) substrate, or the like can be applied. The crystalline semiconductor substrate may be, for example, an n-type polycrystalline silicon substrate or a p-type single crystal or polycrystalline silicon substrate, but it is preferable to use the n-type single crystal silicon substrate 21 exemplified in this embodiment. It is. The n-type single crystal silicon substrate 21 functions as a power generation layer and has a thickness of 100 to 300 μm, for example. A texture structure (not shown) is preferably formed on the light receiving surface 11 of the n-type single crystal silicon substrate 21. Here, the “texture structure” is an uneven structure that suppresses surface reflection and increases the light absorption amount of the photoelectric conversion unit 20. As a specific example of the texture structure, a pyramidal (quadrangular pyramid or quadrangular frustum-shaped) uneven structure obtained by performing anisotropic etching on the light receiving surface 11 having a (100) plane can be exemplified.
　図２は、図１のＡ‐Ａ線断面図である。図２に示すように、ｎ型単結晶シリコン基板２１の受光面１１側には、ｉ型非晶質シリコン膜２２と、ｎ型非晶質シリコン層２３と、保護層２４とが順に形成される。ここで、ｉ型非晶質シリコン層２２及びｎ型非晶質シリコン層２３は、パッシベーション層として機能する。保護層２４は、パッシベーション層を保護すると共に、反射防止機能を有する。 FIG. 2 is a cross-sectional view taken along line AA in FIG. As shown in FIG. 2, an i-type amorphous silicon film 22, an n-type amorphous silicon layer 23, and a protective layer 24 are sequentially formed on the light-receiving surface 11 side of the n-type single crystal silicon substrate 21. The Here, the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23 function as a passivation layer. The protective layer 24 protects the passivation layer and has an antireflection function.
　ｉ型非晶質シリコン層２２及びｎ型非晶質シリコン層２３は、例えば、ｎ型単結晶シリコン基板２１の受光面１１の端縁領域を除く全域に積層される。ｉ型非晶質シリコン層２２は、真性非晶質シリコンの薄膜層であって、０．５ｎｍ～５０ｎｍ程度の厚みを有する。ｎ型非晶質シリコン層２３は、例えば、リン（Ｐ）等がドープされた非晶質シリコンの薄膜層であって、１ｎｍ～５０ｎｍ程度の厚みを有する。 The i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23 are laminated, for example, over the entire region excluding the edge region of the light receiving surface 11 of the n-type single crystal silicon substrate 21. The i-type amorphous silicon layer 22 is a thin film layer of intrinsic amorphous silicon and has a thickness of about 0.5 nm to 50 nm. The n-type amorphous silicon layer 23 is an amorphous silicon thin film layer doped with phosphorus (P) or the like, for example, and has a thickness of about 1 nm to 50 nm.
　保護層２４は、ｎ型非晶質シリコン層２３上の略全域に積層される。保護層２４は、光透過性が高い材料から構成されることが好ましい。保護層２４としては、例えば、酸化ケイ素（ＳｉＯ2）、窒化ケイ素（ＳｉＮ）、又は酸窒化ケイ素（ＳｉＯＮ）等からなる絶縁層であることが好ましく、ＳｉＮ層が特に好適である。保護層２４の厚みは、反射防止特性等を考慮して適宜変更できるが、例えば、８０ｎｍ～１μｍ程度が好適である。 The protective layer 24 is stacked on substantially the entire area on the n-type amorphous silicon layer 23. The protective layer 24 is preferably made of a material having high light transmittance. The protective layer 24 is preferably an insulating layer made of, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), or silicon oxynitride (SiON), and a SiN layer is particularly suitable. The thickness of the protective layer 24 can be appropriately changed in consideration of antireflection characteristics and the like, but for example, about 80 nm to 1 μm is preferable.
　光電変換部２０において、ｎ型単結晶シリコン基板２１の裏面１２側には、ＩＮ非晶質シリコン層２５（以下、ＩＮ層２５とする）と、ＩＰ非晶質シリコン層２６（以下、ＩＰ層２６とする）とがそれぞれ積層される。ＩＮ層２５とＩＰ層２６との間には、絶縁層３１が設けられている。ＩＮ層２５は、ｎ型非晶質半導体領域（以下、Ｎ領域とする）を形成する薄膜層である。ＩＮ層２５は、ｎ型単結晶シリコン基板２１の裏面１２上に積層される第１のｉ型非晶質シリコン層２７ａ及び第２のｉ型非晶質シリコン層２７ｂと、ｉ型非晶質シリコン層２７ａ上に積層された第１のｎ型非晶質シリコン層２８ａと、ｉ型非晶質シリコン層２７ｂ上に積層された第２のｎ型非晶質シリコン層２８ｂとを含む。ｉ型非晶質シリコン層２７ａ，２７ｂは、例えば、ｉ型非晶質シリコン層２２と同様の組成で形成できる。また、ｎ型非晶質シリコン層２８ａ，２８ｂは、例えば、ｎ型非晶質シリコン層２３と同様の組成で形成でき、１ｎｍ～５０ｎｍ程度の厚みを有する。ＩＰ層２６は、ｐ型非晶質半導体領域（以下、Ｐ領域とする）を形成する薄膜層である。Ｐ領域は、Ｎ領域よりも積層面積を大きくすることができる。ＩＰ層２６は、ｎ型単結晶シリコン基板２１の裏面１２上に積層されるｉ型非晶質シリコン層２９と、ｉ型非晶質シリコン層２９上に積層される第１のｐ型非晶質シリコン層３０ａと、ｐ型非晶質シリコン層３０ａ上及びｎ型単結晶シリコン基板２１の裏面１２上に積層されるｐ型非晶質シリコン層３０ｂとを含む。ｉ型非晶質シリコン層２９は、例えば、ｉ型非晶質シリコン層２２、ｉ型非晶質シリコン層２７ａ，２７ｂと同様の組成で形成できる。また、ｐ型非晶質シリコン層３０ａ，３０ｂは、例えば、ボロン（Ｂ）等がドープされた非晶質シリコンの薄膜層であって、１ｎｍ～５０ｎｍ程度の厚みを有する。 In the photoelectric conversion unit 20, an IN amorphous silicon layer 25 (hereinafter referred to as an IN layer 25) and an IP amorphous silicon layer 26 (hereinafter referred to as an IP layer) are formed on the back surface 12 side of the n-type single crystal silicon substrate 21. 26). An insulating layer 31 is provided between the IN layer 25 and the IP layer 26. The IN layer 25 is a thin film layer that forms an n-type amorphous semiconductor region (hereinafter referred to as an N region). The IN layer 25 includes a first i-type amorphous silicon layer 27a and a second i-type amorphous silicon layer 27b stacked on the back surface 12 of the n-type single crystal silicon substrate 21, and an i-type amorphous layer. A first n-type amorphous silicon layer 28a stacked on the silicon layer 27a and a second n-type amorphous silicon layer 28b stacked on the i-type amorphous silicon layer 27b are included. The i-type amorphous silicon layers 27a and 27b can be formed with the same composition as that of the i-type amorphous silicon layer 22, for example. The n-type amorphous silicon layers 28a and 28b can be formed with the same composition as the n-type amorphous silicon layer 23, for example, and have a thickness of about 1 nm to 50 nm. The IP layer 26 is a thin film layer that forms a p-type amorphous semiconductor region (hereinafter referred to as a P region). The P region can have a larger lamination area than the N region. The IP layer 26 includes an i-type amorphous silicon layer 29 stacked on the back surface 12 of the n-type single crystal silicon substrate 21 and a first p-type amorphous silicon stacked on the i-type amorphous silicon layer 29. And a p-type amorphous silicon layer 30b stacked on the p-type amorphous silicon layer 30a and the back surface 12 of the n-type single crystal silicon substrate 21. The i-type amorphous silicon layer 29 can be formed with the same composition as the i-type amorphous silicon layer 22 and the i-type amorphous silicon layers 27a and 27b, for example. The p-type amorphous silicon layers 30a and 30b are, for example, amorphous silicon thin films doped with boron (B) or the like, and have a thickness of about 1 nm to 50 nm.
　ｎ側電極４０は、ＩＮ層２５と電気的に接続される電極であって、主としてＩＮ層２５上に形成される。ｐ側電極５０は、ｎ側電極４０から離間して、ＩＰ層２６と電気的に接続されるように形成された電極であって、ＩＰ層２６上に形成される。ｎ側電極４０とｐ側電極５０との間には、両電極を分離する分離溝６０が形成されている。各電極の積層面積は、ＩＮ層２５及びＩＰ層２６の積層面積に対応して、ｐ側電極５０の方がｎ側電極４０よりも積層面積が大きくなっている。ｎ側電極４０及びｐ側電極５０はそれぞれ、第１導電層４３，５３、第２導電層４４，５４、第３導電層４５，５５、及び第４導電層４６，５６の積層体で構成される。第１導電層４３、第２導電層４４、第３導電層４５、及び第４導電層４６はｎ側の導電層となり、第１導電層５３、第２導電層５４、第３導電層５５、及び第４導電層５６はｐ側の導電層となる。第１導電層４３，５３は、透明導電層によって構成される。第２導電層４４，５４は、金属層によって構成され、例えば、電気伝導率と材料費用の観点から銅（Ｃｕ）が用いられる。第１導電層４３，５３及び第２導電層４４，５４は、スパッタリングによって形成される。透明導電層は、例えば、多結晶構造を有する酸化インジウム（Ｉｎ2Ｏ3）、酸化亜鉛（ＺｎＯ）、酸化錫（ＳｎＯ2）、及び酸化チタン（ＴｉＯ2）等の金属酸化物のうち少なくとも１種を含んで構成されることが好ましい。これらの金属酸化物に、錫（Ｓｎ）、亜鉛（Ｚｎ）、タングステン（Ｗ）、アンチモン（Ｓｂ）、チタン（Ｔｉ）、アルミニウム（Ａｌ）、セリウム（Ｃｅ）、ガリウム（Ｇａ）などのドーパントがドープされていてもよく、例えば、Ｉｎ2Ｏ3にＳｎがドープされたＩＴＯが特に好ましい。ドーパントの濃度は、０～２０ｗｔ％とすることができる。金属層は、例えば、５０ｎｍ～１μｍ程度の厚みとすることが好適である。金属層は、高い導電性を有し、且つ光の反射率が高い金属から構成されることが好ましい。金属層を構成する金属としては、銀（Ａｇ）、アルミニウム（Ａｌ）、チタン（Ｔｉ）、銅（Ｃｕ）、錫（Ｓｎ）などの金属又はそれらの１種以上を含む合金を用いることができる。例えば、第２導電層１４は、Ｃｕ層であることが好ましい。第１導電層４３，５３及び第２導電層４４，５４は、第３導電層４５，５５及び第４導電層４６，５６をめっきによって形成する際の起点となるシード層として機能する。めっきによる第３導電層４５，５５及び第４導電層４６，５６の形成方法については、後に詳述する。第３導電層４５，５５は、金属層によって構成され、例えば、電気伝導率と材料費用の観点から銅（Ｃｕ）が用いられる。第４導電層４６，５６は、金属層によって構成され、例えば、第１導電層４３，５３、第２導電層４４，５４、及び第３導電層４５，５５の腐食を防ぐ観点から錫（Ｓｎ）が用いられる。 The n-side electrode 40 is an electrode electrically connected to the IN layer 25 and is mainly formed on the IN layer 25. The p-side electrode 50 is an electrode formed so as to be separated from the n-side electrode 40 and electrically connected to the IP layer 26, and is formed on the IP layer 26. A separation groove 60 that separates both electrodes is formed between the n-side electrode 40 and the p-side electrode 50. The laminated area of each electrode corresponds to the laminated area of the IN layer 25 and the IP layer 26, and the p-side electrode 50 has a larger laminated area than the n-side electrode 40. The n-side electrode 40 and the p-side electrode 50 are each composed of a laminate of first conductive layers 43 and 53, second conductive layers 44 and 54, third conductive layers 45 and 55, and fourth conductive layers 46 and 56. The The first conductive layer 43, the second conductive layer 44, the third conductive layer 45, and the fourth conductive layer 46 are n-side conductive layers. The first conductive layer 53, the second conductive layer 54, the third conductive layer 55, The fourth conductive layer 56 is a p-side conductive layer. The first conductive layers 43 and 53 are constituted by a transparent conductive layer. The second conductive layers 44 and 54 are composed of a metal layer, and for example, copper (Cu) is used from the viewpoint of electrical conductivity and material cost. The first conductive layers 43 and 53 and the second conductive layers 44 and 54 are formed by sputtering. The transparent conductive layer is, for example, at least one of metal oxides such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), and titanium oxide (TiO 2 ) having a polycrystalline structure. It is preferable that it is comprised including seeds. These metal oxides contain dopants such as tin (Sn), zinc (Zn), tungsten (W), antimony (Sb), titanium (Ti), aluminum (Al), cerium (Ce), and gallium (Ga). For example, ITO in which In 2 O 3 is doped with Sn is particularly preferable. The concentration of the dopant can be 0 to 20 wt%. The metal layer is preferably about 50 nm to 1 μm thick, for example. The metal layer is preferably made of a metal having high conductivity and high light reflectance. As a metal constituting the metal layer, a metal such as silver (Ag), aluminum (Al), titanium (Ti), copper (Cu), tin (Sn), or an alloy containing one or more of them can be used. . For example, the second conductive layer 14 is preferably a Cu layer. The first conductive layers 43 and 53 and the second conductive layers 44 and 54 function as seed layers serving as starting points when the third conductive layers 45 and 55 and the fourth conductive layers 46 and 56 are formed by plating. A method of forming the third conductive layers 45 and 55 and the fourth conductive layers 46 and 56 by plating will be described in detail later. The third conductive layers 45 and 55 are formed of a metal layer, and for example, copper (Cu) is used from the viewpoint of electrical conductivity and material cost. The fourth conductive layers 46 and 56 are formed of a metal layer. For example, tin (Sn) is used to prevent corrosion of the first conductive layers 43 and 53, the second conductive layers 44 and 54, and the third conductive layers 45 and 55. ) Is used.
　ここで、図３～図５をさらに参照し、ＩＮ層２５及びＩＰ層２６の構成を詳説する。特に、電流取り出し領域３３について詳しく説明する。 Here, the configuration of the IN layer 25 and the IP layer 26 will be described in detail with further reference to FIGS. In particular, the current extraction region 33 will be described in detail.
　図３～図５では、ｎ側電極４０及びｐ側電極５０を省略する。図３は、ＩＮ層２５及びＩＰ層２６の平面形状パターンを示す（クロスハッチングを付した領域が、絶縁層３１が設けられる重なり領域３２である）。図４は、図２のＮ領域の拡大図であり、図５は、図２のＰ領域の拡大図である。 3 to 5, the n-side electrode 40 and the p-side electrode 50 are omitted. FIG. 3 shows a planar shape pattern of the IN layer 25 and the IP layer 26 (the region with cross-hatching is the overlapping region 32 where the insulating layer 31 is provided). 4 is an enlarged view of an N region in FIG. 2, and FIG. 5 is an enlarged view of a P region in FIG.
　図３に示すように、ＩＮ層２５及びＩＰ層２６は、互いに噛み合うように形成された櫛歯状、或いはストライプ状の積層形態を有する。ＩＮ層２５及びＩＰ層２６は、光電変換効率等の観点から、裏面１２に平行な一方向に沿って、交互に形成されることが好適である。また、ＩＮ層２５及びＩＰ層２６は、ｎ型単結晶シリコン基板２１の裏面１２上の広範囲を覆うように形成されることが好ましい。このため、ＩＰ層２６の端縁領域がＩＮ層２５の端縁領域上にオーバーラップしながら交互に隙間なく積層される。ＩＮ層２５とＩＰ層２６とが重なり合う領域を「重なり領域３２」と称して説明する。 As shown in FIG. 3, the IN layer 25 and the IP layer 26 have a comb-teeth shape or a stripe-like laminated form formed so as to mesh with each other. The IN layers 25 and the IP layers 26 are preferably formed alternately along one direction parallel to the back surface 12 from the viewpoint of photoelectric conversion efficiency and the like. The IN layer 25 and the IP layer 26 are preferably formed so as to cover a wide area on the back surface 12 of the n-type single crystal silicon substrate 21. For this reason, the edge region of the IP layer 26 is alternately stacked without a gap while overlapping the edge region of the IN layer 25. A region where the IN layer 25 and the IP layer 26 overlap will be referred to as an “overlapping region 32”.
　絶縁層３１は、Ｎ領域とＰ領域とを絶縁する機能を有し、重なり領域３２において、ＩＮ層２５とＩＰ層２６との間に設けられる。絶縁層３１としては、例えば、保護層２４と同様の組成、同様の厚みで形成でき、ＳｉＮ層を適用することが特に好適である。ＩＮ層２５の表面において、ＩＰ層２６が積層されない領域上には、絶縁層３１が形成されない。これにより、ＩＮ層２５とＩＰ層２６との良好な絶縁性を確保しながら、ＩＮ層２５とｎ側電極４０との電気的な接続が可能になる。 The insulating layer 31 has a function of insulating the N region and the P region, and is provided between the IN layer 25 and the IP layer 26 in the overlapping region 32. As the insulating layer 31, for example, it can be formed with the same composition and the same thickness as the protective layer 24, and it is particularly preferable to apply a SiN layer. On the surface of the IN layer 25, the insulating layer 31 is not formed on the region where the IP layer 26 is not stacked. Thereby, the IN layer 25 and the n-side electrode 40 can be electrically connected while ensuring good insulation between the IN layer 25 and the IP layer 26.
　図３～図５に示すように、ｎ型単結晶シリコン基板２１の裏面１２には、各電極によりキャリアが取り出される電流取り出し領域３３が存在する。電流取り出し領域３３とは、各電極が形成される領域であり、且つ各電極との間にキャリアの移動を遮断する層が設けられない裏面１２上の領域を意味する。例えば、ｎ型単結晶シリコン基板２１の厚み方向に沿って非晶質シリコン層及び電極が形成された領域は、電流取り出し領域３３として機能する。これに対して、非晶質シリコン層及び電極が形成された領域であっても、ｎ型単結晶シリコン基板２１と電極との間に絶縁層３１が積層された領域（例えば、重なり領域３２）は、電流取り出し領域３３として機能しない。これは、非晶質シリコン層におけるキャリアの移動度が小さいことに起因する。つまり、ｎ型単結晶シリコン基板２１の厚み方向へは、非晶質シリコン層の膜厚が薄く移動距離が短いためキャリアが十分に通過できるが、非晶質シリコン層の面方向（裏面１２に平行な方向）へは大きく広がってキャリアが移動できないからである。 As shown in FIGS. 3 to 5, the back surface 12 of the n-type single crystal silicon substrate 21 has a current extraction region 33 from which carriers are extracted by each electrode. The current extraction region 33 is a region where each electrode is formed and a region on the back surface 12 where a layer for blocking carrier movement is not provided between each electrode. For example, the region where the amorphous silicon layer and the electrode are formed along the thickness direction of the n-type single crystal silicon substrate 21 functions as the current extraction region 33. On the other hand, even in the region where the amorphous silicon layer and the electrode are formed, the region where the insulating layer 31 is stacked between the n-type single crystal silicon substrate 21 and the electrode (for example, the overlapping region 32). Does not function as the current extraction region 33. This is because the mobility of carriers in the amorphous silicon layer is small. That is, in the thickness direction of the n-type single crystal silicon substrate 21, the amorphous silicon layer is thin and the moving distance is short, so that carriers can sufficiently pass therethrough, but the surface direction of the amorphous silicon layer (on the back surface 12). This is because the carrier cannot move because it spreads greatly in the parallel direction.
　本実施の形態では、ＩＮ層２５が形成されたＮ領域において、絶縁層３１が設けられていない領域が、ｎ側電極４０によりキャリアが取り出される電流取り出し領域３３ｎとなる。即ち、ＩＮ層２５とｎ側電極４０との間に絶縁層３１が設けられた重なり領域３２を除く領域が、電流取り出し領域３３ｎとなる。電流取り出し領域３３ｎには、ｉ型非晶質シリコン層２７ｂ及びｎ型非晶質シリコン層２８ｂが形成されている。また、重なり領域３２には、ｉ型非晶質シリコン層２７ａ及びｎ型非晶質シリコン層２８ａが形成されている。ｉ型非晶質シリコン層２７ｂ及びｎ型非晶質シリコン層２８ｂは、ｎ型非晶質シリコン層２８ａ上の全域を覆うように形成されてもよい。Ｎ領域では、電流取り出し領域３３ｎに形成されたｉ型非晶質シリコン層２７ｂ及びｎ型非晶質シリコン層２８ｂのトータルの膜厚が、重なり領域３２に形成されたｉ型非晶質シリコン層２７ａ及びｎ型非晶質シリコン層２８ａのトータルの膜厚よりも薄くなっている。特に、ｉ型非晶質シリコン層２７ｂの膜厚を、ｉ型非晶質シリコン層２７ａの膜厚よりも薄くすることが好ましい。ｉ型非晶質シリコン層２７ａは、パッシベーション特性の観点から膜厚が設定され、例えば、０．５ｎｍ～５０ｎｍ程度が好適である。これに対し、ｉ型非晶質シリコン層２７ｂの膜厚は、パッシベーション特性と電流の取り出し効率とを考慮して、例えば、ｉ型非晶質シリコン層２７ａの膜厚の２／３～１／３程度とすることが好適である。ｎ型非晶質シリコン層２８ａ，２８ｂは、光電変換装置１０の開放電圧及びｎ側電極４０とのコンタクト抵抗において必要な特性が得られる膜厚とされる。好ましくは、ｎ型非晶質シリコン層２８ｂの膜厚も、ｎ型非晶質シリコン層２８ａの膜厚より薄くする。 In the present embodiment, in the N region where the IN layer 25 is formed, a region where the insulating layer 31 is not provided becomes a current extraction region 33n from which carriers are extracted by the n-side electrode 40. That is, a region excluding the overlapping region 32 where the insulating layer 31 is provided between the IN layer 25 and the n-side electrode 40 is a current extraction region 33n. An i-type amorphous silicon layer 27b and an n-type amorphous silicon layer 28b are formed in the current extraction region 33n. In the overlapping region 32, an i-type amorphous silicon layer 27a and an n-type amorphous silicon layer 28a are formed. The i-type amorphous silicon layer 27b and the n-type amorphous silicon layer 28b may be formed so as to cover the entire area on the n-type amorphous silicon layer 28a. In the N region, the total film thickness of the i-type amorphous silicon layer 27b and the n-type amorphous silicon layer 28b formed in the current extraction region 33n is equal to the i-type amorphous silicon layer formed in the overlapping region 32. 27a and the total film thickness of the n-type amorphous silicon layer 28a. In particular, the i-type amorphous silicon layer 27b is preferably made thinner than the i-type amorphous silicon layer 27a. The thickness of the i-type amorphous silicon layer 27a is set from the viewpoint of passivation characteristics, and for example, about 0.5 nm to 50 nm is preferable. In contrast, the film thickness of the i-type amorphous silicon layer 27b is, for example, 2/3 to 1 / th of the film thickness of the i-type amorphous silicon layer 27a in consideration of passivation characteristics and current extraction efficiency. It is preferable to set it to about 3. The n-type amorphous silicon layers 28 a and 28 b have a film thickness that provides necessary characteristics for the open-circuit voltage of the photoelectric conversion device 10 and the contact resistance with the n-side electrode 40. Preferably, the film thickness of the n-type amorphous silicon layer 28b is also made thinner than the film thickness of the n-type amorphous silicon layer 28a.
　本実施の形態では、ＩＰ層２６が形成されたＰ領域において、絶縁層３１が設けられていない領域が、ｐ側電極５０によりキャリアが取り出される電流取り出し領域３３ｐとなる。即ち、ｎ型単結晶シリコン基板２１とＩＰ層２６との間に絶縁層３１が設けられた重なり領域３２を除く領域が、電流取り出し領域３３ｐとなる。電流取り出し領域３３ｐには、ｐ型非晶質シリコン層３０ｂが形成されている。重なり領域３２には、ｉ型非晶質シリコン層２９及びｐ型非晶質シリコン層３０ａが形成されている。また、電流取り出し領域３３ｐの一部には、ｉ型非晶質シリコン層２９と、ｐ型非晶質シリコン層３０ａと、ｐ型非晶質シリコン層３０ｂとが順に積層されている。ｐ型非晶質シリコン層３０ｂは、ｐ型非晶質シリコン層３０ａ上の全域を覆うように形成されてもよい。電流取り出し領域３３ｐには、ｐ型非晶質シリコン層３０ｂが裏面１２上に直接積層され、ｉ型非晶質シリコン層が積層されない領域が設けられている。なお、ｐ型非晶質シリコン層３０ａ，３０ｂは、例えば、互いに同等の厚みで形成できる。これにより、電流取り出し領域３３ｐにおける非晶質シリコン層（ｐ型非晶質シリコン層３０ｂ）の膜厚が、重なり領域３２に形成された非晶質シリコン層（ｉ型非晶質シリコン層２９及びｐ型非晶質シリコン層３０ａ）の膜厚よりも薄くなっている。 In the present embodiment, in the P region where the IP layer 26 is formed, a region where the insulating layer 31 is not provided becomes a current extraction region 33p from which carriers are extracted by the p-side electrode 50. That is, a region excluding the overlapping region 32 where the insulating layer 31 is provided between the n-type single crystal silicon substrate 21 and the IP layer 26 becomes the current extraction region 33p. A p-type amorphous silicon layer 30b is formed in the current extraction region 33p. In the overlapping region 32, an i-type amorphous silicon layer 29 and a p-type amorphous silicon layer 30a are formed. In addition, an i-type amorphous silicon layer 29, a p-type amorphous silicon layer 30a, and a p-type amorphous silicon layer 30b are sequentially stacked in part of the current extraction region 33p. The p-type amorphous silicon layer 30b may be formed so as to cover the entire area on the p-type amorphous silicon layer 30a. The current extraction region 33p is provided with a region where the p-type amorphous silicon layer 30b is directly stacked on the back surface 12 and the i-type amorphous silicon layer is not stacked. The p-type amorphous silicon layers 30a and 30b can be formed with the same thickness, for example. As a result, the film thickness of the amorphous silicon layer (p-type amorphous silicon layer 30b) in the current extraction region 33p becomes the same as that of the amorphous silicon layer (i-type amorphous silicon layer 29 and 29) formed in the overlapping region 32. It is thinner than the thickness of the p-type amorphous silicon layer 30a).
　非晶質シリコン層の膜厚は、例えば、走査型電子顕微鏡（ＳＥＭ）や透過型電子顕微鏡（ＴＥＭ）による断面観察によって確認することができる。非晶質シリコン層の膜厚は、例えば、最大膜厚に基づいて調整してもよいが、平均膜厚に基づいて調整することが好ましい。 The film thickness of the amorphous silicon layer can be confirmed by, for example, cross-sectional observation with a scanning electron microscope (SEM) or a transmission electron microscope (TEM). The film thickness of the amorphous silicon layer may be adjusted based on the maximum film thickness, for example, but is preferably adjusted based on the average film thickness.
　次に、図６～図１７を参照して、光電変換装置１０の製造方法の一例を説明する。 Next, an example of a method for manufacturing the photoelectric conversion device 10 will be described with reference to FIGS.
　図６～図１４は、光電変換部２０の製造工程を示す図である。
　まず、図６に示すように、プラズマ化学気相成長（ＰＥＣＶＤ）やスパッタリングにより、ｎ型単結晶シリコン基板２１の受光面１１上に、ｉ型非晶質シリコン層２２、ｎ型非晶質シリコン層２３、及び保護層２４を順に積層し、裏面１２上に、ｉ型非晶質シリコン層２７ａ及びｎ型非晶質シリコン層２８ａを順に積層する。ＰＥＣＶＤによるｉ型非晶質シリコン膜２２，２７ａの積層工程では、例えば、シランガス（ＳｉＨ4）を水素（Ｈ2）で希釈したものを原料ガスとして使用できる。また、ｎ型非晶質シリコン膜２３，２８ａの積層工程では、例えば、シラン（ＳｉＨ4）にホスフィン（ＰＨ3）を添加し、水素（Ｈ2）で希釈したものを原料ガスとして使用できる。シランガスの水素希釈率を変化させることにより、ｉ型非晶質シリコン膜２２，２７ａ及びｎ型非晶質シリコン膜２３，２８ａの膜質を変化させることができる。また、ホスフィン（ＰＨ3）の混合濃度を変化させることによって、ｎ型非晶質シリコン膜２３，２８ａのドーピング濃度を変化させることができる。なお、ｉ型非晶質シリコン層２２等を積層する前において、ｎ型単結晶シリコン基板２１の受光面１１にテクスチャ構造を形成しておくことが好適である。ここで、「テクスチャ構造」とは、表面反射を抑制し、光電変換部２０の光吸収量を増大させる凹凸構造である。テクスチャ構造の具体例としては、（１００）面を有する受光面１１に異方性エッチングを施すことによって得られるピラミッド状（四角錐状や四角錐台状）の凹凸構造が例示できる。テクスチャ構造は、例えば、水酸化カリウム（ＫＯＨ）水溶液を用いて、（１００）面を異方性エッチングすることで形成できる。 6 to 14 are diagrams showing manufacturing steps of the photoelectric conversion unit 20.
First, as shown in FIG. 6, an i-type amorphous silicon layer 22 and an n-type amorphous silicon are formed on the light-receiving surface 11 of the n-type single crystal silicon substrate 21 by plasma enhanced chemical vapor deposition (PECVD) or sputtering. The layer 23 and the protective layer 24 are sequentially stacked, and the i-type amorphous silicon layer 27 a and the n-type amorphous silicon layer 28 a are sequentially stacked on the back surface 12. In the lamination process of the i-type amorphous silicon films 22 and 27a by PECVD, for example, a silane gas (SiH 4 ) diluted with hydrogen (H 2 ) can be used as a source gas. In the stacking process of the n-type amorphous silicon films 23 and 28a, for example, phosphine (PH 3 ) added to silane (SiH 4 ) and diluted with hydrogen (H 2 ) can be used as a source gas. The film quality of the i-type amorphous silicon films 22 and 27a and the n-type amorphous silicon films 23 and 28a can be changed by changing the hydrogen dilution rate of the silane gas. Further, the doping concentration of the n-type amorphous silicon films 23 and 28a can be changed by changing the mixed concentration of phosphine (PH 3 ). Note that it is preferable to form a texture structure on the light-receiving surface 11 of the n-type single crystal silicon substrate 21 before the i-type amorphous silicon layer 22 and the like are stacked. Here, the “texture structure” is an uneven structure that suppresses surface reflection and increases the light absorption amount of the photoelectric conversion unit 20. As a specific example of the texture structure, a pyramidal (quadrangular pyramid or quadrangular pyramid-shaped) uneven structure obtained by performing anisotropic etching on the light receiving surface 11 having a (100) plane can be exemplified. The texture structure can be formed, for example, by anisotropically etching the (100) plane using a potassium hydroxide (KOH) aqueous solution.
　続いて、図７に示すように、ｉ型非晶質シリコン層２７ａ及びｎ型非晶質シリコン層２８ａを部分的にエッチングして除去する。エッチングする領域は、電流取り出し領域３３ｎ及び電流取り出し領域３３ｐとなる領域である。このエッチング工程では、例えば、スクリーン印刷やインクジェットによる塗工プロセス、又はフォトリソプロセス等により形成されたレジスト膜をマスクとして使用する。エッチング液としては、例えば、水酸化ナトリウム（ＮａＯＨ）水溶液（例えば、１ｗｔ％　ＮａＯＨ水溶液）等を用いる。 Subsequently, as shown in FIG. 7, the i-type amorphous silicon layer 27a and the n-type amorphous silicon layer 28a are partially etched and removed. The region to be etched is a region that becomes the current extraction region 33n and the current extraction region 33p. In this etching step, for example, a resist film formed by a screen printing or ink jet coating process, a photolithography process or the like is used as a mask. As an etchant, for example, a sodium hydroxide (NaOH) aqueous solution (for example, 1 wt% NaOH aqueous solution) or the like is used.
　続いて、図８に示すように、例えば、ＰＥＣＶＤ等により、裏面１２上の端縁領域を除く全域に、ｉ型非晶質シリコン層２７ｂ、ｎ型非晶質シリコン層２８ｂ、及び絶縁層３１を順に積層する。つまり、ｎ型非晶質シリコン層２８ａ上にも、ｉ型非晶質シリコン層２７ｂ、ｎ型非晶質シリコン層２８ｂ、及び絶縁層３１が積層される。この工程により、電流取り出し領域３３ｎとなる領域に、ｉ型非晶質シリコン層２７ａよりも薄いｉ型非晶質シリコン層２７ｂが形成される。換言すると、ｉ型非晶質シリコン層２７ｂが裏面１２上に直接形成された領域を、電流取り出し領域３３ｎとするように後工程を進める。 Subsequently, as shown in FIG. 8, the i-type amorphous silicon layer 27 b, the n-type amorphous silicon layer 28 b, and the insulating layer 31 are formed over the entire region excluding the edge region on the back surface 12 by, for example, PECVD. Are sequentially stacked. That is, the i-type amorphous silicon layer 27b, the n-type amorphous silicon layer 28b, and the insulating layer 31 are stacked also on the n-type amorphous silicon layer 28a. By this step, an i-type amorphous silicon layer 27b thinner than the i-type amorphous silicon layer 27a is formed in a region that becomes the current extraction region 33n. In other words, the post-process is advanced so that the region where the i-type amorphous silicon layer 27b is directly formed on the back surface 12 becomes the current extraction region 33n.
　続いて、図９及び図１０に示すように、レジスト膜１００をマスクとして、絶縁層３１、ｉ型非晶質シリコン層２７ｂ、及びｎ型非晶質シリコン層２８ｂを部分的にエッチングして除去する。エッチングする領域は、Ｐ領域の電流取り出し領域３３ｐとなる領域である。この工程では、まず、レジスト膜１００をマスクとして、縁層３１をエッチングする。絶縁層３１が、酸化ケイ素（ＳｉＯ2）、窒化ケイ素（ＳｉＮ）、又は酸窒化ケイ素（ＳｉＯＮ）である場合は、例えば、フッ化水素（ＨＦ）水溶液を用いてエッチングできる。次に、パターニングされた絶縁層３１をマスクとして、ｉ型非晶質シリコン層２７ｂ及びｎ型非晶質シリコン層２８ｂをエッチングする。この工程により、ＩＮ層２５により構成されるＮ領域のパターニングが完了する。 Subsequently, as shown in FIGS. 9 and 10, the insulating layer 31, the i-type amorphous silicon layer 27b, and the n-type amorphous silicon layer 28b are partially etched and removed using the resist film 100 as a mask. To do. The region to be etched is a region that becomes the current extraction region 33p of the P region. In this step, first, the edge layer 31 is etched using the resist film 100 as a mask. When the insulating layer 31 is silicon oxide (SiO 2 ), silicon nitride (SiN), or silicon oxynitride (SiON), for example, etching can be performed using an aqueous hydrogen fluoride (HF) solution. Next, the i-type amorphous silicon layer 27b and the n-type amorphous silicon layer 28b are etched using the patterned insulating layer 31 as a mask. By this step, patterning of the N region constituted by the IN layer 25 is completed.
　続いて、図１１に示すように、例えば、裏面１２上の端縁領域を除く全域に、ｉ型非晶質シリコン層２９及びｐ型非晶質シリコン層３０ａを順に積層する。つまり、パターニングされたＮ領域上にも絶縁層３１を介してｉ型非晶質シリコン層２９及びｐ型非晶質シリコン層３０ａが積層される。ｉ型非晶質シリコン層２９及びｐ型非晶質シリコン層３０ａは、ＩＮ層２５の場合と同様に、ＰＥＣＶＤ等によってｉ型非晶質シリコン層２９及びｐ型非晶質シリコン層３０ａを順に成膜することで形成できる。ただし、ＰＥＣＶＤによるｐ型非晶質シリコン層３０ａの積層工程では、例えば、ホスフィン（ＰＨ3）の代わりに、ジボラン（Ｂ2Ｈ6）をドーピングガスとして使用する。 Subsequently, as illustrated in FIG. 11, for example, an i-type amorphous silicon layer 29 and a p-type amorphous silicon layer 30 a are sequentially stacked over the entire region excluding the edge region on the back surface 12. That is, the i-type amorphous silicon layer 29 and the p-type amorphous silicon layer 30a are also stacked on the patterned N region via the insulating layer 31. As in the case of the IN layer 25, the i-type amorphous silicon layer 29 and the p-type amorphous silicon layer 30a are sequentially formed from the i-type amorphous silicon layer 29 and the p-type amorphous silicon layer 30a by PECVD or the like. It can be formed by film formation. However, in the lamination process of the p-type amorphous silicon layer 30a by PECVD, for example, diborane (B 2 H 6 ) is used as a doping gas instead of phosphine (PH 3 ).
　続いて、図１２に示すように、例えば、スクリーン印刷等により形成されるレジスト膜をマスクとして、ｉ型非晶質シリコン層２９及びｐ型非晶質シリコン層３０ａを部分的にエッチングして除去する。エッチングする領域は、例えば、電流取り出し領域３３ｐとなる領域の一部であり、エッチング範囲は適宜調整できる。ＩＰ層２６は、通常、ＩＮ層２５よりもエッチングされ難いため、ＩＮ層２５のエッチングに用いたＮａＯＨ水溶液よりも高濃度のもの（例えば、１０ｗｔ％　ＮａＯＨ水溶液）、又はフッ硝酸（ＨＦ，ＨＮＯ3）（例えば、各々３０ｗｔ％）を用いることが好ましい。或いは、ＮａＯＨ水溶液を７０～９０℃程度に加熱して用いること（熱アルカリ処理）も好ましい。 Subsequently, as shown in FIG. 12, for example, the i-type amorphous silicon layer 29 and the p-type amorphous silicon layer 30a are partially removed by etching using a resist film formed by screen printing or the like as a mask. To do. The region to be etched is, for example, a part of the region that becomes the current extraction region 33p, and the etching range can be adjusted as appropriate. Since the IP layer 26 is usually harder to etch than the IN layer 25, the IP layer 26 has a higher concentration than the NaOH aqueous solution used for etching the IN layer 25 (for example, 10 wt% NaOH aqueous solution) or hydrofluoric acid (HF, HNO 3 ) (For example, 30 wt% each) is preferably used. Alternatively, it is also preferable to use an aqueous NaOH solution heated to about 70 to 90 ° C. (thermal alkali treatment).
　続いて、図１３に示すように、例えば、ＰＥＣＶＤによって、裏面１２上の端縁領域を除く全域に、ｐ型非晶質シリコン層３０ｂを積層する。この工程により、電流取り出し領域３３ｐとなる領域の一部に、ｐ型非晶質シリコン層３０ｂの単層構造が形成される。 Subsequently, as shown in FIG. 13, the p-type amorphous silicon layer 30 b is laminated over the entire region excluding the edge region on the back surface 12 by, for example, PECVD. By this step, a single layer structure of the p-type amorphous silicon layer 30b is formed in a part of the region that becomes the current extraction region 33p.
　続いて、図１４に示すように、例えば、スクリーン印刷等により形成されるレジスト膜をマスクとして、ＩＰ層２６及び絶縁層３１を部分的にエッチングして除去し、ＩＮ層２５を露出させる。エッチングするＩＰ層２６及び絶縁層３１の領域は、ｉ型非晶質シリコン層２７ｂが裏面１２上に直接形成された領域上の領域である。 Subsequently, as shown in FIG. 14, for example, the IP layer 26 and the insulating layer 31 are partially removed by etching using a resist film formed by screen printing or the like as a mask to expose the IN layer 25. The region of the IP layer 26 and the insulating layer 31 to be etched is a region on the region where the i-type amorphous silicon layer 27 b is directly formed on the back surface 12.
　図１５～図１７は、ｎ側電極４０及びｐ側電極５０の形成工程を示す図である。
　以下では、各電極の第２導電層４４，５４をシード層として、電解めっきにより、各電極の第３導電層４５，５５及び第４導電層４６，５６を形成する工程を説明する。 FIGS. 15 to 17 are diagrams showing the steps of forming the n-side electrode 40 and the p-side electrode 50.
Hereinafter, a process of forming the third conductive layers 45 and 55 and the fourth conductive layers 46 and 56 of the respective electrodes by electrolytic plating using the second conductive layers 44 and 54 of the respective electrodes as a seed layer will be described.
　まず、図１５に示すように、例えば、スパッタリング等により、ＩＮ層２５上及びＩＰ層２６上に、第１導電層１３及び第２導電層１４を順に形成する。第１導電層１３は、例えば、ＩＮ層２５上及びＩＰ層２６上の略全域に積層される。ここで、第１導電層１３は、後工程でパターニングされて各電極の第１導電層４３，５３となる層である。第２導電層１４は、後工程でパターニングされて各電極の第２導電層４４，４５となる層である。 First, as shown in FIG. 15, the first conductive layer 13 and the second conductive layer 14 are sequentially formed on the IN layer 25 and the IP layer 26 by, for example, sputtering. For example, the first conductive layer 13 is stacked on substantially the entire area on the IN layer 25 and the IP layer 26. Here, the first conductive layer 13 is a layer that is patterned in a later step to become the first conductive layers 43 and 53 of each electrode. The second conductive layer 14 is a layer that is patterned in a later step to become the second conductive layers 44 and 45 of each electrode.
　続いて、図１６に示すように、第１導電層１３及び第２導電層１４を部分的にエッチングして、各層を分断し、互いに分離された各電極の第１導電層４３，５３及び第２導電層４４，４５を形成する。第１導電層１３及び第２導電層１４のエッチングは、例えば、スクリーン印刷等によって形成されるレジスト膜をマスクとして使用し、塩化第二鉄（ＦｅＣｌ3）及び塩酸（ＨＣｌ）を含有する水溶液を用いて行う。エッチングする領域は、例えば、重なり領域３２上の領域とすることが好適である。 Subsequently, as shown in FIG. 16, the first conductive layer 13 and the second conductive layer 14 are partially etched to divide each layer, and the first conductive layers 43 and 53 and the first conductive layers 43 and 53 of each electrode separated from each other. Two conductive layers 44 and 45 are formed. Etching of the first conductive layer 13 and the second conductive layer 14 uses, for example, a resist film formed by screen printing or the like as a mask, and an aqueous solution containing ferric chloride (FeCl 3 ) and hydrochloric acid (HCl). To do. The region to be etched is preferably a region on the overlapping region 32, for example.
　続いて、図１７に示すように、第２導電層４４，４５をシード層として、それぞれ第３導電層４５，５５を電解めっきにより形成する。次いで、第３導電層４５，５５上に、第４導電層４６，５６を電解めっきにより形成することにより、光電変換部２０の裏面側に、ｎ側電極４０及びｐ側電極５０を備えた光電変換装置１０（図２参照）が得られる。電解めっきは、例えば、ｎ側電極４０を構成する第２導電層４４と、ｐ側電極５０を構成する第２導電層５４とに同じ大きさの電流を流して行うことができる。この場合、第２導電層４４，５４上には、同じ質量の金属めっき層が形成される。ゆえに、ｐ側電極５０より積層面積が小さなｎ側電極４０において、第３導電層の厚みが厚くなる。つまり、同じ大きさの電流を流して電解めっきを行うことにより、ｎ側電極４０の厚みをｐ側電極５０の厚みよりも厚くすることができる。 Subsequently, as shown in FIG. 17, the third conductive layers 45 and 55 are formed by electrolytic plating using the second conductive layers 44 and 45 as seed layers, respectively. Next, the fourth conductive layers 46 and 56 are formed on the third conductive layers 45 and 55 by electrolytic plating, so that the photoelectric conversion unit 20 is provided with the n-side electrode 40 and the p-side electrode 50 on the back surface side. The conversion device 10 (see FIG. 2) is obtained. The electroplating can be performed, for example, by flowing a current of the same magnitude through the second conductive layer 44 constituting the n-side electrode 40 and the second conductive layer 54 constituting the p-side electrode 50. In this case, a metal plating layer having the same mass is formed on the second conductive layers 44 and 54. Therefore, in the n-side electrode 40 having a smaller lamination area than the p-side electrode 50, the thickness of the third conductive layer is increased. That is, the thickness of the n-side electrode 40 can be made thicker than the thickness of the p-side electrode 50 by carrying out electrolytic plating while flowing the same current.
　以上のように、光電変換装置１０では、電流取り出し領域３３に形成された非晶質シリコン層の膜厚が、電流取り出し領域３３の他の領域に形成された非晶質シリコン層の膜厚より薄くなっている。このため、電流取り出し領域３３では、コンタクト抵抗が低減して、電流の取り出し効率を高めることができる。また、電流取り出し領域３３の他の領域では、非晶質シリコン層の膜厚をパッシベーション特性の観点から好適な膜厚に設定して、キャリアの再結合を十分に防止し、キャリアのライフタイムを伸ばすことができる。 As described above, in the photoelectric conversion device 10, the film thickness of the amorphous silicon layer formed in the current extraction region 33 is larger than the film thickness of the amorphous silicon layer formed in another region of the current extraction region 33. It is getting thinner. For this reason, in the current extraction region 33, the contact resistance can be reduced and the current extraction efficiency can be increased. In the other region of the current extraction region 33, the film thickness of the amorphous silicon layer is set to a film thickness that is suitable from the viewpoint of passivation characteristics, and carrier recombination is sufficiently prevented, and the lifetime of the carrier is reduced. Can be stretched.
　光電変換装置１０では、電流取り出し領域３３ｎにおけるｉ型非晶質シリコン層２７ｂの膜厚が、電流取り出し領域３３ｎの他の領域におけるｉ型非晶質シリコン層２７ａの膜厚よりも薄くなっている。このため、電流取り出し領域３３ｎでは、パッシベーション特性を発現しながら、コンタクト抵抗をさらに低減させることができ、電流の取り出し効率をさらに高めることができる。 In the photoelectric conversion device 10, the film thickness of the i-type amorphous silicon layer 27b in the current extraction region 33n is smaller than the film thickness of the i-type amorphous silicon layer 27a in other regions of the current extraction region 33n. . Therefore, in the current extraction region 33n, the contact resistance can be further reduced while exhibiting the passivation characteristics, and the current extraction efficiency can be further increased.
　光電変換装置１０によれば、パッシベーション特性と、電流の取り出し効率とのバランスを最適化できる。光電変換装置１０は、キャリアの再結合を防止しながら、電流の取り出し効率を向上させることにより、光電変換効率を高めることができる。 The photoelectric conversion device 10 can optimize the balance between the passivation characteristics and the current extraction efficiency. The photoelectric conversion device 10 can increase photoelectric conversion efficiency by improving current extraction efficiency while preventing carrier recombination.
　本実施形態は、本発明の目的を損なわない範囲で設計変更することができる。 The design of this embodiment can be changed within a range that does not impair the object of the present invention.
　本実施形態では、Ｎ領域及びＰ領域の両方において、電流取り出し領域における非晶質シリコン層の膜厚が、電流取り出し領域の他の領域における非晶質シリコン層の膜厚より薄いものとして説明したが、いずれか一方の領域のみをそのような構成としてもよい。例えば、Ｐ領域では、電流取り出し領域及びその他の領域における非晶質シリコン層の膜厚を同程度に設定してもよい。 In the present embodiment, it has been described that the film thickness of the amorphous silicon layer in the current extraction region is smaller than the film thickness of the amorphous silicon layer in other regions of the current extraction region in both the N region and the P region. However, only one of the regions may have such a configuration. For example, in the P region, the film thickness of the amorphous silicon layer in the current extraction region and other regions may be set to the same level.
　本実施形態では、ＩＮ層２５を積層してからＩＰ層２６を積層するものとして説明したが、ＩＰ層２６を先に積層してもよい。この場合、電流取り出し領域３３ｎの一部に、ｉ型非晶質半導体層が設けられていない領域を形成してもよい。 In the present embodiment, the IP layer 26 is stacked after the IN layer 25 is stacked, but the IP layer 26 may be stacked first. In this case, a region where the i-type amorphous semiconductor layer is not provided may be formed in a part of the current extraction region 33n.
　１０　光電変換装置、１１　受光面、１２　裏面、１３　第１導電層、１４　第２導電層、２０　光電変換部、２１　ｎ型単結晶シリコン基板、２２，２７ａ，２７ｂ，２９　ｉ型非晶質シリコン層、２３，２８ａ，２８ｂ　ｎ型非晶質シリコン層、２４　保護層、２５　ＩＮ非晶質シリコン層（ＩＮ層）、２６　ＩＰ非晶質シリコン層（ＩＰ層）、３０ａ，３０ｂ　ｐ型非晶質シリコン層、３１　絶縁層、３２，３２ｎ，３２ｐ　重なり領域、３３，３３ｎ，３３ｐ　電流取り出し領域、４０　ｎ側電極、４１，５１　フィンガー電極部、４２，５２　バスバー電極部、４３，５３　第１導電層、４４，５４　第２導電層、４５，５５　第３導電層、４６，５６　第４導電層、５０　ｐ側電極、６０　分離溝。 10 photoelectric conversion device, 11 light receiving surface, 12 back surface, 13 first conductive layer, 14 second conductive layer, 20 photoelectric conversion unit, 21 n-type single crystal silicon substrate, 22, 27a, 27b, 29 i-type amorphous silicon Layer, 23, 28a, 28b n-type amorphous silicon layer, 24 protective layer, 25 IN amorphous silicon layer (IN layer), 26 IP amorphous silicon layer (IP layer), 30a, 30b p-type amorphous Silicon layer, 31 insulating layer, 32, 32n, 32p overlap region, 33, 33n, 33p current extraction region, 40 n side electrode, 41, 51 finger electrode portion, 42, 52 bus bar electrode portion, 43, 53 first conductivity Layer, 44, 54, second conductive layer, 45, 55, third conductive layer, 46, 56, fourth conductive layer, 50 p-side electrode, 60 separation groove.

Claims (3)

  1. 　半導体基板と、
    　前記半導体基板の一方の面上に形成された第１導電型の非晶質半導体層を含む第１非晶質半導体層と、
    　前記半導体基板の前記一方の面上の前記第１非晶質半導体層が形成されていない領域に形成された第２導電型の非晶質半導体層を含む第２非晶質半導体層と、
    　前記第１非晶質半導体層と電気的に接続された第１電極と、
    　前記第１電極から離間して、前記第２非晶質半導体層と電気的に接続されるように形成された第２電極と、
    　を備え、
    　前記第１及び第２電極によりキャリアが取り出される電流取り出し領域に形成された前記第１及び第２非晶質半導体層のうち少なくとも一部の膜厚が、他の領域に形成された対応する前記第１及び第２非晶質半導体層の膜厚よりも薄い光電変換装置。     A semiconductor substrate;
    A first amorphous semiconductor layer including an amorphous semiconductor layer of a first conductivity type formed on one surface of the semiconductor substrate;
    A second amorphous semiconductor layer including a second conductive type amorphous semiconductor layer formed in a region where the first amorphous semiconductor layer is not formed on the one surface of the semiconductor substrate;
    A first electrode electrically connected to the first amorphous semiconductor layer;
    A second electrode formed apart from the first electrode and electrically connected to the second amorphous semiconductor layer;
    With
    The film thickness of at least a part of the first and second amorphous semiconductor layers formed in the current extraction region from which carriers are extracted by the first and second electrodes corresponds to the corresponding one formed in another region. A photoelectric conversion device thinner than the film thickness of the first and second amorphous semiconductor layers.
  2. 　請求項１に記載の光電変換装置において、
    　前記第１及び第２非晶質半導体層は、ｉ型非晶質半導体層をそれぞれ含み、
    　前記電流取り出し領域に形成された前記各ｉ型非晶質半導体層のうち少なくとも一部の膜厚が、他の領域に形成された対応する前記各ｉ型非晶質半導体層の膜厚よりも薄い光電変換装置。     The photoelectric conversion device according to claim 1,
    The first and second amorphous semiconductor layers each include an i-type amorphous semiconductor layer,
    The film thickness of at least a part of each i-type amorphous semiconductor layer formed in the current extraction region is larger than the film thickness of each corresponding i-type amorphous semiconductor layer formed in another region. Thin photoelectric conversion device.
  3. 　請求項１に記載の光電変換装置において、
    　前記第１及び第２非晶質半導体層は、ｉ型非晶質半導体層をそれぞれ含み、
    　前記電流取り出し領域の少なくとも一部に、前記各ｉ型非晶質半導体層が設けられていない領域を有する光電変換装置。     The photoelectric conversion device according to claim 1,
    The first and second amorphous semiconductor layers each include an i-type amorphous semiconductor layer,
    A photoelectric conversion device having a region in which each i-type amorphous semiconductor layer is not provided in at least a part of the current extraction region.
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