WO2012108767A2

WO2012108767A2 - A method of manufacturing a solar cell and solar cell thus obtained

Info

Publication number: WO2012108767A2
Application number: PCT/NL2012/050068
Authority: WO
Inventors: Robertus Adrianus Maria Wolters; Johannes Reinder Marc LUCHIES; Wijnand Michiel Godfried VAN HOOFF; Klaas Heres
Original assignee: Tsc Solar B.V.
Priority date: 2011-02-08
Filing date: 2012-02-08
Publication date: 2012-08-16
Also published as: WO2012108767A9; WO2012108767A3

Abstract

The process includes the manufacturing of a solar cell comprising boron doping after phosphorous doping, so as to obtain a substrate (10) with a double-diffused field region (33) and emitters (30), suitably selective emitters, together forming a p-i-n-diode construction. In order to prevent the formation of boron rich layers detrimental for carrier lifetime, a diffusion resistance layer (22) is applied within the through-holes (20).

Description

A method of manufacturing a solar cell and solar cell thus obtained

FIELD OF THE INVENTION

The invention relates to the manufacturing of a solar cell

The invention further relates to a solar cell thus obtained.

BACKGROUND OF THE INVENTION

Solar cells are large area semiconductor devices which convert radiation (i.e. sunlight) into electricity. One important class of solar cells is the group of back-contacted solar cells, meaning that both terminals to the two oppositely doped regions - the emitter region as the emitter and the field region responsible for the back surface field - of the solar cells are placed on the second, i.e. rear or non-illuminated surface of the solar cell. This class of solar cells avoids shadowing losses caused by the front metal contact grid on standard solar cells. Suitably, an emitter is provided on the front or first side (the terms side and surface are hereinafter used exchangably) of the semiconductor substrate (hereinafter also referred to as substrate) . Therewith it is achieved that the junction between the oppositely charged regions in the substrate is close to the front surface which receives the incoming radiation. Suitably, the emitter extends along walls of through-holes through the substrate to the second side of the substrate. Conductors are provided in the through-holes - defining vias - for coupling the one or more emitter regions to first terminals on the second side of the substrate. This solar cell concept is known as a wrap through cell, for instance a metal wrap through (MWT) cell or an emitter wrap through (EWT) cell.

An example of such a solar cell is known from US3.903.428. This patent proposes the vias for the conductors. Patent EP0985233 is another example. After creating the via, phosphorous or any other dopant is introduced in both surfaces of the substrate including the walls of the vias in order to create a homogeneous and continuous emitter on both surfaces of the substrate. This results in a double carrier collecting junction, since the junction is not only present near the front surface, but also near the back surface, and hence is double. The patent gives the example wherein the substrate is p-type doped and the emitter is n-type doped. Possible techniques to form an n-emitter include the screen printing of a phosphorous containing paste on the areas of the cell where an emitter is to be created; the use of a gaseous source such as P0C1₃; spin-on and spray-on deposition techniques. Techniques such as ion implantation would be possible but not at an industrial level yet; the solar cell is a large scale and relatively cheap product per m² surface area, when compared to other silicon based products such as integrated circuits .

When extending the emitter into the through-holes (thus forming emitter extensions), isolation between the field region and the emitter region needs to be maintained. Otherwise, a short-circuit will be formed. In the wrap-through technology, a common approach for maintaining such isolation is the application of a trench or a groove, such that a portion of the field region adjacent to the through-hole is removed. A trench may have the additional benefit that the emitter is further somewhat shortened, leading to both a lateral and a vertical separation of the emitter region and the field region.

Such isolation subsequent to the provision of the field region, and often also after provision of the emitter region has the drawback of reducing yield; if the extension of either the field region or the emitter region is not properly under control, a leakage path may be created leading to low shunt resistance. Since a solar cell typically requires a plurality of through-holes and it will only be accepted if there is no issue around any of the through-holes, such a step is therefore disadvantageous. This problem is particularly present if the substrate is n-type doped, the emitter region is p-type doped, and the field region is n-type doped. While the use of an n-type substrate is considered most beneficial for performance reasons, it provides the issue that a typical p-type dopant species, boron, has a higher diffusion temperature than a typical n-type dopant species such as phosphorous. If the p-type dopant species would be diffused first, the through-holes must be made before the doping. This gives rise to the problem how to prevent redoping of the walls of the through-holes in the second doping step. If the n-type dopant species is diffused first, the n-type dopant species will further diffuse upon provision of the p-type diffusion, which increases the issue of properly isolating the field region and the emitter region.

Another device is known from US5468652, which discloses a solar cell of p-type substrate and p-type back side contacts in the form of filled grooves. Particularly, Fig. 2 shows a device having a front emitter 22 and a back emitter 23. A heavy boron diffusion or aluminum alloy goes through the back emitter to contact the bulk. This device effectively has a different device structure: rather than a field region, it discloses a back and front emitter. It does not appear appropriate to achieve high performance solar cells. Moreover, as US5468652 admits, its process is expensive, while it is much more difficult in its low-cost process to prevent a short-circuit.

WO2010/049268 proposes therefore an alternative solar cell design based on an n-type substrate, wherein the location of the emitter region and the field region are reversed: the field region is located adjacent to the front side of the substrate and along the walls of the through- holes; the emitter region is present adjacent to the rear side of the substrate. This reversal enables the use of aluminum as a p-type dopant species rather than boron. The aluminum is diffused from the solid state and in accordance with a specified pattern: a part of the solid state aluminum dopant source is removed from the second side by etching. This part is an area defining the through-holes and a first area

circumferential to the through-hole. Hence, the field region does not extend into a first portion of the substrate laterally adjacent to the through-hole .

However, the cell concept of WO2010/049268 has some disadvantages; first the reversed location of emitter region and field region is considered disadvantageous for performance perspective: the most relevant junction between the p⁺ and n-region is shifted from the front to the rear side. Moreover, the use of boron is preferred over aluminum as a p- type dopant.

It is therefore a problem of the invention to overcome this issue and to provide an improved process, in which no additional substrate removal step is required to obtain sufficient isolation of the field region and the emitter region. SUMMARY OF THE INVENTION

According to a first aspect of the invention, the invention provides a method of manufacturing a solar cell comprising the steps of:

Providing a monocrystalline semiconductor substrate with a first side and an opposed second side comprising of a dopant species of a first conductivity type in a first concentration;

Doping the second side of the substrate with dopant species of the first conductivity type to define at least one field region, wherein the second side is doped in accordance with a predefined pattern, such that a first area intended for the provision of a through-hole will be outside the field region.

Providing through-holes into the substrate, located in said first areas , each through-hole being provided with a wall;

Applying dopant species of a second conductivity type opposed to the first type for defining at least one emitter region at the first side of the substrate and extending along said walls of the through-holes, and

- Providing conductive material for definition of conductors

extending from contacts of the at least one emitter region through the through-holes .

In accordance with a second aspect, the invention provides a solar cell comprising a monocrystalline semiconductor substrate with a first side and an opposed second side. The substrate is herein provided with a dopant species of a first conductivity type in a first concentration; at least one emitter region defined adjacent to the first side and

comprising dopant species of a second conductivity type opposed to the first type; a field region defined adjacent to the second side and comprising dopant species of the first conductivity type at a

concentration higher than the first concentration, which emitter region, substrate and field region together defining a p-i-n diode. The solar cell further comprises conductors extending from contacts of the at least one emitter region to first terminals extending from the second side of the substrate, said conductors running in through-holes through the substrate, which through-holes are provided with walls along which said at least one emitter region extends, which through-hole extension of the at least one emitter region being isolated from said field region. The solar cell also comprises second terminals defined locally on the field region at the second side. Herein the field region is patterned, such that a first portion of the substrate at the second side around a through-hole is located outside the field region, and wherein the through-holes and the at least one emitter region therein extend to the second side of the substrate, such that the through-hole extension is isolated from the field region in the first portion of the substrate.

In accordance with a further aspect of the invention, a method of manufacturing a solar cell is provided that comprises the steps of: Providing a monocrystalline semiconductor substrate with a first side and an opposed second side comprising of a dopant species of a first conductivity type in a first concentration;

Doping the second side of the substrate with dopant species of the first conductivity type to define at least one field region, wherein the second side is doped in accordance with a predefined pattern ;

Applying dopant species of a second conductivity type opposed to the first type for defining at least one emitter region at the first side of the substrate and extending along any exposed surfaces towards the second side, and

Providing conductive material for definition of conductors extending from contacts of the at least one emitter region to the second side.

In this embodiment, the exposed surfaces may be exposed within through-holes but alternatively or additionally at one or more side faces of the semiconductor substrate, and/or grooves which are not to be filled with conductive material.

In accordance with a further aspect of the invention, a solar cell comprising a monocrystalline semiconductor substrate with a first side and an opposed second side is provided. The substrate is herein provided with: a dopant species of a first conductivity type in a first

concentration; At least one emitter region defined adjacent to the first side and comprising dopant species of a second conductivity type opposed to the first type; and a field region defined adjacent to the second side and comprising dopant species of the first conductivity type at a concentration higher than the first concentration, which emitter region, substrate and field region together constituting a p-i-n diode. The solar cell further comprises conductors extending from the at least one emitter region to first terminals extending from the second side of the

substrate; and second terminals defined locally on the field region at the second side. Herein, the field region is patterned, such that a first portion of the substrate at the second side is located outside the field region, such that the first portion constitutes an isolation between the field region and an extension of the emitter region towards the second side of the substrate.

In accordance with the process of the invention, the field region is applied in a patterned manner rather than being removed afterwards. It has to be understood that this patterned application of the field region is all but evident in the context of the solar cell manufacturing process: a typical solar cell is based on a monocrystalline substrate with a thickness in the order of 100-300 microns. Such a substrate, particularly when provided in commercially attractive sizes such as 6 inch width and optionally larger than that, is vulnerable to crack initiation, particularly at the high temperatures used for doping steps.

As a result of the process of the invention, a first portion of the substrate adjacent to the second side thereof constitutes an isolation between the field region and an emitter extension towards the second side. This emitter extension is particularly the through-hole extension along the through-hole walls, but alternatively and/or additionally the substrate surface along an edge of the semiconductor substrate. This first portion is typically lowly doped, in accordancewith the substrate bulk, It is not excluded that the resistance of this first portion is increased, if so desired, and becomes highly resistive up to electrically insulating. Generally, a design may be chosen such that any resistance increase is not needed.

In order to minimize stress, it is typically assumed best to process the substrate in the first steps most symmetrically; typically, any texturing is applied on both sides, and the first doping step is also applied on both sides (and only thereafter removed selectively on one side) . This identical processing on both sides moreover serves industrial efficiency: the front side and the rear side need not to be distinguished - hence these are merely a first side and a second side. Such distinction would be difficult in view of the absence of any detectable sign on either side. A mask could be used on one side, but the presence of a mask could lead to development of stress due to differential thermal

expansion, and hence a larger risk of crack initiation.

Specifically, the invention thus is based on the insight that a locally applied mask does not substantially increase the risk of crack initiation. In suitable embodiments, it is furthermore applied at a low temperature, so that no further high temperature treatment of the device is needed. Two major embodiments are available

In a first embodiment, the mask comprises a material that can be etched selectively with respect to the silicate glass. Such etch selectivity may be achieved either by difference in material composition, a thickness difference and appropriate choice of the etchant for the silicate glass. It is herein not required that the etch selectivity is high; it is sufficient if any identification is available. Thereto, the mask may further suitably comprises at least one identification

reference. Such identification reference is not merely suitable to distinguish first and second side, and hence front side and rear side, but also to provide a reference for the lateral positioning.

In a second embodiment, the mask is applied on both sides of the substrate in a corresponding pattern. This enables that the substrate remains symmetric and that there is no need for distinguishing front and rear side. Hence, also if the mask is removed in an etching step typically carried out to remove any silicate glass, the substrate may be safely processed on both sides.

It is observed that the mask may be generated either by deposition of a layer or by modification of the semiconductor substrate surface. The deposition of a layer herein is deemed advantageous, in view thereof that modification of the semiconductor substrate surface typically requires a high temperature process such as thermal oxidation. Moreover, layer deposition allows tuning of the layer composition, which may improve etch selectivity .

It is further observed that the local application of the mask may either be achieved photolithographically or in a printing process. The printing process has the advantage of minimizing processing steps.

Moreover, if a texturing has been applied in advance (which is typically done), the substrate surface is no longer planar, requiring a

sufficiently thick coating in order to cover the substrate surface appropriately. In a printing process, the printed liquid is deposited where needed; viscosity of the printing liquid may be tuned so as to prevent outflow in an undesired manner. Furthermore, a printing process has the advantage that the non-printed areas remain clean such that non- uniformities in the doping concentration across the substrate surface due to any mask rests left behind are prevented. The term printing' herein is understood to refer to any application technique allowing application of fluid or paste onto a limited area of a surface, including inkjet printing, screenprinting, dot printing and the like.

In one implementation, the mask comprises a sol-gel type material, and is applied as a sol-gel process. This process is a wet-chemical technique for the fabrication of materials (typically a metal oxide) starting from a chemical solution (or sol) that acts as the precursor for an integrated network (or gel) of either discrete particles or network polymers. Typical precursors are metal alkoxides and metal chlorides, which undergo various forms of hydrolysis and polycondensation reactions. One typical example is a spin-on-glass (SOG) material, as known in the art of semiconductor processing, which after conversion into the network typically a silicon oxide. A suitable manner for the conversion into the typically inorganic network is a heat treatment after deposition.

Optionally, such heat treatment may be combined with any heating required for the diffusion process. Most suitably, the sol-gel material is provided by printing, for instance inkjet printing.

A feature resulting from the process is a solar cell with a via extending from the front side to the rear side and having an emitter extension along the via, such that a substrate portion between said via and a field region provides isolation against shortcircuitry between the emitter region and the field region. This solar cell has the benefits of a good performance and a good reliability.

In a specific embodiment of the process, texturisation is applied only after the doping to create the patterned field region, rather than at the beginning of the process. Most suitably, such texturisation is applied at the first, e.g. front side of the substrate only. This embodiment is suitably to improve the shape at the front side. Typically, an etching step is carried out at the front side directly after the first doping step, f.i. with phosphorous. This etching step again reduces the texturisation profile. This embodiment is particularly suitable for combination with the second embodiment as discussed above. In a further implementation thereof, a protective layer is applied on the second, e.g. rear, side prior to such delayed texturisation of the front side. This protective layer will protect the rear side and the doping applied thereto against being removed during texturisation. Particularly, the protective layer allows deposition of the substrate on a plate or chuck without running the risk of introduction of contamination into the substrate from said plate or chuck. Simultaneously, it allows a good identification of front side and rear side.

In one further embodiment, the use of a patterned field region is combined with the application of a diffusion resistance layer within the through-hole. Such diffusion resistance layer aims at prevention of a boron rich layer in the substrate adjacent to the through-hole. This boron rich layer is commonly associated with degradation of the carrier lifetime in the bulk of the wafer. Suitable diffusion resistance layer are for instance silicon oxide, silicon nitride, silicon oxynitride, and the like. The thickness of the barrier layer can be in the range of 0.3 nm to 300 nm, preferably 5 to 30 nm. It is not excluded that the barrier layer comprises a stack of sublayers. The diffusion resistance layer acts as a resistance against diffusion of boron through the layer without completely blocking boron. It is herein not excluded that the boron diffusion may be in the form of diffusion of boron oxide. Most

particularly, the diffusion coefficient of the boron diffusion through the diffusion resistance layer at the diffusion temperature is reduced to a level at most equal to the diffusion of boron in the semiconductor substrate at the diffusion temperature.

The diffusion resistance layer is suitably applied by chemical vapour deposition, for instance by Phase Enhanced Chemical Vapour

Deposition (PECVD), Low-Pressure Chemical Vapour Deposition (LPCVD), atomic layer deposition (ALD) or the like. Alternatively, the diffusion resistance layer may be applied in a thermal oxidation step. A preferred implementation hereof is the use of a high temperature oxide layer, for instance a thermal oxide or a layer deposited by LPCVD or by ALD.

In another further embodiment, a diffusion mask is applied on the front side. This allows the creation of selective emitter regions into the semiconductor substrate. Most suitably, such mask is again a diffusion resistance layer, such that dopant may diffuse through the diffusion resistance layer. A difference in doping concentration is then created between selective emitter regions and diffusion regions.

Additional doping may be provided into the selective emitter regions, so as to increase the dopant concentration therein. The resulting emitter is a combination of selective emitter regions defined in accordance with the predefined pattern and a continuous diffusion region at a dopant concentration lower than that in the selective emitter region. Any boron- rich layer that develops in the selective emitter may be subsequently removed by a low-temperature oxidation.

It is not deemed required that the diffusion resistance layer remains in the through-hole and optionally on the front side of the substrate after the diffusion step. However, the maintenance of the diffusion resistance layer in the solar cell is not considered

problematic. Particularly, the diffusion resistance layer, when

maintained, can be beneficially used as an adhesion layer for an antireflection coating to be provided on the front side of the substrate, and suitably, also on the rear side.

The conductors in the through-holes are for instance applied by screenprinting of metal paste. This metal paste is effectively a mixture of metal and additives for the improvement of the rheology. Preferably, use is made of a metal paste free of acids, so as to ensure that the diffusion resistance layer is not removed while applying the metal paste and/or in any subsequent firing step. After such removal metal could contact the substrate, which easily gives rise to a shunt.

In a further implementation, an additional barrier layer is applied after the boron diffusion step. This barrier layer is particularly suitable, if no diffusion resistance layer is applied or if such diffusion resistance layer is removed after the boron diffusion step. This barrier layer is chosen so as to block diffusion of metals in the paste into the substrate. As a typical metal is aluminum, the barrier layer suitably comprises diffusion barriers against the diffusion of aluminum, more preferably nitrogen containing layers, most particularly layers wherein such elements are available for forming covalent bonds with aluminum. In case of silicon nitride, the composition is thereto suitably tuned so as to provide a nitrogen-rich composition.

Most suitably, the method is embodied such that the dopant species of the n-type field region further diffuses during a heat treatment carried out for diffusion of the p-type dopant species. This results in a double-diffused field region.

The above mentioned specific embodiment and any dependent claim may be combined with any of the above mentioned aspects of the invention. Herein, it is specifically observed that the patterning of the field region may also be used for provision of an isolation to any other extensions of the emitter region, such as along a side face of the substrate.

It is a further object of the present invention, to provide an industrially viable process for manufacturing a photovoltaic cell that is subdivided into a plurality of subcells, which subcells are to be arranged in a desired circuit topology and wherein such subcells are to operate independently of neighbouring cells. Another object of the invention related thereto is to provide a photovoltaic cell and a resulting device subdivided into subcells.

This further object is achieved in accordance with the invention in a method of manufacturing a photovoltaic cell device provided with a plurality of subcells, each provided with a p-i-n diode, which method comprises the steps of:

providing a semiconductor substrate with a first side and an opposed second side, which first side is to be exposed to radiation, the substrate comprising charge carriers of a first conductivity type;

- providing a plurality of first doped regions of the second conductivity type adjacent to the first side of the substrate, neighbouring first doped regions being separated by at least substantially insulating or semiconductor areas;

defining a second doped region of the first conductivity type adjacent to the second side of the substrate, an intermediate region extending between the first and second doped regions, the first doped region, the intermediate region and the second doped region jointly defining the p-i-n diode, and

providing a second doped region of the first conductivity type adjacent to the second side of the semiconductor substrate, an intermediate region extending between the first and second doped regions, which second doped region is subdivided by at least substantially insulating or semiconducting subdivisions located correspondingly to the at least substantially electrically insulating or semiconductor areas, therewith defining the subcells.

According to a further aspect of the invention, a photovoltaic cell device is provided, comprising a semiconductor substrate with a first side and an opposed second side, which first side is to be exposed to radiation, which cell device comprises a plurality of subcells each comprising a first doped region and a second doped region of opposite conductivity type and an intermediate region extending between the first and the second doped region, which intermediate region is provided with charge carriers of a first conductivity type in a concentration lower than the concentration of the first conductivity type in either the first or the second doped region, wherein the intermediate region is mechanically continuous between the subcells, wherein subdivisions are present between the second doped regions of neighbouring subcells and wherein substantially insulating or semiconductor areas are present between the first doped regions of neighbouring subcells. In accordance with this aspect of the invention, the semiconductor substrate constitutes both the carrier and an active portion of the solar cell. The provision of the electrically semiconducting or insulating areas between the first doped regions and the application of subdivisions through the second doped region into the intermediate regions ensures decoupling of the neighbouring regions and the junctions with the intermediate region.

The subdivisions of the second doped region may be defined prior to and/or subsequent to the step of applying charge carriers to form the second doped region. When defined prior to the application of charge carriers, it is suitably applied in the form of a mask, so as to prevent the formation of the second doped region in accordance with the

subdivisions. This method is further described above and in the figures, in relation to the first aspect of the invention. However, the present aspect is not limited to the patterning of the second doped regions as described above. When defined after the application of charge carriers, the second doped region is locally removed in accordance with the subdivisions .

In one embodiment, the subdivisions and/or the electrically insulating or semiconductor areas between the first doped regions are trenches extending into the intermediate regions. The term trenches is used herein to refer to a removed and thereafter filled or unfilled substrate portion of any shape and includes are for instance grooves, trenches, channels and the like. The shape and depth does not need to be uniform along the trench. The trench may be filled with a suitable, electrically insulating material. Such material may be provided with a printing technique directly into the subdivisions, and suitably at limited locations only. Due to its fluid composition the printed fluid will be distributed through the channels without contaminating the substrate surface. Suitable printing techniques include screenprinting and inkjet printing. A heat treatment for curing may follow the provision of the filler material as known to the skilled person. The trench suitably has an annular extension so as to extend fully around a subdivided portion of either the first doped region or the second doped region. The trenches could be present between the first doped regions and/or as subdivisions in the second doped region. Most suitably, at least some, and preferably all of the subdivisions of the second doped region are embodied as trenches. The second doped region is doped with the same conductivity type as the substrate, whereas the first doped regions are doped with an opposed conductivity type. Therefore, the provision of the subdivisions as trenches more strongly enhances the resistance between individual subcells.

Although trenches provide suitable isolation, it is a disadvantage that it requires additional process steps, and that the provision of trenches generates the risk of initiation of cracks into the

semiconductor substrate. In an alternative embodiment, thus, no trenches are applied on the first side. This may be achieved, for instance, by application of a mask corresponding to a border between neighbouring subcells, prior to the provision of the first doped regions. The mask should be able to withstand any temperature used during the provision of the first doped regions, typically a step of above 700°C.

In order to minimize leakage between subcells, the first doped regions are embodied, in one implementation, as a combination of a selective emitter and a diffusion region surrounding the selective emitter. The selective emitter suitably has a higher dopant concentration than the diffusion region, and is intended as a contact region to a conductor on top of the first side of the semiconductor substrate. As a result thereof, the effective distance on the first side between the first doped regions is equal to the distance between the selective emitters. This distance is larger than the distance between the first doped regions. It therefore appears that the local absence of the diffusion region in the at least substantially electrically insulating or semiconductor area is sufficient.

Suitably, the first doped regions are p-type doped and the intermediate region and the second doped regions are n-type doped. The doping of the p-type first doped regions is suitably provided with boron implantation or boron diffusion. Diffusion processes are preferred for solar cell manufacture for cost reasons. By application of a suitable barrier layer overlying the electrically insulating areas, the diffusion of boron into those areas can be minimized. Particularly nitrides are suitable barrier layers. Alternatively, high temperature oxide layers of sufficient thickness may be used) .

In a further embodiment, the subcells are grouped into subcell groups, the subcells within one group constituting one string. It has been found that the organization of subcells into strings allows appropriate control of the output current and output voltage. Moreover, the string leads only to a limited leakage current from one subcell to any neighbouring subcell through the intermediate region which does not appear to disturb operation or lifetime of the photovoltaic cell device. The string of subcells in one subcell group is particularly a series connection of subcells. It is however not excluded that the string comprises one or more sections with parallel subcells.

Suitably, the subcell groups are mutually separated through intermediate regions with sufficient electrical insulation. A first and second subcell group may thus carry different voltage levels, and be switched either in series or in parallel. Implementations of such sufficient electrical insulation, which do not disturb the mechanical continuity will be discussed below.

Additionally, the voltage differences between neighbouring subcells in different subcell groups are suitable kept limited to a maximum voltage difference, for instance in the order of 10V, more preferably 8V, most preferably 5V. This maximum voltage difference between neighbouring subcells in different subcell groups is a design rule that allows a designer to arrive at an appropriate design. It is herein observed that a solar panel typically comprises a plurality of photovoltaic cell devices manufactured on different substrates. The electrical isolation between those photovoltaic cell devices is anyhow appropriate, such that the design rule within a single photovoltaic cell device may be more strict.

The resulting subdivision of a photovoltaic cell device into several subcell groups with subcells in series allows the generation of an output voltage and output current at any desired level, particularly a voltage level that will not be too high. Moreover, this subdivision reduces the risk for malfunctioning during to shadow effects during use of the solar panels. Shadows falling on the solar panel, for instance due to trees, lead to a higher resistance through some of the cells or subcells. When all are coupled in series, the generated voltage will be significantly reduced as a consequence of the internal resistance due to the shadow effect. With the subdivision in accordance to the invention, the malfunctioning subcells will simply be non-contributing, whereas the other subcells will function appropriately.

Several options are available for the definition of electrically insulating or semiconductor zones within the intermediate region at locations substantially corresponding to the subdivisions between cell groups .

In a first implementation, use is made of local implantation or irradiation so as to damage the crystal lattice. A first suitable embodiment is an implantation with Argon or another noble or inert gas. Such an implantation will increase the resistance of the silicon. It could even lead to amorphous regions in the silicon substrate. A second suitable embodiment is the irradiation with electron beams or the like. Use of electron beam writing has the further advantage that no separate masking is needed, which reduces process steps.

In a second implementation, trenches (or through-holes) are defined at the required locations. Subsequently, the substrate with the trenches is subjected to a thermal oxidation treatment, wherein the first and second sides of the substrate are substantially covered. The oxidation will then occur in the created trenches. Since the thermal oxidation process consumes silicon, the electrically insulating zones will be extended, while at the same time the trenches may get a reduced diameter or may be filled completely. It is one specific advantage that a single mask may be used for definition of the trenches and for protection of the first side of the substrate against the thermal oxidation.

In a further implementation, trenches are defined over a major portion of the subdivisions. As a result thereof, the intermediate region will be limited between the subcells to mechanical bridges. The trenches could extend completely through the intermediate region, so as to create a through-hole from the one side to the other side of the substrate. In this case, the trenches will be limited in lateral extension.

Alternatively, the trenches may extend merely into the intermediate region, for instance to at least 50% of the intermediate region. In this case, the trenches could be, but need not to be, ring shaped around one or more subcells. In this case, it is preferable that the intermediate region is continuous adjacent to the second side, rather than adjacent to the first side.

In an even further implementation, the mechanical bridges defined by thinned silicon, preferably in combination with through-holes, effectively defines a temporary state. That is: after assembly and fixation to a carrier, the mechanical bridges are punched through, such that the subcells will be completely isolated from each other. It is to be understood that such removal of mechanical bridges could be limited to certain subdivisions only. As will be discussed hereinafter, the subcells are to be ordered into units of subcells. The isolation of a first subcell to a third subcell may be more important from that functional perspective than the isolation of the first subcell to a second subcell.

Suitably, these treatments are carried out prior to defining the doped regions of the first and second conductivity type adjacent to the substrate sides. However, particularly the further embodiment based on the generation of mechanical bridges could alternatively be carried out substantially after completion of the processing.

In a preferred embodiment, the first doped regions are defined as selective emitters. The use of selective emitters is a suitable manner optimizing the design of the subcell. Suitably, the selective emitters are provided in a grid type design. Such a grid type of design comprises emitters extending in at least two mutually crossing directions.

Preferably, the directions include an angle of 90 degrees, but that is not necessary. The number of emitters in the at least two directions need not to be equal .

Most suitably, a first terminal is provided on the second side of the semiconductor substrate and is coupled to the first doped region exposed on the first side with a through-silicon vias extending from the first to the second side. A second terminal is also provided on the second side and contacts the second doped region on the second side. Such a type of cell is known as a back-contacted solar cell. The through silicon via could for instance located at an edge of the subcell, but also within the subcell. The latter arrangement, suitably in combination with the use of more than one through silicon via per subcell, is deemed most beneficial. A suitable number is less than 10 per subcell. Typically, the at least one through silicon via is present at a crossing of said selective emitters.

The first conductivity type may be either p or n, and is preferably n-type, so that also the intermediate region is n-type doped. Solar cells based on n-type silicon are deemed to provide a higher efficiency. The semiconductor substrate is most suitably a monocrystalline silicon substrate. The doping level of the n-type substrate is preferably in the range of 1.10¹⁵-1.10" ( cm ) . The doping level of the first and second doped regions is suitably higher than 1.10¹⁸ crrf³.

The mutual distance between neighbouring subcells is suitably in the range of 10-100 microns. The number of subcells per cell of an 8 inch (20 cm) format as typically used in semiconductor processing, is suitably in the range of 4 to 64, more preferably in the range of 9 to 25.

Suitably, the subcells all have same dimensions, but this is not deemed necessary. The form of a single subcell may be square, circular, hexagonal, octagonal, but also rectangular or oval, such that a first dimension of the subcell is larger than a second dimension (in a direction perpendicular to the first dimension) . The subcell size is preferably optimized such that a single via is sufficient.

BRIEF INTRODUCTION OF THE FIGURES

These and other aspects of the invention will be further elucidated with reference to the figures, in which:

Fig 1-5 show in diagrammatical cross-sectional view several stages of the method of the invention;

Fig. 6 shows in diagrammatical cross-sectional view the device of the invention according to one embodiment;

Fig. 7-9 shows in diagrammatical cross-sectional view several stages of a second embodiment of the method of the invention;

Fig. 10-20 show views and circuit topology of the pho photovoltaic cell device in accordance with one aspect of the invention, comprising microcells ;

Fig. 10 is a diagrammatical, cross-sectional view of said

photovoltaic cell device;

Fig. 11 is a diagrammatical top view of a first embodiment of the photovoltaic cell device, as shown in Fig. 10;

Fig. 12 is a diagrammatical top view of a second embodiment of the photovoltaic cell device comprising microcells;

Fig. 13-16 are diagrammatical figures for representing the circuit topology used in the photovoltaic cell device comprising microcells, and.

Fig. 17-20 are diagrammatical, cross-sectional views of consective stages of for manufacturing a cell device comprising microcells.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The Figures are not drawn to scale and merely intended for illustrative purposes. Equal reference numerals in different figures refer to like or equal parts. Particularly, the semiconductor substrate 10 shown in the following figures is shown as being provided with merely a single through-hole 20 to be converted into a via 40. However, in practice, a plurality of through-holes will be applied into the substrate 10. It is observed that the terms front side will be applied for the first side 11, if and where the first, front side 11 can be distinguished from the second, rear side 12. The semiconductor substrate will also be referred to as the substrate. The term via is used for reference to a through-hole at least partially filled with conductive material so as to constitute a conductor from the first side 11 to the second side 12 of the substrate 10. Where no confusion occurs, the terms may also be used interchangeably, in line with the practice in the art. In addition to providing an well-defined isolation between the field region and the emitter region, the invention further has the advantage of a reduction of process steps.

Fig. 1-6 show consecutive steps of an embodiment of the method of the invention in cross-sectional diagrammatical views. Fig. 1 shows a semiconductor substrate 10 with a first side 11 and a second side 12. The first side 11 and optionally the second side 12 typically have been texturized in advance of doping processes. The semiconductor substrate 10 of this example is a monocrystalline silicon substrate. While silicon substrates constitute the best available compromise between manufacturing costs and quality, it is not excluded that alternative substrates are used. Such alternative substrates could be made of III-V materials, but more likely incorporate one or more layers of a different material, such as a III-V material, or SiGe, SiC and the like as known to the skilled person. The semiconductor substrate is doped with a dopant of the first conductivity type, which is in the preferred example n-type. The doping concentration is moderate, for instance 10¹⁶ /cm³.

In accordance with the present invention, the nH—doped region is to be applied on the second side 12 according to a predefined pattern.

Thereto, a suitable mask 19A, 19B is applied in advance of the doping step. In a first embodiment, the mask is applied both on the first side 11 and the second side 12. In the second, shown embodiment, the mask is applied on the second side 12 only. The second side is therewith identified as the rear side, and the first side as the front side. The front side is the side that is intended for receiving irradiation during use; the solar cell will be assembled on its rear side 12 to a carrier.

The mask 19A, 19B, will effectively be present on limited areas of the substrate 10 only. The mask 19A, 19B typically comprises portions 19A at locations where in a later stage of the process (see Fig. 6) vias 40 are provided and an isolation is needed between a field region 13 and an emitter 31 extending along the via 40. It therewith defines first areas. These areas are typically roughly circular around a central axis where the via 40 is planned. However, variations of such shape (hexagonal, oval, square, rectangular) are not excluded and may be chosen in view of certain tolerances, or in order to compensate for misalignment in a certain direction when applying through-holes 20. A solar cell with a 6 inch or larger diameter is foreseen to comprise 100 vias or less, suitably less than 50. As a result, the extension of the first areas on the rear side 12 of the substrate will therefore be relatively limited in comparison to the complete surface area.

The mask further suitably comprises portions 19B that are

positioned at and/or adjacent to an edge of the substrate 10. In one embodiment of the process, a side face of the substrate 10 is not protected during doping with a p-type dopant such as boron. As a result, some protection is needed in order to provide a shunt at or adjacent to the edge between the field region 13 and the emitter 31. Evidently, alternative process may be envisaged wherein the side face of the substrate 10 is removed or covered or not exposed to the p-type doping process such that such mask portion 19B is not needed.

Several methods are available for application of the mask 19A, 19B that is able to block diffusion from the vapour source. One of these methods is based on the local oxidation of silicon exposed within a patterned nitride layer. After removal of the nitride layer, the diffusion of the dopant species will be blocked through the thermal oxide mask. Another method involves the provision of a mask 19 directly by application of a patterned layer. Such patterned layer is suitably applied either by vapour deposition or by printing; due to the texturing of the substrate that occurs typically both on the first side 11 and on the second side 12, coating processes do not provide a layer with a uniform thickness. Most suitably, use is made of printing; suitably, use is made of a sol-gel type material that is converted into an inorganic layer in a heat treatment. A preferred embodiment thereof is a spin on glass material which after being cured behaves as Si02. A suitable precursor for Si0₂ is tetraethoxyorthosilicate (TEOS) .

Fig. 2 shows the substrate 10 after a second stage of the

processing. Herein, the semiconductor substrate 10 is provided with a region 13 of nH—doped material. Suitably, use is made of phosphorous doping in a manner known to the skilled person, for instance by vapor deposition. According to one embodiment, the phosphorous doping is diffused into the substrate 10 by a heat treatment of approximately 800°C for 5-50 minutes in an atmosphere containing 0₂ and P₂0₅ vapour. This process results in the formation of a silicon oxide film (not shown) which incorporates P₂0₅. At the interface the substrate and the silicon oxide film, the P₂0₅ is reduced to elemental phosphorous, which diffuses into the substrate 10, resulting into a region adjacent to the front side 11 (not shown) and a region 13 adjacent to the rear side. Subsequently, the silicon oxide film is removed (also referred to as PSG etch) by dipping the substrate in a 1-50% HF solution for about 0.5-10 minutes, or exposing the substrate to a HF vapour. The thickness of the mask 19A, 19B is preferably chosen such that after the HF treatment it is still of such thickness remains present at the rear-side 12 of the substrate 10. More specifically, the mask 19A, 19B acts as a protection in the boron diffusion step. As will be understood, any boron diffusion in the first portion of the substrate 10 below the mask 19A, 19B, will create a conductive path from an emitter extension along the walls of the through- hole towards the field region. This again would risk a shunt. It is therefore important that the first portion of the substrate is protected in the boron diffusion step, for instance by the mask 19A, 19B.

It is observed that the phosphorous doping may be applied both on the front side 11 and on the rear side 12. Then, the region adjacent to the front side 11 is removed by etching, for instance using a mixed solution of 1-30% HF and 0.1-50% HN0₃. This result in a substrate 10 that has been doped at its rear side 12 with a dopant species of the first conductivity type to define at least one field region 13.

Instead of using a vapour phase dopant, a solid phase dopant could be applied. Such solid phase dopant could be applied locally, for instance by screenprinting or by patterning a layer of the solid phase dopant in accordance with the desired pattern prior to a heat treatment resulting in the diffusion. This implementation has the advantage that the mask 19a, 19b may be left out.

Fig. 3 shows the substrate 10 after a third stage in the

processing. A through-hole 20 is provided into the semiconductor substrate 10, and extends from the front side 11 to the rear side 12 thereof. Typically, a plurality of through-holes 20 is applied in a single solar cell, so as to reduce a lateral distance over which generated current has to be transported to a terminal. The through-holes are typically applied by laser etching, although other forms of etching, such as reactive ion etching or a combination of reactive ion etching and wet-etching are not excluded. While the through-hole 20 is shown to be straight, it is not excluded that the through-hole 20 is further modified to have a varying diameter, or that any sharp edges at its top and bottom side, i.e. on the front side 11 and the rear side 12 are removed. The diameter of the through-hole is typically in the order of 5-400 microns. In one implementation, the through-hole is filled with a conductor in a metal-wrap through cell. In another implementation, the through-hole is filled with a conductor in an emitter-wrap through cell. The diameter of the through-hole is suitable less in the emitter-wrap through cell than in the metal-wrap through cell.

Optionally, a diffusion resistance layer 22 is suitably applied by chemical vapour deposition or thermal oxidation, and more preferably by low pressure chemical vapour deposition (LPCVD), atomic layer deposition (ALD) or a rapid thermal anneal (RTA) . The diffusion resistance layer is further intended to create selective emitter regions, localized emitter regions on the front side 11 having a higher dopant concentration than other portions of the emitter region and being highly suitable as contact areas for a conductor to be applied on the surface. It is not excluded, and it may even be advantageous, that outside the selective emitter regions p+ material is present but in a lower dopant concentration, particularly resulting from diffusion through the diffusion resistance layer. The diffusion resistance layer for instance has a thickness of 2- 100 nm, preferably 3 to 30 nm.

Fig. 4 shows the substrate 10 in a fourth stage, after the provision of the doping species of a second type, in this case p type, and more particularly a boron diffusion. The Boron diffusion source may be a vapour source or a coating source. In the oven the substrate is heated for a certain period of time and to a certain temperature so as to diffuse Boron into the front side of the substrate 10, and create an emitter region 31. The emitter 31 herein also extends along walls of the through-hole 20, therein defining a through-hole extension 31C of the emitter 31. Simultaneously, the phosphorous doping at the rear side 12 of the substrate 10 is diffused as well, so as to create a double-diffused field region 13. Successful results have been obtained with a Boron vapour source for the diffusion. Two substrates are put back-to-back into the oven and heated at 900-1000°C for 30-120 minutes, for instance at 950°C for 1 hours in an atmosphere including an 0₂ and boron oxide (B₂0₃) vapor. As explained above, this B₂0₃ vapor is typically in situ created from a Boron tribromide (BBr₃) vapour in the presence of oxygen. The boron oxide vapour reacts with the silicon surface to create elemental boron and silicon oxide. The elemental boron then diffuses into the silicon substrate.

The silicon oxide is typically contaminated with boron oxide, resulting in a borosilicate glass. After the termination of the diffusion treatment, the borosilicate glass is suitably removed. The removal of the borosilicate glass may be effected either with an acid such as HF or hot water or any other known etchant which allows etching of the borosilicate glass .

Fig. 5 shows the substrate 10 after the provision of a layer or layer stack 32A, 32B, 32C. The layer or layer stack may be used as a passivation layer and/or as an anti-reflection coating. For sake of clarity, it will be referred to as a passivation layer. The passivation layer 32A, 32B, 32C is in this embodiment applied on the front side 11, in the through-hole 20 and on the rear side 12. The passivation layer suitably comprises SiN, as known to the skilled person, but alternative materials are by no means excluded. It goes without saying that the passivation layers 32A, 32B, 32C could be applied in separate steps and then do not need to have identical composition. A thickness and shape of layer 32C will depend very much on the deposition method employed.

Similarly to layer 32C also a layer at the edge of the wafer may be formed; this layer is not shown in the figure. When using SiN, it is deemed beneficial to apply an adhesion layer between the substrate surface and the silicon nitride layer, for instance an oxide. It is not excluded that the passivation layer 32A, 32B, 32C comprises a plurality of thin layers, which are particularly optimized with respect to its further use as anti-reflection coating. A further alternative for the passivation layer 32A, 32B, 32C resides in the provision of an amorphous silicon layer stack. These amorphous silicon layers are suitably deposited by Plasma enhanced chemical vapour deposition (PECVD), for instance in a parallel plate plasma deposition driven by a 13.5 MHz power source, or in an inductively coupled plasma PECVD set up. The thickness of amorphous silicon layers in the stack is suitably 20 nm or less, preferably lo nm or less. The stacks typically comprise an intrinsic layer and a p-doped layer on the front side 11, and an intrinsic layer and an n-doped layer at the rear side 12. It has turned out that such amorphous silicon layers not merely act as passivation layers, but also result in silicon heteroj unction solar cells with higher efficiency.

Fig. 6 shows the resulting solar cell 100, obtained by the provision of conductive material to define conductors 40, 41 and terminals 51, 52. The conductors include a via 40, i.e. the filled through-silicon through-hole and the conductor 41 on the front side 11. The conductor 41 on the front side 11 suitably comprises silver and or aluminum, the via 40 for instance comprises a silver/aluminum alloy or silver. Such type of conductors are typically applied using a metal paste by screenprinting in a process known in the art, as deemed most beneficial from a cost perspective. The screenprinting paste applied on the front side 11 is typically an acid-containing screenprinted paste that is able, upon heating, to etch away underlying layers, i.e. portions of the passivation layer 32A. After deposition, the screen printed paste is typically fired. The through-holes 20 are suitably filled with conductive material by screenprinting a non-firing through paste, most suitably from the rear side 12. Such non-firing through paste, typically a specific paste composition without or with a low level of activators. Activators in paste material typically include organic acids, such as alkyl and aryl carboxylic acids, organic halogen acid adducts,

halogenated organics, ammonium halides and halogenated pyridines. A non- firing through paste is also known as a low-activity paste, for instance HeraSol SOL 109 as commercially available from Heraeus GmbH.

The present solar cell device 100 is provided with first terminals 51 and second terminals 52. It is observed that typically a plurality of both the first terminals 51 and the second terminals 52 are present on the rear side 12 of the substrate 10. The first terminals 51 are electrically connected to the vias 40; the second terminals 52 are electrically coupled to the field region 13. It is suitable that the field region 13 is contacted in a distributed pattern, for instance in the form of a star, H-shape or the like. The shape may be optimized to reduce series resistance to the field region 13 and to reduce metal consumption. The second terminals 52 may comprise such distributed contacts . Alternatively, an additional layer may be provided for the definition of such contacts. Suitably, both the first and the second terminals 51, 52 are substantially dot-shaped where contact will be made to a conductor in a panel carrier, which is known per se as a back sheet foil. Suitably, the processing is carried out such that both terminals are applied in a single process step. Therefore, most suitably, the via 40 extends to the same level as the substrate 10.

Fig. 7-9 show three steps in an alternative embodiment of the method in accordance with the invention, corresponding to the steps indicated in Fig. 3-5. The other figures are not reproduced again, but it is intended that the process of this second embodiment comprises the same steps as illustrated therein. This is an alternative version of the second embodiment of the invention, based on selective processing of the rear side 12, wherein also an identification of the rear side 12 relative to the front side 11 is maintained. Fig. 7 shows the substrate 10 after a third step. Herein, following the patterned provision of the field region 13 on the rear side 12 of the substrate, the rear side 12 is coated with a protective layer or layer stack 15. In a preferred embodiment, this is a layer stack comprising an adhesion layer, for instance an oxide, such as silicon oxide and another layer, for instance a nitride, such as silicon nitride. This protective layer 15 is suitably provided with chemical vapour deposition, typically low-pressure chemical vapour deposition as known to the skilled person for the provision of passivation layers. This Fig. 7 does not show the mask 19A, 19B, but it is suitably left in, as shown in Fig. 3 to reduce the number of process steps. That is beneficial for identification of rear side 12. After deposition of the protective layer 15, the

identification can be based hereon. Even though it suitably extends on the complete rear side 12, such protective layer 15 will have a surface structure different from that of the blank semiconductor substrate exposed on the front side 11.

Fig. 8 shows the substrate after the fourth stage. Suitably, it is only at this stage that a texturisation step is applied on the front side 11. This late texturisation leads to better controlled front-side pyramids and hence better light trapping. It moreover leads to an improved silicon-oxide interface definition at the front side, reducing dark current and/or surface recombination. Additionally, the late texturization step removes any phosphorous doping from the front side 11 of the substrate 10. Such phosphorous doping of the first side 11 of the substrate 10 may occur intentionally or unintentionally during the phosphorous doping step as shown in Fig.2. While in the conventional process an additional step of removing a substrate part on the first side 11 is required, this step can be left out with the present late

texturisation embodiment. This is considered a relevant process

improvement, particularly suitable in combination with the patterned application of the field region 13 and deemed most suitable for an MWT (metal wrap through) type solar cell.

Furthermore, the late texturization step may further be exploited to remove any phosphorous doping from the wafer edge, i.e. a side face of the semiconductor substrate 10. This removal of wafer edge doping is suitable so as to prevent a shunt between the emitter region and the field region.

Suitably, the protective layer 15 prevents texturisation of the rear side 12. Texturisation is typically carried out with wet-chemical etching, for instance with an etchant such as potassium hydroxide (KOH) . The substrate 10 is then for instance put into suitable bath with the etchant. This protection layer furthermore will prevent occurrence of any parasitic boron doping during the subsequent diffusion step of p-type charge carriers.. The fourth stage further comprises the definition of through-holes 20, either before or after the texturisation .

Fig. 9 shows the diffusion step of the p-type charge carriers, particularly boron on the front side 11, along the walls in the through- holes 20 and along the side faces of the substrate 10. It is observed that any further modification as discussed above, such as the creation of selective emitters on the front side 11 could also be applied in this embodiment .

Fig. 10 shows on a larger scale the device as shown in Fig. 6, with additionally the subdivisions 151, 152 applied as trenches into the semiconductor substrate 10 from the first side 11 and from the second side 12. These trenches 151, 152 clearly indicate the arrangement of the photovoltaic cell device 100 with a plurality of subcells 200. The subcells 200 are mutually mechanically coupled through the intermediate region 35 of the substrate 10. The first doped regions 31 and second doped regions 33 are however mutually insulated through the subdivisions

151, 152.

Instead or in addition to the application of trenches, the field region 13B may be provided in accordance with a predefined pattern, which defines the subdivisions 152. This patterned application is suitably implemented by application of a mask on the second side 12 prior to phosphorous doping. One way of application such mask is wet-chemically, for instance using a sol-gel material, more particularly a spin-on-glass material, as known per se. The spin-on-glass material may herein be provided by printing, for instance inkj etprinting . In addition to defining the subcells, the mask may be used as an alignment feature. Such a mask suitably withstands etching of the phosphosilicate glass (PSG) needed after the doping step. It may then be used as a protection layer against parasitic boron diffusion in the boron diffusion step.

In a similar manner, a mask could be applied on the first side 11 prior to the boron diffusion, so as to prevent the diffusion of boron into the subdivisions 151.

In accordance with one aspect of the invention, the substrate is divided into a plurality of subcells that are located adjacent of each other. The subcells are to be integrated into a circuit or string. As specified in WO2010/037393, such subdivision enables first of all that the resulting output voltage is increased. This increase in output voltage makes the implementation of an efficient and suitable power converter, particularly a DC-DC converter, much simpler. The

WO2010/037393 teaches the formation of a string of subcells (coupled in series) in particular. However, it is not deemed necessary that all subcells are coupled in series; any other circuit topology may be chosen. This may be done for instance to reduce the impact of shadow effects.

In accordance with the invention, the mutual coupling of individual subcells is arranged in an interconnect level provided externally from the semiconductor substrate. Use can be made of a printed circuit board, a tape material, a flexible printed circuit board material, bonding wires, or the like. Preferably, use is made of a sheet-like carrier with conductors. This simplifies the assembly process, which is typically carried out for a solar panel comprising a plurality of substrates, and hence large plurality of subcells.

However, when each subcell would require separate assembly into the solar panel, assembly costs would go up rapidly. It is thus desired that the substrate remains a single unit that can be assembled as such into the solar panel. The photovoltaic cell device as shown in Fig. 11 provides such functional subdivision without negative impact of

electrical interaction between neighbouring subcells and without disintegration of the substrate as a whole.

Fig 11 is a diagrammatical top view of a photovoltaic cell device 100 that in many aspects corresponds to the device shown in Fig. 10. For sake of clarity it is observed that some features are shown several times in this Fig.11, while their reference numeral has been indicated merely once in view of clarity. The subcell 200 is herein delimited by subdivisions 151. Each subcell 200 comprises one or more through silicon vias 40 so as to connect a grid of conductors 41, 50 on the first side to the terminal 51 on the rear side 12 (as shown in Fig. 10) . The grid of conductors 41, 50 is coupled to the first doped region 31 (not shown) . As shown in Fig. 6, the first doped region 31 suitably comprises a selective emitter 30 with higher dopant concentration so as to act as an exposed contact to the conductors 41, 50. The conductors 41 are in the form of straight lines at mutually equal distances. The conductors 41 suitably extend along and over the selective emitter regions. This is deemed beneficial so as to have minimum resistance. It is however not excluded that any other pattern or grid for the conductors is chosen. Object is to ensure that the complete surface of the subcell 200 is adequately provided with a current connection in the form of conductors 41, 50. Furthermore, the number of vias 40 may be defined. A limited number of vias 40 per subcell 200 is preferred so as to loose minimum surface area. However, a via 40 of a certain design (e.g. conductor material, diameter, substrate thickness) typically has a maximum current density. As a consequence, more than one via per subcell may be necessary in certain designs. The subcell 200 of the present embodiment for instance has 4 vias, and the number could alternatively be 2, 3, 5, 6 or even more than 6.

Fig. 12 shows an alternative embodiment of the photovoltaic cell device 100 in accordance with the invention. This embodiment comprises subcells 200 arranged in subcell groups 300. The use of subcell groups 300 typically allows the reduction of size per subcell 200, such that one via 40 per subcell 200 is a realistic design option. This embodiment furthermore allows to provide additional isolation 110 between the subgroups 300. In view of the larger scale of the subgroups 300, a number of trenches 110 can be provided into the substrate 10, or isolation may be provided in an alternative manner. If trenches 110 were applied around each subcell 200, the cell device 100 would likely become too fragile to withstand assembly and logistics in sufficiently high yield. It is not necessary for a proper operation that the trenches 110 completely isolate the subgroup 300 from neighbouring subgroups.

The trenches 110 serve to isolate certain areas, such that the effective resistance for charge transport from between the groups 300 increases. Therewith the leakage current path between one first doped region 31 (emitter) and a second doped region 33 (field region) in a neighbouring cell group 300 will reduce as compared to the intended current path between said first doped region 31 and the second doped region 33 within the same subcell. The location of the trenches 110 is most suitably coupled to the location of selective emitter regions 30 when present. The effect of increased resistance is may be based on twofold microscopic effect: first an effectively longer path through the intermediate region; secondly, a blocking and deviation of field lines, such that the charge carriers running through the substrate 10 (and particularly the intermediate region 35) are less deviated to the neighbouring subcell group. Additionally, the trenches constitute interfaces that may reflect radiation.

In one embodiment, a first and a second neighbouring subcells 200 in different subcell groups 300 are coupled in parallel to each other, while the intermediate region is not partially blocked by means of a trench or other isolation. Being coupled in parallel and hence to be operated on the same voltage level, there is no risk for deviating currents. The absence of any trench or other isolation then supports mechanical stability.

The subcell group 300 constitutes a string of subcells 200, which is preferably a series coupling of the subcells 200. This is considered suitable so as to simplify interconnection. It will however be clear to the skilled person that the string may comprise one or more sections with subcells coupled in parallel within the string. Such parallel connection may be desired if not all subcells have the same size.

Fig. 13-16 are diagrammatical figures for representing the circuit topology used in the photovoltaic cell device in accordance with the invention. For reasons of clarity each individual subcell has been numbered herein as CI to C16. The arrows depict the order in which the subcells are organized in a string. It will be clear that one string corresponds to one subcell group.

Fig. 13 shows diagrammatically a simple order in which a

photovoltaic cell device 100 is subdivided into 9 subcells C1-C9 that constitute a string. The string is suitably implemented such that the second terminal of a first cell (CI) is connected via the backsheet to the first terminal of a second cell (C2) . With a voltage gain of approximately 0.6V per subcell, the current is approximately 2A. The voltage difference between neighbouring subcells is at most 3V,

particularly between subcells CI and C6 and between subcells C4 and C9. A resulting leakage current between these subcells will be at most 9 mA. The overall leakage current will then be between 10 and 40 mA. This corresponds to 0.5 to 2% of the current, which is a minor loss. For a panel with 35 cells, this leads to the option to design a topology based on 5 parallel strings of 7 cells in series. The overall voltage gain is then 35V, and the resulting current 10A. Without subcells, the voltage difference in one cell would still have been 0.6V, while the current is 18A. The maximum achievable voltage gain, with a single string is then 21V. A single string is however very sensitive to shadow effects and local malfunctioning of a cell or assembly connection.

Fig. 14 and 15 show diagrammatically two embodiments of a

photovoltaic cell device 100 subdivided into two subcell groups 300 each with 8 subcells 200, C1-C8 and C9-C16. The Advantage of the configuration of Fig. 15 is that the neighbouring cells C2 and C9 are on the same voltage level. There is thus no need for provision of additional electrical isolation means between them. The same holds for C4 and Cll, for C6 and C13, for C8 and C15, provided that indeed the input voltage for both subcell groups is identical. However, there is a voltage difference between CI and C2 and between C9 and CIO of 4.2V. Moreover, the input of the string is on the same side as the output of the string. For an arrangement with minimum conductors at assembly level - and thus minimum complexity and minimum losses at the assembly level, it is preferred that the input and output of the string are on opposite sides of the subcell group.

Fig. 14 herein shows an alternatively. The voltage difference between subcells C2 and C9 is still identical to zero, with the

assumption of identical input voltages for both subcell groups. The maximum voltage difference between the subcells within a string is now 1.8V, and the input and output of the string are located on opposite sides of the subcell groups.

Fig. 16 shows a further embodiment, with three subgroups in a single photovoltaic cell device 100. The first group comprises the subcells C1-C6. The second group comprises the subcells C7-C12. The third group comprises the subcells C13-C18. The photovoltaic cell device 100 is herein shows as a circular wafer. Typically this wafer is cut into a rectangular shape prior or subsequent to processing of the substrate to the photovoltaic cell device. It will be clear the provision of a rectangular shape results in loss of surface area. Such losses are reduced with a round, hexagonal or octagonal shape, which shapes are however less easily to integrate into a panel without empty corners. The present Figure 16 demonstrates that the subcells do not need to have identical shape, even though in a single string surface area of a subcell is suitably constant. The Fig. 16 furthermore shows that a single photovoltaic cell device 300 may be subdivided into three groups, with variations in the layout. The advantage of using three subgroups per wafer is that there need not to be any straight line with trenches 110 across the substrate. This reduces the risk of cracking of the substrate along such line.

Fig. 17-20 show consecutive stages of an alternative manufacturing method for manufacturing subcell-based devices. While the preceding Figures showed subcell groups mutually isolated with trenches, this alternative manufacturing method leads to trenches filled with oxide. Fig. 17 shows a semiconductor substrate 10 with a first side 11 and an opposed side 12. A protecting layer 101 is provided both on the first side 11 and on the second side 12. The protecting layer is suitably a nitride, such as silicon nitride as known to the skilled person.

Fig. 18 shows the substrate after a second stage in the manufacturing. Trenches 110 extending from the first side 11 to the second side 12 have been created herewith. Typically, use is made of a laser, but reactive ion etching may be used alternatively as known in the art .

Fig. 19 shows the substrate after a thermal oxidation treatment.

The presence of the protecting layer 101 prevents growth of a thermal oxide onto the first or the second side 11, 12 of the substrate 10. However, no protection is applied in the trench 110. As a consequence, the thermal oxide 111 will growth within the trench 110. It is observed that the silicon oxide has a lower density than silicon, such that the trench 110 will be automatically filled with silicon oxide. Though not shown in the figure, thermal oxidation is based on silicon consumption and will lead to a thermal oxide 111 which is wider than the original trench 110. Moreover, while trenches are limited laterally so as to maintain substrate integrity, the oxide will further develop in lateral directions. In other words, the thermal oxide may substantially circumfere a subcell or subcell group. Due to diffusion limitation, the oxide growth may be terminate before the silicon oxide on both sides of the original trench has merged into a single body. This is indicated with the dashed line. It appears beneficial to leave a gap at the end of thermal oxidation; stresses could develop due to the difference in thermal expansion between silicon and silicon oxide (smaller in silicon oxide) . If desired such gaps may be filled at a later stage, for instance with a low temperature oxide applied by chemical vapour deposition or in liquid form.

Fig. 20 shows the resulting photovoltaic cell device 100. After the provision of the thermal oxide, the protecting layer may be removed and processing is continued with the steps indicated in Fig. 1-6, or an alternative process. It is observed that the protecting layer 101 could even be kept on the first side 11 during provision of the second doped region 33 from the second side by means of phosphorous doping. There is then no need to remove the phosphorous doping again from the first side of the substrate 10. As shown in this Figure, the oxide 111 forms a border of an individual subcell 200. It will be understood that the oxide 111 may alternative constitute a border of the subcell group.

Claims

A method of manufacturing a solar cell comprising the steps of: Providing a monocrystalline semiconductor substrate with a first side and an opposed second side comprising of a dopant species of a first conductivity type in a first concentration;

Doping the second side of the substrate with dopant species of the first conductivity type to define at least one field region, wherein the second side is doped in accordance with a predefined pattern, such that a first area intended for the provision of a through-hole will be outside the field region;

Providing through-holes into the substrate, located in said first areas, each through-hole being provided with a wall;

Providing conductive material for definition of conductors extending from the at least one emitter region through the through- holes .

The method as claimed in Claim 1, wherein the doping of the second side comprises the step of applying a mask onto the first area and applying said dopant species through the mask.

The method as claimed in Claim 2, wherein the mask is applied on the second side only and serves for identification of the second side as a rear side.

The method as claimed in Claim 3, wherein a protective layer is applied on the second side prior to provision of the dopant species of the second conductivity type.

The method as claimed in Claim 4, wherein a texturisation step is applied to the first side after the provision of the protective layer on the second side.

6. The method as claimed in Claim 1 or 2, wherein the substrate is doped both from the first side and from the second side with dopant species of the first conductivity type in accordance with the predefined pattern, and wherein a substrate layer with said dopant species is removed from one of the sides prior to the application of dopant species of the second conductivity type, as a consequence of which removal step the first side is distinguished from the second side and identified as a front side.

The method as claimed in Claim 1, further comprising the step of applying a diffusion resistance layer to the walls of the through- holes .

The method as claimed in Claim 7, wherein the diffusion resistance layer is selected such that dopant species of the second conductivity type will diffuse through the diffusion resistance layer at a diffusion rate that is at most substantially equal to a diffusion rate of the said dopant species of the second conductivity in the

semiconductor substrate.

The method as claimed in Claim 1, wherein the definition of the emitter region comprises the step of defining selective emitter regions on predefined local areas at the first side of the substrate.

The method as claimed in Claim 9, wherein the definition of the emitter region further comprises a step of defining diffusion regions around said selective emitter regions, wherein the selective emitter regions are provided with a higher dopant concentration than the diffusion regions.

The method as claimed in Claim 1, wherein the field region is further patterned so as to subdivide the field region in the substrate into a plurality of individual field regions.

A solar cell comprising a monocrystalline semiconductor substrate with a first side and an opposed second side, which substrate is provided with:

a dopant species of a first conductivity type in a first

concentration, At least one emitter region defined adjacent to the first side and comprising dopant species of a second conductivity type opposed to the first type;

A field region defined adjacent to the second side and comprising dopant species of the first conductivity type at a concentration higher than the first concentration, which emitter region, substrate and field region together constituting a p-i-n diode; Which solar cell further comprises:

conductors extending from the at least one emitter region to first terminals extending from the second side of the substrate, said conductors running in through-holes through the substrate, which through-holes are provided with walls along which said at least one emitter region extends, which through-hole extension of the at least one emitter region being isolated from said field region; and Second terminals defined locally on the field region at the second side,

wherein the field region is patterned, such that a first portion of the substrate at the second side around a through-hole is located outside the field region, and wherein the through-holes and the at least one emitter region therein extend to the second side of the substrate, such that the through-hole extension is isolated from the field region through the first portion of the substrate.

13. The solar cell as claimed in Claim 12, wherein merely the first side of the substrate is provided with a texturisation .

14. The solar cell as claimed in Claim 12, wherein the field region in the substrate is subdivided into a plurality of field regions. 15. A solar panel comprising at least one solar cell as claimed in any of the Claims 12-14 and a panel carrier, in which at least some of the first and second terminals of the solar cell are electrically coupled to conductors in the panel carrier. 16. A method of manufacturing a solar cell comprising the steps of:

Providing a monocrystalline semiconductor substrate with a first side and an opposed second side comprising of a dopant species of a first conductivity type in a first concentration; Doping the second side of the substrate with dopant species of the first conductivity type to define at least one field region, wherein the second side is doped in accordance with a predefined pattern ;

- Applying dopant species of a second conductivity type opposed to the first type for defining at least one emitter region at the first side of the substrate and extending along any exposed surfaces towards the second side, and

The method as claimed in Claim 16, wherein the field region is patterned to leave undoped areas adjacent to an edge of the

semiconductor substrate, and wherein the dopant species of the second type extends along a side face of the semiconductor substrate.

The method as claimed in Claim 16, wherein the field region is patterned for subdivision into a plurality of field regions.

a dopant species of a first conductivity type in a first

concentration,

At least one emitter region defined adjacent to the first side and comprising dopant species of a second conductivity type opposed to the first type;

conductors extending from the at least one emitter region to first terminals extending from the second side of the substrate; and Second terminals defined locally on the field region at the second side,

wherein the field region is patterned, such that a first portion of the substrate at the second side is located outside the field region, such that the first portion constitutes an isolation between the field region and an extension of the emitter region towards the second side of the substrate. 20. A method of manufacturing a photovoltaic cell device provided with a plurality of subcells each provided with a p-i-n diode, which method comprises the steps of:

providing a plurality of first doped regions of the second conductivity type adjacent to the first side of the substrate, neighbouring first doped regions being separated by at least substantially insulating or semiconductor areas;

- providing a second doped region of the first conductivity type adjacent to the second side of the semiconductor substrate, an intermediate region extending between the first and second doped regions, which second doped region is subdivided by at least substantially insulating or semiconducting subdivisions located correspondingly to the at least substantially electrically insulating or semiconductor areas, therewith defining the subcells.

21. The method as claimed in Claim 20, wherein step of providing the second doped region comprises the step of applying charge carriers to form the second doped region and applying subdivisions into the second doped region through removal of portions of the semiconductor substrate, the subdivisions extending into the intermediate region,

22. The method as claimed in Claim 20 or 21, wherein the step of providing the second doped region comprises the step of applying a mask to the semiconductor substrate, said mask defining the subdivisions and applying charge carriers to form the second doped region in accordance with the mask to form the subdivided second doped region. 23. The method as claimed in any of the Claims 20-22, wherein the first doped regions are applied by definition of selective emitter regions and diffusion regions, the selective emitter regions being provided with a higher dopant concentration than the diffusion regions, such that a diffusion region is present between an at least substantially insulating or semiconductor area and a selective emitter region.

24. The method as claimed in any of the Claims 20-23, wherein the plurality of first doped regions are defined by doping the semiconductor substrate from the first side to define a first doped region and applying subdivisions into the first doped region.

25. A photovoltaic cell device comprising a semiconductor substrate with a first side and an opposed second side, which first side is to be exposed to radiation, which cell device comprises a plurality of subcells each comprising a first doped region and a second doped region of opposite conductivity type and an intermediate region extending between the first and the second doped region, which intermediate region is provided with charge carriers of a first conductivity type in a concentration lower than a concentration of charge carriers of the first conductivity type in either the first or the second doped region, wherein the intermediate region is mechanically continuous between the subcells, wherein subdivisions are present between the second doped regions of neighbouring subcells and wherein substantially insulating or semiconductor areas are present between the first doped regions of neighbouring subcells.

26. The photovoltaic cell device as claimed in Claim 25, wherein the first doped regions comprise a selective emitter region and a diffusion region, which selective emitter region has a higher dopant concentration than the diffusion region and has an interface to a conductor, and wherein a diffusion region is present between an at least substantially insulating or semiconductor area and a selective emitter region.

27. The photovoltaic cell device as claimed in Claim 25 or 26, wherein the subcells are grouped into subcell groups, the subcells within one subcell group constituting one string.

28. The photovoltaic cell device as claimed in Claim 27, wherein intermediate regions between subcell groups comprise electrically insulating regions .

29. The photovoltaic cell device as claimed in Claim 28, wherein the at least substantially electrically insulating regions are defined by trenches in the semiconductor substrates, said trenches defining mechanical bridges between the subcell groups for mechanical continuity.

30. The photovoltaic cell device as claimed in any of the Claims 25 to 29, wherein each subcell comprises a first and a second terminal, both located on the second side of the semiconductor substrate, wherein the first terminal is electrically coupled to the first doped region at the first side with a through-silicon vias extending from the first to the second side of the semiconductor substrate and wherein the second terminal is electrically coupled to the second doped region adjacent to the second side.

31. The photovoltaic cell device as claimed in Claim 30, wherein the subcells are cells of the metal-wrap-through (MWT) type.

32. The photovoltaic cell device as claimed in Claim 25, wherein the surface area of a single subcell is in the range of 4 to 50 cm², preferably 6 to 40 cm². 33. A solar panel comprising a panel carrier provided with conductors and a plurality of photovoltaic cell devices as claimed in any of the previous Claims 25-32 provided with first and second terminals on the second side, wherein the subcells are arranged in a circuit topology by interconnecting the first and second terminals with the conductors of the panel carrier according to a pattern corresponding to the circuit topology .

34. The solar panel as claimed in Claim 33, wherein the circuit topology is defined with an active DC circuit that is controlled by means of a controller embedded into the solar panel.