WO2012071843A1 - 一种半导体结构及其制造方法 - Google Patents
一种半导体结构及其制造方法 Download PDFInfo
- Publication number
- WO2012071843A1 WO2012071843A1 PCT/CN2011/072917 CN2011072917W WO2012071843A1 WO 2012071843 A1 WO2012071843 A1 WO 2012071843A1 CN 2011072917 W CN2011072917 W CN 2011072917W WO 2012071843 A1 WO2012071843 A1 WO 2012071843A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- source
- drain
- thickness
- layer
- drain extension
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims description 68
- 229910052751 metal Inorganic materials 0.000 claims description 68
- 239000000463 material Substances 0.000 claims description 21
- 125000006850 spacer group Chemical group 0.000 claims description 19
- 238000000137 annealing Methods 0.000 claims description 11
- 229910005883 NiSi Inorganic materials 0.000 claims description 8
- 229910019001 CoSi Inorganic materials 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 99
- 229910021332 silicide Inorganic materials 0.000 description 30
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 30
- 230000008569 process Effects 0.000 description 27
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 23
- 238000000151 deposition Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 229910021334 nickel silicide Inorganic materials 0.000 description 5
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910021339 platinum silicide Inorganic materials 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- DIOQZVSQGTUSAI-UHFFFAOYSA-N decane Chemical compound CCCCCCCCCC DIOQZVSQGTUSAI-UHFFFAOYSA-N 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZTEHOZMYMCEYRM-UHFFFAOYSA-N 1-chlorodecane Chemical compound CCCCCCCCCCCl ZTEHOZMYMCEYRM-UHFFFAOYSA-N 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 1
- 239000005977 Ethylene Substances 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 229910018503 SF6 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 125000002534 ethynyl group Chemical group [H]C#C* 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 150000004678 hydrides Chemical class 0.000 description 1
- XMBWDFGMSWQBCA-UHFFFAOYSA-N hydrogen iodide Chemical compound I XMBWDFGMSWQBCA-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- NFHFRUOZVGFOOS-UHFFFAOYSA-N palladium;triphenylphosphane Chemical compound [Pd].C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1.C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1 NFHFRUOZVGFOOS-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Definitions
- the present invention relates to semiconductor fabrication techniques, and more particularly to a semiconductor structure and method of fabricating the same. Background technique
- MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
- the MOSFET includes: a substrate 100, source/drain regions 110, source/drain extensions 111, dummy gate stacks, and Side wall 240.
- the dummy gate stack is formed on the substrate 100, and includes a gate dielectric layer 210, a dummy gate 220, and a cap layer 230.
- the source/drain regions 110 are formed in the substrate 100,
- the source/drain extension region 111 extends from the source/drain region 110 to below the dummy gate stack, and has a thickness smaller than the source/drain region 110; the sidewall spacer 240 is located
- the source/drain extension region 111 is covered on the sidewall of the dummy gate stack; the contact layer 112 is present on the source/drain region 110 (to reduce the contact resistance), and is formed for the silicon-containing substrate Metal silicide layer.
- a silicon-containing substrate will be described as an example, and the contact layer will be referred to as a metal silicide layer.
- the method can reduce the contact resistance between the source/drain regions and the metal silicide layer, the method is limited to forming a metal silicide layer on the source/drain regions without being located under the sidewall spacers.
- a metal silicide layer is formed on the source/drain extension region, and the contact resistance between the source/drain extension region and the metal silicide layer cannot be further reduced, thereby improving the performance of the MOSFET;
- the gate process it is necessary to remove the dummy gate stack after forming the metal silicide layer 112 and the interlayer dielectric layer covering the source/drain regions 110, and then forming a gate dielectric layer of a MOSFET composed of a high-k dielectric material, thereby effectively reducing Gate leakage current.
- the molecular structure of the high-k gate dielectric layer may be slightly defective. In order to repair this defect, it needs to be annealed at a higher temperature (600 ° C - 800 ° C).
- the metal or alloy used in the metal silicide layer in the MOSFET cannot withstand the high temperatures required to anneal the high-k dielectric layer, and its structure changes at high temperatures, resulting in an increase in the resistivity of the metal silicide, which in turn reduces the transistor. Performance.
- An object of the present invention is to provide a semiconductor structure and a method of fabricating the same that can reduce contact resistance and maintain the performance of a semiconductor structure in a high temperature process.
- a method of fabricating a semiconductor structure comprising the steps of:
- the contact layer Forming a contact layer on the source/drain region and the exposed source/drain extension region, the contact layer being one or a combination of CoSi 2 , NiSi or Ni(Pt)Si 2 _y and The thickness of the contact layer is less than
- Another aspect of the invention also provides a semiconductor structure including a substrate, a source/drain region, a source/drain extension region, and a gate, wherein:
- the source/drain regions and the source/drain extension regions are formed in the substrate, and a thickness of the source/drain extension regions is smaller than a thickness of the source/drain regions;
- a contact layer is present on the source/drain regions and at least a portion of the upper surface of the source/drain extension regions, and the contact layer (112) is in CoSi 2 , NiSi or Ni(Pt)Si ⁇ y One or a combination thereof
- the thickness of the contact layer (112) is less than 10 nm.
- the present invention has the following advantages:
- a contact layer is formed on the source/drain regions, but also a contact layer is formed on some or even all of the source/drain extension regions, and the contact layer is made of CoSi 2 , NiSi or One or a combination of Ni(Pt)Si 2 —y and the thickness of the contact layer being less than 10 nm may cause an annealing temperature of the contact layer when subsequently removing the dummy gate stack and forming a gate stack (eg, 700° C. It is still thermally stable at 800 ° C) and can maintain low resistance up to 850 ° C, which reduces contact resistance and reduces the degradation of semiconductor structure performance.
- the thickness of the contact layer formed thereon is very thin, and when a part of the sidewall spacer is removed, a PN junction between the contact layer and the source/drain extension region and the substrate may also have a certain distance, which is not easy Aggravating the short channel effect also helps to suppress the generation of large leakage currents.
- FIG. 1 is a flow chart of a method of fabricating a semiconductor structure in accordance with the present invention
- FIG. 2 through 5 are cross-sectional views showing various stages of fabricating a semiconductor structure in accordance with the flow of FIG. 1 in accordance with a preferred embodiment of the present invention.
- FIG. 6 is a graph showing the resistivity of nickel-silicide formed at different temperatures by depositing Ni layers of different thicknesses
- FIG. 7 is a resistivity of nickel platinum-silicide formed by depositing NiPt layers of different thicknesses and compositions at different temperatures;
- FIG. 8 is a schematic cross-sectional view of a conventional metal oxide semiconductor field effect transistor device. detailed description
- FIG. 1 a method of forming a semiconductor structure in FIG. 1 will be specifically described with reference to FIGS. 2 to 5.
- step S101 a substrate 100 is provided, a dummy gate stack is formed on the substrate 100, sidewalls 240 are formed on sidewalls of the dummy gate stack, and the dummy gate is formed A source/drain region 110 and a source/drain extension region 111 are formed on both sides of the stack, wherein the dummy gate stack includes a gate dielectric layer 210, a dummy gate 220, and a cap layer 230.
- the substrate 100 includes a silicon substrate (e.g., a silicon wafer).
- the substrate 100 can include various doped configurations in accordance with design requirements well known in the art (e.g., a P-type substrate or an N-type substrate).
- the substrate 100 in other embodiments may also include other basic semiconductors (e.g., Group III-V materials) such as germanium.
- the substrate 100 may include a compound semiconductor such as silicon carbide, gallium arsenide, or indium arsenide.
- substrate 100 can have, but is not limited to, a thickness of about a few hundred microns, such as can range from 400 ⁇ m to 800 ⁇ m.
- isolation regions such as shallow trench isolation (STI) structures 120, may be formed in substrate 100 to electrically isolate the continuous field effect transistor devices.
- STI shallow trench isolation
- the gate dielectric layer 210 is first formed on the substrate 100.
- the gate dielectric layer 210 may be formed of silicon oxide, silicon nitride, or a combination thereof, in other implementations.
- it may be a high K medium, for example, one of Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO or a combination thereof, and the thickness thereof may be 2-10 nm; then, on the gate dielectric layer 210, by depositing, for example, polysilicon, polycrystalline SiGe, amorphous silicon, and/or doped or undoped silicon oxide and silicon nitride, silicon oxynitride, Silicon carbide, or even metal, forms a dummy gate 220, which may have a thickness of 10-80 nm; finally, a cap layer 230 is formed on the dummy gate 220, for example, by depositing silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and The combination is formed to protect the top region of the dummy gate 220 to
- a shallower source/drain extension region 111 is first formed in the substrate 100 by low energy implantation.
- P-type or N-type dopants or impurities may be implanted into the substrate 100, for example, for PMOS, the source/drain extension region 111 may be P-type doped SiGe; for NMOS, source/drain extension regions 111 may be N-doped Si.
- the semiconductor structure is then annealed to activate doping in the source/drain extension 111, which may be formed by other suitable methods including rapid annealing, spike annealing, and the like. Since the thickness of the source/drain extension region 111 is shallow, the short channel effect can be effectively suppressed. Alternatively, source/drain extensions 111 may also be formed later in source/drain regions 110.
- sidewall spacers 240 are formed on sidewalls of the dummy gate stack for spacing the gates.
- the sidewall spacers 240 may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
- the side wall 240 may have a multi-layered structure.
- the sidewall spacers 240 may be formed by a deposition etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
- source/drain regions 110 are implanted into the substrate 100, thereby forming source/drain regions 110 on both sides of the dummy gate stack, for example,
- source/drain regions 110 may be P-type doped SiGe; for NMOS, source/drain regions 110 may be N-type doped Si.
- the energy injected into the source/drain region 110 is greater than the energy implanted in the source/drain extension region 111, so that the thickness of the source/drain region 110 is formed to be greater than the thickness of the source/drain extension region 111, and
- the source/drain extension region 111 has a ladder profile.
- the semiconductor structure is then annealed to activate doping in source/drain regions 110, which may be formed by other suitable methods including rapid annealing, spike annealing, and the like.
- step S102 at least a portion of the sidewall spacers 240 are removed to expose at least a portion of the source/drain extension regions 111.
- wet etching and/or drying may be employed. The etch process removes some or all of the sidewall spacers 240 and exposes some or all of the source/drain extension regions 111 under the sidewall spacers 240.
- the wet etching process includes tetrakis ammonium hydroxide (TMAH), potassium hydroxide (KOH) or other suitable etching solution; the dry etching process includes sulfur hexafluoride (SF 6 ), hydrogen bromide (HBr), hydrogen iodide (HI), chlorine, argon, helium, decane (and chlorodecane), hydrides of carbon such as acetylene, ethylene, and combinations thereof, and/or other suitable materials.
- TMAH tetrakis ammonium hydroxide
- KOH potassium hydroxide
- etching solution includes sulfur hexafluoride (SF 6 ), hydrogen bromide (HBr), hydrogen iodide (HI), chlorine, argon, helium, decane (and chlorodecane), hydrides of carbon such as acetylene, ethylene, and combinations thereof, and/or other suitable materials.
- the material of the dummy gate 220 is made of Si or metal, in order to prevent the metal used to form the metal silicide layer and the metal as the dummy gate from being affected in the subsequent process, the size of the dummy gate stack is affected, thereby affecting It is not appropriate to remove the sidewall spacers 240 until the size of the gate stack structure formed after the replacement gate process is performed; if the dummy gate 220 is made of a material that does not react with the deposited metal layer, the sidewall spacers 240 may all be removed. The region where the source/drain extension region 111 reacts with the deposited metal is maximized, thereby reducing the contact resistance between the source/drain extension region and the metal silicide layer.
- a thin metal layer is formed on the upper surface of the source/drain region 110 and the source/drain extension region 111 exposed after removing at least a portion of the sidewall spacer 240.
- the formed metal silicide layer 112 can be made thermally stable at a relatively high temperature (e.g., 850 ° C), and can maintain a low resistivity. It is advantageous to reduce the increase in the resistivity of the metal silicide layer 112 caused by the high temperature annealing in the subsequent semiconductor structure fabrication process.
- the material of the metal layer 250 includes one or a combination of Co, Ni, NiPt.
- the thickness of the metal layer 250 formed of Co is less than 5 nm.
- the thickness of the metal layer 250 formed of Ni is less than 4 nm, preferably between 2-3 nm, with reference to FIG. Figure 6 shows the resistance of nickel-silicide formed by depositing Ni layers of different thicknesses at different temperatures.
- the abscissa indicates the temperature at which rapid thermal processing (PRT) is performed, and the ordinate indicates the resistance of nickel-silicide. Different curves indicate Ni layers of different thickness deposited when nickel-silicide is formed. D 6 It can be seen that when the temperature of the rapid thermal processing process reaches 700 ° C or higher, the resistance of the nickel-silicide formed by depositing the metal Ni layer to a thickness of 2-3 nm is relatively low.
- the thickness of the metal silicide layer 112 is approximately twice that of the metal layer 250, for example, the thickness of the NiSi formed when the thickness of the deposited Ni layer is 4 nm. About 8nm.
- the thickness of the metal layer 250 formed of NiPt is less than 3 nm, and the content of Pt in NiPt is less than 5%
- Figure 7 shows the resistance of nickel-platinum-silicide formed by depositing NiPt layers of different thicknesses at different temperatures.
- Figure 7 consists of three graphs of upper, middle and lower, and the abscissa indicates the temperature at which the rapid thermal processing is performed. The coordinates represent the resistance of nickel platinum-silicide.
- the different curves in the above figure indicate that the metal layer 250 is NiPt, and the content of Ni is 86%, and the content of Pt is 14%, the NiPt layer of different thickness;
- the different curves in the figure indicate that the metal layer 250 is NiPt, and the content of Ni is 92%, and the content of Pt is 8%, the NiPt layers of different thicknesses;
- the different curves in the following figure indicate that the metal layer 250 is NiPt When the content of Ni is 96% and the content of Pt is 4%, the NiPt layer of different thickness is used.
- Figure 7 when the temperature of the rapid thermal processing process reaches 700!
- the resistivity of the formed nickel platinum-silicide is relatively low, that is, the thermal stability is good. Therefore, if the material of the metal layer 250 is NiPt, the thickness of the metal layer 250 formed of NiPt is less than 3 nm, and preferably, the content of Pt in the NiPt is less than 5%.
- the semiconductor structure is annealed, and after annealing, a metal silicide layer 112 is formed on the upper surface of the source/drain region 110 and the exposed region of the source/drain extension region 111, the metal
- the silicide layer 112 includes one or a combination of CoSi 2 , NiSi or Ni(Pt)Si 2- y having a thickness of less than 10 nm.
- the residual metal layer 250 that does not participate in the reaction to form the metal silicide layer 112 is removed by selective etching.
- the fabrication of the semiconductor structure is then completed in accordance with the steps of a conventional semiconductor fabrication process. For example, depositing an interlayer dielectric layer on a substrate of the semiconductor structure; then performing a replacement gate process to anneal the high-k gate dielectric layer; and etching the interlayer dielectric layer to form a contact hole and filling the contact hole The metal is contacted to form a contact plug. Since the above conventional manufacturing processes are well known to those skilled in the art, they will not be described herein. [0041] After the above steps are completed, in the semiconductor structure, not only the source/drain region 110 but also the metal silicide layer 112 is formed on the source/drain extension region 111, which lowers the contact resistance, thereby improving The performance of the semiconductor structure.
- the metal silicide layer 112 is also thermally stable, and can maintain a low electrical resistance up to 850 ° C, so even if there is high temperature treatment in the subsequent process, such as high temperature annealing of the high K gate dielectric layer in the replacement gate process
- the resistance of the metal silicide layer 112 is also not increased, thereby facilitating a reduction in the performance of the semiconductor structure.
- the thickness of the metal silicide layer 112 is less than 10 nm, a certain distance may exist between the bonding surface of the source/drain extension region and the substrate, so that the short channel effect is not easily aggravated, and the suppression is also suppressed. Large junction leakage current generation.
- the semiconductor structure will be described below with reference to FIG.
- FIG. 5 is a cross-sectional view of the semiconductor structure finally formed after the steps shown in FIG. 1 are completed.
- the semiconductor structure includes: a substrate 100, source/drain regions 110, and source/drain extension regions 111.
- the source/drain region 110 and the source/drain extension region 111 are both formed in the substrate 100; the source/drain extension region 111 has a thickness smaller than the source/drain region 110, and
- the source/drain regions 110 have a ladder-like profile; since the thickness of the source/drain extension regions 111 is thin, d and short channel effects can be effectively reduced.
- the presence of the metal silicide layer 112 on the source/drain regions 110 and at least a portion of the upper surface of the source/drain extension regions 111 reduces contact resistance, thereby improving the performance of the semiconductor structure.
- the layer 112 comprises a metal silicide CoSi 2, NiSi or Ni (Pt) Si 2 ⁇ or a combination of one having a thickness of less than 10nm.
- the metal silicide layer 112 is thermally stable, it can maintain a low electrical resistance at up to 850 ° C, so even if there is high temperature treatment in the subsequent process, such as high temperature annealing of the high K gate dielectric layer in the replacement gate process The resistance of the metal silicide layer 112 is also not increased, thereby contributing to a reduction in the performance of the semiconductor structure.
- the thickness of the metal silicide layer 112 is thin, and there is a certain distance from the bonding surface between the source/drain extension region and the substrate, the short channel effect is not easily aggravated, and the suppression is also facilitated. Large junction leakage current generation.
- the dummy gate 220 may be formed using a material that does not react with the deposited metal layer 250, including but not limited to oxides, nitrides, and any combination thereof.
- the dummy gate 220 does not need special protection, so all the sidewall spacers 240 can be removed to maximize the exposure of the source/drain extension region 111, thereby increasing the region where the source/drain extension region 111 reacts with the metal layer 250, thereby The contact resistance between the source/drain extension region and the metal silicide layer is lowered, and the performance of the semiconductor structure is improved.
- each part in each embodiment of the semiconductor structure may be the same as those described in the method embodiment of the foregoing semiconductor structure, and are not described herein.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/380,612 US8822334B2 (en) | 2010-12-03 | 2011-04-18 | Semiconductor structure and method for manufacturing the same |
CN201190000068.XU CN202487541U (zh) | 2010-12-03 | 2011-04-18 | 一种半导体结构 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010105726168A CN102487015A (zh) | 2010-12-03 | 2010-12-03 | 一种半导体结构及其制造方法 |
CN201010572616.8 | 2010-12-03 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2012071843A1 true WO2012071843A1 (zh) | 2012-06-07 |
Family
ID=46152491
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2011/072917 WO2012071843A1 (zh) | 2010-12-03 | 2011-04-18 | 一种半导体结构及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8822334B2 (zh) |
CN (2) | CN102487015A (zh) |
WO (1) | WO2012071843A1 (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102487015A (zh) * | 2010-12-03 | 2012-06-06 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
US20120235244A1 (en) * | 2011-03-18 | 2012-09-20 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor Structure and Method for Manufacturing the Same |
US8822283B2 (en) | 2011-09-02 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned insulated film for high-k metal gate device |
US9515155B2 (en) | 2013-12-20 | 2016-12-06 | Globalfoundries Inc. | E-fuse design for high-K metal-gate technology |
US9524962B2 (en) * | 2013-12-20 | 2016-12-20 | Globalfoundries Inc. | Semiconductor device comprising an e-fuse and a FET |
US9496394B2 (en) | 2014-10-24 | 2016-11-15 | Globalfoundries Inc. | Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s) |
US9466685B2 (en) | 2015-02-23 | 2016-10-11 | Globalfoundries Inc. | Semiconductor structure including at least one electrically conductive pillar, semiconductor structure including a contact contacting an outer layer of an electrically conductive structure and method for the formation thereof |
US9478468B1 (en) | 2015-07-09 | 2016-10-25 | International Business Machines Corporation | Dual metal contact scheme for CMOS devices |
US9875332B2 (en) * | 2015-09-11 | 2018-01-23 | Arm Limited | Contact resistance mitigation |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1585128A (zh) * | 2003-08-22 | 2005-02-23 | 三星电子株式会社 | 高度集成半导体器件及其制造方法 |
US20070102726A1 (en) * | 2005-10-31 | 2007-05-10 | Ryota Watanabe | Semiconductor device for improving channel mobility |
CN1983595A (zh) * | 2005-12-13 | 2007-06-20 | 松下电器产业株式会社 | 半导体装置及其制造方法 |
JP2009152342A (ja) * | 2007-12-20 | 2009-07-09 | Hitachi Kokusai Electric Inc | 半導体装置の製造方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6153455A (en) * | 1998-10-13 | 2000-11-28 | Advanced Micro Devices | Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer |
US20040188765A1 (en) * | 2003-03-28 | 2004-09-30 | International Business Machines Corporation | Cmos device integration for low external resistance |
US7029966B2 (en) * | 2003-09-18 | 2006-04-18 | International Business Machines Corporation | Process options of forming silicided metal gates for advanced CMOS devices |
US7148143B2 (en) * | 2004-03-24 | 2006-12-12 | Texas Instruments Incorporated | Semiconductor device having a fully silicided gate electrode and method of manufacture therefor |
DE102004031743B4 (de) * | 2004-06-30 | 2006-10-05 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer Epitaxieschicht für erhöhte Drain-und Sourcegebiete durch Entfernen von Oberflächendefekten der anfänglichen Kristalloberfläche |
KR100882930B1 (ko) * | 2004-12-17 | 2009-02-10 | 삼성전자주식회사 | 소오스 및 드레인 영역들을 갖는 씨모스 반도체 소자들 및 그 제조방법들 |
US7419907B2 (en) * | 2005-07-01 | 2008-09-02 | International Business Machines Corporation | Eliminating metal-rich silicides using an amorphous Ni alloy silicide structure |
US7348248B2 (en) * | 2005-07-12 | 2008-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS transistor with high drive current and low sheet resistance |
US7545006B2 (en) * | 2006-08-01 | 2009-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS devices with graded silicide regions |
US8008157B2 (en) * | 2006-10-27 | 2011-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS device with raised source and drain regions |
JP5003515B2 (ja) * | 2007-03-20 | 2012-08-15 | ソニー株式会社 | 半導体装置 |
US7585716B2 (en) * | 2007-06-27 | 2009-09-08 | International Business Machines Corporation | High-k/metal gate MOSFET with reduced parasitic capacitance |
JP5070969B2 (ja) * | 2007-07-20 | 2012-11-14 | ソニー株式会社 | 半導体装置の製造方法 |
US8395191B2 (en) * | 2009-10-12 | 2013-03-12 | Monolithic 3D Inc. | Semiconductor device and structure |
CN102087980A (zh) * | 2009-12-04 | 2011-06-08 | 中国科学院微电子研究所 | 高性能半导体器件及其形成方法 |
WO2011077629A1 (ja) * | 2009-12-25 | 2011-06-30 | シャープ株式会社 | フォトセンサー素子、フォトセンサー回路、薄膜トランジスタ基板、表示パネル及びフォトセンサー素子の製造方法 |
CN102110650A (zh) * | 2009-12-29 | 2011-06-29 | 中国科学院微电子研究所 | 一种半导体器件及其制造方法 |
US8741773B2 (en) * | 2010-01-08 | 2014-06-03 | International Business Machines Corporation | Nickel-silicide formation with differential Pt composition |
KR101576529B1 (ko) * | 2010-02-12 | 2015-12-11 | 삼성전자주식회사 | 습식 식각을 이용한 실리콘 파셋트를 갖는 반도체 장치 및 제조방법 |
CN102487015A (zh) * | 2010-12-03 | 2012-06-06 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
-
2010
- 2010-12-03 CN CN2010105726168A patent/CN102487015A/zh active Pending
-
2011
- 2011-04-18 US US13/380,612 patent/US8822334B2/en active Active
- 2011-04-18 WO PCT/CN2011/072917 patent/WO2012071843A1/zh active Application Filing
- 2011-04-18 CN CN201190000068.XU patent/CN202487541U/zh not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1585128A (zh) * | 2003-08-22 | 2005-02-23 | 三星电子株式会社 | 高度集成半导体器件及其制造方法 |
US20070102726A1 (en) * | 2005-10-31 | 2007-05-10 | Ryota Watanabe | Semiconductor device for improving channel mobility |
CN1983595A (zh) * | 2005-12-13 | 2007-06-20 | 松下电器产业株式会社 | 半导体装置及其制造方法 |
JP2009152342A (ja) * | 2007-12-20 | 2009-07-09 | Hitachi Kokusai Electric Inc | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN102487015A (zh) | 2012-06-06 |
CN202487541U (zh) | 2012-10-10 |
US20120217589A1 (en) | 2012-08-30 |
US8822334B2 (en) | 2014-09-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9076819B2 (en) | Contact structure of semiconductor device | |
KR101027107B1 (ko) | 완전 변환된 반도체 금속 합금에 의한 금속 게이트mosfet | |
KR100844933B1 (ko) | 반도체 소자의 트랜지스터 및 그 제조 방법 | |
US9384986B2 (en) | Dual-metal gate CMOS devices and method for manufacturing the same | |
WO2012071843A1 (zh) | 一种半导体结构及其制造方法 | |
WO2012071813A1 (zh) | 一种半导体结构及其制造方法 | |
WO2013071656A1 (zh) | 一种半导体结构及其制造方法 | |
US20140191301A1 (en) | Transistor and fabrication method | |
WO2011079596A1 (zh) | Mosfet结构及其制作方法 | |
US8980718B2 (en) | PMOS transistors and fabrication method | |
JP2008235568A (ja) | 半導体装置およびその製造方法 | |
WO2013078882A1 (zh) | 半导体器件及其制造方法 | |
WO2013067725A1 (zh) | 一种半导体结构的制造方法 | |
US20210234035A1 (en) | Transistor manufacturing method and gate-all-around device structure | |
WO2012171323A1 (zh) | 一种半导体结构及其制造方法 | |
JP2009152342A (ja) | 半導体装置の製造方法 | |
WO2013075349A1 (zh) | 一种半导体结构及其制造方法 | |
CN108573910B (zh) | 半导体结构及其形成方法 | |
US8889554B2 (en) | Semiconductor structure and method for manufacturing the same | |
CN102683210B (zh) | 一种半导体结构及其制造方法 | |
CN111211055B (zh) | 半导体结构及其形成方法 | |
WO2013139063A1 (zh) | 一种半导体结构及其制造方法 | |
CN103779212B (zh) | 半导体结构及其制造方法 | |
CN104465377A (zh) | Pmos晶体管及其形成方法 | |
US20080237744A1 (en) | Semiconductor Device and Manufacturing Method Thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201190000068.X Country of ref document: CN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13380612 Country of ref document: US |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 11845942 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 11845942 Country of ref document: EP Kind code of ref document: A1 |