WO2012023662A1 - Light emitting diode having multi-cell structure and manufacturing method thereof - Google Patents

Light emitting diode having multi-cell structure and manufacturing method thereof Download PDF

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Publication number
WO2012023662A1
WO2012023662A1 PCT/KR2010/007668 KR2010007668W WO2012023662A1 WO 2012023662 A1 WO2012023662 A1 WO 2012023662A1 KR 2010007668 W KR2010007668 W KR 2010007668W WO 2012023662 A1 WO2012023662 A1 WO 2012023662A1
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Prior art keywords
electrode
layer
semiconductor layer
light emitting
emitting diode
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PCT/KR2010/007668
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French (fr)
Korean (ko)
Inventor
김상묵
백종협
이광철
오화섭
유은미
박재우
박준모
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한국광기술원
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Priority to US13/504,522 priority Critical patent/US8710520B2/en
Publication of WO2012023662A1 publication Critical patent/WO2012023662A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Definitions

  • the present invention relates to a light emitting diode having a multi-cell structure including a plurality of unit cells, and provides a contact between a mesa etching region and a p-type semiconductor layer for forming an electrode of a conventional n-type semiconductor layer.
  • the present invention relates to a light emitting diode that reduces light loss and increases light efficiency of a light emitting diode surface due to a bonding pad formed therein.
  • the present invention relates to a light emitting diode capable of controlling a chip size even though the same chip manufacturing process as in the prior art is possible, and thus making chips of different sizes.
  • LEDs Light Emitting Diodes
  • LEDs Light Emitting Diodes
  • LCD displays LCD displays
  • LED has the advantage of low heat generation and long life due to high energy efficiency while being able to drive at a relatively low voltage, and most of the currently used technologies have been developed to provide high brightness of white light, which was difficult to implement in the past. It is expected to replace the light source device.
  • LEDs are a type of solid state device that converts electrical energy into light and generally include an active layer of semiconductor material sandwiched between two opposing doped layers. When a bias is applied across the two doped layers, holes and electrons are injected into the active layer and then recombined therein to generate light, which is emitted in all directions to be emitted out of the semiconductor chip through all exposed surfaces. do.
  • Conventional nitride semiconductor light emitting diode structures include a buffer layer, an n-type nitride semiconductor layer, an active layer having a multi-quantum well structure, and a p-type nitride semiconductor layer sequentially formed on a substrate, and the p-type nitride semiconductor layer and the active layer The partial region is removed by a process such as etching to expose a part of the upper surface of the n-type nitride semiconductor layer.
  • An n-type electrode is formed on the exposed n-type nitride semiconductor layer, and a transparent electrode layer is formed on the p-type nitride semiconductor layer to form ohmic contact, and then a p-type bonding electrode is formed.
  • a light emitting diode formed by a conventional method of manufacturing such a light emitting diode should remove a portion of an active layer to form an n-type electrode on an n-type nitride semiconductor layer, which has a problem of weakening light output due to the loss of the active layer. .
  • the present invention has been made to solve the above-described problems of the prior art, it is possible to control the size of the chip by taking a multi-cell structure by tying a plurality of unit cells into one, by adding a protective film and a metal pad to the multi-cell structure It is an object of the present invention to provide a light emitting diode having a wafer level package structure that does not require wire bonding.
  • the present invention adopts a structure that minimizes the portion where the loss of the active layer occurs in order to improve the current diffusion when manufacturing the light emitting diode, thereby minimizing the area of the contact portion of the first semiconductor layer at the manufacturing level of the light emitting diode device
  • Another purpose is to improve the brightness and improve the electrical and thermal characteristics of the light emitting diode by freeing the contact of the two semiconductor layers.
  • Another object of the present invention is to provide a light emitting diode in which n-type pads and p-type pads for package mounting are formed on the same surface so that a bonding pad formed on a mesa-etched surface is not additionally formed.
  • a transparent substrate (Substrate); A first semiconductor layer, an active layer, and a second semiconductor layer sequentially formed on the light transmissive substrate; A plurality of holes formed to be spaced apart from each other by removing a portion of the second semiconductor layer and the active layer; A first electrode contacting the first semiconductor layer through a portion of the plurality of holes and contacting the first semiconductor layer to expose the upper surface to the outside; A first passivation layer surrounding a side circumference of the first electrode to prevent a short between the first semiconductor layer and the second semiconductor layer; A second passivation layer formed on side and bottom surfaces of the hole in which the first electrode is not formed among the plurality of holes; A reflection layer or a current diffusion layer formed on the second passivation layer and the second semiconductor layer; And a second cell formed on the reflective layer or the current spreading layer.
  • the light emitting diode having a multi-cell structure is provided.
  • the present invention includes a plurality of unit cells, wherein the plurality of unit cells are connected by a first electrode and a second electrode formed in the form of a metal line.
  • the present invention includes a third passivation layer covering an upper portion of the first electrode and the metal line and in contact with a side surface of the second electrode and preventing a short between the first electrode and the second electrode; A first metal pad contacting the first electrode through a hole from which a predetermined region of the second passivation layer is removed; And a second metal pad contacted with the second electrode and spaced apart from the first metal pad.
  • the present invention further includes a fourth passivation layer formed on an area where the first metal pad and the second metal pad are not formed on the third passivation layer, and preventing a short between the first metal pad and the second metal pad. It is preferable to provide.
  • the first protective film, the second protective film, the third protective film or the fourth protective film is formed of any one material selected from SiO 2 , Si 3 N 4 , resin, or spin on glass (SOG). It is desirable to be.
  • the reflective layer or the current diffusion layer silver (Ag), nickel (Ni), aluminum (Al), titanium (Ti), palladium (Pd), platinum (Pt), ruthenium (Ru), gold (Au), choose from rhodium (Rh), iridium (Ir), indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide, tin oxide, silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide, titanium oxide It is preferably formed of any one or more materials.
  • the current diffusion layer is preferably formed of any one material selected from indium tin oxide (ITO), zinc oxide (ZnO), Ni / Au.
  • the present invention preferably further includes the step of connecting the respective unit cells by forming the first electrode and the second electrode in the form of a metal line after the second electrode forming step.
  • a third passivation layer covering an upper portion of the first electrode and the metal line and in contact with a side surface of the second electrode; Removing a predetermined region of the third passivation layer to form a plurality of holes spaced apart from each other; Forming a first metal pad contacting a first electrode through the hole; And forming a second metal pad in contact with the second electrode and separated from the first metal pad.
  • the present invention preferably further includes forming a fourth passivation layer on the third passivation layer on which the first metal pad and the second metal pad are not formed after the second metal pad forming step.
  • each chip having a unit cell structure divided into a protective film process and a metal line process connecting the same may be configured as a single light emitting diode multi-cell, it is possible to have flexibility in chip size, and to improve productivity and manufacturing cost. Can bring about savings.
  • light extraction efficiency can be improved by forming a reflective metal or a transparent electrode in a section between a plurality of unit cells, and the size and position of the second electrode in contact with the second semiconductor layer can be arbitrarily determined to form a light emitting diode. Can bring flexibility.
  • the present invention by reducing the etching portion for the contact of the n-type semiconductor layer (first semiconductor layer) compared to the prior art in manufacturing the light emitting diode to minimize the loss area of the active layer and widen the effective light emitting area to increase the light output
  • the number of pads required is reduced, and thus the light output of the package is improved by preventing light absorption by the pad.
  • n-type pad formed on an n-type pad (first metal pad) and a p-type pad (second metal pad) formed on the same surface and mesa-etched. There is no effect that the manufacturing process is simplified and the manufacturing cost is reduced.
  • Figure 1a is an exemplary view showing an electrode structure of a light emitting diode according to the prior art.
  • FIGS. 1B to 1C are top views of a light emitting diode having a multi-cell structure according to an embodiment of the present invention.
  • FIGS. 2A to 2G are exemplary views illustrating a step-by-step manufacturing procedure of a light emitting diode having a multi-cell structure according to an embodiment of the present invention.
  • FIG 3 is a top view of a light emitting diode having a multi-cell structure including a metal pad according to an embodiment of the present invention.
  • 4A to 4C are exemplary views illustrating a manufacturing procedure of a light emitting diode having a multi-cell structure including a metal pad according to an embodiment of the present invention.
  • FIG. 5 is a flow chart of a method of manufacturing a light emitting diode having a multi-cell structure according to an embodiment of the present invention.
  • Figure 1a is an exemplary view showing an electrode structure of a light emitting diode according to the prior art.
  • a structure of a conventional light emitting diode includes an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer sequentially formed on a substrate, and the p-type nitride semiconductor layer and the active layer The partial region is removed by a process such as etching to expose a part of the upper surface of the n-type nitride semiconductor layer.
  • the n-type electrode or the first electrode 120 is formed on the exposed n-type nitride semiconductor layer and the transparent electrode layer is formed on the p-type nitride semiconductor layer to form ohmic contact, the p-type electrode or the second electrode 110 To form.
  • the light emitting diode formed by the prior art should remove a portion of the active layer to form the n-type electrode or the first electrode 120 on the n-type nitride semiconductor layer, which weakens the light output due to the loss of the active layer. There was a problem and the current spreading in the horizontal direction is limited.
  • a finger type electrode structure has appeared.
  • This finger type electrode structure has advantages in terms of current diffusion, but also mesa etching is required for the contact between the n-type semiconductor layer and the n-type electrode or the first electrode 220, This caused the loss of the active layer has a problem that is difficult to secure the production of high-output light emitting diodes.
  • FIGS. 1B to 1C are top views of a light emitting diode having a multi-cell structure according to an embodiment of the present invention.
  • a light transmitting substrate A first semiconductor layer, an active layer, and a second semiconductor layer sequentially formed on the light transmissive substrate; A plurality of holes formed to be spaced apart from each other by removing a portion of the second semiconductor layer and the active layer; A first electrode contacting the first semiconductor layer through a portion of the plurality of holes, the upper electrode being exposed to the outside; A first passivation layer surrounding a side circumference of the first electrode to prevent a short between the first semiconductor layer and the second semiconductor layer; A second passivation layer formed on side and bottom surfaces of the hole in which the first electrode is not formed among the plurality of holes; A reflection layer or a current diffusion layer formed on the second passivation layer and the second semiconductor layer; And a second electrode formed on the reflective layer or the current spreading layer.
  • the present invention is provided with a plurality of unit cells, the plurality of unit cells is preferably connected by the first electrode 140 and the second electrode 150 formed in the form of a metal line.
  • the first electrode, the upper surface may be in the form of a circle, a square or a polygon, the cross-section of the side may have a rectangular shape.
  • the first semiconductor layer is an n-type nitride semiconductor layer
  • the second semiconductor layer is a p-type nitride semiconductor layer, but vice versa.
  • FIGS. 2A to 2G are exemplary views illustrating a step-by-step manufacturing procedure of a light emitting diode having a multi-cell structure according to an embodiment of the present invention.
  • 2A to 2H may be referred to as an exemplary view showing a manufacturing procedure centering on a cross section of the light emitting diode device of FIG. 1C cut along the direction A-A '.
  • the first semiconductor layer 220, the active layer 230, and the second semiconductor layer 240 are sequentially deposited on the transparent substrate 210.
  • the light transmissive substrate 210 may be a sapphire substrate or the like, and may further include a buffer layer (not shown) between the light transmissive substrate 410 and the first semiconductor layer 220 to form a light emitting diode device.
  • the first semiconductor layer 220 may be an n-type nitride semiconductor layer
  • the second semiconductor layer 240 may be a p-type nitride semiconductor layer.
  • n-GaN gallium nitride
  • p-GaN p-GaN
  • an n-GaN layer may be formed after forming a buffer layer on the light-transmissive substrate as needed.
  • a buffer layer is used to reduce the lattice constant difference between the substrate and the semiconductor layer.
  • the structure may be selected from a stacked structure of InGaN / GaN stacked structure and AlInGaN / InGaN / GaN.
  • a first semiconductor layer 220 is formed on the light transmissive substrate or on the buffer layer.
  • the first semiconductor layer 220 may be formed of an n-GaN layer, and silicon (Si) is used as a dopant. Can be doped. It proceeds at high temperature and can combine ammonia (NH3) as a carrier gas and Ga, N, Si as a compound.
  • NH3 ammonia
  • the active layer 230 is formed, which may be a semiconductor layer to which a light emitting material made of InGaN is added.
  • a material such as AlGaN and AlInGaN may also be used as the active layer 230.
  • the active layer 230 may form an InGaN / GaN quantum well (QW) structure, and a plurality of quantum well structures may be formed to improve luminance, thereby forming a multi-quantum well (MQW) structure.
  • QW InGaN / GaN quantum well
  • MQW multi-quantum well
  • a second semiconductor layer 240 is formed on the active layer, which may be formed of a p-GaN layer, and magnesium (Mg) may be used as a dopant. This process is also carried out at a high temperature and can combine Ga, N, Mg as a compound with an ammonia (NH3) carrier gas.
  • NH3 ammonia
  • predetermined regions of the second semiconductor layer 240 and the active layer 230 are removed to form holes 250 spaced apart from each other.
  • the hole is formed to expose the top surface of the first semiconductor layer 220.
  • the holes 250 are used to form the first electrode 270 and the reflective layer or the current spreading layer 290.
  • the holes 250 spaced apart from each other by a predetermined distance on the second semiconductor layer 240 may be formed. Patterning and etching process to be carried out, in this case, the wet etching (Wet Etching) or dry etching (Dry Etching) method may be used.
  • the first protective layer 260 is formed on the side surface of some of the plurality of holes 250.
  • the first passivation layer 260 may be formed only in the even-numbered holes or the odd-numbered holes from the outermost end.
  • the first protective layer 260 may be formed to prevent a short between the first electrode 270 and the second electrode 291.
  • the first passivation layer 260 may be formed of any one material selected from SiO 2 , Si 3 N 4 , resin, or spin on glass (SOG).
  • a first electrode 270 is formed in a region surrounded by the first passivation layer 260 and the first semiconductor layer 220. Since the first electrodes 270 are formed to be divided independently from each other, the first electrodes 270 are preferably connected to metal lines later.
  • the first electrode 270 may be formed using a known electrode material, and may be formed by applying an electrode paste.
  • the second protective layer 280 is formed in a hole in which the first electrode 270 is not formed among the plurality of holes 250.
  • the second passivation layer 280 is formed not only on the side of the hole but also on the bottom thereof to insulate the first semiconductor layer 220 from the reflective layer or the current diffusion layer 290.
  • the reflective layer or the current diffusion layer 290 is formed on the hole and the second semiconductor layer 240 on which the second passivation layer 280 is formed. have.
  • the reflective layer or the current spreading layer 290 is prevented from being shorted with the first electrode 270 by the first passivation layer 260.
  • the current diffusion layer it may be preferable to use a metal such as Ni / Au or an oxide film such as ITO or ZnO.
  • a metal line process may be performed to connect the independent first electrodes 270. Due to the metal line process, each unit cell is connected, and chip size can be controlled in a wafer-level packaging process.
  • the second electrode 291 is formed on the reflective layer 290.
  • the second electrode 291 is formed on the upper surface of the second semiconductor layer 240, and the etching of a predetermined region of the reflective layer 290 must be preceded. That is, a hole is formed on the reflective layer 290 so that the upper surface of the second semiconductor layer 240 is exposed by a patterning process and a wet etching or dry etching, and a second electrode 291 is formed in the hole.
  • a known material may be used as the material of the electrode, and may be formed by applying an electrode paste.
  • the second electrode 291 may be formed in the form of a finger. Even though the second electrode 291 is configured in the form of a finger, since the first electrode 270 has an independent electrode structure, loss of the active layer may occur. By minimizing this, there is no problem in improving the light output.
  • first electrode 270 and the second electrode 291 may be formed in the form of a metal line, thereby connecting a plurality of unit cells in one package.
  • the light-transmitting substrate 210 or the first semiconductor layer 220 may further increase the light extraction effect by forming an uneven structure (not shown) on the upper surface. That is, the concave-convex structure may be formed on the interface between the transparent substrate 210 and the first semiconductor layer 220 or the interface between the first semiconductor layer 220 and the active layer 230.
  • the uneven structure may be formed by using a photoresist.
  • the uneven pattern may be photo-lithography, e-beam lithography, or ion beam lithography. It may be formed using a method such as Lithography, Extreme Ultraviolet Lithography, Proximity X-ray Lithography or nano imprint lithography. In addition, this process may use dry etching or wet etching.
  • FIG 3 is a top view of a light emitting diode having a multi-cell structure including a metal pad according to an embodiment of the present invention.
  • FIG. 3 is a top view of a light emitting diode device including the metal pads 340 and 350. Can be.
  • the present invention covers the upper part of the first electrode 270 and the metal line, and is formed to be in contact with the side surface of the second electrode 291.
  • the present invention may further include a fourth passivation layer 293 formed in a region where the first metal pad 340 and the second metal pad 350 are not formed on the third passivation layer 292.
  • a fourth passivation layer 293 formed in a region where the first metal pad 340 and the second metal pad 350 are not formed on the third passivation layer 292.
  • 4A to 4C are exemplary views illustrating a manufacturing procedure of a light emitting diode having a multi-cell structure including a metal pad according to an embodiment of the present invention.
  • 4A through 4C are diagrams illustrating a top view of the light emitting diode of FIG. 3 centered on a cross-sectional view taken along the B-B 'direction.
  • a third passivation layer 292 is formed on the reflective layer 290 and covers the first electrode 270 and the metal line.
  • the third passivation layer 292 may be formed to contact the side surface of the second electrode 291.
  • the third passivation layer 292 is formed to prevent short of the first electrode 270 and the second electrode 291, and is formed of SiO 2 , Si 3 N 4 , resin, or SOG ( Spin on Glass) may be formed of any one material selected from.
  • the light emitting diodes of the present invention may be formed even if they are formed of the same material or different materials. There is no crowd.
  • a first metal pad 340 is in contact with a predetermined first electrode 270 of the plurality of first electrodes 270, and a second metal pad is in contact with the second electrode 291. 350 is formed.
  • the first metal pad 340 and the second metal pad 350 are independent of the light emitting efficiency of the light emitting diode, and may be configured to adjust the size in consideration of the packaging process.
  • the metal pad is formed as described above, the light emitting diode package may be configured by mounting on the substrate to be applied to various applications.
  • a fourth protective layer 293 is formed on the third protective layer 292.
  • the fourth passivation layer 293 is formed to ensure stability of the device and to insulate the first metal pad 340 and the second metal pad 350 from each other.
  • the manufacturing process of the light emitting diode having the multi-cell structure proposed by the present invention is completed, and the wafer-level light emitting diode package can be manufactured using the light emitting diode. do.
  • FIG. 5 is a flow chart of a method of manufacturing a light emitting diode having a multi-cell structure according to an embodiment of the present invention.
  • the first semiconductor is patterned and then etched for each area spaced by a predetermined distance on the second semiconductor layer.
  • the second semiconductor layer and the active layer are removed to form a plurality of holes to expose the top surface of the layer (S502). Since the removal of the predetermined region of the second semiconductor layer and the active layer forms holes at a predetermined distance with a minimum size, unlike the conventional light emitting diode manufacturing process, the loss of the active layer is much less than that of the general light emitting diode device. have.
  • the step of forming a first passivation layer (S503) on a side surface of a part of the holes (holes) of the plurality of holes (hole) is to prevent the short (short) of the first electrode.
  • a first electrode is contacted with the first semiconductor layer through a hole in which the first passivation layer is formed, and a first electrode is formed to expose the upper surface thereof to the outside.
  • a second passivation layer is formed on the side and the bottom of the hole in which the first electrode is not formed.
  • a reflection layer or a current diffusion layer is formed in each space between the unit cell and the unit cell to extract light. To further improve.
  • a step of forming a reflective layer or a current spreading layer on the hole and the second semiconductor layer on which the second passivation layer is formed is performed (s506).
  • the reflective layer returns light generated from the active layer onto the light-transmissive substrate. It can help to increase efficiency.
  • the light extraction efficiency can be further improved by helping to spread the current in the horizontal direction.
  • a step of forming a second electrode for contact with the second semiconductor layer on the reflective layer or the current diffusion layer is performed (s507).
  • a predetermined region of the reflective layer (or current diffusion layer) is etched away and then the second semiconductor is removed.
  • the second electrode is formed in an area surrounded by the layer and the reflective layer (or current diffusion layer).
  • An upper surface of the second electrode may be formed in a finger shape to connect each unit cell.
  • a step of forming a third passivation layer covering an upper portion of the first electrode and the metal line and contacting the side surface of the second electrode is performed (S509).
  • the third passivation layer is to prevent a short circuit between the first electrode and the second electrode, and the third passivation layer may be formed of the same material as or different from the first and second passivation layers.
  • a step (s510) of removing the predetermined region of the third passivation layer to form two or more holes spaced apart from each other is performed, for the contact between the first metal pad and the first electrode. to be.
  • a step (s511) of forming a first metal pad in contact with the first electrode is performed.
  • the electrode paste is applied and cured through the hole, the first electrode and The first metal pad may be formed to be contacted. If necessary, it is also possible to form a first metal pad after additionally forming a first passivation layer in the hole.
  • the third metal pad and the second metal pad are not formed.
  • the fourth passivation layer on the passivation layer (S512) the light emitting diode element having the multi-cell structure for forming the light emitting diode package is completed.
  • the size of the first metal pad and the second metal pad is sufficiently large, there is an advantage in that the package can be easily mounted in a large package as well as a small package.
  • the first metal pad and the second metal pad for package mounting are formed on the same surface, there is no need to additionally form a bonding pad formed on the mesa-etched surface.
  • the number of pads required is reduced to prevent light absorption by the pads, thereby improving the light output of the LED package.
  • the light emitting diode having the multi-cell structure according to the present invention can be configured as a single light-emitting diode multi-cell through a metal line process connecting the chip of each unit cell structure to the protective film process, thereby providing flexibility in chip size. It can have a productivity improvement and a reduction of manufacturing cost.

Abstract

The present invention relates to a light emitting diode having a multi-cell structure including a plurality of unit cells, which reduces optical loss and enhances optical efficiency in a light emitting diode surface due to a bonding pad which is formed for a contact between an existing mesa-etching region for forming an electrode of a n-type semiconductor layer and a p-type semiconductor layer. Additionally, the invention allows the adjustment of chip size even if the same chip manufacturing process as the prior art is used, thereby manufacturing different sizes of chips. More specifically, one aspect of the present invention provides the light emitting diode having a multi-cell structure including the unit cells, comprising: a transparent substrate; a first semiconductor layer, an active layer, and a second semiconductor layer which are sequentially formed on the transparent substrate; a plurality of holes which are formed apart from each other by removing the second semiconductor layer and a part of the active layer; a first electrode which is in contact with the first semiconductor layer through some holes among the plurality of holes and an upper surface of which is exposed to the outside; a first protective layer which surrounds a lateral periphery of the first electrode to prevent a short circuit between the first semiconductor layer and the second semiconductor layer; a second protective layer which is formed at the lateral surfaces and lower surfaces of the holes in which the first electrode is not formed; a reflective layer or a current diffusion layer which is formed on the second protective layer and the second semiconductor layer; and a second electrode which is formed on the reflective layer or the current diffusion layer.

Description

멀티셀 구조를 갖는 발광다이오드 및 그 제조방법Light emitting diode having multi-cell structure and manufacturing method
본 발명은 다수의 단위셀을 포함하는 멀티셀(Multi-Cell)구조를 갖는 발광다이오드에 관한 것으로써, 기존의 n형 반도체층의 전극형성을 위한 메사식각 영역과 p형 반도체층과의 컨택을 위해 형성되는 본딩 패드로 인한 발광다이오드면의 광손실을 줄이고, 광 효율을 높이는 발광다이오드에 관한 것이다. 또한, 종래기술과 동일한 칩(chip) 제작공정을 거치더라도 칩 사이즈(Chip size)의 조절이 가능하여, 서로 다른 사이즈의 칩을 제작할 수 있는 발광다이오드에 관한 것이다. The present invention relates to a light emitting diode having a multi-cell structure including a plurality of unit cells, and provides a contact between a mesa etching region and a p-type semiconductor layer for forming an electrode of a conventional n-type semiconductor layer. The present invention relates to a light emitting diode that reduces light loss and increases light efficiency of a light emitting diode surface due to a bonding pad formed therein. In addition, the present invention relates to a light emitting diode capable of controlling a chip size even though the same chip manufacturing process as in the prior art is possible, and thus making chips of different sizes.
최근 LED(Light Emitting Diode: 발광다이오드)로 구성된 조명기구 등은 기존의 백열등 또는 형광등에 비해 수명이 길고 상대적으로 저전력을 소비하며 제조공정에서 오염물질을 배출하지 않는 장점 등으로 인하여 수요가 폭발적으로 증가하고 있으며, LED는 발광을 이용한 표시 장치는 물론이고 조명장치나 LCD 표시장치의 백라이트 소자에도 응용되는 등 적용 영역이 점차 다양해지고 있다. 특히 LED는 비교적 낮은 전압으로 구동이 가능하면서도 높은 에너지 효율로 인해 발열이 낮고 수명이 긴 장점을 가지고 있으며, 종래에는 구현이 어려웠던 백색광을 고휘도로 제공할 수 있는 기술이 개발됨에 따라 현재 사용되고 있는 대부분의 광원 장치를 대체할 수 있을 것으로 기대하고 있다.Recently, luminaires composed of LEDs (Light Emitting Diodes) have exploded in demand due to their long lifespan, relatively low power consumption, and no emission of pollutants in the manufacturing process compared to conventional incandescent or fluorescent lamps. In addition, LEDs are being applied to a variety of applications such as display devices using light emission, as well as backlight devices of lighting devices and LCD displays. In particular, LED has the advantage of low heat generation and long life due to high energy efficiency while being able to drive at a relatively low voltage, and most of the currently used technologies have been developed to provide high brightness of white light, which was difficult to implement in the past. It is expected to replace the light source device.
LED는 전기 에너지를 빛으로 변환시키는 고체 소자의 일종으로서, 일반적으로 2개의 상반된 도핑층 사이에 개재된 반도체 재료의 활성층을 포함한다. 2개의 도핑층 양단에 바이어스가 인가되면, 정공과 전자가 활성층으로 주입된 후 그곳에서 재결합되어 빛이 발생되며, 활성층에서 발생된 빛은 모든 방향으로 방출되어 모든 노출 표면을 통해 반도체 칩밖으로 방출되게 된다. LEDs are a type of solid state device that converts electrical energy into light and generally include an active layer of semiconductor material sandwiched between two opposing doped layers. When a bias is applied across the two doped layers, holes and electrons are injected into the active layer and then recombined therein to generate light, which is emitted in all directions to be emitted out of the semiconductor chip through all exposed surfaces. do.
통상적인 질화물 반도체 발광다이오드의 구조는 서브스트레이트 기판상에 순차적으로 형성된 버퍼층, n형 질화물 반도체층, 다중양자우물구조인 활성층 및 p형 질화물 반도체층을 포함하며, 상기 p형 질화물 반도체층과 활성층은 그 일부 영역을 식각등의 공정으로 제거하여 n형 질화물 반도체층의 일부 상면이 노출된 구조를 갖는다. 상기 노출된 n형 질화물 반도체층 상에는 n형 전극이 형성되고 p형 질화물 반도체층 상에는 오믹접촉을 형성하기 위하여 투명 전극층이 형성된 후에, p형 본딩전극을 형성한다.Conventional nitride semiconductor light emitting diode structures include a buffer layer, an n-type nitride semiconductor layer, an active layer having a multi-quantum well structure, and a p-type nitride semiconductor layer sequentially formed on a substrate, and the p-type nitride semiconductor layer and the active layer The partial region is removed by a process such as etching to expose a part of the upper surface of the n-type nitride semiconductor layer. An n-type electrode is formed on the exposed n-type nitride semiconductor layer, and a transparent electrode layer is formed on the p-type nitride semiconductor layer to form ohmic contact, and then a p-type bonding electrode is formed.
종래의 이러한 발광다이오드의 제조방법에 따라 형성된 발광다이오드는 n형 질화물 반도체층상에 n형 전극을 형성하기 위해 활성층의 일부영역을 제거해야 하는데, 이러한 활성층의 손실로 인한 광출력을 약화시키는 문제점이 있었다. 또한, 칩 사이즈에 비해 상대적으로 크게 형성되는 메탈 패드로 인한 반사막 효율 저하 등의 문제점이 있었다. A light emitting diode formed by a conventional method of manufacturing such a light emitting diode should remove a portion of an active layer to form an n-type electrode on an n-type nitride semiconductor layer, which has a problem of weakening light output due to the loss of the active layer. . In addition, there is a problem such as decrease in reflecting film efficiency due to the metal pad formed relatively large compared to the chip size.
따라서, ① n형 전극 형성을 위한 메사식각 등으로 인한 활성층의 손실이 발생하지 않고, ② n형 전극 형성에 있어서 활성층의 손실을 최소화하고 이에 따른 p형 전극의 사이즈와 위치를 조절하여 휘도(Brightness) 향상을 기대할 수 있으며, ③ 여러개의 단위셀을 묶어 하나의 칩을 형성하여 칩 사이즈에 유연성을 부여하고, ④ 이렇게 다수의 단위셀을 묶어서 발광다이오드를 형성하더라도 단위셀 사이에 반사층 또는 전류확산층을 채워 광 출력이 향상되는 발광소자가 요구되고 있다. Therefore, ① the loss of the active layer due to mesa etching, etc. for forming the n-type electrode does not occur, and ② in the formation of the n-type electrode to minimize the loss of the active layer and thereby adjust the size and position of the p-type electrode brightness (Brightness ) It can be expected to improve, and ③ it is possible to bundle several unit cells to form one chip to give flexibility to the chip size, and ④ even if a plurality of unit cells are bundled to form a light emitting diode, a reflective layer or a current diffusion layer is formed between the unit cells. There is a need for a light emitting device that fills and improves light output.
본 발명은 전술한 종래기술의 문제점을 해결하기 위해 안출된 것으로써, 다수의 단위셀을 하나로 묶어 멀티셀 구조를 취함으로서 칩 사이즈의 조절이 가능하며, 멀티셀 구조에 보호막과 메탈 패드를 추가하여 와이어 본딩이 필요없는 웨이퍼레벨 패키지 구조의 발광다이오드를 제공함에 그 목적이 있다. The present invention has been made to solve the above-described problems of the prior art, it is possible to control the size of the chip by taking a multi-cell structure by tying a plurality of unit cells into one, by adding a protective film and a metal pad to the multi-cell structure It is an object of the present invention to provide a light emitting diode having a wafer level package structure that does not require wire bonding.
또한, 본 발명은 발광다이오드 제작시에 전류확산의 향상을 위해 활성층의 손실이 발생 하는 부분을 최소화하는 구조를 채택함으로써, 발광다이오드 소자 제작레벨에서 제 1반도체층의 컨택부분의 면적을 최소화하고 제 2반도체층의 컨택을 자유롭게 하여 휘도(Brightness)향상 및 발광다이오드의 전기적 특성, 열적특성을 향상시키는데 또 다른 목적이 있다. In addition, the present invention adopts a structure that minimizes the portion where the loss of the active layer occurs in order to improve the current diffusion when manufacturing the light emitting diode, thereby minimizing the area of the contact portion of the first semiconductor layer at the manufacturing level of the light emitting diode device Another purpose is to improve the brightness and improve the electrical and thermal characteristics of the light emitting diode by freeing the contact of the two semiconductor layers.
본 발명은 패키지 실장을 위한 n형 패드 및 p형 패드를 동일면에 형성하여 메사 식각 되어진 면에 형성되는 본딩 패드를 추가로 형성할 필요가 없는 발광다이오드를 제공함에 또 다른 목적이 있다. Another object of the present invention is to provide a light emitting diode in which n-type pads and p-type pads for package mounting are formed on the same surface so that a bonding pad formed on a mesa-etched surface is not additionally formed.
본 발명이 이루고자 하는 기술적 과제들은 이상에서 언급한 기술적 과제들로 제한되지 않으며, 언급되지 않은 또 다른 기술적 과제들은 본 발명의 기재로부터 당해 분야에서 통상의 지식을 가진 자에게 명확하게 이해될 수 있을 것이다. Technical problems to be achieved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description of the present invention. .
상술한 종래기술의 문제점을 해결하기 위하여 본 발명의 일측면에 의하면, 투광성 기판(Substrate); 상기 투광성 기판상에 순차적으로 형성되는 제 1반도체층, 활성층 및 제 2반도체층; 상기 제 2반도체층 및 활성층의 일부영역이 제거되어 서로 이격되어 형성되는 복수의 홀(hole); 상기 복수의 홀(hole) 중 일부의 홀(hole)을 통해 상기 제 1반도체층과 컨택(contact)되며, 그 상면이 외부로 노출되도록 형성되는 제 1전극; 상기 제 1전극의 측면 둘레를 감싸서 상기 제 1반도체층과 제 2반도체층의 쇼트(short)를 방지하는 제 1보호막; 상기 복수의 홀(hole) 중 상기 제 1전극이 형성되지 아니한 홀의 측면 및 하부면에 형성되는 제 2보호막; 상기 제 2보호막 및 상기 제 2반도체층 상에 형성되는 반사층 또는 전류확산층; 및 상기 반사층 또는 전류확산층상에 형성되는 제 2전극;을 구비하는 단위셀을 포함하는 것을 특징으로 하는 멀티셀(Muti-Cell) 구조를 갖는 발광다이오드를 제공한다. According to an aspect of the present invention to solve the above-mentioned problems of the prior art, a transparent substrate (Substrate); A first semiconductor layer, an active layer, and a second semiconductor layer sequentially formed on the light transmissive substrate; A plurality of holes formed to be spaced apart from each other by removing a portion of the second semiconductor layer and the active layer; A first electrode contacting the first semiconductor layer through a portion of the plurality of holes and contacting the first semiconductor layer to expose the upper surface to the outside; A first passivation layer surrounding a side circumference of the first electrode to prevent a short between the first semiconductor layer and the second semiconductor layer; A second passivation layer formed on side and bottom surfaces of the hole in which the first electrode is not formed among the plurality of holes; A reflection layer or a current diffusion layer formed on the second passivation layer and the second semiconductor layer; And a second cell formed on the reflective layer or the current spreading layer. The light emitting diode having a multi-cell structure is provided.
본 발명은 상기 단위셀을 다수 구비하되, 상기 다수의 단위셀은 메탈라인의 형태로 형성되는 제 1전극 및 제 2전극에 의해 연결되는 것이 바람직하다. Preferably, the present invention includes a plurality of unit cells, wherein the plurality of unit cells are connected by a first electrode and a second electrode formed in the form of a metal line.
본 발명은 상기 제 1전극 및 메탈라인의 상부를 커버하고, 상기 제 2전극의 측면과 접하도록 형성되며 제 1전극과 제 2전극의 쇼트(short)를 방지하는 제 3보호막; 상기 제 2보호막의 소정영역이 제거된 홀(hole)을 통해 상기 제 1전극과 컨택되는 제 1메탈패드; 및 상기 제 2전극과 컨택되며, 상기 제 1메탈패드와 이격되어 형성되는 제 2메탈패드;를 더 구비하는 것이 바람직하다. The present invention includes a third passivation layer covering an upper portion of the first electrode and the metal line and in contact with a side surface of the second electrode and preventing a short between the first electrode and the second electrode; A first metal pad contacting the first electrode through a hole from which a predetermined region of the second passivation layer is removed; And a second metal pad contacted with the second electrode and spaced apart from the first metal pad.
본 발명은 상기 제 3보호막 상의 상기 제 1메탈패드와 제 2메탈패드가 형성되지 않은 영역에 형성되고, 상기 제 1메탈패드 및 제 2메탈패드의 쇼트(short)를 방지하는 제 4보호막을 더 구비하는 것이 바람직하다. The present invention further includes a fourth passivation layer formed on an area where the first metal pad and the second metal pad are not formed on the third passivation layer, and preventing a short between the first metal pad and the second metal pad. It is preferable to provide.
본 발명에서 상기 제 1보호막, 제 2보호막, 제 3보호막 또는 제 4보호막은, SiO2, Si3N4, 레진(Resin)수지 또는 SOG(Spin on Glass) 중에서 선택되는 어느 하나의 물질로 형성되는 것이 바람직하다. In the present invention, the first protective film, the second protective film, the third protective film or the fourth protective film is formed of any one material selected from SiO 2 , Si 3 N 4 , resin, or spin on glass (SOG). It is desirable to be.
본 발명에서 상기 반사층 또는 전류확산층은, 은(Ag), 니켈(Ni), 알루미늄(Al), 티타늄(Ti), 팔라듐(Pd), 백금(Pt), 루테늄(Ru), 금(Au), 로듐(Rh), 이리듐(Ir), 인듐주석산화물(ITO), 인듐아연산화물(IZO), 인듐 산화물, 주석산화물, 실리콘 옥사이드(SiO₂), 실리콘 나이트라이드(Si₃N₄), 알루미늄 산화물, 티타늄 산화물 중에서 선택되는 어느 하나 이상의 물질로 형성되는 것이 바람직하다. In the present invention, the reflective layer or the current diffusion layer, silver (Ag), nickel (Ni), aluminum (Al), titanium (Ti), palladium (Pd), platinum (Pt), ruthenium (Ru), gold (Au), Choose from rhodium (Rh), iridium (Ir), indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide, tin oxide, silicon oxide (SiO₂), silicon nitride (Si₃N₄), aluminum oxide, titanium oxide It is preferably formed of any one or more materials.
본 발명에서 상기 전류확산층은, 인듐주석산화물(ITO), 산화아연(ZnO), Ni/Au 중에서 선택되는 어느 하나의 물질로 형성되는 것이 바람직하다. In the present invention, the current diffusion layer is preferably formed of any one material selected from indium tin oxide (ITO), zinc oxide (ZnO), Ni / Au.
상술한 종래기술의 문제점을 해결하기 위한 본 발명의 타측면에 의하면, 투광성 기판 상에 제 1반도체층, 활성층 및 제 2반도체층을 순차적으로 형성하는 단계; 상기 제 2반도체층상의 소정거리로 이격된 영역마다 패터닝 후 식각하여 제 1반도체층의 상면이 노출되도록 상기 제 2반도체층 및 활성층을 제거하여 복수의 홀(hole)을 형성하는 단계; 상기 복수의 홀(hole) 중 일부의 홀(hole)의 측면부에 제 1보호막을 형성하는 단계; 상기 제 1보호막이 형성된 홀(hole)을 통해 제 1반도체층과 컨택(contact)되며, 그 상면이 외부로 노출되도록 형성되는 제 1전극을 형성하는 단계;상기 제 1전극이 형성되지 아니한 홀(hole)의 측면과 하부면에 제 2보호막을 형성하는 단계; 상기 제 2보호막이 형성된 홀(hole)과 상기 제 2반도체층상에 반사층 또는 전류확산층을 형성하는 단계; 및 상기 반사층 또는 전류확산층상에 상기 제 2반도체층과의 컨택을 위한 제 2전극을 형성하는 단계;를 포함하는 멀티셀(Muti-Cell) 구조를 갖는 발광다이오드의 제조방법을 제공한다. According to another aspect of the present invention for solving the above-described problems of the prior art, the steps of sequentially forming a first semiconductor layer, an active layer and a second semiconductor layer on a light transmissive substrate; Forming a plurality of holes by removing the second semiconductor layer and the active layer so that the top surface of the first semiconductor layer is exposed by etching after patterning each region spaced by a predetermined distance on the second semiconductor layer; Forming a first passivation layer on side surfaces of some of the holes; Forming a first electrode contacted with the first semiconductor layer through a hole in which the first passivation layer is formed, and having an upper surface exposed to the outside; a hole in which the first electrode is not formed; forming a second passivation layer on side and bottom surfaces of the hole); Forming a reflective layer or a current spreading layer on the hole where the second passivation layer is formed and on the second semiconductor layer; And forming a second electrode for contact with the second semiconductor layer on the reflective layer or the current spreading layer.
본 발명은 상기 제 2전극 형성단계 후에, 상기 제 1전극 및 제 2전극을 각각 메탈라인의 형태로 형성하여 각각의 단위셀을 연결하는 단계를 더 구비하는 것이 바람직하다. The present invention preferably further includes the step of connecting the respective unit cells by forming the first electrode and the second electrode in the form of a metal line after the second electrode forming step.
본 발명은 상기 메탈라인 형성단계 후에, 상기 제 1전극 및 메탈라인의 상부를 커버하고, 상기 제 2전극의 측면에 접하는 제 3 보호막을 형성하는 단계; 상기 제 3보호막의 소정영역을 제거하여 서로 이격되는 복수의 홀(holel)을 형성하는 단계; 상기 홀(hole)을 통해 제 1전극과 컨택하는 제 1메탈패드를 형성하는 단계; 및 상기 제 2전극과 컨택되며, 상기 제 1메탈패드와 격리된 위치에 제 2메탈패드를 형성하는 단계;를 더 구비하는 것이 바람직하다. According to an embodiment of the present disclosure, after the metal line forming step, forming a third passivation layer covering an upper portion of the first electrode and the metal line and in contact with a side surface of the second electrode; Removing a predetermined region of the third passivation layer to form a plurality of holes spaced apart from each other; Forming a first metal pad contacting a first electrode through the hole; And forming a second metal pad in contact with the second electrode and separated from the first metal pad.
본 발명은 상기 제 2메탈패드 형성단계 후에, 상기 제 1메탈패드 및 제 2메탈패드가 형성되지 않은 제 3보호막상에 제 4보호막을 형성하는 단계를 더 구비하는 것이 바람직하다. The present invention preferably further includes forming a fourth passivation layer on the third passivation layer on which the first metal pad and the second metal pad are not formed after the second metal pad forming step.
본 발명에 의하여, 각각 구분되어진 단위 셀 구조의 칩을 보호막 공정과 이를 연결하는 메탈라인 공정을 통하여 하나의 발광다이오드 멀티 셀로 구성될 수 있으므로, 칩 사이즈에 유연성을 가질 수 있고, 생산성 향상 및 제조비용의 절감을 가져올 수 있다. 또한, 다수의 단위셀 사이의 구간에 반사메탈 또는 투명전극 등을 형성하여 광추출 효율을 향상 시킬 수 있으며, 제 2 반도체층과 컨택되는 제 2전극의 사이즈와 위치를 임의로 정할 수 있으므로 발광다이오드 형태의 유연성을 가져올 수 있다. According to the present invention, since each chip having a unit cell structure divided into a protective film process and a metal line process connecting the same may be configured as a single light emitting diode multi-cell, it is possible to have flexibility in chip size, and to improve productivity and manufacturing cost. Can bring about savings. In addition, light extraction efficiency can be improved by forming a reflective metal or a transparent electrode in a section between a plurality of unit cells, and the size and position of the second electrode in contact with the second semiconductor layer can be arbitrarily determined to form a light emitting diode. Can bring flexibility.
또한, 본 발명에 의하여, 동일 웨이퍼 내에서 컷팅공정의 차이에 의하여 서로 다른 칩 사이즈를 갖는 발광다이오드를 구현 할 수 있어 생산성 향상 및 원가 절감의 효과가 있다. In addition, according to the present invention, it is possible to implement light emitting diodes having different chip sizes by different cutting processes in the same wafer, thereby improving productivity and reducing costs.
또한, 본 발명에 의하여, 발광다이오드 제작에 있어 종래기술에 비해 n형 반도체층(제 1반도체층)의 컨택을 위한 식각부분을 줄여줌으로써 활성층의 손실영역을 최소화하고 유효 발광 면적을 넓혀서 광출력이 향상되는 효과가 있고, 이와 더불어 대면적 칩(chip)의 경우 필요한 패드(pad) 숫자가 줄어들어 패드에 의한 광 흡수를 방지하여 패키지의 광 출력이 향상되는 효과가 있다. In addition, according to the present invention, by reducing the etching portion for the contact of the n-type semiconductor layer (first semiconductor layer) compared to the prior art in manufacturing the light emitting diode to minimize the loss area of the active layer and widen the effective light emitting area to increase the light output In addition, in the case of a large area chip, the number of pads required is reduced, and thus the light output of the package is improved by preventing light absorption by the pad.
또한 본 발명에 의하여, n형 패드(제 1메탈패드) 및 p형 패드(제 2메탈패드)가 동일면에 형성 되어 메사 식각 되어진 면에 형성되는 n형 패드에 추가로 본딩 패드를 형성할 필요가 없어 제조공정이 단순해지고 제조비용이 절감되는 효과가 있다. In addition, according to the present invention, it is necessary to form an additional bonding pad on an n-type pad formed on an n-type pad (first metal pad) and a p-type pad (second metal pad) formed on the same surface and mesa-etched. There is no effect that the manufacturing process is simplified and the manufacturing cost is reduced.
또한 본 발명에 의하여, 반사층과 본딩 메탈간의 직접 컨택이 없으므로 금속 등으로 형성되는 반사층의 손상을 방지하는 효과가 있다.In addition, according to the present invention, since there is no direct contact between the reflective layer and the bonding metal, there is an effect of preventing damage to the reflective layer formed of a metal or the like.
도 1a는 종래기술에 의한 발광다이오드의 전극구조를 나타낸 일예시도.Figure 1a is an exemplary view showing an electrode structure of a light emitting diode according to the prior art.
도 1b 내지 도 1c는 본 발명의 일실시예에 따른 멀티셀 구조를 갖는 발광다이오드의 상면도. 1B to 1C are top views of a light emitting diode having a multi-cell structure according to an embodiment of the present invention.
도 2a 내지 도 2g는 본 발명의 일실시예에 따른 멀티셀 구조를 갖는 발광다이오드의 단계별 제조순서를 나타낸 일예시도. 2A to 2G are exemplary views illustrating a step-by-step manufacturing procedure of a light emitting diode having a multi-cell structure according to an embodiment of the present invention.
도 3은 본 발명의 일실시예에 따른 메탈패드를 포함하는 멀티셀 구조를 갖는 발광다이오드의 상면도. 3 is a top view of a light emitting diode having a multi-cell structure including a metal pad according to an embodiment of the present invention.
도 4a 내지 도 4c는 본 발명의 일실시예에 따른 메탈패드를 포함하는 멀티셀 구조를 갖는 발광다이오드의 제조순서를 나타낸 일예시도. 4A to 4C are exemplary views illustrating a manufacturing procedure of a light emitting diode having a multi-cell structure including a metal pad according to an embodiment of the present invention.
도 5는 본 발명의 일실시예에 따른 멀티셀 구조를 갖는 발광다이오드 제조방법의 순서도.5 is a flow chart of a method of manufacturing a light emitting diode having a multi-cell structure according to an embodiment of the present invention.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 이에 앞서, 본 명세서 및 청구범위에 사용된 용어나 단어는 통상적이거나 사전적인 의미로 한정해서 해석되어서는 아니되며, 발명자는 그 자신의 발명을 가장 최선의 방법으로 설명하기 위해 용어의 개념을 적절하게 정의할 수 있다는 원칙에 입각하여 본 발명의 기술적 사상에 부합하는 의미와 개념으로 해석되어야만 한다. 따라서, 본 명세서에 기재된 실시예와 도면에 도시된 구성은 본 발명의 가장 바람직한 일실시예에 불과할 뿐이고 본 발명의 기술적 사상을 모두 대변하는 것은 아니므로, 본 출원시점에 있어서 이들을 대체할 수 있는 다양한 균등물과 변형예들이 있을 수 있음을 이해하여야 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only one of the most preferred embodiments of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.
도 1a는 종래기술에 의한 발광다이오드의 전극구조를 나타낸 일예시도이다.Figure 1a is an exemplary view showing an electrode structure of a light emitting diode according to the prior art.
도 1을 참조하면, 통상적인 발광다이오드의 구조는 서브스트레이트(substrate) 기판상에 순차적으로 형성된 n형 질화물 반도체층, 활성층 및 p형 질화물 반도체층을 포함하며, 상기 p형 질화물 반도체층과 활성층은 그 일부 영역을 식각등의 공정으로 제거하여 n형 질화물 반도체층의 일부 상면이 노출된 구조를 갖는다. 상기 노출된 n형 질화물 반도체층 상에는 n형 전극 또는 제 1전극(120)이 형성되고 p형 질화물 반도체층 상에는 오믹접촉을 형성하기 위하여 투명 전극층이 형성된 후에, p형 전극 또는 제 2전극(110)을 형성한다.Referring to FIG. 1, a structure of a conventional light emitting diode includes an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer sequentially formed on a substrate, and the p-type nitride semiconductor layer and the active layer The partial region is removed by a process such as etching to expose a part of the upper surface of the n-type nitride semiconductor layer. After the n-type electrode or the first electrode 120 is formed on the exposed n-type nitride semiconductor layer and the transparent electrode layer is formed on the p-type nitride semiconductor layer to form ohmic contact, the p-type electrode or the second electrode 110 To form.
이러한 종래기술에 의해 형성되는 발광다이오드는 n형 질화물 반도체층상에 n형 전극 또는 제 1전극(120)을 형성하기 위해 활성층의 일부영역을 제거해야 하는데, 이러한 활성층의 손실로 인한 광출력을 약화시키는 문제점과 수평방향의 전류확산이 제한되는 문제점이 있었다. The light emitting diode formed by the prior art should remove a portion of the active layer to form the n-type electrode or the first electrode 120 on the n-type nitride semiconductor layer, which weakens the light output due to the loss of the active layer. There was a problem and the current spreading in the horizontal direction is limited.
종래기술에 의하면, 특히 수평구조 발광다이오드의 전극구조에 있어서 수평방향으로의 전류 확산이 제한되는 문제점을 극복하기 위하여 핑거(finger) 형태의 전극구조가 출현하게 되었다. 이러한 핑거(finger) 형태의 전극구조는 전류 확산 측면에서는 이점이 있으나, 이 역시 n형 반도체층과 n형 전극 또는 제 1전극(220)의 컨택을 위해 메사 식각 등이 필수적으로 구비되어야 하므로, 빛이 나오는 활성층의 손실이 발생하게 되어 고출력 발광다이오드의 제작을 담보하기에는 어려운 문제점이 있었다. According to the prior art, in order to overcome the problem that current spreading in the horizontal direction is limited, especially in the electrode structure of the horizontal structure light emitting diode, a finger type electrode structure has appeared. This finger type electrode structure has advantages in terms of current diffusion, but also mesa etching is required for the contact between the n-type semiconductor layer and the n-type electrode or the first electrode 220, This caused the loss of the active layer has a problem that is difficult to secure the production of high-output light emitting diodes.
도 1b 내지 도 1c는 본 발명의 일실시예에 따른 멀티셀 구조를 갖는 발광다이오드의 상면도이다. 1B to 1C are top views of a light emitting diode having a multi-cell structure according to an embodiment of the present invention.
본 발명에 의한 멀티셀 구조를 갖는 발광다이오드에 의하면, 투광성 기판; 상기 투광성 기판상에 순차적으로 형성되는 제 1반도체층, 활성층 및 제 2반도체층; 상기 제 2반도체층 및 활성층의 일부영역이 제거되어 서로 이격되어 형성되는 복수의 홀(hole); 상기 복수의 홀 중 일부의 홀을 통해 상기 제 1반도체층과 컨택되며, 그 상면이 외부로 노출되도록 형성되는 제 1전극; 상기 제 1전극의 측면 둘레를 감싸서 상기 제 1반도체층과 제 2반도체층의 쇼트를 방지하는 제 1보호막; 상기 복수의 홀 중 상기 제 1전극이 형성되지 아니한 홀의 측면 및 하부면에 형성되는 제 2보호막; 상기 제 2보호막 및 상기 제 2반도체층 상에 형성되는 반사층 또는 전류확산층; 및 상기 반사층 또는 전류확산층상에 형성되는 제 2전극;을 구비하는 단위셀을 포함하는 것을 특징으로 한다.According to the light emitting diode having the multi-cell structure according to the present invention, there is provided a light transmitting substrate; A first semiconductor layer, an active layer, and a second semiconductor layer sequentially formed on the light transmissive substrate; A plurality of holes formed to be spaced apart from each other by removing a portion of the second semiconductor layer and the active layer; A first electrode contacting the first semiconductor layer through a portion of the plurality of holes, the upper electrode being exposed to the outside; A first passivation layer surrounding a side circumference of the first electrode to prevent a short between the first semiconductor layer and the second semiconductor layer; A second passivation layer formed on side and bottom surfaces of the hole in which the first electrode is not formed among the plurality of holes; A reflection layer or a current diffusion layer formed on the second passivation layer and the second semiconductor layer; And a second electrode formed on the reflective layer or the current spreading layer.
여기서 본 발명은 상기 단위셀을 다수 구비하되, 상기 다수의 단위셀은 메탈라인의 형태로 형성되는 제 1전극(140) 및 제 2전극(150)에 의해 연결되는 것이 바람직하다. 본 발명에서 상기 제 1전극은, 그 상면이 원, 사각형 또는 다각형의 형태를 갖고, 그 측면의 단면부가 직사각형의 형태를 가질 수 있다. The present invention is provided with a plurality of unit cells, the plurality of unit cells is preferably connected by the first electrode 140 and the second electrode 150 formed in the form of a metal line. In the present invention, the first electrode, the upper surface may be in the form of a circle, a square or a polygon, the cross-section of the side may have a rectangular shape.
본 발명에서 상기 제 1반도체층은 n형 질화물 반도체층이고, 제 2반도체층은 p형 질화물 반도체층인 것이 바람직하나, 그 역의 경우도 배제하는 것은 아니다. In the present invention, it is preferable that the first semiconductor layer is an n-type nitride semiconductor layer, and the second semiconductor layer is a p-type nitride semiconductor layer, but vice versa.
이하, 도 2a 내지 도 2g에서 본 발명이 제시하는 발광다이오드의 구조 및 제조순서에 대해 살펴보기로 한다. Hereinafter, the structure and manufacturing procedure of the light emitting diode of the present invention will be described with reference to FIGS. 2A to 2G.
도 2a 내지 도 2g는 본 발명의 일실시예에 따른 멀티셀 구조를 갖는 발광다이오드의 단계별 제조순서를 나타낸 일예시도이다. 2A to 2G are exemplary views illustrating a step-by-step manufacturing procedure of a light emitting diode having a multi-cell structure according to an embodiment of the present invention.
도 2a 내지 도 2h는 도 1c의 발광다이오드 소자를 A - A' 방향으로 자른 단면을 중심으로 제조순서를 나타낸 예시도라고 할 수 있다. 2A to 2H may be referred to as an exemplary view showing a manufacturing procedure centering on a cross section of the light emitting diode device of FIG. 1C cut along the direction A-A '.
먼저, 도 2a를 참조하면, 투광성 기판(210) 상에 제 1반도체층(220), 활성층(230) 및 제 2반도체층(240)을 순차적으로 증착된 모습을 도시하고 있다. First, referring to FIG. 2A, the first semiconductor layer 220, the active layer 230, and the second semiconductor layer 240 are sequentially deposited on the transparent substrate 210.
본 발명에서 상기 투광성 기판(210)은 사파이어 기판 등을 이용할 수 있고, 투광성기판(410)과 제 1반도체층(220)사이에 버퍼층(미도시)을 더 포함하여 발광다이오드 소자를 구성할 수 있다. 또한, 본 발명에서 상기 제 1반도체층(220)은 n형 질화물 반도체층이고, 제 2반도체층(240)은 p형 질화물 반도체층일 수 있다. In the present invention, the light transmissive substrate 210 may be a sapphire substrate or the like, and may further include a buffer layer (not shown) between the light transmissive substrate 410 and the first semiconductor layer 220 to form a light emitting diode device. . In addition, in the present invention, the first semiconductor layer 220 may be an n-type nitride semiconductor layer, and the second semiconductor layer 240 may be a p-type nitride semiconductor layer.
본 발명에서 질화갈륨(GaN)계 반도체층을 이용하는 경우, 투광성 기판상에 n형 질화갈륨층(n-GaN)층, 다중양자우물구조로 형성되어 광을 방출하는 활성층과 p형 질화갈륨층(p-GaN)층을 포함하여 구성될 수 있다. In the present invention, when using a gallium nitride (GaN) -based semiconductor layer, an n-type gallium nitride layer (n-GaN) layer, a multi-quantum well structure is formed on the transmissive substrate to emit light and p-type gallium nitride layer ( p-GaN) layer.
또한, 필요에 따라 투광성 기판상에 버퍼층을 형성한 후 n-GaN층을 형성할수도 있는데, 이러한 버퍼층은 기판과 반도체층의 격자상수 차이를 줄여주기 위한 것으로써, AlInN구조, InGaN/GaN초격자구조, InGaN/GaN적층구조, AlInGaN/InGaN/GaN의 적층구조 중에서 선택되어 형성될 수 있다.In addition, an n-GaN layer may be formed after forming a buffer layer on the light-transmissive substrate as needed. Such a buffer layer is used to reduce the lattice constant difference between the substrate and the semiconductor layer. The structure may be selected from a stacked structure of InGaN / GaN stacked structure and AlInGaN / InGaN / GaN.
투광성 기판상에 또는 상기 버퍼층 상에는 제 1반도체층(220)이 형성되는데, 상기 제 1반도체층(220)은 n-GaN층으로 형성될 수있으며, 실리콘(Si)을 도펀트(Dopant)로 사용하여 도핑될 수 있다. 고온에서 진행되며 암모니아(NH₃)를 캐리어가스로 Ga, N, Si를 화합물로 결합시킬수 있다. A first semiconductor layer 220 is formed on the light transmissive substrate or on the buffer layer. The first semiconductor layer 220 may be formed of an n-GaN layer, and silicon (Si) is used as a dopant. Can be doped. It proceeds at high temperature and can combine ammonia (NH₃) as a carrier gas and Ga, N, Si as a compound.
상기 제 1반도체층(220)이 형성된 후, 활성층(230)을 형성하게 되는데, InGaN으로된 발광체 물질을 첨가한 반도체 층일 수 있고 이외에도 AlGaN, AlInGaN 등의 물질도 활성층(230)으로 이용될 수 있다. 이때 활성층(230)은 InGaN/GaN 양자우물(QW) 구조를 이룰 수 있으며, 휘도 향상을 위하여 양자우물 구조가 복수로 형성되어 다중 양자우물(MQW) 구조를 이룰 수 있다.After the first semiconductor layer 220 is formed, the active layer 230 is formed, which may be a semiconductor layer to which a light emitting material made of InGaN is added. In addition, a material such as AlGaN and AlInGaN may also be used as the active layer 230. . In this case, the active layer 230 may form an InGaN / GaN quantum well (QW) structure, and a plurality of quantum well structures may be formed to improve luminance, thereby forming a multi-quantum well (MQW) structure.
상기 활성층(230)이 형성된 후, 활성층 상에 제 2반도체층(240)이 형성되는데, p-GaN층으로 형성될 수 있으며, 마그네슘(Mg)을 도펀트로 사용할 수 있다. 본 공정도 고온에서 진행되며 암모니아(NH₃) 캐리어가스로 Ga, N, Mg를 화합물로 결합시킬 수 있다. After the active layer 230 is formed, a second semiconductor layer 240 is formed on the active layer, which may be formed of a p-GaN layer, and magnesium (Mg) may be used as a dopant. This process is also carried out at a high temperature and can combine Ga, N, Mg as a compound with an ammonia (NH₃) carrier gas.
도 2b를 참조하면, 상기 제 2반도체층(240) 및 활성층(230)의 소정영역을 제거하여, 서로 이격되어 형성되는 홀(hole)(250)을 형성하게 된다. 상기 홀은 제 1반도체층(220)의 상면이 노출되도록 형성된다. Referring to FIG. 2B, predetermined regions of the second semiconductor layer 240 and the active layer 230 are removed to form holes 250 spaced apart from each other. The hole is formed to expose the top surface of the first semiconductor layer 220.
이러한 홀(250)은 제 1전극(270)과, 반사층 또는 전류확산층(290)의 형성을 위함인데, 제 2반도체층(240)상에 소정의 거리를 두고 이격된 홀(250)이 형성될 수 있도록 패터닝하고 식각공정을 거치게 되는데, 이때, 습식 식각방법(Wet Etching) 또는 건식식각(Dry Etching) 방법이 이용될 수 있다.The holes 250 are used to form the first electrode 270 and the reflective layer or the current spreading layer 290. The holes 250 spaced apart from each other by a predetermined distance on the second semiconductor layer 240 may be formed. Patterning and etching process to be carried out, in this case, the wet etching (Wet Etching) or dry etching (Dry Etching) method may be used.
도 2c를 참조하면, 상기 복수의 홀(250) 중 일부의 홀의 측면부에 제 1보호막(260)을 형성한 모습을 도시하고 있다. 바람직하게는 최측단부터 짝수번 째 홀 또는 홀수번 째 홀에만 제 1보호막(260)을 형성함이 바람직할 것이다. Referring to FIG. 2C, the first protective layer 260 is formed on the side surface of some of the plurality of holes 250. Preferably, the first passivation layer 260 may be formed only in the even-numbered holes or the odd-numbered holes from the outermost end.
이러한 제 1보호막(260)은 제 1전극(270)과 제 2전극(291)의 쇼트(short)를 방지하기 위하여 형성되는 것이라고 할 수 있다. 상기 제 1보호막(260)은, SiO2, Si3N4, 레진(Resin)수지 또는 SOG(Spin on Glass) 중에서 선택되는 어느 하나의 물질로 형성될 수 있다. The first protective layer 260 may be formed to prevent a short between the first electrode 270 and the second electrode 291. The first passivation layer 260 may be formed of any one material selected from SiO 2 , Si 3 N 4 , resin, or spin on glass (SOG).
도 2d를 참조하면, 상기 제 1보호막(260)과 제 1반도체층(220)로 둘러쌓인 영역에 제 1전극(270)을 형성하게 된다. 상기 제 1전극(270)은 각각 독립되어 분할된 구조로 형성되게 되므로 추후 메탈라인으로 연결되는 것이 바람직하다. 상기 제 1전극(270)은 공지된 전극물질을 이용하여 형성할 수 있으며, 전극 페이스트를 도포하여 형성하는 것이 가능하다. Referring to FIG. 2D, a first electrode 270 is formed in a region surrounded by the first passivation layer 260 and the first semiconductor layer 220. Since the first electrodes 270 are formed to be divided independently from each other, the first electrodes 270 are preferably connected to metal lines later. The first electrode 270 may be formed using a known electrode material, and may be formed by applying an electrode paste.
도 2e를 참조하면, 상기 복수의 홀(250)중 제 1전극(270)이 형성되지 아니한 홀에 제 2보호막(280)을 형성한 모습을 도시하고 있다. 상기 제 2보호막(280)은 홀의 측면 뿐만 아니라 하부면에도 형성되어 제 1반도체층(220)과 반사층 또는 전류확산층(290)을 절연하는 역할을 수행한다. Referring to FIG. 2E, the second protective layer 280 is formed in a hole in which the first electrode 270 is not formed among the plurality of holes 250. The second passivation layer 280 is formed not only on the side of the hole but also on the bottom thereof to insulate the first semiconductor layer 220 from the reflective layer or the current diffusion layer 290.
도 2f를 참조하면, 상기 제 2보호막(280) 형성 후에, 상기 제 2보호막(280)이 형성된 홀과 제 2반도체층(240)상에 반사층 또는 전류확산층(290)을 형성한 모습을 도시하고 있다. 상기 반사층 또는 전류확산층(290)은 제 1보호막(260)에 의해 제 1전극(270)과의 쇼트(short)가 방지된다. Referring to FIG. 2F, after the second passivation layer 280 is formed, the reflective layer or the current diffusion layer 290 is formed on the hole and the second semiconductor layer 240 on which the second passivation layer 280 is formed. have. The reflective layer or the current spreading layer 290 is prevented from being shorted with the first electrode 270 by the first passivation layer 260.
상기 반사층 또는 전류확산층(290)에 있어서, 반사층을 형성하는 경우에는 필요에 따라 은(Ag), 니켈(Ni), 알루미늄(Al), 티타늄(Ti), 팔라듐(Pd), 백금(Pt), 루테늄(Ru), 금(Au), 로듐(Rh), 이리듐(Ir), 인듐주석산화물(ITO), 인듐아연산화물(IZO), 인듐 산화물, 주석산화물, 실리콘 옥사이드(SiO₂), 실리콘 나이트라이드(Si₃N₄), 알루미늄 산화물, 티타늄 산화물 중에서 선택되는 어느 하나의 물질을 이용해서 형성할 수 있다. 이러한 단위셀 사이의 반사층(290)의 형성으로 인해, 발광다이오드 내부로부터 광흡수를 억제하여 광추출 효율을 더욱 향상시킬 수 있다. In the reflective layer or the current diffusion layer 290, when forming the reflective layer, silver (Ag), nickel (Ni), aluminum (Al), titanium (Ti), palladium (Pd), platinum (Pt), Ruthenium (Ru), Gold (Au), Rhodium (Rh), Iridium (Ir), Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Oxide, Tin Oxide, Silicon Oxide (SiO₂), Silicon Nitride ( Si 3 N₄), aluminum oxide, titanium oxide can be formed using any one material selected from. Due to the formation of the reflective layer 290 between the unit cells, it is possible to further suppress the light absorption from the inside of the light emitting diode to further improve the light extraction efficiency.
또한, 전류확산층을 형성하는 경우에는 Ni/Au 등의 메탈이나, ITO, ZnO 등의 산화막을 사용하는 것이 바람직할 것이다. In the case of forming the current diffusion layer, it may be preferable to use a metal such as Ni / Au or an oxide film such as ITO or ZnO.
이후, 각기 독립된 제 1전극(270)을 연결하기 위해 메탈라인 공정을 수행할 수 있다. 이러한 메탈라인 공정으로 인해 각각의 단위셀은 연결되고, 웨이퍼 레벨의 패키징 공정에 있어서 칩 사이즈를 조절할 수 있는 잇점이 있다. Thereafter, a metal line process may be performed to connect the independent first electrodes 270. Due to the metal line process, each unit cell is connected, and chip size can be controlled in a wafer-level packaging process.
도 2h를 참조하면, 상기 반사층(290)상에 제 2전극(291)이 형성된 모습을 도시하고 있다. Referring to FIG. 2H, the second electrode 291 is formed on the reflective layer 290.
상기 제 2전극(291)은 상기 제 2반도체층(240)의 상부면에 형성되게 되며, 반사층(290)의 소정영역의 식각이 선행되어야 한다. 즉 반사층(290)상에 패터닝공정 및 습식식각 또는 건식식각에 의해 제 2반도체층(240)의 상면이 노출되도록 홀을 형성하고, 상기 홀에 제 2전극(291)을 형성하게 된다. 이때, 전극의 재료로는 공지된 물질을 이용할 수 있으며, 전극 페이스트를 도포하여 형성할 수 있다. The second electrode 291 is formed on the upper surface of the second semiconductor layer 240, and the etching of a predetermined region of the reflective layer 290 must be preceded. That is, a hole is formed on the reflective layer 290 so that the upper surface of the second semiconductor layer 240 is exposed by a patterning process and a wet etching or dry etching, and a second electrode 291 is formed in the hole. In this case, a known material may be used as the material of the electrode, and may be formed by applying an electrode paste.
또한, 상기 제 2전극(291)은 핑거(finger)형태로 형성할 수 있는데, 이렇게 핑거형태로 제 2전극(291)을 구성하더라도 제 1전극(270)은 독립된 전극구조를 가지므로 활성층의 손실을 최소화하여 광출력 향상에는 문제가 없다. In addition, the second electrode 291 may be formed in the form of a finger. Even though the second electrode 291 is configured in the form of a finger, since the first electrode 270 has an independent electrode structure, loss of the active layer may occur. By minimizing this, there is no problem in improving the light output.
종합하면 상기 제 1전극(270)과 제 2전극(291)은 메탈라인의 형태로 형성됨으로써 다수의 단위셀을 하나의 패키지로 연결된다고 할 수 있다. In sum, the first electrode 270 and the second electrode 291 may be formed in the form of a metal line, thereby connecting a plurality of unit cells in one package.
또한, 발명의 필요에 따라, 상기 투광성 기판(210) 또는 제 1반도체층(220)은 그 상부면에 요철구조(미도시)를 형성하여 광추출효과를 더욱 높일수 있다. 즉, 투광성 기판(210)과 제 1반도체층(220)의 경계면 또는 제 1반도체층(220)과 활성층(230)의 경계면에 요철구조를 형성할 수 있다. In addition, according to the needs of the invention, the light-transmitting substrate 210 or the first semiconductor layer 220 may further increase the light extraction effect by forming an uneven structure (not shown) on the upper surface. That is, the concave-convex structure may be formed on the interface between the transparent substrate 210 and the first semiconductor layer 220 or the interface between the first semiconductor layer 220 and the active layer 230.
상기의 요철구조는 포토레지스트를 이용하여 형성할 수 있는데, 패턴 마스크로 포토 레지스트를 이용하는 경우에 요철패턴은 포토 리소그래피(photo-lithography), 전자빔 리소그래피(e-beam lithography), 이온빔 리소그래피(Ion-beam Lithography),극자외선 리소그래피(Extreme Ultraviolet Lithography), 근접 X선 리소그라피(Proximity X-ray Lithography) 또는 나노 임프린트 리소그래피(nano imprint lithography) 등의 방법을 이용하여 형성할 수 있다. 또한 이와 같은 과정은 건식 식각 또는 습식 식각을 이용할 수 있다.The uneven structure may be formed by using a photoresist. When the photoresist is used as a pattern mask, the uneven pattern may be photo-lithography, e-beam lithography, or ion beam lithography. It may be formed using a method such as Lithography, Extreme Ultraviolet Lithography, Proximity X-ray Lithography or nano imprint lithography. In addition, this process may use dry etching or wet etching.
도 3은 본 발명의 일실시예에 따른 메탈패드를 포함하는 멀티셀 구조를 갖는 발광다이오드의 상면도이다. 3 is a top view of a light emitting diode having a multi-cell structure including a metal pad according to an embodiment of the present invention.
본 발명은 멀티셀 구조를 갖는 발광다이오드 소자를 형성한 후에 발광다이오드 패키지의 형성을 위해서, 메탈패드를 부착하게 되는데, 도 3는 이러한 메탈패드(340,350)를 구비한 발광다이오드 소자의 상면도라고 할 수 있다. In the present invention, a metal pad is attached to form a light emitting diode package after forming a light emitting diode device having a multi-cell structure. FIG. 3 is a top view of a light emitting diode device including the metal pads 340 and 350. Can be.
즉, 본 발명은 상술한 멀티셀 구조를 갖는 발광다이오드 소자에 있어서, 상기 제 1전극(270) 및 메탈라인의 상부를 커버하고, 상기 제 2전극(291)의 측면과 접하도록 형성되며 제 1전극(270)과 제 2전극(291)의 쇼트를 방지하는 제 3보호막(292), 상기 제 2보호막의 소정영역이 제거된 홀을 통해 상기 제 1전극과 컨택되는 제 1메탈패드(340) 및 상기 제 2전극과 컨택되며, 상기 제 1메탈패드와 이격되어 형성되는 제 2메탈패드(350)를 더 구비하는 발광다이오드를 형성할 수 있다. That is, in the light emitting diode device having the multi-cell structure described above, the present invention covers the upper part of the first electrode 270 and the metal line, and is formed to be in contact with the side surface of the second electrode 291. A third passivation layer 292 for preventing short between the electrode 270 and the second electrode 291, and a first metal pad 340 contacting the first electrode through a hole from which a predetermined region of the second passivation layer is removed; And a second metal pad 350 contacted with the second electrode and spaced apart from the first metal pad.
또한, 본 발명은 상기 제 3보호막(292)상의 제 1메탈패드(340)와 제 2메탈패드(350)가 형성되지 않은 영역에 형성되는 제 4보호막(293)을 더 포함할 수 있다. 이하 상기 구조는 도 4a 내지 도 4c에서 상세하게 설명하기로 한다. The present invention may further include a fourth passivation layer 293 formed in a region where the first metal pad 340 and the second metal pad 350 are not formed on the third passivation layer 292. Hereinafter, the structure will be described in detail with reference to FIGS. 4A to 4C.
도 4a 내지 도 4c는 본 발명의 일실시예에 따른 메탈패드를 포함하는 멀티셀 구조를 갖는 발광다이오드의 제조순서를 나타낸 일예시도이다. 4A to 4C are exemplary views illustrating a manufacturing procedure of a light emitting diode having a multi-cell structure including a metal pad according to an embodiment of the present invention.
도 4a 내지 도 4c는 상기 도 3의 발광다이오드의 상면도를 B - B' 방향으로 자른 단면도를 중심으로 나타낸 그림이라고 할 수 있다. 4A through 4C are diagrams illustrating a top view of the light emitting diode of FIG. 3 centered on a cross-sectional view taken along the B-B 'direction.
먼저 도 4a를 참조하면, 상기 반사층(290)상에 형성되고, 제 1전극(270) 및 메탈라인을 커버하는 제 3보호막(292)이 형성된다. 또한, 상기 제 3보호막(292)은 제 2전극(291)의 측면에 접하도록 형성될 수 있다. 상기 제 3보호막(292)은 제 1전극(270) 및 제 2전극(291)의 쇼트(short)를 방지하기 위해서 형성하는 것인데, SiO2, Si3N4, 레진(Resin)수지 또는 SOG(Spin on Glass) 중에서 선택되는 어느 하나의 물질로 형성되는 것이 가능하다. First, referring to FIG. 4A, a third passivation layer 292 is formed on the reflective layer 290 and covers the first electrode 270 and the metal line. In addition, the third passivation layer 292 may be formed to contact the side surface of the second electrode 291. The third passivation layer 292 is formed to prevent short of the first electrode 270 and the second electrode 291, and is formed of SiO 2 , Si 3 N 4 , resin, or SOG ( Spin on Glass) may be formed of any one material selected from.
따라서, 상기 제 1보호막(260), 제 2보호막(280) 및 제 3보호막(292)은 절연효과를 나타내면 충분하므로, 동일한 물질로 형성되거나 다른 물질로 형성되더라도 본 발명의 발광다이오드를 구성함에는 무리가 없다. Therefore, since the first protective film 260, the second protective film 280, and the third protective film 292 are sufficient to have an insulating effect, the light emitting diodes of the present invention may be formed even if they are formed of the same material or different materials. There is no crowd.
도 4b를 참조하면, 상기 복수의 제 1전극(270) 중 소정의 제 1전극(270)과 컨택되는 제 1메탈패드(340)와, 상기 제 2전극(291)과 컨택되는 제 2메탈패드(350)가 형성되게 된다. 상기 제 1메탈패드(340) 및 제 2메탈 패드(350)는 발광다이오드의 발광 효율과는 무관한 것으로 패키지 공정을 고려하여 사이즈를 조절하여 발광다이오드 소자를 구성할 수 있을 것이다. 상기와 같이 메탈패드가 형성되면, 서브스트레이트 기판에 실장하여 발광다이오드 패키지를 구성하여 다양한 어플리케이션에 응용될 수 있을 것이다. Referring to FIG. 4B, a first metal pad 340 is in contact with a predetermined first electrode 270 of the plurality of first electrodes 270, and a second metal pad is in contact with the second electrode 291. 350 is formed. The first metal pad 340 and the second metal pad 350 are independent of the light emitting efficiency of the light emitting diode, and may be configured to adjust the size in consideration of the packaging process. When the metal pad is formed as described above, the light emitting diode package may be configured by mounting on the substrate to be applied to various applications.
도 4c를 참조하면, 상기 제 1메탈패드(340) 및 제 2메탈 패드(350)가 형성되지 아니한 영역에 있어서, 제 3보호막(292)상에 제 4보호막(293)이 형성되게 되는데, 상기 제 4보호막(293)은 소자의 안정성을 담보하고 상기 제 1메탈패드(340) 및 제 2메탈패드(350)의 절연을 보장하기 위해 형성된다. Referring to FIG. 4C, in the region where the first metal pad 340 and the second metal pad 350 are not formed, a fourth protective layer 293 is formed on the third protective layer 292. The fourth passivation layer 293 is formed to ensure stability of the device and to insulate the first metal pad 340 and the second metal pad 350 from each other.
위와 같이 제 4보호막(293) 형성단계까지 끝나게 되면, 본 발명이 제안하는 멀티셀 구조를 갖는 발광다이오드의 제조공정이 마무리되게 되며, 상기 발광다이오드를 이용해서 웨이퍼 레벨의 발광다이오드 패키지 제작이 가능하게 된다. When the fourth protective layer 293 is formed as described above, the manufacturing process of the light emitting diode having the multi-cell structure proposed by the present invention is completed, and the wafer-level light emitting diode package can be manufactured using the light emitting diode. do.
도 5는 본 발명의 일실시예에 따른 멀티셀 구조를 갖는 발광다이오드 제조방법의 순서도이다. 5 is a flow chart of a method of manufacturing a light emitting diode having a multi-cell structure according to an embodiment of the present invention.
먼저 사파이어기판 등 투광성 기판상에 제 1반도체층, 활성층 및 제 2반도체층을 순차적으로 형성하는 단계(s501)를 거쳐서, 제 2반도체층상의 소정거리로 이격된 영역마다 패터닝 후 식각하여 제 1반도체층의 상면이 노출되도록 상기 제 2반도체층 및 활성층을 제거하여 복수의 홀(hole)을 형성하는 단계(s502)를 거치게 된다. 상기 제 2반도체층 및 활성층의 소정영역의 제거는 통상의 발광다이오드 제조공정과는 다르게 최소한의 사이즈로 소정의 거리를 두고 홀을 형성하므로, 활성층의 손실이 일반적인 발광다이오드 소자보다 훨씬 적다고 할 수 있다. First, through the step (s501) of sequentially forming the first semiconductor layer, the active layer, and the second semiconductor layer on a light-transmissive substrate such as a sapphire substrate, the first semiconductor is patterned and then etched for each area spaced by a predetermined distance on the second semiconductor layer. The second semiconductor layer and the active layer are removed to form a plurality of holes to expose the top surface of the layer (S502). Since the removal of the predetermined region of the second semiconductor layer and the active layer forms holes at a predetermined distance with a minimum size, unlike the conventional light emitting diode manufacturing process, the loss of the active layer is much less than that of the general light emitting diode device. have.
이후 상기 복수의 홀(hole) 중 일부의 홀(hole)의 측면부에 제 1보호막을 형성하는 단계(s503)를 거치게 되는데, 이는 제 1전극의 쇼트(short)방지하기 위함이다. Thereafter, the step of forming a first passivation layer (S503) on a side surface of a part of the holes (holes) of the plurality of holes (hole) is to prevent the short (short) of the first electrode.
상기의 공정이후, 상기 제 1보호막이 형성된 홀(hole)을 통해 제 1반도체층과 컨택(contact)되며, 그 상면이 외부로 노출되도록 형성되는 제 1전극을 형성하는 단계를 거치게 된다.(s504)After the above process, a first electrode is contacted with the first semiconductor layer through a hole in which the first passivation layer is formed, and a first electrode is formed to expose the upper surface thereof to the outside. )
이후 상기 제 1전극이 형성되지 아니한 홀(hole)의 측면과 하부면에 제 2보호막을 형성하게 된다.(s505) 이는 단위셀과 단위셀 사이의 공간마다 반사층 또는 전류확산층을 형성하여 광 추출효율을 더욱 향상시키기 위함이다. Thereafter, a second passivation layer is formed on the side and the bottom of the hole in which the first electrode is not formed. In operation S505, a reflection layer or a current diffusion layer is formed in each space between the unit cell and the unit cell to extract light. To further improve.
이후 상기 제 2보호막이 형성된 홀(hole)과 상기 제 2반도체층상에 반사층 또는 전류확산층을 형성하는 단계를 거치게 된다.(s506) 상기 반사층은 활성층에서 발생하는 빛을 투광성 기판상으로 되돌려보내서 광추출효율을 높이는데 일조할 수 있다. 전류확산층을 형성하는 경우에는 수평방향으로 전류를 확산하는데 일조하여 광추출효율을 더욱 높일 수 있다. Thereafter, a step of forming a reflective layer or a current spreading layer on the hole and the second semiconductor layer on which the second passivation layer is formed is performed (s506). The reflective layer returns light generated from the active layer onto the light-transmissive substrate. It can help to increase efficiency. In the case of forming the current spreading layer, the light extraction efficiency can be further improved by helping to spread the current in the horizontal direction.
이후 상기 반사층 또는 전류확산층상에 상기 제 2반도체층과의 컨택을 위한 제 2전극을 형성하는 단계를 거치게 되는데(s507), 먼저 반사층(또는 전류확산층)의 소정영역을 식각하여 제거한 후 제 2반도체층과 반사층(또는 전류확산층)으로 둘러쌓인 영역에 제 2전극을 형성하게 된다. 상기 제 2전극은 그 상면이 핑거(finger) 형태로 형성되어 각각의 단위셀을 연결할 수 있을 것이다. Thereafter, a step of forming a second electrode for contact with the second semiconductor layer on the reflective layer or the current diffusion layer is performed (s507). First, a predetermined region of the reflective layer (or current diffusion layer) is etched away and then the second semiconductor is removed. The second electrode is formed in an area surrounded by the layer and the reflective layer (or current diffusion layer). An upper surface of the second electrode may be formed in a finger shape to connect each unit cell.
이후, 상기 복수의 제 1전극 또는 제 2전극을 연결하는 메탈라인을 형성하는 단계(s508)를 거치면, 각각의 단위셀의 연결이 완료되게 된다. 이와 같은 과정을 지나면, 발광다이오드 패키지 형성을 위한 공정이 진행되게 된다. Subsequently, after forming the metal lines connecting the plurality of first electrodes or the second electrodes (S508), the connection of each unit cell is completed. After such a process, a process for forming a light emitting diode package is performed.
먼저 상기 제 1전극 및 메탈라인의 상부를 커버하고, 상기 제 2전극의 측면에 접하는 제 3보호막을 형성하는 단계(s509)를 거치게 된다. 제 3보호막은 제 1전극과 제 2전극의 단락을 방지하기 위함인데, 상기 제 1, 2보호막과 동일한 물질 또는 다른 물질로 형성하는 것이 가능하다. First, a step of forming a third passivation layer covering an upper portion of the first electrode and the metal line and contacting the side surface of the second electrode is performed (S509). The third passivation layer is to prevent a short circuit between the first electrode and the second electrode, and the third passivation layer may be formed of the same material as or different from the first and second passivation layers.
이후 메탈패드 형성을 위해서, 상기 제 3보호막의 소정영역을 제거하여 서로 이격되는 둘 이상의 홀(hole)을 형성하는 단계(s510)를 거치게 되는데, 이는 제 1메탈패드와 제 1전극의 컨택을 위함이다.Subsequently, in order to form the metal pad, a step (s510) of removing the predetermined region of the third passivation layer to form two or more holes spaced apart from each other is performed, for the contact between the first metal pad and the first electrode. to be.
상기 홀(hole)이 완성되면, 제 1전극과 컨택하는 제 1메탈패드를 형성하는 단계(s511)을 거치게 되는데, 상기 홀(hole)을 통해서, 전극 페이스트를 도포하고 경화시키면, 제 1전극과 컨택되는 제 1메탈패드를 형성할 수 있다. 필요에 따라서는 상기 홀(hole)에 제 1보호막을 추가로 형성한 후 제 1메탈패드를 형성하는 것도 가능하다. When the hole is completed, a step (s511) of forming a first metal pad in contact with the first electrode is performed. When the electrode paste is applied and cured through the hole, the first electrode and The first metal pad may be formed to be contacted. If necessary, it is also possible to form a first metal pad after additionally forming a first passivation layer in the hole.
이후 상기 제 2전극과 컨택되며, 상기 제 1메탈패드와 격리된 위치에 제 2메탈패드를 형성하는 단계(s511)를 거친 후, 상기 제 1메탈패드 및 제 2메탈패드가 형성되지 않은 제 3보호막상에 제 4보호막을 형성하는 단계(s512)를 거치면, 발광다이오드 패키지를 형성하기 위한 멀티셀 구조를 갖는 발광다이오드소자가 완성되게 된다. Thereafter, after contacting with the second electrode and forming a second metal pad at a position isolated from the first metal pad (S511), the third metal pad and the second metal pad are not formed. After the forming of the fourth passivation layer on the passivation layer (S512), the light emitting diode element having the multi-cell structure for forming the light emitting diode package is completed.
상기 제 1메탈패드 및 제 2메탈패드의 사이즈는 충분히 커도 관계가 없으므로, 소형 패키지는 물론 대형 패키지에도 용이하게 실장하여 패키지를 구성할 수 있는 장점이 있다. 또한, 패키지 실장을 위한 제 1메탈패드 및 제 2메탈패드를 동일면에 형성하므로 메사 식각 되어진 면에 형성되는 본딩 패드를 추가로 형성할 필요가 없는 장점이 있다. 또한, 대면적 칩(chip)의 경우 필요한 패드(pad) 숫자가 줄어들어 패드에 의한 광 흡수를 방지하여 발광다이오드 패키지의 광 출력이 향상되는 효과가 있다. Since the size of the first metal pad and the second metal pad is sufficiently large, there is an advantage in that the package can be easily mounted in a large package as well as a small package. In addition, since the first metal pad and the second metal pad for package mounting are formed on the same surface, there is no need to additionally form a bonding pad formed on the mesa-etched surface. In addition, in the case of a large area chip, the number of pads required is reduced to prevent light absorption by the pads, thereby improving the light output of the LED package.
이와 같이 본 발명에 의한 멀티셀 구조를 갖는 발광다이오드는, 각각의 단위셀 구조의 칩을 보호막 공정과 이를 연결하는 메탈라인 공정을 통하여 하나의 발광다이오드 멀티 셀로 구성될 수 있으므로, 칩 사이즈에 유연성을 가질 수 있고, 생산성 향상 및 제조비용의 절감을 가져올 수 있다. 이에 부대하여 다수의 단위셀 사이의 구간에 반사메탈을 형성하여 광추출 효율을 향상 시킬 수 있으며, 제 2 반도체층과 컨택되는 제 2전극의 사이즈와 위치를 임의로 정할 수 있으므로 발광다이오드 형태의 유연성을 가져올 수 있는 장점이 있다.As described above, the light emitting diode having the multi-cell structure according to the present invention can be configured as a single light-emitting diode multi-cell through a metal line process connecting the chip of each unit cell structure to the protective film process, thereby providing flexibility in chip size. It can have a productivity improvement and a reduction of manufacturing cost. In addition, it is possible to improve the light extraction efficiency by forming a reflective metal in the section between the plurality of unit cells, and the size and position of the second electrode contacting the second semiconductor layer can be arbitrarily determined, thereby providing flexibility in the shape of the light emitting diode. There is an advantage that can be brought.
이상 본 발명의 구체적 실시형태와 관련하여 본 발명을 설명하였으나 이는 예시에 불과하며 본 발명은 이에 제한되지 않는다. 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자는 본 발명의 범위를 벗어나지 않고 설명된 실시형태를 변경 또는 변형할 수 있으며, 본 발명의 기술사상과 아래에 기재될 특허청구범위의 균등범위 내에서 다양한 수정 및 변형이 가능하다.The present invention has been described above in connection with specific embodiments of the present invention, but this is only an example and the present invention is not limited thereto. Those skilled in the art can change or modify the described embodiments without departing from the scope of the present invention, and within the equivalent scope of the technical spirit of the present invention and the claims to be described below. Various modifications and variations are possible.
<부호의 설명><Description of the code>
110, 291: 제 2전극110, 291: second electrode
120, 270: 제 1전극120, 270: first electrode
130, 310: 단위셀 130, 310: unit cell
140, 320: 제 1전극의 메탈라인 140 and 320: metal lines of the first electrode
150, 330: 제 2전극의 메탈라인150 and 330: metal line of the second electrode
210: 투광성 기판210: light transmissive substrate
220: 제 1반도체층220: first semiconductor layer
230: 활성층230: active layer
240: 제 2반도체층240: second semiconductor layer
250: 홀(hole)250: hole
260: 제 1보호막260: first protective film
280: 제 2보호막280: second protective film
290: 반사층 또는 전류확산층290: reflective layer or current diffusion layer
291: 제 2전극291: second electrode
292: 제 3보호막292: Third Shield
293: 제 4보호막293: Fourth Shield
340: 제 1메탈패드340: first metal pad
350: 제 2메탈패드350: second metal pad

Claims (11)

  1. 투광성 기판(Substrate);Translucent substrate;
    상기 투광성 기판상에 순차적으로 형성되는 제 1반도체층, 활성층 및 제 2반도체층;A first semiconductor layer, an active layer, and a second semiconductor layer sequentially formed on the light transmissive substrate;
    상기 제 2반도체층 및 활성층의 일부영역이 제거되어 서로 이격되어 형성되는 복수의 홀(hole);A plurality of holes formed to be spaced apart from each other by removing a portion of the second semiconductor layer and the active layer;
    상기 복수의 홀(hole) 중 일부의 홀(hole)을 통해 상기 제 1반도체층과 컨택(contact)되며, 그 상면이 외부로 노출되도록 형성되는 제 1전극;A first electrode contacting the first semiconductor layer through a portion of the plurality of holes and contacting the first semiconductor layer to expose the upper surface to the outside;
    상기 제 1전극의 측면 둘레를 감싸서 상기 제 1반도체층과 제 2반도체층의 쇼트(short)를 방지하는 제 1보호막;A first passivation layer surrounding a side circumference of the first electrode to prevent a short between the first semiconductor layer and the second semiconductor layer;
    상기 복수의 홀(hole) 중 상기 제 1전극이 형성되지 아니한 홀의 측면 및 하부면에 형성되는 제 2보호막;A second passivation layer formed on side and bottom surfaces of the hole in which the first electrode is not formed among the plurality of holes;
    상기 제 2보호막 및 상기 제 2반도체층 상에 형성되는 반사층 또는 전류확산층; 및 상기 반사층 또는 전류확산층상에 형성되는 제 2전극;A reflection layer or a current diffusion layer formed on the second passivation layer and the second semiconductor layer; And a second electrode formed on the reflective layer or the current spreading layer.
    을 구비하는 단위셀을 포함하는 것을 특징으로 하는 멀티셀(Muti-Cell) 구조를 갖는 발광다이오드. A light emitting diode having a multi-cell structure, comprising a unit cell having a multi-cell structure.
  2. 제 1항에 있어서, The method of claim 1,
    상기 단위셀을 다수 구비하되, It is provided with a plurality of unit cells,
    상기 다수의 단위셀은 메탈라인의 형태로 형성되는 제 1전극 및 제 2전극에 의해 연결되는 것을 특징으로 하는 멀티셀(Muti-Cell) 구조를 갖는 발광다이오드. The plurality of unit cells are light emitting diodes having a multi-cell structure, characterized in that connected by the first electrode and the second electrode formed in the form of a metal line.
  3. 제 2항에 있어서, The method of claim 2,
    상기 제 1전극 및 메탈라인의 상부를 커버하고, 상기 제 2전극의 측면과 접하도록 형성되며 제 1전극과 제 2전극의 쇼트(short)를 방지하는 제 3보호막;A third passivation layer covering an upper portion of the first electrode and the metal line and being in contact with a side surface of the second electrode and preventing a short between the first electrode and the second electrode;
    상기 제 2보호막의 소정영역이 제거된 홀(hole)을 통해 상기 제 1전극과 컨택되는 제 1메탈패드; 및A first metal pad contacting the first electrode through a hole from which a predetermined region of the second passivation layer is removed; And
    상기 제 2전극과 컨택되며, 상기 제 1메탈패드와 이격되어 형성되는 제 2메탈패드; A second metal pad contacted with the second electrode and spaced apart from the first metal pad;
    를 더 구비하는 것을 특징으로 하는 멀티셀(Muti-Cell) 구조를 갖는 발광다이오드. The light emitting diode having a multi-cell (Muti-Cell) structure characterized in that it further comprises.
  4. 제 3항에 있어서, The method of claim 3, wherein
    상기 제 3보호막 상의 상기 제 1메탈패드와 제 2메탈패드가 형성되지 않은 영역에 형성되고, 상기 제 1메탈패드 및 제 2메탈패드의 쇼트(short)를 방지하는 제 4보호막을 더 구비하는 것을 특징으로 하는 멀티셀(Muti-Cell) 구조를 갖는 발광다이오드. And a fourth passivation layer formed on an area where the first metal pad and the second metal pad are not formed on the third passivation layer and preventing a short between the first metal pad and the second metal pad. A light emitting diode having a multi-cell structure.
  5. 제 1항 내지 제 4항 중 어느 한 항에 있어서, 상기 제 1보호막, 제 2보호막, 제 3보호막 또는 제 4보호막은, The method according to any one of claims 1 to 4, wherein the first protective film, the second protective film, the third protective film or the fourth protective film,
    SiO2, Si3N4, 레진(Resin)수지 또는 SOG(Spin on Glass) 중에서 선택되는 어느 하나의 물질로 형성되는 것을 특징으로 하는 멀티셀(Muti-Cell) 구조를 갖는 발광다이오드. Light emitting diode having a multi-cell structure, characterized in that formed of any one material selected from SiO 2 , Si 3 N 4 , resin (Resin) resin or SOG (Spin on Glass).
  6. 제 1항 내지 제 4항 중 어느 한 항에 있어서, 상기 반사층은, The method according to any one of claims 1 to 4, wherein the reflective layer,
    은(Ag), 니켈(Ni), 알루미늄(Al), 티타늄(Ti), 팔라듐(Pd), 백금(Pt), 루테늄(Ru), 금(Au), 로듐(Rh), 이리듐(Ir), 인듐주석산화물(ITO), 인듐아연산화물(IZO), 인듐 산화물, 주석산화물, 실리콘 옥사이드(SiO₂), 실리콘 나이트라이드(Si₃N₄), 알루미늄 산화물, 티타늄 산화물 중에서 선택되는 어느 하나 이상의 물질로 형성되는 것을 특징으로 하는 멀티셀(Muti-Cell) 구조를 갖는 발광다이오드. Silver (Ag), nickel (Ni), aluminum (Al), titanium (Ti), palladium (Pd), platinum (Pt), ruthenium (Ru), gold (Au), rhodium (Rh), iridium (Ir), Indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide, tin oxide, silicon oxide (SiO₂), silicon nitride (Si₃N₄), formed of any one or more materials selected from oxides of aluminum, titanium oxide A light emitting diode having a multi-cell structure.
  7. 제 1항 내지 제 4항 중 어느 한 항에 있어서, 상기 전류확산층은, The method of claim 1, wherein the current diffusion layer,
    인듐주석산화물(ITO), 산화아연(ZnO), Ni/Au 중에서 선택되는 어느 하나의 물질로 형성되는 것을 특징으로 하는 멀티셀(Muti-Cell) 구조를 갖는 발광다이오드. A light emitting diode having a multi-cell structure, which is formed of any one selected from indium tin oxide (ITO), zinc oxide (ZnO), and Ni / Au.
  8. 투광성 기판 상에 제 1반도체층, 활성층 및 제 2반도체층을 순차적으로 형성하는 단계;Sequentially forming a first semiconductor layer, an active layer, and a second semiconductor layer on the light transmissive substrate;
    상기 제 2반도체층상의 소정거리로 이격된 영역마다 패터닝 후 식각하여 제 1반도체층의 상면이 노출되도록 상기 제 2반도체층 및 활성층을 제거하여 복수의 홀(hole)을 형성하는 단계;Forming a plurality of holes by removing the second semiconductor layer and the active layer so that the top surface of the first semiconductor layer is exposed by etching after patterning each region spaced by a predetermined distance on the second semiconductor layer;
    상기 복수의 홀(hole) 중 일부의 홀(hole)의 측면부에 제 1보호막을 형성하는 단계;Forming a first passivation layer on side surfaces of some of the holes;
    상기 제 1보호막이 형성된 홀(hole)을 통해 제 1반도체층과 컨택(contact)되며, 그 상면이 외부로 노출되도록 형성되는 제 1전극을 형성하는 단계;Forming a first electrode contacted with the first semiconductor layer through a hole in which the first passivation layer is formed, the upper electrode being exposed to the outside;
    상기 제 1전극이 형성되지 아니한 홀(hole)의 측면과 하부면에 제 2보호막을 형성하는 단계;Forming a second passivation layer on side and bottom surfaces of the hole in which the first electrode is not formed;
    상기 제 2보호막이 형성된 홀(hole)과 상기 제 2반도체층상에 반사층 또는 전류확산층을 형성하는 단계; 및Forming a reflective layer or a current spreading layer on the hole where the second passivation layer is formed and on the second semiconductor layer; And
    상기 반사층 또는 전류확산층상에 상기 제 2반도체층과의 컨택을 위한 제 2전극을 형성하는 단계;Forming a second electrode on the reflective layer or the current spreading layer for contact with the second semiconductor layer;
    를 포함하는 멀티셀(Muti-Cell) 구조를 갖는 발광다이오드의 제조방법. Method of manufacturing a light emitting diode having a multi-cell (Muti-Cell) structure comprising a.
  9. 제 8항에 있어서, 상기 제 2전극 형성단계 후에, The method of claim 8, wherein after forming the second electrode,
    상기 제 1전극 및 제 2전극을 각각 메탈라인의 형태로 형성하여 각각의 단위셀을 연결하는 단계를 더 구비하는 것을 특징으로 하는 멀티셀(Muti-Cell) 구조를 갖는 발광다이오드의 제조방법. The method of manufacturing a light emitting diode having a multi-cell structure, characterized in that the step of forming the first electrode and the second electrode in the form of a metal line, respectively, and connecting each unit cell.
  10. 제 9항에 있어서, 상기 메탈라인 형성단계 후에,The method of claim 9, after the metal line forming step,
    상기 제 1전극 및 메탈라인의 상부를 커버하고, 상기 제 2전극의 측면에 접하는 제 3 보호막을 형성하는 단계;Forming a third passivation layer covering an upper portion of the first electrode and the metal line and in contact with a side surface of the second electrode;
    상기 제 3보호막의 소정영역을 제거하여 서로 이격되는 복수의 홀(hole)을 형성하는 단계;Removing a predetermined region of the third passivation layer to form a plurality of holes spaced apart from each other;
    상기 홀(hole)을 통해 제 1전극과 컨택하는 제 1메탈패드를 형성하는 단계; 및 Forming a first metal pad contacting a first electrode through the hole; And
    상기 제 2전극과 컨택되며, 상기 제 1메탈패드와 격리된 위치에 제 2메탈패드를 형성하는 단계;Forming a second metal pad in contact with the second electrode and separated from the first metal pad;
    를 더 구비하는 것을 특징으로 하는 멀티셀(Muti-Cell) 구조를 갖는 발광다이오드의 제조방법. Method of manufacturing a light emitting diode having a multi-cell (Muti-Cell) structure characterized in that it further comprises.
  11. 제 10항에 있어서, 상기 제 2메탈패드 형성단계 후에,The method of claim 10, wherein after forming the second metal pad,
    상기 제 1메탈패드 및 제 2메탈패드가 형성되지 않은 제 3보호막상에 제 4보호막을 형성하는 단계를 더 구비하는 것을 특징으로 하는 멀티셀(Muti-Cell) 구조를 갖는 발광다이오드의 제조방법. And forming a fourth passivation layer on a third passivation layer on which the first metal pad and the second metal pad are not formed.
PCT/KR2010/007668 2010-08-16 2010-11-02 Light emitting diode having multi-cell structure and manufacturing method thereof WO2012023662A1 (en)

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