WO2012004927A1 - Rectifier circuit device - Google Patents

Rectifier circuit device Download PDF

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Publication number
WO2012004927A1
WO2012004927A1 PCT/JP2011/002996 JP2011002996W WO2012004927A1 WO 2012004927 A1 WO2012004927 A1 WO 2012004927A1 JP 2011002996 W JP2011002996 W JP 2011002996W WO 2012004927 A1 WO2012004927 A1 WO 2012004927A1
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WO
WIPO (PCT)
Prior art keywords
voltage
chopping
phase
period
waveform
Prior art date
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PCT/JP2011/002996
Other languages
French (fr)
Japanese (ja)
Inventor
吉田　泉
吉朗 土山
京極　章弘
シンホイ 戴
川崎　智広
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to JP2012523508A priority Critical patent/JP5830691B2/en
Priority to KR1020137003271A priority patent/KR20130031379A/en
Priority to BR112013000139A priority patent/BR112013000139A2/en
Priority to CN201180033930.1A priority patent/CN103004075B/en
Publication of WO2012004927A1 publication Critical patent/WO2012004927A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a rectifier circuit device and a control circuit for the rectifier circuit device, and in particular, a circuit device for driving a DC load by rectifying a single-phase AC power source such as a home to make it a direct current, and the obtained direct current
  • This is a device that is applied to a device that performs high-efficiency drive control with technology that reduces the burden on the power transmission system by reducing harmonic components contained in the power supply current and improving the power factor.
  • the present invention relates to a rectifier circuit device and a control circuit for the rectifier circuit device.
  • FIG. 20 is a circuit diagram showing a configuration of a rectifier circuit device according to the prior art disclosed in Patent Document 1
  • FIG. 21 is a block diagram showing a detailed configuration of the control unit 13 of FIG.
  • both output terminals of the AC power supply 1 are short-circuited by a semiconductor switch 3c via a rectifier bridge 2 and a reactor 3a, and the reactor 3a is charged with current.
  • the switch 3c is turned off, a current is supplied to the load 4 by the diode 3b so that the power supply current flows even when the instantaneous voltage of the AC power supply 1 is low.
  • the harmonic component of the power supply current is reduced and the power factor is improved.
  • the semiconductor switch 3c is finely turned on / off at a frequency sufficiently higher than the frequency of the AC power supply 1, thereby chopping the AC voltage of the AC power supply 1 (hereinafter, “the semiconductor switch is chopped”) or (Referred to as “chopping by a semiconductor switch”), a current flows through the semiconductor switch 3c, causing a problem of circuit loss.
  • the power is supplied to the smoothing capacitor 3d and the load 4 via the reactor 3a and the diode 3b.
  • the output voltage from the rectifier bridge 2 can be short-circuited by the semiconductor switch 3c via the reactor 3a, thereby forming a rectifier circuit device having a power factor improving function by a known boost chopper circuit 3.
  • the boost chopper circuit 3 detects the input current with the input current detector 6 and the input current detector 10, and the input current has the same shape as the input voltage waveform (power supply voltage waveform) detected by the input voltage detector 11.
  • the semiconductor switch 3c is chopped and the magnitude of the input current is adjusted so that the output voltage becomes a desired voltage.
  • Patent Document 1 proposes a contrivance for reducing the circuit loss by causing the semiconductor switch to perform a chopping operation only in a minimum interval for reducing harmonics.
  • FIG. 21 shows a control method for that purpose.
  • the phase of the power supply voltage is detected by the power supply zero-cross detection means 5, and the chopping operation of the semiconductor switch 3c of FIG. 20 is permitted only for a certain period by the pulse counter 13a, and in the other periods, the semiconductor switch 3c Holds to be off.
  • a low-loss rectifier circuit device can be realized with almost no increase in power supply harmonics.
  • Patent Document 1 requires a waveform of the power supply voltage
  • Patent Document 2 a method for realizing the same operation with a predetermined waveform without using the waveform of the power supply voltage has been proposed (for example, Patent Document 2). reference).
  • Patent Document 3 a simple method that aims at the same effect without having a target current waveform has been proposed (see, for example, Patent Document 3).
  • the input current is substituted with the current after rectification.
  • the absolute value of the input current is obtained and the magnitude of the absolute value is adjusted. It is well known that it is equivalent to adjusting the amplitude of the current.
  • the output voltage is controlled to be constant under the condition where the load is determined, and the period during which the semiconductor switch is chopped is also fixed. For this reason, if there is an error in the detected output voltage, the current waveform changes.
  • the current waveform changes greatly only by changing the direct current voltage by 1V.
  • An accuracy of 1V with respect to a DC voltage of 280V corresponds to 0.3%, and a resistor with very high accuracy is required when the voltage is divided by a resistor to make it a low voltage. For this reason, in consideration of the detection accuracy of the output voltage, it is necessary to set a longer chopping period and to slightly increase the circuit loss so that the harmonics are reduced even in the changed current waveform. Have.
  • Such a control method is generally realized by using a digital computer.
  • the DC voltage is converted into a high resolution, that is, an analog-to-digital conversion (hereinafter referred to as a high bit number). "AD conversion”) is required, which increases the circuit load.
  • AD conversion analog-to-digital conversion
  • the lower the output voltage the smaller the loss.
  • the AC voltage during the period of chopping the semiconductor switch is used. Even if the output voltage is lower than the output voltage, a phenomenon occurs in which the output voltage rises due to the boost operation during the chopping operation of the semiconductor switch, and therefore it is difficult to set a lower output voltage with less loss. Also have.
  • the power supply harmonics generated depending on whether or not the input current has pulsation depending on the electrical characteristics of the connected load are greatly different, and a preset semiconductor
  • control is performed during the chopping period of the switch, switching is performed even in a low power region where the current amplitude is relatively small and the harmonic current is very small, which does not adversely affect peripheral devices and the power supply system.
  • loss as an integrated value increases.
  • the object of the present invention is to solve the above-mentioned problems, the rectifier circuit device capable of reducing the power supply harmonic current and reducing the loss according to the characteristics of the connected load, regardless of the detection accuracy of the output voltage, and the aforementioned It is to provide a control circuit for a rectifier circuit device.
  • the rectifier circuit device is: By chopping the semiconductor switch, the output terminal of the single-phase AC power supply is short-circuited or opened via the reactor, and the AC voltage supplied from the single-phase AC power supply via the reactor is rectified into a DC voltage and loaded.
  • a rectifier circuit device for supplying to Waveform forming means for forming a target current waveform having the same frequency as the waveform of the AC voltage;
  • Current detecting means for detecting an alternating current flowing from the single-phase AC power source;
  • Voltage detecting means for detecting the DC voltage;
  • First control means for controlling the chopping operation of the semiconductor switch so that the waveform of the detected alternating current substantially becomes the target current waveform;
  • Second control means for controlling the amplitude of the target current waveform such that the detected DC voltage is substantially a predetermined target DC voltage;
  • the predetermined target DC voltage is controlled so that a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state is substantially a predetermined phase width.
  • third control means for supplying to Waveform forming means for forming a target current waveform having the same frequency as the waveform of the AC voltage;
  • Current detecting means for detecting an
  • the predetermined phase width is set by being changed depending on an electrical characteristic of the load.
  • the electrical characteristic of the load is a fluctuation range of the alternating current or a rotational speed command to a compressor motor when the load is a compressor.
  • the third control means has a plurality of the chopping operation phase widths or a plurality of the chopping pause phase widths within a period in which the polarity of the AC voltage is fixed.
  • the predetermined target DC voltage is controlled such that any one of the phase widths within the period or the total phase width is substantially the predetermined phase width.
  • the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
  • A From the starting point of the period to the predetermined intermediate point, it increases at least over time, or at least increases and increases substantially at least monotonously so as to be constant over a period of time,
  • B A period from the intermediate point to the end point that has at least decreased with time, or at least decreased and substantially monotonically decreased to be constant in a certain period, and then has a period that becomes zero. It is characterized by being set.
  • the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
  • A From the starting point of the period to the predetermined first intermediate point, there is a period that becomes zero with time, (B) from the first intermediate point to the predetermined second intermediate point at least increases or at least increases and substantially monotonically increases to be constant over a period of time; (C) from the second intermediate point to the end point, a time period that is at least decreased with time, or at least decreased and substantially monotonically decreased so as to be constant in a certain period, and then becomes zero. It is set to have.
  • the rectifier circuit device further includes phase detection means for generating a binary signal by comparing the AC voltage with a predetermined threshold voltage,
  • the waveform forming means detects a period and a phase of the AC voltage based on the binary signal, and a target current waveform having the same frequency as the waveform of the AC voltage based on the detected period and phase of the AC voltage.
  • the third control means detects, based on the binary signal, a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state.
  • the rectifier circuit device further includes AD conversion means provided between the voltage detection means and the second control means, and AD-converts the detected DC voltage into a digital voltage; Provided between the AD conversion means and the second control means, and after performing a low-pass filter operation on the digital voltage, the voltage of the calculation result is detected by the second control means And an arithmetic means for outputting as a DC voltage.
  • the sampling frequency of the AD conversion means is set to be sufficiently higher than the frequency of the single-phase AC power supply.
  • the low-pass filter operation may be performed by multiplying the immediately preceding operation result by a coefficient “(2 n ⁇ 1) / (2 n )” (n is an integer), It is characterized by being added to the digital voltage thus obtained and executed using the value of the addition result as the next calculation result.
  • a control circuit for a rectifier circuit device short-circuits or opens an output terminal of a single-phase AC power source through a reactor by chopping a semiconductor switch, and the reactor is connected to the reactor from the single-phase AC power source.
  • the control circuit is Waveform forming means for forming a target current waveform having the same frequency as the waveform of the AC voltage; First control means for controlling a chopping operation of the semiconductor switch so that a waveform of an alternating current flowing from the single-phase alternating current power supply substantially becomes the target current waveform; Second control means for controlling the amplitude of the target current waveform so that the DC voltage substantially becomes a predetermined target DC voltage; The predetermined target DC voltage is controlled so that a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state is substantially a predetermined phase width. And third control means.
  • the control circuit is characterized in that the predetermined phase width is changed and set depending on electrical characteristics of the load.
  • the electrical characteristic of the load is a fluctuation range of the alternating current or a rotational speed command to a compressor motor when the load is a compressor.
  • the third control unit may be configured such that when there are a plurality of the chopping operation phase widths or a plurality of the chopping pause phase widths in a period in which the polarity of the AC voltage is fixed.
  • the predetermined target DC voltage is controlled so that any one of the phase widths within the period or the total phase width becomes substantially the predetermined phase width.
  • the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
  • A From the starting point of the period to the predetermined intermediate point, it increases at least over time, or at least increases and increases substantially at least monotonously so as to be constant over a period of time,
  • B A period from the intermediate point to the end point that has at least decreased with time, or at least decreased and substantially monotonically decreased to be constant in a certain period, and then has a period that becomes zero. It is characterized by being set.
  • the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
  • A From the starting point of the period to the predetermined first intermediate point, there is a period that becomes zero with time, (B) from the first intermediate point to the predetermined second intermediate point at least increases or at least increases and substantially monotonically increases to be constant over a period of time; (C) from the second intermediate point to the end point, a time period that is at least decreased with time, or at least decreased and substantially monotonically decreased so as to be constant in a certain period, and then becomes zero. It is set to have.
  • the rectifier circuit device further includes phase detection means for generating a binary signal by comparing the AC voltage with a predetermined threshold voltage,
  • the waveform forming means detects a period and a phase of the AC voltage based on the binary signal, and a target current waveform having the same frequency as the waveform of the AC voltage based on the detected period and phase of the AC voltage.
  • the third control means detects, based on the binary signal, a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state.
  • control circuit further includes AD conversion means provided between the voltage detection means and the second control means, and AD-converts the DC voltage into a digital voltage; Provided between the AD conversion means and the second control means, and after performing a low-pass filter operation on the digital voltage, the voltage of the calculation result is sent to the second control means as the DC voltage. And an arithmetic means for outputting.
  • the sampling frequency of the AD converter is set to be sufficiently higher than the frequency of the single-phase AC power supply.
  • the low-pass filter operation is input after the previous operation result is multiplied by a coefficient (n is an integer) of “(2 n ⁇ 1) / (2 n )”. It is added to the digital voltage, and the value of the addition result is used as the next calculation result.
  • the DC voltage is adjusted to a relatively appropriate value to obtain a similar current waveform, and a desired current according to the characteristics of the load.
  • a DC voltage is converted into a digital signal by an AD conversion means at a sampling frequency sufficiently higher than the frequency of the AC power supply, and the obtained digital signal is subjected to LPF calculation for each period, and digitally Interpolate minute information below resolution to interpolate minute information so that the digital signal interpolated with minute information is DC voltage information so that the phase width that is actually chopped is the desired value Adjust the digital signal. Even if there is fluctuations in the power supply frequency component included in the smoothing voltage of the DC voltage and the resolution of the digital information is rough, the digital signal is dispersed due to fluctuations, so a digital signal equivalent to a high resolution is obtained on average. be able to.
  • the rectifier circuit device can always realize a rectification operation with little loss and less harmonic current even when the input current pulsates due to the characteristics of the connected load.
  • FIG. 2 is a block diagram illustrating a detailed configuration of a control circuit 100 in FIG. 1. It is a figure for demonstrating the control action which concerns on the 1st operation example of the control circuit 100 of FIG. 1, Comprising: AC voltage (henceforth AC voltage) and the DC voltage after rectification (henceforth DC voltage) And a target current waveform to be controlled, and an AC current after actual control (hereinafter referred to as AC current). It is a figure for demonstrating the control operation
  • FIG. 9 is a diagram for explaining a first operation example of binarization processing of the voltage level comparator 109 of the rectifier circuit device according to the first to tenth embodiments of the present invention, and the relationship between the AC voltage and the threshold voltage Vth. And a signal waveform diagram showing a binary signal from the voltage level comparator 109.
  • FIG. FIG. 9 is a diagram for explaining a first operation example of binarization processing of the voltage level comparator 109 of the rectifier circuit device according to the first to tenth embodiments of the present invention, and the relationship between the AC voltage and the threshold voltage Vth.
  • a signal waveform diagram showing a binary signal from the voltage level comparator 109.
  • FIG. 10 is a diagram for explaining a second operation example of the binarization process of the voltage level comparator 109 of the rectifier circuit device according to Embodiments 1 to 10 of the present invention, and the relationship between the AC voltage and the threshold voltage Vth. And a signal waveform diagram showing a binary signal from the voltage level comparator 109.
  • FIG. It is a block diagram which shows the detailed structure of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 11 of this invention.
  • FIG. 18 is a block diagram showing a detailed configuration of a low-pass filter computing unit (hereinafter referred to as “LPF computing unit”) 231 in FIG. 17.
  • LPF computing unit low-pass filter computing unit
  • FIG. 17 is a circuit diagram which shows the structure of the rectifier circuit apparatus based on a prior art. It is a block diagram which shows the detailed structure of the control part 13 of FIG.
  • a rectifier circuit device includes: By chopping the semiconductor switch, the output terminal of the single-phase AC power supply is short-circuited or opened via the reactor, and the AC voltage supplied from the single-phase AC power supply via the reactor is rectified into a DC voltage and loaded.
  • a rectifier circuit device for supplying to Waveform forming means for forming a target current waveform having the same frequency as the waveform of the AC voltage;
  • Current detecting means for detecting an alternating current flowing from the single-phase AC power source;
  • Voltage detecting means for detecting the DC voltage;
  • First control means for controlling the chopping operation of the semiconductor switch so that the waveform of the detected alternating current substantially becomes the target current waveform;
  • Second control means for controlling the amplitude of the target current waveform such that the detected DC voltage is substantially a predetermined target DC voltage;
  • the predetermined target DC voltage is controlled so that a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state is substantially a predetermined phase width.
  • third control means for supplying to Waveform forming means for forming a target current waveform having the same frequency as the waveform of the AC voltage;
  • Current detecting means for detecting an
  • the predetermined phase width is set by being changed depending on an electrical characteristic of the load.
  • the electrical characteristic of the load is a fluctuation range of the alternating current or a rotational speed command to a compressor motor when the load is a compressor.
  • the third control means has a plurality of the chopping operation phase widths or a plurality of the chopping pause phase widths within a period in which the polarity of the AC voltage is fixed.
  • the predetermined target DC voltage is controlled such that any one of the phase widths within the period or the total phase width is substantially the predetermined phase width.
  • the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
  • A From the starting point of the period to the predetermined intermediate point, it increases at least over time, or at least increases and increases substantially at least monotonously so as to be constant over a period of time,
  • B A period from the intermediate point to the end point that has at least decreased with time, or at least decreased and substantially monotonically decreased to be constant in a certain period, and then has a period that becomes zero. It is characterized by being set.
  • the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
  • A From the starting point of the period to the predetermined first intermediate point, there is a period that becomes zero with time, (B) from the first intermediate point to the predetermined second intermediate point at least increases or at least increases and substantially monotonically increases to be constant over a period of time; (C) from the second intermediate point to the end point, a time period that is at least decreased with time, or at least decreased and substantially monotonically decreased so as to be constant in a certain period, and then becomes zero. It is set to have.
  • the rectifier circuit device further includes phase detection means for generating a binary signal by comparing the AC voltage with a predetermined threshold voltage,
  • the waveform forming means detects a period and a phase of the AC voltage based on the binary signal, and a target current waveform having the same frequency as the waveform of the AC voltage based on the detected period and phase of the AC voltage.
  • the third control means detects, based on the binary signal, a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state.
  • the rectifier circuit device further includes AD conversion means provided between the voltage detection means and the second control means, and AD-converts the detected DC voltage into a digital voltage; Provided between the AD conversion means and the second control means, and after performing a low-pass filter operation on the digital voltage, the voltage of the calculation result is detected by the second control means And an arithmetic means for outputting as a DC voltage.
  • the sampling frequency of the AD conversion means is set to be sufficiently higher than the frequency of the single-phase AC power supply.
  • the low-pass filter operation may be performed by multiplying the immediately preceding operation result by a coefficient “(2 n ⁇ 1) / (2 n )” (n is an integer), It is characterized by being added to the digital voltage thus obtained and executed using the value of the addition result as the next calculation result.
  • control circuit for the rectifier circuit device short-circuits or opens the output terminal of the single-phase AC power source through the reactor by chopping the semiconductor switch, and the single-phase AC
  • the control circuit is Waveform forming means for forming a target current waveform having the same frequency as the waveform of the AC voltage; First control means for controlling a chopping operation of the semiconductor switch so that a waveform of an alternating current flowing from the single-phase alternating current power supply substantially becomes the target current waveform; Second control means for controlling the amplitude of the target current waveform so that the DC voltage substantially becomes a predetermined target DC voltage;
  • the predetermined target DC voltage is controlled so that a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping
  • the control circuit is characterized in that the predetermined phase width is changed and set depending on electrical characteristics of the load.
  • the electrical characteristic of the load is a fluctuation range of the alternating current or a rotational speed command to a compressor motor when the load is a compressor.
  • the third control unit may be configured such that when there are a plurality of the chopping operation phase widths or a plurality of the chopping pause phase widths in a period in which the polarity of the AC voltage is fixed.
  • the predetermined target DC voltage is controlled so that any one of the phase widths within the period or the total phase width becomes substantially the predetermined phase width.
  • the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
  • A From the starting point of the period to the predetermined intermediate point, it increases at least over time, or at least increases and increases substantially at least monotonously so as to be constant over a period of time,
  • B A period from the intermediate point to the end point that has at least decreased with time, or at least decreased and substantially monotonically decreased to be constant in a certain period, and then has a period that becomes zero. It is characterized by being set.
  • the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
  • A From the starting point of the period to the predetermined first intermediate point, there is a period that becomes zero with time, (B) from the first intermediate point to the predetermined second intermediate point at least increases or at least increases and substantially monotonically increases to be constant over a period of time; (C) from the second intermediate point to the end point, a time period that is at least decreased with time, or at least decreased and substantially monotonically decreased so as to be constant in a certain period, and then becomes zero. It is set to have.
  • the rectifier circuit device further includes phase detection means for generating a binary signal by comparing the AC voltage with a predetermined threshold voltage,
  • the waveform forming means detects a period and a phase of the AC voltage based on the binary signal, and a target current waveform having the same frequency as the waveform of the AC voltage based on the detected period and phase of the AC voltage.
  • the third control means detects, based on the binary signal, a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state.
  • control circuit further includes AD conversion means provided between the voltage detection means and the second control means, and AD-converts the DC voltage into a digital voltage; Provided between the AD conversion means and the second control means, and after performing a low-pass filter operation on the digital voltage, the voltage of the calculation result is sent to the second control means as the DC voltage. And an arithmetic means for outputting.
  • the sampling frequency of the AD converter is set to be sufficiently higher than the frequency of the single-phase AC power supply.
  • the low-pass filter operation is input after the previous operation result is multiplied by a coefficient (n is an integer) of “(2 n ⁇ 1) / (2 n )”. It is added to the digital voltage, and the value of the addition result is used as the next calculation result.
  • the DC voltage is adjusted to a relatively appropriate value to obtain a similar current waveform and according to the characteristics of the load.
  • a rectification operation with always low loss and low harmonic current is realized.
  • a DC voltage is converted into a digital signal by an AD conversion means at a sampling frequency sufficiently higher than the frequency of the AC power supply, and the obtained digital signal is subjected to LPF calculation for each period, and digitally Interpolate minute information below resolution to interpolate minute information so that the digital signal interpolated with minute information is DC voltage information so that the phase width that is actually chopped is the desired value Adjust the digital signal. Even if there is fluctuations in the power supply frequency component included in the smoothing voltage of the DC voltage and the resolution of the digital information is rough, the digital signal is dispersed due to fluctuations, so a digital signal equivalent to a high resolution is obtained on average. be able to.
  • the rectifier circuit device can always realize a rectification operation with little loss and less harmonic current even when the input current pulsates due to the characteristics of the connected load.
  • FIG. FIG. 1 is a circuit diagram showing a configuration of a rectifier circuit device according to Embodiment 1 of the present invention.
  • a single loop is formed by short-circuiting both output terminals of the single-phase AC power supply 1 by the semiconductor switch 104 via the reactor 102.
  • the current detector 103 detects the current of the loop and outputs a signal indicating the detected current value Iac to the control circuit 100.
  • the semiconductor switch 104 When the semiconductor switch 104 is turned on, the current in the reactor 102 increases.
  • the semiconductor switch 104 when the semiconductor switch 104 is turned off, the current flowing through the reactor 102 is rectified by the diode bridge 105, and the rectified current is It flows into the load 4 and drives the load 4.
  • the DC voltage Vdc across the smoothing capacitor 106 applied to the load 4 is detected by the DC voltage detector 110, and the DC voltage detector 110 outputs a signal indicating the detected DC voltage Vdc to the control circuit 100.
  • the voltage level comparator 109 compares the AC voltage level of the AC power supply 1 with a predetermined threshold voltage to generate a binary signal Scom indicating whether or not the threshold voltage is higher than the threshold voltage. Output to 100. Based on the binary signal Scom, the control circuit 100 detects the phase of the AC voltage output from the AC power supply 1 based on the cycle and phase, and determines the AC voltage based on the detected phase of the AC voltage.
  • the semiconductor switch 104 generates a target current waveform having a shape that is substantially the same frequency and similar to the AC voltage, and the Iac detected by the current detector 103 approaches the similar shape of the generated target current waveform. It is characterized in that it is controlled to perform a chopping operation.
  • control circuit 100 resembles the target current waveform to be generated according to the deviation so that the DC voltage Vdc detected by the DC voltage detector 110 becomes a desired voltage set in the control circuit 100. Adjust the ratio.
  • the control circuit 100 increases the similarity ratio of the target current command so as to obtain a large current, and the actual DC voltage is higher than the desired DC voltage. If it is higher, control is performed so that a small current is obtained.
  • the control circuit 100 detects the phase width that drives the semiconductor switch 104 by pulse width modulation (hereinafter referred to as “PWM”) based on the chopping state of the semiconductor switch 104, and the phase width and a desired value are detected. And the desired DC voltage value is adjusted according to the deviation.
  • PWM pulse width modulation
  • FIG. 2 is a block diagram showing a detailed configuration of the control circuit 100 of FIG.
  • the final control target of the control system is to control the chopping operation phase width ⁇ w ON in which chopping driving is performed to a desired phase width ⁇ w ON * .
  • the AC voltage phase detector 201 detects the AC phase based on the binary signal Scom binarized by comparing the voltage level of the AC power source 1 with a predetermined threshold voltage Vth, and detects the detected AC A signal indicating the phase is output to the target current waveform former 202 and the chopping phase width detector 212.
  • the specific operation of the AC voltage phase detector 201 will be described later in detail.
  • the target current waveform former 202 generates a predetermined target current waveform, which will be described later in detail, based on the signal indicating the AC phase, and outputs it to the multiplier 208.
  • the chopping phase width detector 212 determines the phase of the AC voltage indicated by the signal from the AC voltage phase detector 201 based on the chopping drive signal Sch for the semiconductor switch 104 output from the Iac compensation calculator 210 to the PWM modulator 211.
  • a phase width in the chopping state (hereinafter referred to as “chopping operation phase width” or simply “chopping phase width”) ⁇ w ON is detected, and a signal indicating the chopping phase width ⁇ w ON is output to the subtractor 204 To do.
  • the target phase width setting unit 203 outputs a signal indicating a desired chopping phase width ⁇ w ON * that is set and stored in advance to the subtracter 204.
  • the subtractor 204 is a so-called phase comparator, which calculates the deviation of the phase width by subtracting the desired chopping phase width ⁇ w ON * from the actual chopping phase width ⁇ w ON and compensates the signal indicating the deviation with the phase width compensation
  • the result is output to the calculator 205.
  • the phase width compensation calculator 205 generates a command voltage Vdc * of a DC voltage to be output by the rectifier circuit device by performing a predetermined compensation calculation for keeping the phase width in the PWM driving state stable.
  • a signal indicating the voltage Vdc * is output to the subtractor 206.
  • a signal indicating the actual output DC voltage Vdc detected by the DC voltage detector 110 is input to the subtractor 206.
  • the subtractor 206 calculates the voltage deviation by subtracting the actual output DC voltage Vdc from the DC voltage command voltage Vdc * , generates a signal indicating the voltage deviation, and outputs the signal to the Vdc compensation calculator 207.
  • the compensation calculator 207 outputs a signal indicating the voltage deviation after the compensation calculation to the multiplier 208 by executing a compensation calculation for the actual DC voltage Vdc to substantially match the command voltage Vdc * and become stable. To do.
  • the multiplier 208 multiplies the target current waveform from the target current waveform former 202 by the voltage deviation after the compensation calculation, generates an instantaneous current command value Iac * as a multiplication result, and outputs it to the subtracter 209. .
  • the subtractor 209 subtracts the actual current value Iac detected by the current detector 103 from the instantaneous current command value Iac * , thereby outputting a signal indicating the current deviation as a subtraction result to the Iac compensation calculator 210.
  • the Iac compensation calculator 210 performs a predetermined compensation calculation so that the current input from the AC power supply 1 substantially and stably matches the current command value Iac * , and indicates a current deviation after the compensation calculation.
  • the PWM modulator 211 generates a chopping drive signal Sch for turning on and off the semiconductor switch 104 and outputs it to the semiconductor switch 104 by performing PWM modulation on the current deviation after compensation calculation indicated by the input signal.
  • the chopping phase width detector 212 receives the signal from the AC voltage phase detector 201 based on the chopping drive signal Sch for the semiconductor switch 104 output from the Iac compensation calculator 210 to the PWM modulator 211 as described above. relative to the phase of the AC voltage indicated detects the chopping phase width .theta.w oN, and outputs a signal indicating the chopping phase width .theta.w oN to the subtractor 204. Thereby, a control loop of the chopping phase width is configured.
  • the loops (204 to 205, 206, 207, 208, 209, 210, 212 on the right side of the subtractor 204 in FIG.
  • the DC voltage Vdc so that the chopping phase width detected by the chopping phase width detector 212 substantially matches the target phase width set by the target phase width setting unit 203.
  • Is controlled. 2 is detected by the DC voltage detector 110 in a loop on the right side of the subtracter 206 in FIG. 2 (refers to a loop returning from 206 to 206 through 206, 207, 208, 209, 210, 211, 104, 110).
  • the chopping drive control is performed by controlling the amplitude of the target current so that the DC voltage Vdc substantially matches the desired DC voltage Vdc * indicated by the phase width compensation calculator 205. Further, in a loop on the right side of the subtracter 209 in FIG. 2 (referring to a loop returning from 209 to 209 through 210, 211, 104, 103), the current Iac detected by the current detector 103 is a target current waveform. The chopping drive control is performed so as to substantially match the target current Iac * generated based on the target current waveform formed by the former 202.
  • FIG. 3A is a diagram for explaining the control operation according to the first operation example of the control circuit 100 of FIG. 1, in which the relationship between the AC voltage and the DC voltage after rectification, the target current waveform to be controlled, It is a signal waveform diagram which shows AC current after actually controlling.
  • FIG. 3B is a diagram for explaining the control operation according to the second operation example of the control circuit 100 of FIG. 1, and the relationship between the AC voltage and the DC voltage after rectification, and the target current waveform to be controlled.
  • FIG. 6 is a signal waveform diagram showing AC current after actual control.
  • the output DC voltage is relatively low, and the chopping phase width (for example, the minimum phase width) ⁇ w ON for the semiconductor switch 104 is smaller than the desired phase width ⁇ w ON *. This is the case.
  • the phase period in which the AC voltage is higher than the DC voltage increases, the current flowing from the AC power source 1 to the DC side via the reactor 102 and the diode bridge 105 increases. For this reason, the waveform of the AC current becomes sharp, and the harmonic component of the AC current increases.
  • the output DC voltage is relatively high, and the chopping phase width (for example, the maximum phase width) ⁇ w ON for the semiconductor switch 104 is larger than the desired phase width ⁇ w ON *. This is the case.
  • the phase period in which the AC voltage is higher than the DC voltage is reduced as compared with the first operation example, the current flowing from the AC power source 1 through the reactor 102 and the diode bridge 105 to the DC side is also reduced. The harmonic component of the AC current is reduced.
  • the period during which chopping is performed on the semiconductor switch 104 is increased as compared with the waveform in the first operation example of FIG. 3A, the loss of the circuit increases.
  • the chopping phase The width detector 212 may perform the chopping control by selecting a chopping phase width close to 0 degree or 180 degrees of the phase of the AC voltage as the control chopping phase width. Further, the chopping phase width detector 212 uses the phase width closer to the reference phase for determining the polarity of the AC current or the AC voltage instead of 0 degree or 180 degrees of the AC voltage phase as the control chopping phase width. And the chopping control may be performed. Further, the chopping phase width detector 212 may perform the chopping control by adding the obtained chopping phase widths and setting the phase width of the addition result as a control chopping phase width. Even if comprised in this way, it has the same effect.
  • Embodiment 2 the chopping phase width ⁇ w ON is detected and the DC voltage command Vdc * is adjusted.
  • the phase width in which the chopping is in a pause state (hereinafter referred to as “chopping pause”). It is characterized by obtaining the same effect by detecting ⁇ w OFF and adjusting the DC voltage command Vdc.
  • FIG. 4A is a diagram for explaining a control operation according to the third operation example of the control circuit 100 of the rectifier circuit device according to the second embodiment of the present invention, and shows the relationship between the AC voltage and the DC voltage after rectification.
  • FIG. 5 is a signal waveform diagram showing a target current waveform to be controlled and an AC current after actual control.
  • FIG. 4B is a diagram for explaining the control operation according to the fourth operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 2 of the present invention, in which the AC voltage and the DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling.
  • the output DC voltage is relatively low, and the chopping pause phase width (for example, the maximum phase width) ⁇ w OFF in which the semiconductor switch 104 is not chopped is large.
  • the output DC voltage is higher than that in the third operation example, and the chopping pause phase width (for example, the minimum phase width) ⁇ w OFF in which the semiconductor switch 104 is not chopped is This is a case where it is smaller than that in the third operation example. Since the chopping pause phase width ⁇ w OFF is complementary to the chopping operation phase width ⁇ w ON , the same effect can be obtained.
  • the chopping phase width detector 212 may perform the chopping control by selecting the chopping pause phase width ⁇ w OFF in the off period close to 90 degrees or 180 degrees as the control chopping phase width.
  • 4A and 4B show the waveform of only the half cycle of the AC voltage. As is clear from FIGS. 3A and 3B and the prior art, the remaining half cycles are also absolute values (instantaneous absolute values). (Value) will be omitted because it has the same waveform. 4A and 4B show waveforms for only a half cycle of the AC voltage. As is clear from FIGS. 3A and 3B and the conventional example, the remaining half cycles are the same as absolute values. The waveform is omitted because it is
  • FIG. The third embodiment is characterized in that the control method of the first embodiment is simplified, and the chopping phase width detector 212 has a polarity (symbol) of the AC voltage from 0 degree or 180 degrees until the chopping is in a resting state.
  • the chopping control is performed by detecting the first half phase width ⁇ 1w ON in a section (positive section or negative section) in which is not changed.
  • FIG. 5A is a diagram for explaining a control operation according to a fifth operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 3 of the present invention, and shows the relationship between the AC voltage and the DC voltage after rectification.
  • FIG. 5 is a signal waveform diagram showing a target current waveform to be controlled and an AC current after actual control.
  • FIG. 5B is a diagram for explaining the control operation according to the sixth operation example of the control circuit 100 of the rectifier circuit device according to the third embodiment of the present invention, in which the AC voltage and the DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling.
  • the fifth operation example in FIG. 5A is a case where the output DC voltage is relatively low and the phase width in which the semiconductor switch 104 is chopped is relatively small.
  • the sixth operation example in FIG. This is a case where the output DC voltage is higher than that in the fifth operation example, and the phase width in which the semiconductor switch 104 is chopped is larger than that in the fifth operation example. Since the phase width ⁇ 1w ON in which the first half of the chopping is performed has a similar tendency in the period of the half cycle of the AC voltage, the same effects as those of the first embodiment can be obtained.
  • Embodiment 4 is characterized in that the control method of the first embodiment is simplified as in the third embodiment, and the chopping phase width detector 212 is used from 0 degree or 180 degrees until the chopping enters a resting state.
  • the chopping control is performed by detecting the latter phase width ⁇ w2 ON in the section (positive section or negative section) where the polarity of the AC voltage is fixed without changing.
  • FIG. 6A is a diagram for explaining the control operation according to the seventh operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 4 of the present invention, and shows the relationship between the AC voltage and the rectified DC voltage.
  • FIG. 5 is a signal waveform diagram showing a target current waveform to be controlled and an AC current after actual control.
  • FIG. 6B is a diagram for explaining the control operation according to the eighth operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 4 of the present invention, in which the AC voltage and the DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling.
  • the seventh operation example in FIG. 6A is a case where the output DC voltage is relatively low, and the chopping phase width ⁇ w2 ON in which the semiconductor switch 104 is chopped is relatively small.
  • the eighth operation in FIG. 6B An example is a case where the output DC voltage is higher than that in the seventh operation example, and the chopping phase width ⁇ w2 ON in which the semiconductor switch 104 is chopped is larger than that in the seventh operation example. Since the chopping operation phase width ⁇ w2 ON in the second half also has the same tendency in the half-cycle section of the AC power supply 1, the same effect as that of the first embodiment can be obtained.
  • FIG. Embodiment 5 includes a chopping phase width Shitadaburyu1 ON embodiment 3 detects the sum of the phase width ( ⁇ w1 ON + ⁇ w2 ON) the chopping phase width detector 212 with chopping phase width Shitadaburyu2 ON embodiment 4, the The DC voltage is controlled so that the total phase width ( ⁇ w1 ON + ⁇ w2 ON ) becomes a desired phase width.
  • FIG. 7A is a diagram for explaining the control operation according to the ninth operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 5 of the present invention, and shows the relationship between the AC voltage and the DC voltage after rectification.
  • FIG. 5 is a signal waveform diagram showing a target current waveform to be controlled and an AC current after actual control.
  • FIG. 7B is a diagram for explaining a control operation according to the tenth operation example of the control circuit 100 of the rectifier circuit device according to the fifth embodiment of the present invention, in which an AC voltage and a DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling.
  • the same effects as in the first to fourth embodiments can be obtained.
  • FIG. FIG. 8 is a circuit diagram showing a configuration of a rectifier circuit device according to Embodiment 6 of the present invention.
  • FIG. 9 is a block diagram showing a detailed configuration of the control circuit 111 of FIG. 8, the rectifier circuit device according to the sixth embodiment is characterized by including a control circuit 111 instead of the control circuit 100 of FIG. 1, and the control circuit 111 is configured as illustrated in FIG.
  • an input situation determination unit 213 having an input current fluctuation determination blood setting unit 213a, a target phase width selector 214 (provided instead of the target phase width setting unit 203 in FIG. 1), and chopping A phase width extractor 216 is further provided.
  • a desired chopping phase width in a pulsating region is provided separately from a desired chopping phase width in a region that does not pulsate, and the pulsating region has a preset constant time or constant period. The maximum or average chopping phase width in the number is extracted and the chopping control is performed.
  • the control circuit 111 performs chopping control of the semiconductor switch 104, thereby reducing harmonics of the power supply voltage and controlling the DC voltage.
  • the final control target of the control system is such that the chopping phase width ⁇ w ON for which chopping driving is performed matches the desired phase width ⁇ w ON * from the target phase width selector 214. Is to control.
  • the configuration and operation of the control circuit 111 in FIG. 9 will be described focusing on differences from the control circuit 100 in FIG. 2, and description of the same configuration and operation as the control circuit 100 in FIG. 2 will be omitted.
  • the current detector 103 outputs a signal indicating the detected AC current Iac to the input status determiner 213.
  • the input status determination means 213 calculates the fluctuation range of the input current from the peak values of a plurality of power supply voltage periods, and determines the input current fluctuation determination preset by the input current fluctuation determination value setting unit 213a from the calculated fluctuation width. The value is subtracted and a signal indicating the fluctuation width deviation as a subtraction result is output to the target phase width selector 214 and the chopping phase width extractor 216.
  • the target phase width selector 214 stores in advance the desired chopping phase width ⁇ w ON * to be set corresponding to various numerical ranges of the fluctuation width deviation in the built-in table memory 214m as a chopping phase width table, and determines the input status Based on the signal indicating the fluctuation width deviation (degree of fluctuation of the input current) from the device 213, the corresponding chopping phase width ⁇ w ON * is determined with reference to the chopping phase width table, and the signal indicating it is subtracted. Output to the device 204.
  • the chopping phase width extractor 216 generates a pulsation of a predetermined value or more in the phase width based on the phase width in the chopping state from the chopping phase width detector 212 and the fluctuation width deviation from the input status determination unit 213.
  • a signal indicating the chopping phase width ⁇ w ON in the chopping state from the chopping phase width detector 212 is output to the subtractor 204 as it is.
  • the chopping phase width extractor 216 determines that a pulsation of a predetermined value or more has occurred in the chopping phase width ⁇ w ON , the maximum or average chopping state in a preset fixed time or fixed number of cycles And a signal indicating the phase width is output to the subtracter 204.
  • the rectifier circuit device having the control circuit 111 of FIG. 9 configured as described above, even when there is a pulsating load that generates a pulsation of a predetermined value or more, the harmonics of the power supply voltage are greatly affected.
  • the phase width ⁇ w ON in the chopping state can be extracted, and both reduction of the harmonics of the power supply voltage and reduction of the circuit loss can be achieved.
  • FIG. FIG. 10 is a circuit diagram showing a configuration of a rectifier circuit device according to Embodiment 7 of the present invention.
  • FIG. 11 is a block diagram showing a detailed configuration of the control circuit 112 of FIG.
  • the rectifier circuit device of FIG. 10 is characterized by driving a motor of a compressor 301 connected to the compressor driving unit 300 as a load, and the control is executed by the compressor control circuit 302.
  • the compressor control circuit 302 outputs a rotation speed command Srot to the compressor drive unit 300 and the control circuit 112 to rotate the motor of the compressor 301 at a desired rotation speed.
  • the rectifier circuit device according to Embodiment 7 in FIGS. 10 and 11 provides a desired chopping phase width in the pulsating region separately from the desired chopping phase width in the non-pulsating region, as in Embodiment 6.
  • the chopping control is performed by selecting the maximum or average chopping phase width in a predetermined time or a predetermined number of periods.
  • the control circuit 112 in FIG. 11 is compared with the control circuit 111 in FIG. (A) In place of the input status determiner 213, a drive status determiner 215 that determines the drive status based on the rotational speed command Srot from the compressor control circuit 302 is provided. (B) In place of the target phase width selector 214, a target phase width selector 214A having a built-in table memory 214Am is provided, (C) Instead of the chopping phase width extractor 216, a chopping phase width extractor 216A is provided.
  • a motor rotation speed command Srot is input from the compressor control circuit 302 to the drive status determination unit 215.
  • the drive status determiner 215 calculates a rotational speed deviation by subtracting a preset rotational speed from the motor rotational speed command Srot, and outputs a signal indicating the rotational speed deviation to the target phase width selector 214A and the chopping phase width. Output to the extractor 216A.
  • the target phase width selector 214A stores in advance the desired chopping phase width ⁇ w ON * to be set corresponding to various numerical ranges of the rotational speed deviation in the built-in table memory 214Am as a chopping phase width table, and determines the drive status
  • the corresponding chopping phase width ⁇ w ON * is determined with reference to the chopping phase width table based on the signal indicating the rotational speed deviation from the unit 215, and a signal indicating it is output to the subtractor 204.
  • the number of rotations for driving the compressor 301 is set in advance based on the phase width in the chopping state from the chopping phase width detector 212 and the rotational speed deviation from the driving state determination unit 215.
  • the signal indicating the chopping phase width ⁇ w ON from the chopping phase width detector 212 is output to the subtractor 204 as it is.
  • the chopping phase width extractor 216A when the rotational speed for driving the compressor 301 is equal to or lower than the preset rotational speed, is the maximum or average chopping state for a predetermined time period or constant frequency.
  • the phase width is extracted and a signal indicating the phase width is output to the subtracter 204.
  • a reciprocating type or rolling piston type compressor 301 used in a small-sized refrigeration and air-conditioning apparatus for home use has a characteristic that required power in each of a suction stroke, a compression stroke, and a discharge stroke is significantly different. If the necessary power in each stroke is not properly supplied, the compressor 301 will vibrate and cause damage to the piping. For this reason, control which suppresses vibration by controlling the instantaneous instantaneous speed of the electric motor for driving in each stroke to be constant is performed. As a result, the load of the rectifier circuit device according to the present invention has a pulsation with a cycle of changing each stroke.
  • the occurrence of vibration is also related to the transition cycle of each stroke, and if the cycle is shortened, it has a characteristic that it is attenuated by the inertia effect due to the moment of inertia, and when the cycle is short, that is, when the motor rotation speed is high, It is not necessary to perform control for suppressing vibration, and it is possible to maintain a state in which vibration is small even with average speed control alone. In the case of only average speed control, the load on the DC side has less pulsation.
  • the chopping phase width extractor 216A has either the number of rotations that exceeds or is less than the predetermined rotation number.
  • the phase width of the chopping state is output to the subtractor 204 as it is, or the phase width of the maximum or average chopping state in a predetermined time or a predetermined number of cycles is extracted. Whether to output to the subtractor 204 is switched.
  • the chopping phase width extractor 216A outputs the phase width information of the chopping state to the subtractor 204 as it is in the region where the rotation speed of the compressor 301 is high, and in advance in the region where the rotation speed of the compressor 301 is low.
  • the threshold value of the rotation speed in these switchings is a value that changes depending on the specification specifications such as the compression ratio and the moment of inertia of the compressor 301.
  • the chopping phase width ⁇ w ON or the phase width ⁇ w OFF in which the chopping is in a suspend state may be determined based on whether or not the power supply cycle changes every time.
  • the state of the pulsating load can be estimated by using the rotation speed command Srot of the motor of the compressor 301, so the pulsating state is directly detected. Therefore, the phase width of the chopping state can be extracted, and both reduction of harmonics of the power supply voltage and reduction of circuit loss can be achieved.
  • the drive rotation speed command Scot of the compressor 301 is used as the input of the drive status determination unit 215. However, it is necessary to suppress the occurrence of vibration due to the rotation speed when the compressor 301 is driven. Whether or not the instantaneous speed control to be executed is input as input from the compressor control circuit 302, and the target phase width selection signal is output to the target phase width selector 214 and the chopping phase width extractor 216A according to the presence or absence of the instantaneous speed control. Similar chopping control can be performed.
  • FIG. FIG. 12A is a diagram for explaining the control operation according to the eleventh operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 8 of the present invention, and shows the relationship between the AC voltage and the DC voltage after rectification.
  • FIG. 5 is a signal waveform diagram showing a target current waveform to be controlled and an AC current after actual control.
  • FIG. 12B is a diagram for explaining the control operation according to the twelfth operation example of the control circuit 100 of the rectifier circuit device according to the eighth embodiment of the present invention, in which the AC voltage and the DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling.
  • the control circuit 100 according to the eighth embodiment is characterized in that the target current waveform is a waveform other than a sine wave, for example, a triangular wave, thereby further reducing circuit loss.
  • the target current waveform is a waveform other than a sine wave, for example, a triangular wave, thereby further reducing circuit loss.
  • the harmonic current itself is small, so that the loss can be further reduced.
  • the eleventh operation example in FIG. 12A is a case where the output DC voltage is relatively low and the phase width ⁇ w ON where the semiconductor switch 104 is chopped is smaller than the desired phase width ⁇ w ON * . Also at this time, since the phase period in which the AC voltage is higher than the DC voltage increases, the current flowing from the AC power source 1 to the DC side via the reactor 102 and the diode bridge 105 increases. For this reason, the waveform of the AC current becomes sharp, and the harmonic component of the AC current increases.
  • the output DC voltage is higher than that in the eleventh operation example, and the phase width ⁇ w ON where the semiconductor switch 104 is chopped is higher than the desired phase width ⁇ w ON *. This is the case when it is getting bigger.
  • the phase period in which the AC voltage is higher than the DC voltage decreases, the AC current flowing from the AC power source 1 to the DC side via the reactor 102 and the diode bridge 105 also decreases, and the harmonic component of the AC current decreases.
  • the period (phase width) during which the chopping of the semiconductor switch 104 is performed is increased compared to the waveform in FIG. 12A, as in FIGS. 3A and 3B. As a result, circuit loss increases.
  • the instantaneous absolute value of the target current waveform is from 0 degree (start point) to 180 degrees (end point) of the AC voltage with time.
  • a triangular waveform having a section that monotonously increases with a certain slope then monotonously decreases with a certain slope from a predetermined intermediate point (an angle smaller than 90 degrees), and then becomes zero until the end point. Is used.
  • one chopping phase width ⁇ w ON is shown in the half cycle of the AC voltage, so two chopping pause phase widths are shown in the half cycle of the AC voltage. Therefore, as described above, chopping control may be performed based on one of the two chopping pause phase widths or the total phase width.
  • FIG. 13A is a diagram for explaining the control operation according to the thirteenth operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 8 of the present invention, and shows the relationship between the AC voltage and the rectified DC voltage.
  • FIG. 5 is a signal waveform diagram showing a target current waveform to be controlled and an AC current after actual control.
  • FIG. 13B is a diagram for explaining the control operation according to the fourteenth operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 8 of the present invention, in which the AC voltage and the DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling. Further, FIG.
  • FIG. 13C is a diagram for explaining the control operation according to the fifteenth operation example of the control circuit 100 of the rectifier circuit device according to the eighth embodiment of the present invention, in which the AC voltage and the DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling.
  • FIG. 13D is a diagram for explaining the control operation according to the sixteenth operation example of the control circuit 100 of the rectifier circuit device according to the eighth embodiment of the present invention, in which the AC voltage and the DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling.
  • the target current waveform of the thirteenth operation example of FIG. 13A is instantaneously at a predetermined angle (for example, 110 degrees) exceeding 90 degrees in the second half, instead of the monotonously decreasing period, as compared with the target current waveform of FIG. 12A. It is the triangular waveform comprised so that it may have the area (zero and constant area) to make it zero.
  • the target current waveform in the fourteenth operation example of FIG. 13B is a predetermined angle exceeding 90 degrees in the latter half by increasing the monotonically increasing section as a sine wave with the passage of time as compared with the target current waveform of FIG. 13A. It is a waveform having a section (for example, a constant section at zero) that instantaneously becomes zero at (eg, 110 degrees).
  • the target current waveform of the fifteenth operation example of FIG. 13C is provided with a constraint condition in the target current waveform of FIG. 13B, and the angle of the intermediate point before 90 degrees (for example, 70 degrees) in the sine waveform of the first half.
  • the waveform is instantaneously zeroed.
  • the target current waveform of the sixteenth operation example of FIG. 13D is zero (a constant period at zero) for a predetermined period from 0 degree to the first intermediate point with time in the target current waveform of FIG. 13C. Thereafter, the waveform is configured to monotonously increase to the second intermediate point.
  • the target current is set to zero before 90 degrees.
  • the chopping operation of the semiconductor switch 104 is stopped from the chopping operation before the phase to be zero. It can be used with a heavy load.
  • the current flows from the AC power source 1 through the reactor 102 and the diode bridge 105 in the vicinity of 90 degrees, so that the target current becomes zero.
  • AC current continues to flow for a while, a current with less harmonic components can be realized with high efficiency.
  • the target current waveform may be monotonously increased or decreased, and a certain period may be included, that is, it may be substantially monotonically increased or substantially monotonically decreased.
  • substantially monotonically increasing means a monotonically increasing in a broad sense having a relationship of f ( ⁇ 1) ⁇ f ( ⁇ 2) when the phase of the target current waveform is ⁇ 1 ⁇ 2, in other words, time With the passage of time, it means at least increasing, or at least increasing and substantially monotonically increasing so as to be constant over a period of time.
  • substantially monotonically decreasing refers to a monotonic decreasing in a broad sense having a relation of f ( ⁇ 1) ⁇ f ( ⁇ 2) when the phase ⁇ 1 ⁇ 2 of the target current waveform, in other words, the passage of time
  • it means to substantially decrease monotonically so as to at least decrease, or at least decrease and to be constant in a part period.
  • FIG. FIG. 14 is a circuit diagram showing a configuration of a rectifier circuit device according to Embodiment 9 of the present invention.
  • the rectifier circuit device according to the ninth embodiment rectifies an AC voltage from the AC power source 1 through a reactor 602 by a bridge circuit configured by semiconductor switches 604a and 604b and diodes 605a, 605b, 605c, and 605d, The load 4 is driven through the smoothing capacitor 106.
  • the chopping control method according to the present embodiment is the same as that of the control circuit 100 of FIG. 1 according to the first embodiment, and the two semiconductor switches 604b and 604d are simultaneously driven using the chopping drive signal Sch.
  • Embodiment 10 FIG. FIG.
  • FIG. 15 is a circuit diagram showing a configuration of a rectifier circuit device according to Embodiment 10 of the present invention.
  • the rectifier circuit device according to the tenth embodiment rectifies the AC voltage from the AC power source 1 through the reactor 702 with a bridge circuit configured by semiconductor switches 704a and 704b and diodes 705a, 705b, 705c, and 705d,
  • the load 4 is driven through the smoothing capacitor 106.
  • the chopping control method according to the present embodiment only one of the semiconductor switches 705a or 705b is chopped using two chopping drive signals Sch1 and Sch2 in accordance with the polarity of the AC voltage from the AC power supply 1.
  • the semiconductor switch 704b is chopped using the chopping drive signal Sch2, and the AC voltage polarity is low on the side where the reactor 702 is connected. If so, the semiconductor switch 704a is chopped using the chopping drive signal Sch1.
  • the semiconductor switches 704a and 704b when the semiconductor switches 704a and 704b are turned on at the same time, the DC output voltage to the load 4 is short-circuited. Therefore, which of the semiconductor switches 704a and 704b is in the vicinity where the polarity of the AC voltage is reversed. May also be set not to turn on. In such a case, in FIGS. 3A and 3B, the phase in which the chopping is changed to the resting state can occur even in the vicinity of 0 degree and 180 degrees. However, in this case, since the chopping is intentionally suspended to prevent a short circuit of the DC output voltage, it is easily realized by not handling the chopping according to the present invention as a phase that has changed to a suspended state. Can do.
  • FIG. 16A is a diagram for explaining a first operation example of the binarization processing of the voltage level comparator 109 of the rectifier circuit device according to Embodiments 1 to 10 of the present invention, and illustrates an AC voltage and a threshold voltage Vth. And a binary waveform signal from the voltage level comparator 109.
  • FIG. 16B is a diagram for explaining a second operation example of the binarization processing of the voltage level comparator 109 of the rectifier circuit device according to Embodiments 1 to 10 of the present invention. It is a signal waveform diagram showing the relationship with the voltage Vth and the binary signal from the voltage level comparator 109.
  • FIGS. 16A and 16B show a method of detecting a voltage phase from information on whether or not the AC voltage is equal to or higher than a certain level.
  • This information obtains as a binary signal whether or not the instantaneous voltage of the AC voltage exceeds the threshold value. That is, the voltage level comparator 109 compares the AC voltage with the threshold voltage Vth and outputs a high level signal when the AC voltage is equal to or higher than the threshold voltage Vth, while the AC voltage is lower than the threshold voltage Vth. When a low level signal is output.
  • the cycle of the binary signal is the same as the power supply frequency. If the midpoint of the high level side or low level side of the binary signal is obtained, the AC voltage phase is 90 degrees. Or you can know the time of 270 degrees. Further, the midpoints of 90 degrees and 270 degrees of the AC voltage phase are 180 degrees and 0 degrees. If the information thus obtained is multiplied using a PLL or the like, the instantaneous instantaneous phase can be accurately known.
  • phase information in units of degrees can be obtained. Then, the instantaneous instantaneous target current waveform may be called from the obtained phase information.
  • Other methods for detecting the phase using binary information obtained from level comparison have been proposed in, for example, Patent Document 4 disclosed by the present inventor, and are not particularly limited.
  • the DC voltage is relatively adjusted so that the phase width in which the chopping operation is performed becomes a desired phase width.
  • a current waveform is obtained, and a rectification operation with always low loss and low harmonic current is realized.
  • FIG. FIG. 17 is a block diagram showing a detailed configuration of the control circuit 100 of the rectifier circuit device according to Embodiment 11 of the present invention.
  • the control circuit 100 of the rectifier circuit device according to the eleventh embodiment includes an AD converter 230 and an LPF between the DC voltage detector 110 and the subtractor 206, as compared with the control circuit 100 of FIG.
  • the present invention is characterized in that an arithmetic unit 231 is inserted, and provides an embodiment that is particularly effective when implemented by digital computation.
  • differences from the control circuit 100 of FIG. 2 will be described.
  • an analog signal indicating a DC voltage detected by the DC voltage detector 110 is converted into a digital signal indicating an AD conversion value Vad by an AD converter 230 that performs AD conversion at a sampling frequency sufficiently higher than the frequency of the AC power supply 1.
  • an LPF operation is performed by an LPF operation unit 231 that performs an operation (described later in detail) having a low-pass filter characteristic, and a signal (LPF operation value Vdca) as a result of the operation is output to the subtracter 206.
  • the frequency of the AC power source 1 is 60 Hz
  • the sampling frequency is 600 kHz.
  • FIG. 18 is a block diagram showing a detailed configuration of the LPF calculator 231 of FIG.
  • a signal indicating the AD conversion value from the AD converter 230 is input to the adder 253.
  • the adder 253 adds the signal indicating the input AD conversion value and the signal from the constant multiplier 251 to output a signal indicating the LPF operation value Vdca as an addition result to the subtractor 206 and one clock.
  • the data is output to the constant multiplier 251 through a delay device 252 that is delayed by time.
  • the constant multiplier 251 multiplies the input signal by a predetermined constant (2 n ⁇ 1) / (2 n ) and outputs a signal indicating the multiplication result to the adder 253.
  • This LPF calculation process is a first-order low-pass filter having a time constant “2 n ” times the calculation cycle, and the amplitude is “2 n ” times. Therefore, by executing this calculation, n-bit information below the decimal point is added to the AD conversion value Vad.
  • FIG. 19 is a diagram illustrating the operation of the rectifier circuit device of FIG. 17, in which the AC current Iac from the AC power source 1, the DC voltage Vdc, and the AD conversion value Vad of the AD converter 230 (the DC voltage Vdc is indicated by a dotted line).
  • FIG. 19 shows an operation principle that can improve the voltage detection accuracy by performing the low-pass filter process with a single-phase AC rectifier circuit.
  • the DC voltage still has a fluctuation having a frequency twice the power source frequency. . In order to reduce this fluctuation, it is necessary to increase the capacitor capacity of the smoothing capacitor 106 infinitely, which is practically impossible.
  • FIG. 19C shows an AD conversion value Vad when the DC voltage Vdc (indicated by a dotted line) is AD converted at a sampling frequency sufficiently higher than the frequency of the AC power supply 1.
  • the obtained AD conversion value Vad (digital value) takes values of K, K + 1, K + 2, K + 3,.
  • the low-pass filter operation is performed on the AD conversion value Vad, the value converges to a value between (K + 1) and (K + 2) in the case of FIG. Further, as shown in FIG.
  • the command voltage Vdc * needs to have the same resolution as that of the AD converter 230. However, since the command voltage Vdc * is information only, the resolution is similar to the above. It is easy to increase the value.
  • the LPF calculation the case of using a power of 2 has been described.
  • the constant of the constant multiplier 251 is set to a value between 0 and 1, the LPF calculation can be similarly realized. Further, as apparent from the operation principle of FIG. 19, the same effect can be obtained even if the LPF calculation is a method other than the method shown in FIG.
  • the technique according to the eleventh embodiment can be implemented by combining the first to tenth embodiments described so far.
  • chopping when chopping changes from the resting state to the chopping state, it may change again to the resting state for a moment due to circuit fluctuations or noise.
  • the chopping in the invention can be easily realized by not handling as a phase changed to a dormant state.
  • the AC voltage phase detector 201 detects the phase of the AC voltage and detects the chopping phase width based on the detected phase.
  • the present invention is not limited to this, and the AC power source 1 If the frequency is fixed, the chopping phase width may be detected based on information such as zero crossing of the AC power supply 1. Further, when detecting the chopping phase width, the time of the chopping phase width may be measured by counting with the number of pulses of the carrier signal that realizes the PWM control which is an example of the chopping technique.
  • the rectifier circuit device can achieve both suppression of harmonic current and reduction of circuit loss, so that a heat pump is configured by compressing refrigerant with a compressor,
  • the present invention can also be applied to applications such as cooling, heating, or freezing foods.
  • Diode bridge circuit, 106 smoothing capacitor, 109 ... voltage level comparator, 110 ... DC voltage detector, 201 ... AC voltage phase detector, 202 ... target current waveform former, 203 ... Target phase width setting device, 204, 206, 209 ... subtractor, 205 ... Phase width compensation calculator, 207 ... Vdc compensation calculator, 208 ... multiplier, 210 ... Iac compensation calculator, 211 ... pulse width modulator, 212 ...
  • chopping phase width detector 213... Input status determination device, 213a: Input current fluctuation judgment value setting device, 214, 214A ... Target phase width selector, 214m, 214Am ... built-in table memory, 215 ... Driving status determiner, 216, 216A ... Chopping phase width extractor, 230: AD converter, 231 ... Low-pass filter computing unit, 251 ... Constant multiplier, 252 ... delay device, 253 ... Adder, 300 ... compression drive unit, 301 ... Compressor, 302 ... compressor control circuit, 605a to 605d, 705a to 705d, diodes.

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Abstract

Disclosed is a rectifier circuit device that, by chopping a semiconductor switch (104), shorts or opens the output terminal of a single-phase AC power source (1) via a reactance, rectifying the AC voltage supplied by the single-phase AC power source (1) via the reactance (102) into a DC voltage and supplying said DC voltage to a load. A control device (100) in said rectifier circuit device: controls the chopping of the semiconductor switch (104) so as to make a detected current waveform match a target current waveform; controls the amplitude of the target current waveform so as to make a detected DC voltage match a prescribed target DC voltage; and controls said prescribed target DC voltage so as to make either the width of a chopping motion phase, which is when the semiconductor switch (104) is in a chopping motion state, or the width of a chopping rest phase, which is when the semiconductor switch (104) is in a chopping rest state, match a prescribed phase width.

Description

整流回路装置Rectifier circuit device
　本発明は、整流回路装置及び前記整流回路装置のための制御回路に関し、特に、家庭などの単相交流電源を整流して略直流とし、直流負荷を駆動する回路装置や、得られた直流をインバータ回路により、再度、任意周波数の交流に変換して、電動機の可変速度駆動する装置であって、例えば圧縮機により冷媒を圧縮することによりヒートポンプを構成し、冷房、暖房、又は食品などの冷凍を行う装置に適用させる装置であり、その中での電源電流に含まれる高調波成分の低減や、力率を改善することにより、送電系統の負担を軽減させる技術の高効率な駆動制御を行う整流回路装置及び前記整流回路装置のための制御回路に関する。 The present invention relates to a rectifier circuit device and a control circuit for the rectifier circuit device, and in particular, a circuit device for driving a DC load by rectifying a single-phase AC power source such as a home to make it a direct current, and the obtained direct current A device that converts again to an arbitrary frequency alternating current by an inverter circuit and drives the motor at a variable speed, for example, a refrigerant is compressed by a compressor to constitute a heat pump, and cooling, heating, refrigeration such as food This is a device that is applied to a device that performs high-efficiency drive control with technology that reduces the burden on the power transmission system by reducing harmonic components contained in the power supply current and improving the power factor. The present invention relates to a rectifier circuit device and a control circuit for the rectifier circuit device.
　図２０は、特許文献１に開示された、従来技術に係る整流回路装置の構成を示す回路図であり、図２１は図２０の制御部１３の詳細構成を示すブロック図である。 FIG. 20 is a circuit diagram showing a configuration of a rectifier circuit device according to the prior art disclosed in Patent Document 1, and FIG. 21 is a block diagram showing a detailed configuration of the control unit 13 of FIG.
　従来、この種の整流回路装置は、図２０に示すように、交流電源１の両出力端子を整流ブリッジ２とリアクタ３ａを介して半導体スイッチ３ｃで短絡せしめ、リアクタ３ａに電流を充電し、半導体スイッチ３ｃがオフ状態になったときに、ダイオード３ｂにより負荷４に電流を流すことにより、交流電源１の瞬時電圧が低い期間にも電源電流が流れるようにする構成をとっている。これにより、電源電流の高調波成分が少なくなり、力率が改善する。ところが、半導体スイッチ３ｃを、交流電源１の周波数よりも十分に高い周波数で、きめ細かくオン／オフ駆動することにより、交流電源１の交流電圧をチョッピングする（以下、「半導体スイッチをチョッピング動作させる」又は「半導体スイッチによるチョッピング」という。）ときに、半導体スイッチ３ｃを電流が流れるため、回路の損失が発生するという課題があった。 Conventionally, in this type of rectifier circuit device, as shown in FIG. 20, both output terminals of the AC power supply 1 are short-circuited by a semiconductor switch 3c via a rectifier bridge 2 and a reactor 3a, and the reactor 3a is charged with current. When the switch 3c is turned off, a current is supplied to the load 4 by the diode 3b so that the power supply current flows even when the instantaneous voltage of the AC power supply 1 is low. As a result, the harmonic component of the power supply current is reduced and the power factor is improved. However, the semiconductor switch 3c is finely turned on / off at a frequency sufficiently higher than the frequency of the AC power supply 1, thereby chopping the AC voltage of the AC power supply 1 (hereinafter, “the semiconductor switch is chopped”) or (Referred to as “chopping by a semiconductor switch”), a current flows through the semiconductor switch 3c, causing a problem of circuit loss.
　この課題を解決するため、半導体スイッチ３ｃを常にチョッピング動作させるのではなく、交流位相の特定の期間だけチョッピング動作させ、残りの期間は休止させる方法が提案されている（例えば、特許文献１参照）。 In order to solve this problem, a method has been proposed in which the semiconductor switch 3c is not always chopped, but is chopped only for a specific period of the AC phase and is rested for the remaining period (see, for example, Patent Document 1). .
　図２０において、交流電源１からの交流電圧を整流ブリッジ２で整流して、脈動を含む直流電圧に変換した後、その電力をリアクタ３ａ、ダイオード３ｂを介して、平滑コンデンサ３ｄ及び負荷４に供給する。さらに、リアクタ３ａを介して、前記整流ブリッジ２からの出力電圧を半導体スイッチ３ｃで短絡できるように構成することにより、周知の昇圧チョッパ回路３による力率改善機能つきの整流回路装置を構成している。ここで、昇圧チョッパ回路３は、入力電流検出器６及び入力電流検出部１０で入力電流を検出し、入力電流が入力電圧検出部１１で検出した入力電圧波形（電源電圧波形）と同じ形状になるように半導体スイッチ３ｃをチョッピング動作させ、かつ、出力電圧が所望の電圧になるように、入力電流の大きさを調整する。 In FIG. 20, after the AC voltage from the AC power source 1 is rectified by the rectifier bridge 2 and converted into a DC voltage including pulsation, the power is supplied to the smoothing capacitor 3d and the load 4 via the reactor 3a and the diode 3b. To do. Further, the output voltage from the rectifier bridge 2 can be short-circuited by the semiconductor switch 3c via the reactor 3a, thereby forming a rectifier circuit device having a power factor improving function by a known boost chopper circuit 3. . Here, the boost chopper circuit 3 detects the input current with the input current detector 6 and the input current detector 10, and the input current has the same shape as the input voltage waveform (power supply voltage waveform) detected by the input voltage detector 11. Thus, the semiconductor switch 3c is chopped and the magnitude of the input current is adjusted so that the output voltage becomes a desired voltage.
　特に、特許文献１では、半導体スイッチを高調波が少なくなるための最低限の区間のみチョッピング動作させることにより、回路の損失を低減させる工夫を提案している。図２１はそのための制御方法を示す。図２１において、電源ゼロクロス検出手段５により、電源電圧の位相を検出し、パルスカウンタ１３ａにより一定の期間のみ、図２０の半導体スイッチ３ｃのチョッピング動作を許可し、それ以外の期間では、半導体スイッチ３ｃがオフになるように保持している。この方法により、電源高調波をほとんど増加させることなく、かつ低損失な整流回路装置を実現することができる。 In particular, Patent Document 1 proposes a contrivance for reducing the circuit loss by causing the semiconductor switch to perform a chopping operation only in a minimum interval for reducing harmonics. FIG. 21 shows a control method for that purpose. In FIG. 21, the phase of the power supply voltage is detected by the power supply zero-cross detection means 5, and the chopping operation of the semiconductor switch 3c of FIG. 20 is permitted only for a certain period by the pulse counter 13a, and in the other periods, the semiconductor switch 3c Holds to be off. By this method, a low-loss rectifier circuit device can be realized with almost no increase in power supply harmonics.
　また、特許文献１の手法では電源電圧の波形が必要であるが、電源電圧の波形を使用せず、予め決めた波形で同様の動作を実現する方法も提案されている（例えば、特許文献２参照）。さらに、目標となる電流波形を有せずに同様の効果をねらう簡便な方法も提案されている（例えば、特許文献３参照）。 Further, although the method of Patent Document 1 requires a waveform of the power supply voltage, a method for realizing the same operation with a predetermined waveform without using the waveform of the power supply voltage has been proposed (for example, Patent Document 2). reference). Furthermore, a simple method that aims at the same effect without having a target current waveform has been proposed (see, for example, Patent Document 3).
　なお、図２０の場合は、入力電流をいったん整流した後の電流で代用しており、この場合には、入力電流の絶対値の情報を得て、絶対値の大きさを調整するが、入力電流の振幅を調整することと等価であることは、広く知られている。 In the case of FIG. 20, the input current is substituted with the current after rectification. In this case, the absolute value of the input current is obtained and the magnitude of the absolute value is adjusted. It is well known that it is equivalent to adjusting the amplitude of the current.
特開２００５－２５３２８４号公報JP 2005-253284 A 特開２００７－１２９８４９号公報JP 2007-129849 A 特開２０００－２２４８５８号公報JP 2000-224858 A 特開２００１－０４５７６３号公報JP 2001-045763 A
　しかしながら、前記従来技術に係る整流回路装置の構成では、負荷が決まっている条件では、出力電圧が一定になるように制御され、また、半導体スイッチをチョッピング動作させる期間も固定されている。このため、検出された出力電圧に誤差があると、電流波形が変化してしまう。例えば、実効値２００Ｖの交流を整流して約２８０Ｖの直流を得る場合に、直流電圧が１Ｖ変化するだけで電流波形が大きく変化する。２８０Ｖの直流電圧に対して１Ｖの精度は、０．３％に相当し、抵抗で電圧を分圧して低い電圧にする場合に、非常に高い精度の抵抗が必要になってしまう。このため、出力電圧の検出精度を加味して、変化した電流波形でも高調波が少なくなるように、チョッピングする期間をより長く設定して、回路の損失を少し増加させる必要があるというという課題を有している。 However, in the configuration of the rectifier circuit device according to the conventional technique, the output voltage is controlled to be constant under the condition where the load is determined, and the period during which the semiconductor switch is chopped is also fixed. For this reason, if there is an error in the detected output voltage, the current waveform changes. For example, when an alternating current having an effective value of 200V is rectified to obtain a direct current of about 280V, the current waveform changes greatly only by changing the direct current voltage by 1V. An accuracy of 1V with respect to a DC voltage of 280V corresponds to 0.3%, and a resistor with very high accuracy is required when the voltage is divided by a resistor to make it a low voltage. For this reason, in consideration of the detection accuracy of the output voltage, it is necessary to set a longer chopping period and to slightly increase the circuit loss so that the harmonics are reduced even in the changed current waveform. Have.
　また、このような制御方法は一般にデジタルコンピュータを用いて実現されるが、高精度な直流電圧の電圧制御を実現しようとすると、直流電圧を高分解能すなわちビット数の多いアナログ－デジタル変換（以下、「ＡＤ変換」という。）器が必要になり、回路負担が大きくなってしまう。この場合も、実際に制御回路が検出できる精度を加味して、変化した電流波形でも高調波が少なくなるように、チョッピングする期間をより長く設定して、回路の損失を少し増加させる必要があるという課題を有している。 Such a control method is generally realized by using a digital computer. However, in order to realize high-precision voltage control of a DC voltage, the DC voltage is converted into a high resolution, that is, an analog-to-digital conversion (hereinafter referred to as a high bit number). "AD conversion") is required, which increases the circuit load. In this case as well, it is necessary to increase the circuit loss slightly by setting the chopping period longer so that the harmonics are reduced even in the changed current waveform, taking into account the accuracy that the control circuit can actually detect. It has a problem.
　さらに、このような整流回路装置では、出力電圧が低いほど損失が少なくなるが、電源電圧の瞬時値よりも低い電圧に出力電圧を設定しようとした場合、半導体スイッチをチョッピング動作させる期間の交流電圧が出力電圧より低くても、半導体スイッチをチョッピング動作させる期間に昇圧動作により出力電圧が上昇してしまう現象が発生し、このため、より損失の少ない、低い出力電圧に設定することが難しいという課題も有している。 Further, in such a rectifier circuit device, the lower the output voltage, the smaller the loss. However, when the output voltage is set to a voltage lower than the instantaneous value of the power supply voltage, the AC voltage during the period of chopping the semiconductor switch is used. Even if the output voltage is lower than the output voltage, a phenomenon occurs in which the output voltage rises due to the boost operation during the chopping operation of the semiconductor switch, and therefore it is difficult to set a lower output voltage with less loss. Also have.
　また、このような整流回路装置では、入力電流が、接続される負荷の電気的特性に依存して脈動を持つか、持たないかで発生する電源高調波が大きく異なり、予め設定されている半導体スイッチをチョッピング動作させる期間で制御を行った場合、電流振幅が比較的小さく、高調波電流も非常に小さくて周辺機器や電源系統に悪影響を与えない低電力領域においてもスイッチングが実施されることとなり、積算値としての損失が増加するという課題も有している。 Further, in such a rectifier circuit device, the power supply harmonics generated depending on whether or not the input current has pulsation depending on the electrical characteristics of the connected load are greatly different, and a preset semiconductor When control is performed during the chopping period of the switch, switching is performed even in a low power region where the current amplitude is relatively small and the harmonic current is very small, which does not adversely affect peripheral devices and the power supply system. There is also a problem that loss as an integrated value increases.
　本発明の目的は以上の問題点を解決し、出力電圧の検出精度によらず、接続されている負荷の特性に応じて電源高調波電流を低減でき、かつ損失も低減できる整流回路装置及び前記整流回路装置のための制御回路を提供することにある。 The object of the present invention is to solve the above-mentioned problems, the rectifier circuit device capable of reducing the power supply harmonic current and reducing the loss according to the characteristics of the connected load, regardless of the detection accuracy of the output voltage, and the aforementioned It is to provide a control circuit for a rectifier circuit device.
　第１の発明に係る整流回路装置は、
　半導体スイッチをチョッピング動作させることにより、単相交流電源の出力端子をリアクタを介して短絡又は開放し、前記単相交流電源から前記リアクタを介して供給される交流電圧を直流電圧に整流して負荷に供給する整流回路装置であって、
　前記交流電圧の波形と同一周波数の目標電流波形を形成する波形形成手段と、
　前記単相交流電源から流れる交流電流を検出する電流検出手段と、
　前記直流電圧を検出する電圧検出手段と、
　前記検出された交流電流の波形が実質的に前記目標電流波形となるように前記半導体スイッチのチョッピング動作を制御する第１の制御手段と、
　前記検出された直流電圧が実質的に所定の目標直流電圧となるように前記目標電流波形の振幅を制御する第２の制御手段と、
　前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、もしくは、前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御する第３の制御手段とを備えたことを特徴とする。 The rectifier circuit device according to the first invention is:
By chopping the semiconductor switch, the output terminal of the single-phase AC power supply is short-circuited or opened via the reactor, and the AC voltage supplied from the single-phase AC power supply via the reactor is rectified into a DC voltage and loaded. A rectifier circuit device for supplying to
Waveform forming means for forming a target current waveform having the same frequency as the waveform of the AC voltage;
Current detecting means for detecting an alternating current flowing from the single-phase AC power source;
Voltage detecting means for detecting the DC voltage;
First control means for controlling the chopping operation of the semiconductor switch so that the waveform of the detected alternating current substantially becomes the target current waveform;
Second control means for controlling the amplitude of the target current waveform such that the detected DC voltage is substantially a predetermined target DC voltage;
The predetermined target DC voltage is controlled so that a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state is substantially a predetermined phase width. And third control means.
　上記整流回路装置において、前記所定の位相幅は、前記負荷の電気的特性に依存して変更して設定されることを特徴とする。ここで、前記負荷の電気的特性は、前記交流電流の変動幅、もしくは前記負荷が圧縮機であるときの圧縮機モータへの回転数指令であることを特徴とする。 In the rectifier circuit device, the predetermined phase width is set by being changed depending on an electrical characteristic of the load. Here, the electrical characteristic of the load is a fluctuation range of the alternating current or a rotational speed command to a compressor motor when the load is a compressor.
　また、上記整流回路装置において、前記第３の制御手段は、前記交流電圧の極性が固定されている期間内において、複数の前記チョッピング動作位相幅又は複数の前記チョッピング休止位相幅があるときに、当該期間内のいずれかの位相幅、もしくは、合計の位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御することを特徴とする。 Further, in the rectifier circuit device, the third control means has a plurality of the chopping operation phase widths or a plurality of the chopping pause phase widths within a period in which the polarity of the AC voltage is fixed. The predetermined target DC voltage is controlled such that any one of the phase widths within the period or the total phase width is substantially the predetermined phase width.
　さらに、上記整流回路装置において、前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、
（ａ）当該期間の開始点から、所定の中間点までは、時間経過とともに、少なくとも増加し、もしくは少なくとも増加しかつ一部期間で一定であるように実質的に単調増加し、
（ｂ）前記中間点から終了点までに、時間経過とともに、少なくとも減少し、もしくは少なくとも減少しかつ一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定されたことを特徴とする。 Further, in the above rectifier circuit device, the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
(A) From the starting point of the period to the predetermined intermediate point, it increases at least over time, or at least increases and increases substantially at least monotonously so as to be constant over a period of time,
(B) A period from the intermediate point to the end point that has at least decreased with time, or at least decreased and substantially monotonically decreased to be constant in a certain period, and then has a period that becomes zero. It is characterized by being set.
　またさらに、上記整流回路装置において、前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、
（ａ）当該期間の開始点から、所定の第１の中間点までは、時間経過とともに、ゼロとなる期間を有し、
（ｂ）前記第１の中間点から所定の第２の中間点までは、少なくとも増加し、もしくは少なくとも増加しかつ一部期間で一定であるように実質的に単調増加し、
（ｃ）前記第２の中間点から終了点までに、時間経過とともに、少なくとも減少し、もしくは少なくとも減少しかつ一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定されたことを特徴とする。 Furthermore, in the rectifier circuit device, the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
(A) From the starting point of the period to the predetermined first intermediate point, there is a period that becomes zero with time,
(B) from the first intermediate point to the predetermined second intermediate point at least increases or at least increases and substantially monotonically increases to be constant over a period of time;
(C) from the second intermediate point to the end point, a time period that is at least decreased with time, or at least decreased and substantially monotonically decreased so as to be constant in a certain period, and then becomes zero. It is set to have.
　また、上記整流回路装置は、前記交流電圧を所定のしきい値電圧と比較することにより２値信号を発生する位相検出手段をさらに備え、
　前記波形形成手段は、前記２値信号に基づいて前記交流電圧の周期及び位相を検出し、当該検出された交流電圧の周期及び位相に基づいて、前記交流電圧の波形と同一周波数の目標電流波形を形成し、
　前記第３の制御手段は、前記２値信号に基づいて、前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、もしくは、前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅を検出することを特徴とする。 The rectifier circuit device further includes phase detection means for generating a binary signal by comparing the AC voltage with a predetermined threshold voltage,
The waveform forming means detects a period and a phase of the AC voltage based on the binary signal, and a target current waveform having the same frequency as the waveform of the AC voltage based on the detected period and phase of the AC voltage. Form the
The third control means detects, based on the binary signal, a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state. Features.
　さらに、前記整流回路装置はさらに、
　前記電圧検出手段と前記第２の制御手段との間に設けられ、前記検出された直流電圧をデジタル電圧にＡＤ変換するＡＤ変換手段と、
　前記ＡＤ変換手段と前記第２の制御手段との間に設けられ、前記デジタル電圧に対して低域フィルタ演算を行った後、当該演算結果の電圧を前記第２の制御手段に前記検出された直流電圧として出力する演算手段とを備えたことを特徴とする。 Furthermore, the rectifier circuit device further includes
AD conversion means provided between the voltage detection means and the second control means, and AD-converts the detected DC voltage into a digital voltage;
Provided between the AD conversion means and the second control means, and after performing a low-pass filter operation on the digital voltage, the voltage of the calculation result is detected by the second control means And an arithmetic means for outputting as a DC voltage.
　また、上記整流回路装置において、前記ＡＤ変換手段のサンプリング周波数は、前記単相交流電源の周波数よりも十分に高くなるように設定されたことを特徴とする。 Further, in the above rectifier circuit device, the sampling frequency of the AD conversion means is set to be sufficiently higher than the frequency of the single-phase AC power supply.
　さらに、上記整流回路装置において、前記低域通過フィルタ演算は、直前の演算結果に「（２ｎ－１）／（２ｎ）」なる係数（ｎは整数である。）を乗算した後、入力されたデジタル電圧と加算し、当該加算結果の値を次の演算結果として用いて実行されることを特徴とする。 Further, in the rectifier circuit device, the low-pass filter operation may be performed by multiplying the immediately preceding operation result by a coefficient “(2 n −1) / (2 n )” (n is an integer), It is characterized by being added to the digital voltage thus obtained and executed using the value of the addition result as the next calculation result.
　第２の発明に係る整流回路装置のための制御回路は、半導体スイッチをチョッピング動作させることにより、単相交流電源の出力端子をリアクタを介して短絡又は開放し、前記単相交流電源から前記リアクタを介して供給される交流電圧を直流電圧に整流して負荷に供給する整流回路装置のための制御回路において、
　上記制御回路は、
　前記交流電圧の波形と同一周波数の目標電流波形を形成する波形形成手段と、
　前記単相交流電源から流れる交流電流の波形が実質的に前記目標電流波形となるように前記半導体スイッチのチョッピング動作を制御する第１の制御手段と、
　前記直流電圧が実質的に所定の目標直流電圧となるように前記目標電流波形の振幅を制御する第２の制御手段と、
　前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、もしくは、前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御する第３の制御手段とを備えたことを特徴とする。 A control circuit for a rectifier circuit device according to a second aspect of the present invention short-circuits or opens an output terminal of a single-phase AC power source through a reactor by chopping a semiconductor switch, and the reactor is connected to the reactor from the single-phase AC power source. In a control circuit for a rectifier circuit device that rectifies an AC voltage supplied via a DC voltage and supplies it to a load,
The control circuit is
Waveform forming means for forming a target current waveform having the same frequency as the waveform of the AC voltage;
First control means for controlling a chopping operation of the semiconductor switch so that a waveform of an alternating current flowing from the single-phase alternating current power supply substantially becomes the target current waveform;
Second control means for controlling the amplitude of the target current waveform so that the DC voltage substantially becomes a predetermined target DC voltage;
The predetermined target DC voltage is controlled so that a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state is substantially a predetermined phase width. And third control means.
　上記制御回路において、前記所定の位相幅は、前記負荷の電気的特性に依存して変更して設定されることを特徴とする。ここで、前記負荷の電気的特性は、前記交流電流の変動幅、もしくは前記負荷が圧縮機であるときの圧縮機モータへの回転数指令であることを特徴とする。 The control circuit is characterized in that the predetermined phase width is changed and set depending on electrical characteristics of the load. Here, the electrical characteristic of the load is a fluctuation range of the alternating current or a rotational speed command to a compressor motor when the load is a compressor.
　また、上記制御回路において、前記第３の制御手段は、前記交流電圧の極性が固定されている期間内において、複数の前記チョッピング動作位相幅又は複数の前記チョッピング休止位相幅があるときに、当該期間内のいずれかの位相幅、もしくは、合計の位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御することを特徴とする。 Further, in the control circuit, the third control unit may be configured such that when there are a plurality of the chopping operation phase widths or a plurality of the chopping pause phase widths in a period in which the polarity of the AC voltage is fixed. The predetermined target DC voltage is controlled so that any one of the phase widths within the period or the total phase width becomes substantially the predetermined phase width.
　さらに、上記制御回路において、前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、
（ａ）当該期間の開始点から、所定の中間点までは、時間経過とともに、少なくとも増加し、もしくは少なくとも増加しかつ一部期間で一定であるように実質的に単調増加し、
（ｂ）前記中間点から終了点までに、時間経過とともに、少なくとも減少し、もしくは少なくとも減少しかつ一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定されたことを特徴とする。 Furthermore, in the control circuit, the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
(A) From the starting point of the period to the predetermined intermediate point, it increases at least over time, or at least increases and increases substantially at least monotonously so as to be constant over a period of time,
(B) A period from the intermediate point to the end point that has at least decreased with time, or at least decreased and substantially monotonically decreased to be constant in a certain period, and then has a period that becomes zero. It is characterized by being set.
　またさらに、上記制御回路において、前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、
（ａ）当該期間の開始点から、所定の第１の中間点までは、時間経過とともに、ゼロとなる期間を有し、
（ｂ）前記第１の中間点から所定の第２の中間点までは、少なくとも増加し、もしくは少なくとも増加しかつ一部期間で一定であるように実質的に単調増加し、
（ｃ）前記第２の中間点から終了点までに、時間経過とともに、少なくとも減少し、もしくは少なくとも減少しかつ一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定されたことを特徴とする。 Still further, in the control circuit, the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
(A) From the starting point of the period to the predetermined first intermediate point, there is a period that becomes zero with time,
(B) from the first intermediate point to the predetermined second intermediate point at least increases or at least increases and substantially monotonically increases to be constant over a period of time;
(C) from the second intermediate point to the end point, a time period that is at least decreased with time, or at least decreased and substantially monotonically decreased so as to be constant in a certain period, and then becomes zero. It is set to have.
　また、上記整流回路装置は、前記交流電圧を所定のしきい値電圧と比較することにより２値信号を発生する位相検出手段をさらに備え、
　前記波形形成手段は、前記２値信号に基づいて前記交流電圧の周期及び位相を検出し、当該検出された交流電圧の周期及び位相に基づいて、前記交流電圧の波形と同一周波数の目標電流波形を形成し、
　前記第３の制御手段は、前記２値信号に基づいて、前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、もしくは、前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅を検出することを特徴とする。 The rectifier circuit device further includes phase detection means for generating a binary signal by comparing the AC voltage with a predetermined threshold voltage,
The waveform forming means detects a period and a phase of the AC voltage based on the binary signal, and a target current waveform having the same frequency as the waveform of the AC voltage based on the detected period and phase of the AC voltage. Form the
The third control means detects, based on the binary signal, a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state. Features.
　さらに、前記制御回路はさらに、
　前記電圧検出手段と前記第２の制御手段との間に設けられ、前記直流電圧をデジタル電圧にＡＤ変換するＡＤ変換手段と、
　前記ＡＤ変換手段と前記第２の制御手段との間に設けられ、前記デジタル電圧に対して低域フィルタ演算を行った後、当該演算結果の電圧を前記第２の制御手段に前記直流電圧として出力する演算手段とを備えたことを特徴とする。 Further, the control circuit further includes
AD conversion means provided between the voltage detection means and the second control means, and AD-converts the DC voltage into a digital voltage;
Provided between the AD conversion means and the second control means, and after performing a low-pass filter operation on the digital voltage, the voltage of the calculation result is sent to the second control means as the DC voltage. And an arithmetic means for outputting.
　また、上記制御回路において、前記ＡＤ変換手段のサンプリング周波数は、前記単相交流電源の周波数よりも十分に高くなるように設定されたことを特徴とする。 In the above control circuit, the sampling frequency of the AD converter is set to be sufficiently higher than the frequency of the single-phase AC power supply.
　さらに、上記制御回路において、前記低域通過フィルタ演算は、直前の演算結果に「（２ｎ－１）／（２ｎ）」なる係数（ｎは整数である。）を乗算した後、入力されたデジタル電圧と加算し、当該加算結果の値を次の演算結果として用いて実行されることを特徴とする。 Further, in the above control circuit, the low-pass filter operation is input after the previous operation result is multiplied by a coefficient (n is an integer) of “(2 n −1) / (2 n )”. It is added to the digital voltage, and the value of the addition result is used as the next calculation result.
　従って、本発明によれば、直流電圧の検出精度に誤差があっても、直流電圧が相対的に適正な値に調整されて、同様の電流波形になり、かつ負荷の特性に応じて所望の位相幅を切り換えることで常に損失が少なく、かつ高調波電流が少ない整流動作が実現される。 Therefore, according to the present invention, even if there is an error in the detection accuracy of the DC voltage, the DC voltage is adjusted to a relatively appropriate value to obtain a similar current waveform, and a desired current according to the characteristics of the load. By switching the phase width, a rectification operation with always low loss and low harmonic current is realized.
　また、交流電源の周波数よりも十分に高いサンプリング周波数で、直流電圧をＡＤ変換手段により、デジタル信号に変換して検出し、得られたデジタル信号を前記周期毎にＬＰＦ演算を実行して、デジタル信号に分解能以下の微小情報を補間するように追加し、微小情報を補間したデジタル信号を直流電圧情報として、チョッピングが実際になされている位相幅が所望の値になるように、微小情報を補間したデジタル信号を調整する。直流電圧の平滑電圧に含まれている電源周波数成分の揺らぎがあり、デジタル情報の分解能が粗い場合でも、揺らぎによりデジタル信号が分散されるため、平均的には高い分解能と等価なデジタル信号を得ることができる。これによって、粗い分解能のＡＤ変換手段を用いても、直流電圧の平均値を高精度に調節することができ、常に損失が少なく、かつ、高調波電流が少ない整流動作が実現される。従って、本発明に係る整流回路装置は、接続された負荷の特性で入力電流が脈動する場合においても常に損失が少なく、かつ高調波電流が少ない整流動作を実現することができる。 In addition, a DC voltage is converted into a digital signal by an AD conversion means at a sampling frequency sufficiently higher than the frequency of the AC power supply, and the obtained digital signal is subjected to LPF calculation for each period, and digitally Interpolate minute information below resolution to interpolate minute information so that the digital signal interpolated with minute information is DC voltage information so that the phase width that is actually chopped is the desired value Adjust the digital signal. Even if there is fluctuations in the power supply frequency component included in the smoothing voltage of the DC voltage and the resolution of the digital information is rough, the digital signal is dispersed due to fluctuations, so a digital signal equivalent to a high resolution is obtained on average. be able to. As a result, the average value of the DC voltage can be adjusted with high accuracy even when using an A / D converter having a coarse resolution, and a rectification operation with always low loss and low harmonic current is realized. Therefore, the rectifier circuit device according to the present invention can always realize a rectification operation with little loss and less harmonic current even when the input current pulsates due to the characteristics of the connected load.
本発明の実施形態１に係る整流回路装置の構成を示す回路図である。It is a circuit diagram which shows the structure of the rectifier circuit apparatus which concerns on Embodiment 1 of this invention. 図１の制御回路１００の詳細構成を示すブロック図である。FIG. 2 is a block diagram illustrating a detailed configuration of a control circuit 100 in FIG. 1. 図１の制御回路１００の第１の動作例に係る制御動作を説明するための図であって、交流電圧（以下、ＡＣ電圧という。）と整流後の直流電圧（以下、ＤＣ電圧という。）との関係と、制御すべき目標電流波形と、実際に制御した後の交流電流（以下、ＡＣ電流という。）とを示す信号波形図である。It is a figure for demonstrating the control action which concerns on the 1st operation example of the control circuit 100 of FIG. 1, Comprising: AC voltage (henceforth AC voltage) and the DC voltage after rectification (henceforth DC voltage) And a target current waveform to be controlled, and an AC current after actual control (hereinafter referred to as AC current). 図１の制御回路１００の第２の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。It is a figure for demonstrating the control operation | movement which concerns on the 2nd operation example of the control circuit 100 of FIG. 1, Comprising: The relationship between AC voltage and DC voltage after rectification, the target current waveform to be controlled, and actual control It is a signal waveform diagram which shows AC current after having performed. 本発明の実施形態２に係る整流回路装置の制御回路１００の第３の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。It is a figure for demonstrating the control action which concerns on the 3rd operation example of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 2 of this invention, Comprising: The relationship between AC voltage and DC voltage after rectification, and control are performed. It is a signal waveform diagram which shows the target current waveform which should be, and AC current after actually controlling. 本発明の実施形態２に係る整流回路装置の制御回路１００の第４の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。It is a figure for demonstrating the control operation which concerns on the 4th operation example of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 2 of this invention, Comprising: The relationship between AC voltage and DC voltage after rectification, and control are performed. It is a signal waveform diagram which shows the target current waveform which should be, and AC current after actually controlling. 本発明の実施形態３に係る整流回路装置の制御回路１００の第５の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。It is a figure for demonstrating the control action which concerns on the 5th operation example of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 3 of this invention, Comprising: The relationship between AC voltage and DC voltage after rectification, and control are performed. It is a signal waveform diagram which shows the target current waveform which should be, and AC current after actually controlling. 本発明の実施形態３に係る整流回路装置の制御回路１００の第６の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。It is a figure for demonstrating the control operation which concerns on the 6th operation example of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 3 of this invention, Comprising: The relationship between AC voltage and DC voltage after rectification, and control are performed. It is a signal waveform diagram which shows the target current waveform which should be, and AC current after actually controlling. 本発明の実施形態４に係る整流回路装置の制御回路１００の第７の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。It is a figure for demonstrating the control action which concerns on the 7th operation example of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 4 of this invention, Comprising: The relationship between AC voltage and DC voltage after rectification, and control are performed. It is a signal waveform diagram which shows the target current waveform which should be, and AC current after actually controlling. 本発明の実施形態４に係る整流回路装置の制御回路１００の第８の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。It is a figure for demonstrating the control action which concerns on the 8th operation example of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 4 of this invention, Comprising: The relationship between AC voltage and DC voltage after rectification, and control are performed. It is a signal waveform diagram which shows the target current waveform which should be, and AC current after actually controlling. 本発明の実施形態５に係る整流回路装置の制御回路１００の第９の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。It is a figure for demonstrating the control action which concerns on the 9th operation example of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 5 of this invention, Comprising: The relationship between AC voltage and DC voltage after rectification, and control are performed. It is a signal waveform diagram which shows the target current waveform which should be, and AC current after actually controlling. 本発明の実施形態５に係る整流回路装置の制御回路１００の第１０の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。It is a figure for demonstrating the control operation | movement which concerns on the 10th operation example of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 5 of this invention, Comprising: The relationship between AC voltage and DC voltage after rectification | straightening is controlled. It is a signal waveform diagram which shows the target current waveform which should be, and AC current after actually controlling. 本発明の実施形態６に係る整流回路装置の構成を示す回路図である。It is a circuit diagram which shows the structure of the rectifier circuit apparatus which concerns on Embodiment 6 of this invention. 図８の制御回路１１１の詳細構成を示すブロック図である。It is a block diagram which shows the detailed structure of the control circuit 111 of FIG. 本発明の実施形態７に係る整流回路装置の構成を示す回路図である。It is a circuit diagram which shows the structure of the rectifier circuit apparatus which concerns on Embodiment 7 of this invention. 図８の制御回路１１２の詳細構成を示すブロック図である。It is a block diagram which shows the detailed structure of the control circuit 112 of FIG. 本発明の実施形態８に係る整流回路装置の制御回路１００の第１１の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。It is a figure for demonstrating the control action which concerns on the 11th operation example of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 8 of this invention, Comprising: The relationship between AC voltage and DC voltage after rectification, and control are performed. It is a signal waveform diagram which shows the target current waveform which should be, and AC current after actually controlling. 本発明の実施形態８に係る整流回路装置の制御回路１００の第１２の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。It is a figure for demonstrating the control action which concerns on the 12th operation example of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 8 of this invention, Comprising: The relationship between AC voltage and DC voltage after rectification, and control are performed. It is a signal waveform diagram which shows the target current waveform which should be, and AC current after actually controlling. 本発明の実施形態８に係る整流回路装置の制御回路１００の第１３の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。It is a figure for demonstrating the control action which concerns on the 13th operation example of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 8 of this invention, Comprising: The relationship between AC voltage and DC voltage after rectification, and control are performed. It is a signal waveform diagram which shows the target current waveform which should be, and AC current after actually controlling. 本発明の実施形態８に係る整流回路装置の制御回路１００の第１４の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。It is a figure for demonstrating the control action which concerns on the 14th operation example of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 8 of this invention, Comprising: The relationship between AC voltage and DC voltage after rectification, and control are performed. It is a signal waveform diagram which shows the target current waveform which should be, and AC current after actually controlling. 本発明の実施形態８に係る整流回路装置の制御回路１００の第１５の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。It is a figure for demonstrating the control operation | movement which concerns on the 15th operation example of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 8 of this invention, Comprising: The relationship between AC voltage and DC voltage after rectification, and control are performed. It is a signal waveform diagram which shows the target current waveform which should be, and AC current after actually controlling. 本発明の実施形態８に係る整流回路装置の制御回路１００の第１６の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。It is a figure for demonstrating the control action which concerns on the 16th operation example of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 8 of this invention, Comprising: The relationship between AC voltage and DC voltage after rectification, and control are performed. It is a signal waveform diagram which shows the target current waveform which should be, and AC current after actually controlling. 本発明の実施形態９に係る整流回路装置の構成を示す回路図である。It is a circuit diagram which shows the structure of the rectifier circuit apparatus which concerns on Embodiment 9 of this invention. 本発明の実施形態１０に係る整流回路装置の構成を示す回路図である。It is a circuit diagram which shows the structure of the rectifier circuit apparatus which concerns on Embodiment 10 of this invention. 本発明の実施形態１～１０に係る整流回路装置の電圧レベル比較器１０９の２値化処理の第１の動作例を説明するための図であって、ＡＣ電圧としきい値電圧Ｖｔｈとの関係と、電圧レベル比較器１０９からの２値信号とを示す信号波形図である。FIG. 9 is a diagram for explaining a first operation example of binarization processing of the voltage level comparator 109 of the rectifier circuit device according to the first to tenth embodiments of the present invention, and the relationship between the AC voltage and the threshold voltage Vth. And a signal waveform diagram showing a binary signal from the voltage level comparator 109. FIG. 本発明の実施形態１～１０に係る整流回路装置の電圧レベル比較器１０９の２値化処理の第２の動作例を説明するための図であって、ＡＣ電圧としきい値電圧Ｖｔｈとの関係と、電圧レベル比較器１０９からの２値信号とを示す信号波形図である。FIG. 10 is a diagram for explaining a second operation example of the binarization process of the voltage level comparator 109 of the rectifier circuit device according to Embodiments 1 to 10 of the present invention, and the relationship between the AC voltage and the threshold voltage Vth. And a signal waveform diagram showing a binary signal from the voltage level comparator 109. FIG. 本発明の実施形態１１に係る整流回路装置の制御回路１００の詳細構成を示すブロック図である。It is a block diagram which shows the detailed structure of the control circuit 100 of the rectifier circuit apparatus which concerns on Embodiment 11 of this invention. 図１７のローパスフィルタ演算器（以下、「ＬＰＦ演算器」という。）２３１の詳細構成を示すブロック図である。FIG. 18 is a block diagram showing a detailed configuration of a low-pass filter computing unit (hereinafter referred to as “LPF computing unit”) 231 in FIG. 17. 図１７の整流回路装置の動作を示す図であって、ＡＣ電源１からのＡＣ電流Ｉａｃと、ＤＣ電圧Ｖｄｃと、ＡＤ変換器２３０のＡＤ変換値Ｖａｄ（上記ＤＣ電圧Ｖｄｃを点線で示す。）とを示す信号波形図である。FIG. 18 is a diagram illustrating an operation of the rectifier circuit device of FIG. 17, in which an AC current Iac from the AC power source 1, a DC voltage Vdc, and an AD conversion value Vad of the AD converter 230 (the DC voltage Vdc is indicated by a dotted line). FIG. 従来技術に係る整流回路装置の構成を示す回路図である。It is a circuit diagram which shows the structure of the rectifier circuit apparatus based on a prior art. 図２０の制御部１３の詳細構成を示すブロック図である。It is a block diagram which shows the detailed structure of the control part 13 of FIG.
　以下、本発明に係る実施形態について図面を参照して説明する。なお、以下の各実施形態において、同様の構成要素については同一の符号を付している。 Embodiments according to the present invention will be described below with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.
　本発明の実施形態に係る整流回路装置は、
　半導体スイッチをチョッピング動作させることにより、単相交流電源の出力端子をリアクタを介して短絡又は開放し、前記単相交流電源から前記リアクタを介して供給される交流電圧を直流電圧に整流して負荷に供給する整流回路装置であって、
　前記交流電圧の波形と同一周波数の目標電流波形を形成する波形形成手段と、
　前記単相交流電源から流れる交流電流を検出する電流検出手段と、
　前記直流電圧を検出する電圧検出手段と、
　前記検出された交流電流の波形が実質的に前記目標電流波形となるように前記半導体スイッチのチョッピング動作を制御する第１の制御手段と、
　前記検出された直流電圧が実質的に所定の目標直流電圧となるように前記目標電流波形の振幅を制御する第２の制御手段と、
　前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、もしくは、前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御する第３の制御手段とを備えたことを特徴とする。 A rectifier circuit device according to an embodiment of the present invention includes:
By chopping the semiconductor switch, the output terminal of the single-phase AC power supply is short-circuited or opened via the reactor, and the AC voltage supplied from the single-phase AC power supply via the reactor is rectified into a DC voltage and loaded. A rectifier circuit device for supplying to
Waveform forming means for forming a target current waveform having the same frequency as the waveform of the AC voltage;
Current detecting means for detecting an alternating current flowing from the single-phase AC power source;
Voltage detecting means for detecting the DC voltage;
First control means for controlling the chopping operation of the semiconductor switch so that the waveform of the detected alternating current substantially becomes the target current waveform;
Second control means for controlling the amplitude of the target current waveform such that the detected DC voltage is substantially a predetermined target DC voltage;
The predetermined target DC voltage is controlled so that a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state is substantially a predetermined phase width. And third control means.
　上記整流回路装置において、前記所定の位相幅は、前記負荷の電気的特性に依存して変更して設定されることを特徴とする。ここで、前記負荷の電気的特性は、前記交流電流の変動幅、もしくは前記負荷が圧縮機であるときの圧縮機モータへの回転数指令であることを特徴とする。 In the rectifier circuit device, the predetermined phase width is set by being changed depending on an electrical characteristic of the load. Here, the electrical characteristic of the load is a fluctuation range of the alternating current or a rotational speed command to a compressor motor when the load is a compressor.
　また、上記整流回路装置において、前記第３の制御手段は、前記交流電圧の極性が固定されている期間内において、複数の前記チョッピング動作位相幅又は複数の前記チョッピング休止位相幅があるときに、当該期間内のいずれかの位相幅、もしくは、合計の位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御することを特徴とする。 Further, in the rectifier circuit device, the third control means has a plurality of the chopping operation phase widths or a plurality of the chopping pause phase widths within a period in which the polarity of the AC voltage is fixed. The predetermined target DC voltage is controlled such that any one of the phase widths within the period or the total phase width is substantially the predetermined phase width.
　さらに、上記整流回路装置において、前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、
（ａ）当該期間の開始点から、所定の中間点までは、時間経過とともに、少なくとも増加し、もしくは少なくとも増加しかつ一部期間で一定であるように実質的に単調増加し、
（ｂ）前記中間点から終了点までに、時間経過とともに、少なくとも減少し、もしくは少なくとも減少しかつ一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定されたことを特徴とする。 Further, in the above rectifier circuit device, the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
(A) From the starting point of the period to the predetermined intermediate point, it increases at least over time, or at least increases and increases substantially at least monotonously so as to be constant over a period of time,
(B) A period from the intermediate point to the end point that has at least decreased with time, or at least decreased and substantially monotonically decreased to be constant in a certain period, and then has a period that becomes zero. It is characterized by being set.
　またさらに、上記整流回路装置において、前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、
（ａ）当該期間の開始点から、所定の第１の中間点までは、時間経過とともに、ゼロとなる期間を有し、
（ｂ）前記第１の中間点から所定の第２の中間点までは、少なくとも増加し、もしくは少なくとも増加しかつ一部期間で一定であるように実質的に単調増加し、
（ｃ）前記第２の中間点から終了点までに、時間経過とともに、少なくとも減少し、もしくは少なくとも減少しかつ一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定されたことを特徴とする。 Furthermore, in the rectifier circuit device, the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
(A) From the starting point of the period to the predetermined first intermediate point, there is a period that becomes zero with time,
(B) from the first intermediate point to the predetermined second intermediate point at least increases or at least increases and substantially monotonically increases to be constant over a period of time;
(C) from the second intermediate point to the end point, a time period that is at least decreased with time, or at least decreased and substantially monotonically decreased so as to be constant in a certain period, and then becomes zero. It is set to have.
　また、上記整流回路装置は、前記交流電圧を所定のしきい値電圧と比較することにより２値信号を発生する位相検出手段をさらに備え、
　前記波形形成手段は、前記２値信号に基づいて前記交流電圧の周期及び位相を検出し、当該検出された交流電圧の周期及び位相に基づいて、前記交流電圧の波形と同一周波数の目標電流波形を形成し、
　前記第３の制御手段は、前記２値信号に基づいて、前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、もしくは、前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅を検出することを特徴とする。 The rectifier circuit device further includes phase detection means for generating a binary signal by comparing the AC voltage with a predetermined threshold voltage,
The waveform forming means detects a period and a phase of the AC voltage based on the binary signal, and a target current waveform having the same frequency as the waveform of the AC voltage based on the detected period and phase of the AC voltage. Form the
The third control means detects, based on the binary signal, a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state. Features.
　さらに、前記整流回路装置はさらに、
　前記電圧検出手段と前記第２の制御手段との間に設けられ、前記検出された直流電圧をデジタル電圧にＡＤ変換するＡＤ変換手段と、
　前記ＡＤ変換手段と前記第２の制御手段との間に設けられ、前記デジタル電圧に対して低域フィルタ演算を行った後、当該演算結果の電圧を前記第２の制御手段に前記検出された直流電圧として出力する演算手段とを備えたことを特徴とする。 Furthermore, the rectifier circuit device further includes
AD conversion means provided between the voltage detection means and the second control means, and AD-converts the detected DC voltage into a digital voltage;
Provided between the AD conversion means and the second control means, and after performing a low-pass filter operation on the digital voltage, the voltage of the calculation result is detected by the second control means And an arithmetic means for outputting as a DC voltage.
　また、上記整流回路装置において、前記ＡＤ変換手段のサンプリング周波数は、前記単相交流電源の周波数よりも十分に高くなるように設定されたことを特徴とする。 Further, in the above rectifier circuit device, the sampling frequency of the AD conversion means is set to be sufficiently higher than the frequency of the single-phase AC power supply.
　さらに、上記整流回路装置において、前記低域通過フィルタ演算は、直前の演算結果に「（２ｎ－１）／（２ｎ）」なる係数（ｎは整数である。）を乗算した後、入力されたデジタル電圧と加算し、当該加算結果の値を次の演算結果として用いて実行されることを特徴とする。 Further, in the rectifier circuit device, the low-pass filter operation may be performed by multiplying the immediately preceding operation result by a coefficient “(2 n −1) / (2 n )” (n is an integer), It is characterized by being added to the digital voltage thus obtained and executed using the value of the addition result as the next calculation result.
　また、本発明の実施形態に係る、整流回路装置のための制御回路は、半導体スイッチをチョッピング動作させることにより、単相交流電源の出力端子をリアクタを介して短絡又は開放し、前記単相交流電源から前記リアクタを介して供給される交流電圧を直流電圧に整流して負荷に供給する整流回路装置のための制御回路において、
　上記制御回路は、
　前記交流電圧の波形と同一周波数の目標電流波形を形成する波形形成手段と、
　前記単相交流電源から流れる交流電流の波形が実質的に前記目標電流波形となるように前記半導体スイッチのチョッピング動作を制御する第１の制御手段と、
　前記直流電圧が実質的に所定の目標直流電圧となるように前記目標電流波形の振幅を制御する第２の制御手段と、
　前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、もしくは、前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御する第３の制御手段とを備えたことを特徴とする。 Further, the control circuit for the rectifier circuit device according to the embodiment of the present invention short-circuits or opens the output terminal of the single-phase AC power source through the reactor by chopping the semiconductor switch, and the single-phase AC In a control circuit for a rectifier circuit device that rectifies an AC voltage supplied from a power source through the reactor to a DC voltage and supplies the DC voltage to a load,
The control circuit is
Waveform forming means for forming a target current waveform having the same frequency as the waveform of the AC voltage;
First control means for controlling a chopping operation of the semiconductor switch so that a waveform of an alternating current flowing from the single-phase alternating current power supply substantially becomes the target current waveform;
Second control means for controlling the amplitude of the target current waveform so that the DC voltage substantially becomes a predetermined target DC voltage;
The predetermined target DC voltage is controlled so that a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state is substantially a predetermined phase width. And third control means.
　上記制御回路において、前記所定の位相幅は、前記負荷の電気的特性に依存して変更して設定されることを特徴とする。ここで、前記負荷の電気的特性は、前記交流電流の変動幅、もしくは前記負荷が圧縮機であるときの圧縮機モータへの回転数指令であることを特徴とする。 The control circuit is characterized in that the predetermined phase width is changed and set depending on electrical characteristics of the load. Here, the electrical characteristic of the load is a fluctuation range of the alternating current or a rotational speed command to a compressor motor when the load is a compressor.
　また、上記制御回路において、前記第３の制御手段は、前記交流電圧の極性が固定されている期間内において、複数の前記チョッピング動作位相幅又は複数の前記チョッピング休止位相幅があるときに、当該期間内のいずれかの位相幅、もしくは、合計の位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御することを特徴とする。 Further, in the control circuit, the third control unit may be configured such that when there are a plurality of the chopping operation phase widths or a plurality of the chopping pause phase widths in a period in which the polarity of the AC voltage is fixed. The predetermined target DC voltage is controlled so that any one of the phase widths within the period or the total phase width becomes substantially the predetermined phase width.
　さらに、上記制御回路において、前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、
（ａ）当該期間の開始点から、所定の中間点までは、時間経過とともに、少なくとも増加し、もしくは少なくとも増加しかつ一部期間で一定であるように実質的に単調増加し、
（ｂ）前記中間点から終了点までに、時間経過とともに、少なくとも減少し、もしくは少なくとも減少しかつ一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定されたことを特徴とする。 Furthermore, in the control circuit, the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
(A) From the starting point of the period to the predetermined intermediate point, it increases at least over time, or at least increases and increases substantially at least monotonously so as to be constant over a period of time,
(B) A period from the intermediate point to the end point that has at least decreased with time, or at least decreased and substantially monotonically decreased to be constant in a certain period, and then has a period that becomes zero. It is characterized by being set.
　またさらに、上記制御回路において、前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、
（ａ）当該期間の開始点から、所定の第１の中間点までは、時間経過とともに、ゼロとなる期間を有し、
（ｂ）前記第１の中間点から所定の第２の中間点までは、少なくとも増加し、もしくは少なくとも増加しかつ一部期間で一定であるように実質的に単調増加し、
（ｃ）前記第２の中間点から終了点までに、時間経過とともに、少なくとも減少し、もしくは少なくとも減少しかつ一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定されたことを特徴とする。 Still further, in the control circuit, the target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
(A) From the starting point of the period to the predetermined first intermediate point, there is a period that becomes zero with time,
(B) from the first intermediate point to the predetermined second intermediate point at least increases or at least increases and substantially monotonically increases to be constant over a period of time;
(C) from the second intermediate point to the end point, a time period that is at least decreased with time, or at least decreased and substantially monotonically decreased so as to be constant in a certain period, and then becomes zero. It is set to have.
　また、上記整流回路装置は、前記交流電圧を所定のしきい値電圧と比較することにより２値信号を発生する位相検出手段をさらに備え、
　前記波形形成手段は、前記２値信号に基づいて前記交流電圧の周期及び位相を検出し、当該検出された交流電圧の周期及び位相に基づいて、前記交流電圧の波形と同一周波数の目標電流波形を形成し、
　前記第３の制御手段は、前記２値信号に基づいて、前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、もしくは、前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅を検出することを特徴とする。 The rectifier circuit device further includes phase detection means for generating a binary signal by comparing the AC voltage with a predetermined threshold voltage,
The waveform forming means detects a period and a phase of the AC voltage based on the binary signal, and a target current waveform having the same frequency as the waveform of the AC voltage based on the detected period and phase of the AC voltage. Form the
The third control means detects, based on the binary signal, a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state. Features.
　さらに、前記制御回路はさらに、
　前記電圧検出手段と前記第２の制御手段との間に設けられ、前記直流電圧をデジタル電圧にＡＤ変換するＡＤ変換手段と、
　前記ＡＤ変換手段と前記第２の制御手段との間に設けられ、前記デジタル電圧に対して低域フィルタ演算を行った後、当該演算結果の電圧を前記第２の制御手段に前記直流電圧として出力する演算手段とを備えたことを特徴とする。 Further, the control circuit further includes
AD conversion means provided between the voltage detection means and the second control means, and AD-converts the DC voltage into a digital voltage;
Provided between the AD conversion means and the second control means, and after performing a low-pass filter operation on the digital voltage, the voltage of the calculation result is sent to the second control means as the DC voltage. And an arithmetic means for outputting.
　また、上記制御回路において、前記ＡＤ変換手段のサンプリング周波数は、前記単相交流電源の周波数よりも十分に高くなるように設定されたことを特徴とする。 In the above control circuit, the sampling frequency of the AD converter is set to be sufficiently higher than the frequency of the single-phase AC power supply.
　さらに、上記制御回路において、前記低域通過フィルタ演算は、直前の演算結果に「（２ｎ－１）／（２ｎ）」なる係数（ｎは整数である。）を乗算した後、入力されたデジタル電圧と加算し、当該加算結果の値を次の演算結果として用いて実行されることを特徴とする。 Further, in the above control circuit, the low-pass filter operation is input after the previous operation result is multiplied by a coefficient (n is an integer) of “(2 n −1) / (2 n )”. It is added to the digital voltage, and the value of the addition result is used as the next calculation result.
　従って、本発明の実施形態によれば、直流電圧の検出精度に誤差があっても、直流電圧が相対的に適正な値に調整されて、同様の電流波形になり、かつ負荷の特性に応じて所望の位相幅を切り換えることで常に損失が少なく、かつ高調波電流が少ない整流動作が実現される。 Therefore, according to the embodiment of the present invention, even if there is an error in the detection accuracy of the DC voltage, the DC voltage is adjusted to a relatively appropriate value to obtain a similar current waveform and according to the characteristics of the load. By switching the desired phase width, a rectification operation with always low loss and low harmonic current is realized.
　また、交流電源の周波数よりも十分に高いサンプリング周波数で、直流電圧をＡＤ変換手段により、デジタル信号に変換して検出し、得られたデジタル信号を前記周期毎にＬＰＦ演算を実行して、デジタル信号に分解能以下の微小情報を補間するように追加し、微小情報を補間したデジタル信号を直流電圧情報として、チョッピングが実際になされている位相幅が所望の値になるように、微小情報を補間したデジタル信号を調整する。直流電圧の平滑電圧に含まれている電源周波数成分の揺らぎがあり、デジタル情報の分解能が粗い場合でも、揺らぎによりデジタル信号が分散されるため、平均的には高い分解能と等価なデジタル信号を得ることができる。これによって、粗い分解能のＡＤ変換手段を用いても、直流電圧の平均値を高精度に調節することができ、常に損失が少なく、かつ、高調波電流が少ない整流動作が実現される。従って、本発明に係る整流回路装置は、接続された負荷の特性で入力電流が脈動する場合においても常に損失が少なく、かつ高調波電流が少ない整流動作を実現することができる。 In addition, a DC voltage is converted into a digital signal by an AD conversion means at a sampling frequency sufficiently higher than the frequency of the AC power supply, and the obtained digital signal is subjected to LPF calculation for each period, and digitally Interpolate minute information below resolution to interpolate minute information so that the digital signal interpolated with minute information is DC voltage information so that the phase width that is actually chopped is the desired value Adjust the digital signal. Even if there is fluctuations in the power supply frequency component included in the smoothing voltage of the DC voltage and the resolution of the digital information is rough, the digital signal is dispersed due to fluctuations, so a digital signal equivalent to a high resolution is obtained on average. be able to. As a result, the average value of the DC voltage can be adjusted with high accuracy even when using an A / D converter having a coarse resolution, and a rectification operation with always low loss and low harmonic current is realized. Therefore, the rectifier circuit device according to the present invention can always realize a rectification operation with little loss and less harmonic current even when the input current pulsates due to the characteristics of the connected load.
　以下、本発明の実施形態について、図面を参照しながら説明する。なお、この実施形態によって本発明が限定されない。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, this invention is not limited by this embodiment.
実施形態１．
　図１は本発明の実施形態１に係る整流回路装置の構成を示す回路図である。 Embodiment 1. FIG.
FIG. 1 is a circuit diagram showing a configuration of a rectifier circuit device according to Embodiment 1 of the present invention.
　図１において、単相のＡＣ電源１の両出力端子を、リアクタ１０２を介して半導体スイッチ１０４により短絡することで１つのループを構成する。電流検出器１０３は、そのループの電流を検出し、検出された電流値Ｉａｃを示す信号を制御回路１００に出力する。半導体スイッチ１０４をオンすると、リアクタ１０２の電流は増加する一方、半導体スイッチ１０４をオフすると、リアクタ１０２を流れていた電流はダイオードブリッジ１０５にて整流されて、その整流された電流は平滑コンデンサ１０６及び負荷４に流れ込み、負荷４を駆動する。負荷４へ印加される平滑コンデンサ１０６の両端のＤＣ電圧ＶｄｃはＤＣ電圧検出器１１０により検出され、ＤＣ電圧検出器１１０は検出されたＤＣ電圧Ｖｄｃを示す信号を制御回路１００に出力する。 1, a single loop is formed by short-circuiting both output terminals of the single-phase AC power supply 1 by the semiconductor switch 104 via the reactor 102. The current detector 103 detects the current of the loop and outputs a signal indicating the detected current value Iac to the control circuit 100. When the semiconductor switch 104 is turned on, the current in the reactor 102 increases. On the other hand, when the semiconductor switch 104 is turned off, the current flowing through the reactor 102 is rectified by the diode bridge 105, and the rectified current is It flows into the load 4 and drives the load 4. The DC voltage Vdc across the smoothing capacitor 106 applied to the load 4 is detected by the DC voltage detector 110, and the DC voltage detector 110 outputs a signal indicating the detected DC voltage Vdc to the control circuit 100.
　また、電圧レベル比較器１０９は交流電源１のＡＣ電圧レベルを所定のしきい値電圧と比較することにより当該しきい値電圧以上であるか否かを示す２値信号Ｓｃｏｍを発生して制御回路１００に出力する。制御回路１００は、２値信号Ｓｃｏｍに基づいて、その周期及び位相に基づいて、交流電源１から出力されるＡＣ電圧の位相を検出し、検出されたＡＣ電圧の位相に基づいて、ＡＣ電圧と実質的に同一の周波数であってＡＣ電圧と相似形状を有する目標電流波形を生成し、電流検出器１０３により検出されるＩａｃが上記生成した目標電流波形の相似形状に漸近するように半導体スイッチ１０４をチョッピング動作させるように制御することを特徴としている。 The voltage level comparator 109 compares the AC voltage level of the AC power supply 1 with a predetermined threshold voltage to generate a binary signal Scom indicating whether or not the threshold voltage is higher than the threshold voltage. Output to 100. Based on the binary signal Scom, the control circuit 100 detects the phase of the AC voltage output from the AC power supply 1 based on the cycle and phase, and determines the AC voltage based on the detected phase of the AC voltage. The semiconductor switch 104 generates a target current waveform having a shape that is substantially the same frequency and similar to the AC voltage, and the Iac detected by the current detector 103 approaches the similar shape of the generated target current waveform. It is characterized in that it is controlled to perform a chopping operation.
　さらに、制御回路１００は、ＤＣ電圧検出器１１０により検出されたＤＣ電圧Ｖｄｃが、制御回路１００内で設定された所望の電圧になるように、その偏差に応じて、生成する目標電流波形の相似比率を調整する。ここで、制御回路１００は、実際のＤＣ電圧が所望の電圧より低ければ、目標電流指令の相似比率を増大させて、大きな電流になるように制御し、実際のＤＣ電圧が所望のＤＣ電圧よりも高ければ、小さな電流になるように制御を行う。また、制御回路１００は、半導体スイッチ１０４のチョッピング状態に基づいて、半導体スイッチ１０４をパルス幅変調（以下、「ＰＷＭ」という。）駆動している位相幅を検出し、その位相幅と所望の値との偏差を検出し、当該偏差に応じて前記所望のＤＣ電圧値を調整する。 Furthermore, the control circuit 100 resembles the target current waveform to be generated according to the deviation so that the DC voltage Vdc detected by the DC voltage detector 110 becomes a desired voltage set in the control circuit 100. Adjust the ratio. Here, if the actual DC voltage is lower than the desired voltage, the control circuit 100 increases the similarity ratio of the target current command so as to obtain a large current, and the actual DC voltage is higher than the desired DC voltage. If it is higher, control is performed so that a small current is obtained. Further, the control circuit 100 detects the phase width that drives the semiconductor switch 104 by pulse width modulation (hereinafter referred to as “PWM”) based on the chopping state of the semiconductor switch 104, and the phase width and a desired value are detected. And the desired DC voltage value is adjusted according to the deviation.
　図２は図１の制御回路１００の詳細構成を示すブロック図である。図２の制御回路１００において、当該制御システムの最終制御目標は、チョッピング駆動がなされているチョッピング動作位相幅θｗＯＮを所望の位相幅θｗＯＮ ＊に制御することである。まず、ＡＣ電圧位相検出器２０１は、ＡＣ電源１の電圧レベルを所定のしきい値電圧Ｖｔｈと比較することにより２値化した２値信号Ｓｃｏｍに基づいて、ＡＣ位相を検出し、検出したＡＣ位相を示す信号を目標電流波形形成器２０２及びチョッピング位相幅検出器２１２に出力する。なお、ＡＣ電圧位相検出器２０１の具体的な動作は詳細後述する。次いで、目標電流波形形成器２０２は上記ＡＣ位相を示す信号に基づいて、詳細後述する所定の目標電流波形を発生して乗算器２０８に出力する。 FIG. 2 is a block diagram showing a detailed configuration of the control circuit 100 of FIG. In the control circuit 100 of FIG. 2, the final control target of the control system is to control the chopping operation phase width θw ON in which chopping driving is performed to a desired phase width θw ON * . First, the AC voltage phase detector 201 detects the AC phase based on the binary signal Scom binarized by comparing the voltage level of the AC power source 1 with a predetermined threshold voltage Vth, and detects the detected AC A signal indicating the phase is output to the target current waveform former 202 and the chopping phase width detector 212. The specific operation of the AC voltage phase detector 201 will be described later in detail. Next, the target current waveform former 202 generates a predetermined target current waveform, which will be described later in detail, based on the signal indicating the AC phase, and outputs it to the multiplier 208.
　チョッピング位相幅検出器２１２は、Ｉａｃ補償演算器２１０からＰＷＭ変調器２１１に出力される半導体スイッチ１０４に対するチョッピング駆動信号Ｓｃｈに基づいて、ＡＣ電圧位相検出器２０１からの信号が示すＡＣ電圧の位相を基準として、チョッピング状態である位相幅（以下、「チョッピング動作位相幅」又は、単に「チョッピング位相幅」という。）θｗＯＮを検出して、チョッピング位相幅θｗＯＮを示す信号を減算器２０４に出力する。一方、目標位相幅設定器２０３は予め設定されて格納された所望のチョッピング位相幅θｗＯＮ ＊を示す信号を減算器２０４に出力する。減算器２０４はいわゆる位相比較器であり、実際のチョッピング位相幅θｗＯＮから所望のチョッピング位相幅θｗＯＮ ＊を減算することによりその位相幅の偏差を演算して当該偏差を示す信号を位相幅補償演算器２０５に出力する。位相幅補償演算器２０５は、ＰＷＭ駆動状態の位相幅を安定に保つための所定の補償演算を行うことにより、当該整流回路装置により出力すべきＤＣ電圧の指令電圧Ｖｄｃ＊を発生して当該指令電圧Ｖｄｃ＊を示す信号を減算器２０６に出力する。一方、ＤＣ電圧検出器１１０により検出された実際の出力ＤＣ電圧Ｖｄｃを示す信号は減算器２０６に入力される。 The chopping phase width detector 212 determines the phase of the AC voltage indicated by the signal from the AC voltage phase detector 201 based on the chopping drive signal Sch for the semiconductor switch 104 output from the Iac compensation calculator 210 to the PWM modulator 211. As a reference, a phase width in the chopping state (hereinafter referred to as “chopping operation phase width” or simply “chopping phase width”) θw ON is detected, and a signal indicating the chopping phase width θw ON is output to the subtractor 204 To do. On the other hand, the target phase width setting unit 203 outputs a signal indicating a desired chopping phase width θw ON * that is set and stored in advance to the subtracter 204. The subtractor 204 is a so-called phase comparator, which calculates the deviation of the phase width by subtracting the desired chopping phase width θw ON * from the actual chopping phase width θw ON and compensates the signal indicating the deviation with the phase width compensation The result is output to the calculator 205. The phase width compensation calculator 205 generates a command voltage Vdc * of a DC voltage to be output by the rectifier circuit device by performing a predetermined compensation calculation for keeping the phase width in the PWM driving state stable. A signal indicating the voltage Vdc * is output to the subtractor 206. On the other hand, a signal indicating the actual output DC voltage Vdc detected by the DC voltage detector 110 is input to the subtractor 206.
　減算器２０６は、ＤＣ電圧の指令電圧Ｖｄｃ＊から実際の出力ＤＣ電圧Ｖｄｃを減算することにより電圧偏差を演算し、電圧偏差を示す信号を発生してＶｄｃ補償演算器２０７に出力する。補償演算器２０７は、実際のＤＣ電圧Ｖｄｃが指令電圧Ｖｄｃ＊と実質的に一致しかつ安定になるための補償演算を実行することにより補償演算後の電圧偏差を示す信号を乗算器２０８に出力する。乗算器２０８は、目標電流波形形成器２０２からの目標電流波形に対して補償演算後の電圧偏差を乗算し、乗算結果である瞬時の電流指令値Ｉａｃ＊を発生して減算器２０９に出力する。乗算器２０８の動作では、実際の電圧Ｖｄｃが指令電圧Ｖｄｃ＊よりも低いとき、目標電流波形の振幅を増大させる一方、実際の電圧Ｖｄｃが指令電圧Ｖｄｃ＊よりも高いとき、目標電流波形の振幅を減少させる。 The subtractor 206 calculates the voltage deviation by subtracting the actual output DC voltage Vdc from the DC voltage command voltage Vdc * , generates a signal indicating the voltage deviation, and outputs the signal to the Vdc compensation calculator 207. The compensation calculator 207 outputs a signal indicating the voltage deviation after the compensation calculation to the multiplier 208 by executing a compensation calculation for the actual DC voltage Vdc to substantially match the command voltage Vdc * and become stable. To do. The multiplier 208 multiplies the target current waveform from the target current waveform former 202 by the voltage deviation after the compensation calculation, generates an instantaneous current command value Iac * as a multiplication result, and outputs it to the subtracter 209. . In the operation of the multiplier 208, when the actual voltage Vdc is lower than the command voltage Vdc * , the amplitude of the target current waveform is increased, while when the actual voltage Vdc is higher than the command voltage Vdc * , the amplitude of the target current waveform. Decrease.
　減算器２０９は、瞬時の電流指令値Ｉａｃ＊から、電流検出器１０３により検出された実際の電流値Ｉａｃを減算することにより、減算結果である電流偏差を示す信号をＩａｃ補償演算器２１０に出力する。Ｉａｃ補償演算器２１０は、ＡＣ電源１から入力される電流が電流指令値Ｉａｃ＊に安定かつ速やかに実質的に一致するように所定の補償演算を行って、補償演算後の電流偏差を示す信号をＰＷＭ変調器２１１及びチョッピング位相幅検出器２１２に出力する。ＰＷＭ変調器２１１は入力される信号が示す補償演算後の電流偏差に対してＰＷＭ変調することにより、半導体スイッチ１０４をオンオフするためのチョッピング駆動信号Ｓｃｈを発生して半導体スイッチ１０４に出力する。一方、チョッピング位相幅検出器２１２は、上述のように、Ｉａｃ補償演算器２１０からＰＷＭ変調器２１１に出力される半導体スイッチ１０４に対するチョッピング駆動信号Ｓｃｈに基づいて、ＡＣ電圧位相検出器２０１からの信号が示すＡＣ電圧の位相を基準として、チョッピング位相幅θｗＯＮを検出して、チョッピング位相幅θｗＯＮを示す信号を減算器２０４に出力する。これにより、チョッピング位相幅の制御ループが構成される。 The subtractor 209 subtracts the actual current value Iac detected by the current detector 103 from the instantaneous current command value Iac * , thereby outputting a signal indicating the current deviation as a subtraction result to the Iac compensation calculator 210. To do. The Iac compensation calculator 210 performs a predetermined compensation calculation so that the current input from the AC power supply 1 substantially and stably matches the current command value Iac * , and indicates a current deviation after the compensation calculation. Are output to the PWM modulator 211 and the chopping phase width detector 212. The PWM modulator 211 generates a chopping drive signal Sch for turning on and off the semiconductor switch 104 and outputs it to the semiconductor switch 104 by performing PWM modulation on the current deviation after compensation calculation indicated by the input signal. On the other hand, the chopping phase width detector 212 receives the signal from the AC voltage phase detector 201 based on the chopping drive signal Sch for the semiconductor switch 104 output from the Iac compensation calculator 210 to the PWM modulator 211 as described above. relative to the phase of the AC voltage indicated detects the chopping phase width .theta.w oN, and outputs a signal indicating the chopping phase width .theta.w oN to the subtractor 204. Thereby, a control loop of the chopping phase width is configured.
　以上のように構成された、半導体スイッチ１０４をチョッピング駆動制御する制御回路１００においては、図２の減算器２０４よりも右側のループ（２０４から２０５，２０６，２０７，２０８，２０９，２１０，２１２を介して２０４に戻るループをいう。）において、チョッピング位相幅検出器２１２により検出されたチョッピング位相幅が目標位相幅設定器２０３により設定された目標位相幅に実質的に一致するようにＤＣ電圧Ｖｄｃが制御される。また、図２の減算器２０６よりも右側のループ（２０６から２０７，２０８，２０９，２１０，２１１，１０４，１１０を介して２０６に戻るループをいう。）において、ＤＣ電圧検出器１１０により検出されたＤＣ電圧Ｖｄｃが位相幅補償演算器２０５により示される所望のＤＣ電圧Ｖｄｃ＊と実質的に一致するように目標電流の振幅が制御されてチョッピング駆動制御される。さらに、図２の減算器２０９よりも右側のループ（２０９から２１０，２１１，１０４，１０３を介して２０９に戻るループをいう。）において、電流検出器１０３により検出された電流Ｉａｃが目標電流波形形成器２０２により形成された目標電流波形に基づいて発生された目標電流Ｉａｃ＊に実質的に一致するようにチョッピング駆動制御される。 In the control circuit 100 configured as described above for chopping drive control of the semiconductor switch 104, the loops (204 to 205, 206, 207, 208, 209, 210, 212 on the right side of the subtractor 204 in FIG. The DC voltage Vdc so that the chopping phase width detected by the chopping phase width detector 212 substantially matches the target phase width set by the target phase width setting unit 203. Is controlled. 2 is detected by the DC voltage detector 110 in a loop on the right side of the subtracter 206 in FIG. 2 (refers to a loop returning from 206 to 206 through 206, 207, 208, 209, 210, 211, 104, 110). The chopping drive control is performed by controlling the amplitude of the target current so that the DC voltage Vdc substantially matches the desired DC voltage Vdc * indicated by the phase width compensation calculator 205. Further, in a loop on the right side of the subtracter 209 in FIG. 2 (referring to a loop returning from 209 to 209 through 210, 211, 104, 103), the current Iac detected by the current detector 103 is a target current waveform. The chopping drive control is performed so as to substantially match the target current Iac * generated based on the target current waveform formed by the former 202.
　図３Ａは図１の制御回路１００の第１の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。また、図３Ｂは図１の制御回路１００の第２の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。 FIG. 3A is a diagram for explaining the control operation according to the first operation example of the control circuit 100 of FIG. 1, in which the relationship between the AC voltage and the DC voltage after rectification, the target current waveform to be controlled, It is a signal waveform diagram which shows AC current after actually controlling. FIG. 3B is a diagram for explaining the control operation according to the second operation example of the control circuit 100 of FIG. 1, and the relationship between the AC voltage and the DC voltage after rectification, and the target current waveform to be controlled. FIG. 6 is a signal waveform diagram showing AC current after actual control.
　図３Ａの第１の動作例は、出力されるＤＣ電圧が比較的低く、半導体スイッチ１０４に対するチョッピング位相幅（例えば、最小の位相幅）θｗＯＮが所望の位相幅θｗＯＮ ＊よりも小さくなっている場合である。このときには、ＡＣ電圧がＤＣ電圧より高い位相期間が増加するので、ＡＣ電源１からリアクタ１０２とダイオードブリッジ１０５を経由してＤＣ側へと流れ込む電流が増加する。このため、ＡＣ電流の波形が先鋭になり、ＡＣ電流の高調波成分が増加する。 In the first operation example of FIG. 3A, the output DC voltage is relatively low, and the chopping phase width (for example, the minimum phase width) θw ON for the semiconductor switch 104 is smaller than the desired phase width θw ON *. This is the case. At this time, since the phase period in which the AC voltage is higher than the DC voltage increases, the current flowing from the AC power source 1 to the DC side via the reactor 102 and the diode bridge 105 increases. For this reason, the waveform of the AC current becomes sharp, and the harmonic component of the AC current increases.
　一方、図３Ｂの第２の動作例は、出力されるＤＣ電圧が比較的高く、半導体スイッチ１０４に対するチョッピング位相幅（例えば、最大の位相幅）θｗＯＮが所望の位相幅θｗＯＮ ＊よりも大きくなっている場合である。このときには、ＡＣ電圧がＤＣ電圧より高い位相期間が第１の動作例に比較して減少するので、ＡＣ電源１からリアクタ１０２とダイオードブリッジ１０５を経由してＤＣ側へと流れ込む電流も減少し、ＡＣ電流の高調波成分が減少する。しかし、図３Ａの第１の動作例での波形に比べて、半導体スイッチ１０４に対するチョッピングが行われている期間が増加しているため、回路の損失が増加してしまう。 On the other hand, in the second operation example of FIG. 3B, the output DC voltage is relatively high, and the chopping phase width (for example, the maximum phase width) θw ON for the semiconductor switch 104 is larger than the desired phase width θw ON *. This is the case. At this time, since the phase period in which the AC voltage is higher than the DC voltage is reduced as compared with the first operation example, the current flowing from the AC power source 1 through the reactor 102 and the diode bridge 105 to the DC side is also reduced. The harmonic component of the AC current is reduced. However, since the period during which chopping is performed on the semiconductor switch 104 is increased as compared with the waveform in the first operation example of FIG. 3A, the loss of the circuit increases.
　ここで、ＡＣ電源１からのＡＣ電圧にひずみが含まれていると、ＡＣ電圧の半周期の間にチョッピングがなされている区間が複数回数出現することがあるが、その場合には、チョッピング位相幅検出器２１２は、ＡＣ電圧の位相の０度又は１８０度に近いチョッピング位相幅を制御用チョッピング位相幅として選択して当該チョッピング制御を行ってもよい。また、チョッピング位相幅検出器２１２は、ＡＣ電圧の位相の０度又は１８０度の代わりに、ＡＣ電流又はＡＣ電圧の極性を判定している基準位相に近いほうの位相幅を制御用チョッピング位相幅として選択して当該チョッピング制御を行ってもよい。さらに、チョッピング位相幅検出器２１２は、上記複数個得られたチョッピング位相幅を加算し、加算結果の位相幅を制御用チョッピング位相幅として当該チョッピング制御を行ってもよい。このように構成しても同様の作用効果を有する。 Here, when distortion is included in the AC voltage from the AC power supply 1, a section where chopping is performed may appear a plurality of times during a half cycle of the AC voltage. In this case, the chopping phase The width detector 212 may perform the chopping control by selecting a chopping phase width close to 0 degree or 180 degrees of the phase of the AC voltage as the control chopping phase width. Further, the chopping phase width detector 212 uses the phase width closer to the reference phase for determining the polarity of the AC current or the AC voltage instead of 0 degree or 180 degrees of the AC voltage phase as the control chopping phase width. And the chopping control may be performed. Further, the chopping phase width detector 212 may perform the chopping control by adding the obtained chopping phase widths and setting the phase width of the addition result as a control chopping phase width. Even if comprised in this way, it has the same effect.
実施形態２．
　実施形態１では、チョッピングしている位相幅θｗＯＮを検出し、ＤＣ電圧指令Ｖｄｃ＊を調整しているが、実施形態２では、チョッピングが休止状態になっている位相幅（以下、「チョッピング休止位相幅」という。）θｗＯＦＦを検出し、ＤＣ電圧指令Ｖｄｃを調整することで同様の作用効果を得ることを特徴としている。 Embodiment 2. FIG.
In the first embodiment, the chopping phase width θw ON is detected and the DC voltage command Vdc * is adjusted. However, in the second embodiment, the phase width in which the chopping is in a pause state (hereinafter referred to as “chopping pause”). It is characterized by obtaining the same effect by detecting θw OFF and adjusting the DC voltage command Vdc.
　図４Ａは本発明の実施形態２に係る整流回路装置の制御回路１００の第３の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。また、図４Ｂは本発明の実施形態２に係る整流回路装置の制御回路１００の第４の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。 FIG. 4A is a diagram for explaining a control operation according to the third operation example of the control circuit 100 of the rectifier circuit device according to the second embodiment of the present invention, and shows the relationship between the AC voltage and the DC voltage after rectification. FIG. 5 is a signal waveform diagram showing a target current waveform to be controlled and an AC current after actual control. FIG. 4B is a diagram for explaining the control operation according to the fourth operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 2 of the present invention, in which the AC voltage and the DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling.
　図４Ａの第３の動作例では、出力されるＤＣ電圧が比較的低く、半導体スイッチ１０４がチョッピング動作されないチョッピング休止位相幅（例えば、最大の位相幅）θｗＯＦＦが大きくなっている場合である。一方、図４Ｂの第４の動作例では、出力されるＤＣ電圧が第３の動作例に比較して高く、半導体スイッチ１０４がチョッピングされないチョッピング休止位相幅（例えば、最小の位相幅）θｗＯＦＦが第３の動作例に比較して小さくなっている場合である。チョッピング休止位相幅θｗＯＦＦはチョッピング動作位相幅θｗＯＮと相補的であるため、同様の作用効果を得ることができる。 In the third operation example of FIG. 4A, the output DC voltage is relatively low, and the chopping pause phase width (for example, the maximum phase width) θw OFF in which the semiconductor switch 104 is not chopped is large. On the other hand, in the fourth operation example of FIG. 4B, the output DC voltage is higher than that in the third operation example, and the chopping pause phase width (for example, the minimum phase width) θw OFF in which the semiconductor switch 104 is not chopped is This is a case where it is smaller than that in the third operation example. Since the chopping pause phase width θw OFF is complementary to the chopping operation phase width θw ON , the same effect can be obtained.
　また、ＡＣ電源１からのＡＣ電圧にひずみが含まれていると、ＡＣ電圧の半周期の間にチョッピングがなされている区間が複数回数出現することがある。このような場合には、チョッピング位相幅検出器２１２は、９０度又は１８０度に近いオフ期間のチョッピング休止位相幅θｗＯＦＦを制御用チョッピング位相幅として選択して当該チョッピング制御を行ってもよい。 In addition, when the AC voltage from the AC power supply 1 includes distortion, a section in which chopping is performed during a half cycle of the AC voltage may appear a plurality of times. In such a case, the chopping phase width detector 212 may perform the chopping control by selecting the chopping pause phase width θw OFF in the off period close to 90 degrees or 180 degrees as the control chopping phase width.
　なお、図４Ａ及び図４Ｂでは、ＡＣ電圧の半周期分のみの波形を示しているが、図３Ａ及び図３Ｂや従来技術などからも明らかなように、残りの半周期も絶対値（瞬時絶対値）としては同様の波形になるので省略する。また、図４Ａ及び図４Ｂでは、ＡＣ電圧の半周期分のみの波形を示しているが、図３Ａ及び図３Ｂや従来例などからも明らかなように、残りの半周期も絶対値としては同様の波形になるので省略する。 4A and 4B show the waveform of only the half cycle of the AC voltage. As is clear from FIGS. 3A and 3B and the prior art, the remaining half cycles are also absolute values (instantaneous absolute values). (Value) will be omitted because it has the same waveform. 4A and 4B show waveforms for only a half cycle of the AC voltage. As is clear from FIGS. 3A and 3B and the conventional example, the remaining half cycles are the same as absolute values. The waveform is omitted because it is
実施形態３．
　実施形態３は、実施形態１の制御方法を簡素化したことを特徴としており、チョッピング位相幅検出器２１２は、０度又は１８０度からチョッピングが休止状態になるまでのＡＣ電圧の極性（符号）が変化せず固定されている区間（正の区間又は負の区間）での前半の位相幅θ１ｗＯＮを検出して当該チョッピング制御する。 Embodiment 3. FIG.
The third embodiment is characterized in that the control method of the first embodiment is simplified, and the chopping phase width detector 212 has a polarity (symbol) of the AC voltage from 0 degree or 180 degrees until the chopping is in a resting state. The chopping control is performed by detecting the first half phase width θ1w ON in a section (positive section or negative section) in which is not changed.
　図５Ａは本発明の実施形態３に係る整流回路装置の制御回路１００の第５の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。また、図５Ｂは本発明の実施形態３に係る整流回路装置の制御回路１００の第６の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。 FIG. 5A is a diagram for explaining a control operation according to a fifth operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 3 of the present invention, and shows the relationship between the AC voltage and the DC voltage after rectification. FIG. 5 is a signal waveform diagram showing a target current waveform to be controlled and an AC current after actual control. FIG. 5B is a diagram for explaining the control operation according to the sixth operation example of the control circuit 100 of the rectifier circuit device according to the third embodiment of the present invention, in which the AC voltage and the DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling.
　図５Ａの第５の動作例は、出力されるＤＣ電圧が比較的低く、半導体スイッチ１０４がチョッピングされる位相幅が比較的小さくなっている場合であり、図５Ｂの第６の動作例は、出力されるＤＣ電圧が第５の動作例に比較して高く、半導体スイッチ１０４がチョッピングされる位相幅が第５の動作例に比較して大きくなっている場合である。ＡＣ電圧の半周期の区間において、前半のチョッピングがなされている位相幅θ１ｗＯＮも同様の傾向があるので、実施形態１と同様の作用効果を得ることができる。 The fifth operation example in FIG. 5A is a case where the output DC voltage is relatively low and the phase width in which the semiconductor switch 104 is chopped is relatively small. The sixth operation example in FIG. This is a case where the output DC voltage is higher than that in the fifth operation example, and the phase width in which the semiconductor switch 104 is chopped is larger than that in the fifth operation example. Since the phase width θ1w ON in which the first half of the chopping is performed has a similar tendency in the period of the half cycle of the AC voltage, the same effects as those of the first embodiment can be obtained.
実施形態４．
　実施形態４は、実施形態３と同様に、実施形態１の制御方法を簡素化したことを特徴としており、チョッピング位相幅検出器２１２は、０度又は１８０度からチョッピングが休止状態になるまでのＡＣ電圧の極性が変化せず固定されている区間（正の区間又は負の区間）での後半の位相幅θｗ２ＯＮを検出して当該チョッピング制御する。 Embodiment 4 FIG.
The fourth embodiment is characterized in that the control method of the first embodiment is simplified as in the third embodiment, and the chopping phase width detector 212 is used from 0 degree or 180 degrees until the chopping enters a resting state. The chopping control is performed by detecting the latter phase width θw2 ON in the section (positive section or negative section) where the polarity of the AC voltage is fixed without changing.
　図６Ａは本発明の実施形態４に係る整流回路装置の制御回路１００の第７の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。また、図６Ｂは本発明の実施形態４に係る整流回路装置の制御回路１００の第８の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。 FIG. 6A is a diagram for explaining the control operation according to the seventh operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 4 of the present invention, and shows the relationship between the AC voltage and the rectified DC voltage. FIG. 5 is a signal waveform diagram showing a target current waveform to be controlled and an AC current after actual control. FIG. 6B is a diagram for explaining the control operation according to the eighth operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 4 of the present invention, in which the AC voltage and the DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling.
　図６Ａの第７の動作例は、出力されるＤＣ電圧が比較的低く、半導体スイッチ１０４がチョッピングされるチョッピング位相幅θｗ２ＯＮが比較的小さくなっている場合であり、図６Ｂの第８の動作例は、出力されるＤＣ電圧が第７の動作例に比較して高く、半導体スイッチ１０４がチョッピングされるチョッピング位相幅θｗ２ＯＮが第７の動作例に比較して大きくなっている場合である。ＡＣ電源１の半周期の区間において、後半のチョッピング動作位相幅θｗ２ＯＮも同様の傾向があるので、実施形態１と同様の作用効果を得ることができる。 The seventh operation example in FIG. 6A is a case where the output DC voltage is relatively low, and the chopping phase width θw2 ON in which the semiconductor switch 104 is chopped is relatively small. The eighth operation in FIG. 6B An example is a case where the output DC voltage is higher than that in the seventh operation example, and the chopping phase width θw2 ON in which the semiconductor switch 104 is chopped is larger than that in the seventh operation example. Since the chopping operation phase width θw2 ON in the second half also has the same tendency in the half-cycle section of the AC power supply 1, the same effect as that of the first embodiment can be obtained.
実施形態５．
　実施形態５は、実施形態３のチョッピング位相幅θｗ１ＯＮと、実施形態４のチョッピング位相幅θｗ２ＯＮとの合計の位相幅（θｗ１ＯＮ＋θｗ２ＯＮ）をチョッピング位相幅検出器２１２により検出して、当該合計の位相幅（θｗ１ＯＮ＋θｗ２ＯＮ）が所望の位相幅になるようにＤＣ電圧を制御することを特徴としている。 Embodiment 5. FIG.
Embodiment 5 includes a chopping phase width Shitadaburyu1 ON embodiment 3 detects the sum of the phase width (θw1 ON + θw2 ON) the chopping phase width detector 212 with chopping phase width Shitadaburyu2 ON embodiment 4, the The DC voltage is controlled so that the total phase width (θw1 ON + θw2 ON ) becomes a desired phase width.
　図７Ａは本発明の実施形態５に係る整流回路装置の制御回路１００の第９の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。また、図７Ｂは本発明の実施形態５に係る整流回路装置の制御回路１００の第１０の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。実施形態５においても、実施形態１～４と同様の作用効果を得ることができる。 FIG. 7A is a diagram for explaining the control operation according to the ninth operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 5 of the present invention, and shows the relationship between the AC voltage and the DC voltage after rectification. FIG. 5 is a signal waveform diagram showing a target current waveform to be controlled and an AC current after actual control. FIG. 7B is a diagram for explaining a control operation according to the tenth operation example of the control circuit 100 of the rectifier circuit device according to the fifth embodiment of the present invention, in which an AC voltage and a DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling. In the fifth embodiment, the same effects as in the first to fourth embodiments can be obtained.
実施形態６．
　図８は本発明の実施形態６に係る整流回路装置の構成を示す回路図である。また、図９は図８の制御回路１１１の詳細構成を示すブロック図である。図８において、実施形態６に係る整流回路装置は、図１の制御回路１００に代えて制御回路１１１を備えたことを特徴としており、制御回路１１１は、図９に示すように、図１の制御回路１００に比較して、入力電流変動判定血設定器２１３ａを有する入力状況判定器２１３と、目標位相幅選定器２１４（図１の目標位相幅設定器２０３に代えて設けられる）と、チョッピング位相幅抽出器２１６とをさらに備えたことを特徴としている。 Embodiment 6. FIG.
FIG. 8 is a circuit diagram showing a configuration of a rectifier circuit device according to Embodiment 6 of the present invention. FIG. 9 is a block diagram showing a detailed configuration of the control circuit 111 of FIG. 8, the rectifier circuit device according to the sixth embodiment is characterized by including a control circuit 111 instead of the control circuit 100 of FIG. 1, and the control circuit 111 is configured as illustrated in FIG. Compared to the control circuit 100, an input situation determination unit 213 having an input current fluctuation determination blood setting unit 213a, a target phase width selector 214 (provided instead of the target phase width setting unit 203 in FIG. 1), and chopping A phase width extractor 216 is further provided.
　従来技術に係る装置において、接続される負荷４の電気的負荷特性により入力電流が脈動する場合、電源電圧の周期に基づいて同一のチョッピング位相幅は得られない。そこで、本実施形態では、脈動しない領域での所望のチョッピング位相幅とは別に、脈動する領域における所望のチョッピング位相幅を設け、かつ、この脈動する領域では、予め設定された一定時間又は一定周期数における、最大又は平均のチョッピング位相幅を抽出して当該チョッピング制御を行うことを特徴としている。 In the device according to the prior art, when the input current pulsates due to the electrical load characteristic of the connected load 4, the same chopping phase width cannot be obtained based on the period of the power supply voltage. Therefore, in the present embodiment, a desired chopping phase width in a pulsating region is provided separately from a desired chopping phase width in a region that does not pulsate, and the pulsating region has a preset constant time or constant period. The maximum or average chopping phase width in the number is extracted and the chopping control is performed.
　本実施形態に係る図８及び図９の構成において、制御回路１１１により半導体スイッチ１０４をチョッピング制御することにより、電源電圧の高調波の低減とＤＣ電圧の制御が行われる。図９の制御回路１１１において、当該制御システムの最終制御目標は、チョッピング駆動がなされているチョッピング位相幅θｗＯＮを、目標位相幅選定器２１４からの所望の位相幅θｗＯＮ ＊に一致するように制御することである。以下、図９の制御回路１１１の構成及び動作について、図２の制御回路１００との相違点を中心に説明し、図２の制御回路１００と同様の構成及び動作の説明については省略する。 In the configuration of FIGS. 8 and 9 according to the present embodiment, the control circuit 111 performs chopping control of the semiconductor switch 104, thereby reducing harmonics of the power supply voltage and controlling the DC voltage. In the control circuit 111 of FIG. 9, the final control target of the control system is such that the chopping phase width θw ON for which chopping driving is performed matches the desired phase width θw ON * from the target phase width selector 214. Is to control. Hereinafter, the configuration and operation of the control circuit 111 in FIG. 9 will be described focusing on differences from the control circuit 100 in FIG. 2, and description of the same configuration and operation as the control circuit 100 in FIG. 2 will be omitted.
　電流検出器１０３は検出したＡＣ電流Ｉａｃを示す信号を入力状況判定器２１３に出力する。入力状況判定手段２１３は、複数の電源電圧周期のピーク値から入力電流の変動幅を計算し、当該計算した変動幅から、入力電流変動判定値設定器２１３ａにより予め設定されている入力電流変動判定値を減算して、減算結果である変動幅偏差を示す信号を目標位相幅選定器２１４及びチョッピング位相幅抽出器２１６に出力する。目標位相幅選定器２１４は予め、変動幅偏差の各種数値範囲に対応して設定すべき所望のチョッピング位相幅θｗＯＮ ＊をチョッピング位相幅テーブルとして内蔵テーブルメモリ２１４ｍに格納しており、入力状況判定器２１３からの変動幅偏差（入力電流の変動の程度）を示す信号に基づいて、上記チョッピング位相幅テーブルを参照して、対応するチョッピング位相幅θｗＯＮ ＊を決定してそれを示す信号を減算器２０４に出力する。 The current detector 103 outputs a signal indicating the detected AC current Iac to the input status determiner 213. The input status determination means 213 calculates the fluctuation range of the input current from the peak values of a plurality of power supply voltage periods, and determines the input current fluctuation determination preset by the input current fluctuation determination value setting unit 213a from the calculated fluctuation width. The value is subtracted and a signal indicating the fluctuation width deviation as a subtraction result is output to the target phase width selector 214 and the chopping phase width extractor 216. The target phase width selector 214 stores in advance the desired chopping phase width θw ON * to be set corresponding to various numerical ranges of the fluctuation width deviation in the built-in table memory 214m as a chopping phase width table, and determines the input status Based on the signal indicating the fluctuation width deviation (degree of fluctuation of the input current) from the device 213, the corresponding chopping phase width θw ON * is determined with reference to the chopping phase width table, and the signal indicating it is subtracted. Output to the device 204.
　チョッピング位相幅抽出器２１６は、チョッピング位相幅検出器２１２からのチョッピング状態の位相幅と、入力状況判定器２１３からの変動幅偏差とに基づいて、当該位相幅において所定値以上の脈動が発生していないと判断したとき、チョッピング位相幅検出器２１２からのチョッピング状態のチョッピング位相幅θｗＯＮを示す信号をそのまま減算器２０４に出力する。一方、チョッピング位相幅抽出器２１６は、当該チョッピング位相幅θｗＯＮにおいて所定値以上の脈動が発生していると判断したとき、予め設定された一定時間又は一定周期数における、最大又は平均のチョッピング状態の位相幅を抽出して当該位相幅を示す信号を減算器２０４に出力する The chopping phase width extractor 216 generates a pulsation of a predetermined value or more in the phase width based on the phase width in the chopping state from the chopping phase width detector 212 and the fluctuation width deviation from the input status determination unit 213. When it is determined that the chopping phase width is not, a signal indicating the chopping phase width θw ON in the chopping state from the chopping phase width detector 212 is output to the subtractor 204 as it is. On the other hand, when the chopping phase width extractor 216 determines that a pulsation of a predetermined value or more has occurred in the chopping phase width θw ON , the maximum or average chopping state in a preset fixed time or fixed number of cycles And a signal indicating the phase width is output to the subtracter 204.
　以上のように構成された図９の制御回路１１１を備えた整流回路装置によれば、所定値以上の脈動が発生する脈動的な負荷がある場合でも、電源電圧の高調波に大きく影響を与えるチョッピング状態の位相幅θｗＯＮを抽出することができ、電源電圧の高調波の低減と回路損失の低減との両立をはかることができる。 According to the rectifier circuit device having the control circuit 111 of FIG. 9 configured as described above, even when there is a pulsating load that generates a pulsation of a predetermined value or more, the harmonics of the power supply voltage are greatly affected. The phase width θw ON in the chopping state can be extracted, and both reduction of the harmonics of the power supply voltage and reduction of the circuit loss can be achieved.
実施形態７．
　図１０は本発明の実施形態７に係る整流回路装置の構成を示す回路図である。また、図１１は図８の制御回路１１２の詳細構成を示すブロック図である。図１０の整流回路装置は、負荷として、圧縮機駆動部３００に接続された圧縮機３０１のモータを駆動し、その制御は圧縮機制御回路３０２にて実行することを特徴としている。圧縮機制御回路３０２は、図１０に示すように、所望の回転数で圧縮機３０１のモータを回転させるべく圧縮機駆動部３００及び制御回路１１２に対して回転数指令Ｓｒｏｔを出力する。 Embodiment 7. FIG.
FIG. 10 is a circuit diagram showing a configuration of a rectifier circuit device according to Embodiment 7 of the present invention. FIG. 11 is a block diagram showing a detailed configuration of the control circuit 112 of FIG. The rectifier circuit device of FIG. 10 is characterized by driving a motor of a compressor 301 connected to the compressor driving unit 300 as a load, and the control is executed by the compressor control circuit 302. As shown in FIG. 10, the compressor control circuit 302 outputs a rotation speed command Srot to the compressor drive unit 300 and the control circuit 112 to rotate the motor of the compressor 301 at a desired rotation speed.
　図１０及び図１１の実施形態７に係る整流回路装置は、実施形態６と同様に、脈動しない領域での所望のチョッピング位相幅とは別に、脈動する領域における所望のチョッピング位相幅を設け、かつ、この脈動する位相幅の領域では、予め設定された一定時間又は一定周期数における、最大又は平均のチョッピング位相幅を選択して当該チョッピング制御することを特徴としている。 The rectifier circuit device according to Embodiment 7 in FIGS. 10 and 11 provides a desired chopping phase width in the pulsating region separately from the desired chopping phase width in the non-pulsating region, as in Embodiment 6. In the region of the pulsating phase width, the chopping control is performed by selecting the maximum or average chopping phase width in a predetermined time or a predetermined number of periods.
　図１１の制御回路１１２は、図９の制御回路１１１に比較して、
（ａ）入力状況判定器２１３に代えて、圧縮機制御回路３０２からの回転数指令Ｓｒｏｔに基づいて駆動状況を判定する駆動状況判定器２１５を備え、
（ｂ）目標位相幅選定器２１４に代えて、内蔵テーブルメモリ２１４Ａｍを有する目標位相幅選定器２１４Ａを備え、
（ｃ）チョッピング位相幅抽出器２１６に代えて、チョッピング位相幅抽出器２１６Ａを備えたことを特徴としている。 The control circuit 112 in FIG. 11 is compared with the control circuit 111 in FIG.
(A) In place of the input status determiner 213, a drive status determiner 215 that determines the drive status based on the rotational speed command Srot from the compressor control circuit 302 is provided.
(B) In place of the target phase width selector 214, a target phase width selector 214A having a built-in table memory 214Am is provided,
(C) Instead of the chopping phase width extractor 216, a chopping phase width extractor 216A is provided.
　図１１において、圧縮機制御回路３０２からモータの回転数指令Ｓｒｏｔは駆動状況判定器２１５に入力される。駆動状況判定器２１５は、モータの回転数指令Ｓｒｏｔから予め設定されている回転数を減算することにより回転数偏差を演算し、回転数偏差を示す信号を目標位相幅選定器２１４Ａ及びチョッピング位相幅抽出器２１６Ａに出力する。目標位相幅選定器２１４Ａは予め、回転数偏差の各種数値範囲に対応して設定すべき所望のチョッピング位相幅θｗＯＮ ＊をチョッピング位相幅テーブルとして内蔵テーブルメモリ２１４Ａｍに格納しており、駆動状況判定器２１５からの回転数偏差を示す信号に基づいて、上記チョッピング位相幅テーブルを参照して、対応するチョッピング位相幅θｗＯＮ ＊を決定してそれを示す信号を減算器２０４に出力する。 In FIG. 11, a motor rotation speed command Srot is input from the compressor control circuit 302 to the drive status determination unit 215. The drive status determiner 215 calculates a rotational speed deviation by subtracting a preset rotational speed from the motor rotational speed command Srot, and outputs a signal indicating the rotational speed deviation to the target phase width selector 214A and the chopping phase width. Output to the extractor 216A. The target phase width selector 214A stores in advance the desired chopping phase width θw ON * to be set corresponding to various numerical ranges of the rotational speed deviation in the built-in table memory 214Am as a chopping phase width table, and determines the drive status The corresponding chopping phase width θw ON * is determined with reference to the chopping phase width table based on the signal indicating the rotational speed deviation from the unit 215, and a signal indicating it is output to the subtractor 204.
　チョッピング位相幅抽出器２１６Ａは、チョッピング位相幅検出器２１２からのチョッピング状態の位相幅と、駆動状況判定器２１５からの回転数偏差とに基づいて、圧縮機３０１を駆動する回転数が予め設定されている回転数を超える場合は、チョッピング位相幅検出器２１２からのチョッピング状態の位相幅θｗＯＮを示す信号をそのまま減算器２０４に出力する。一方、チョッピング位相幅抽出器２１６Ａは、圧縮機３０１を駆動する回転数が予め設定されている回転数以下の場合は、予め設定された一定時間又は一定周期数における、最大又は平均のチョッピング状態の位相幅を抽出して当該位相幅を示す信号を減算器２０４に出力する In the chopping phase width extractor 216A, the number of rotations for driving the compressor 301 is set in advance based on the phase width in the chopping state from the chopping phase width detector 212 and the rotational speed deviation from the driving state determination unit 215. When the rotation speed exceeds the value, the signal indicating the chopping phase width θw ON from the chopping phase width detector 212 is output to the subtractor 204 as it is. On the other hand, the chopping phase width extractor 216A, when the rotational speed for driving the compressor 301 is equal to or lower than the preset rotational speed, is the maximum or average chopping state for a predetermined time period or constant frequency. The phase width is extracted and a signal indicating the phase width is output to the subtracter 204.
　ここで、本実施形態での圧縮機３０１と負荷との関連をまず説明する。一般に、家庭用などの小型の冷凍空調機器に用いられる、往復動型やローリングピストン型の圧縮機３０１は、吸入行程、圧縮行程、吐出行程のそれぞれの行程における必要な動力が大幅に異なる特性を有しており、各行程における必要動力を適切に供給しなければ、圧縮機３０１が振動を起こし、配管の破損などを引き起こす。このため、各行程における駆動用の電動機の瞬時瞬時の速度を一定に制御して振動を抑制する制御を行う。その結果、本発明に係る整流回路装置の負荷としては、各行程を推移する周期での脈動を有するものになる。また、振動の発生は各行程の推移周期にも関連し、周期が短くなれば、慣性モーメントによる慣性効果により減衰する特性を有しており、周期が短い、すなわちモータの回転数が高いときには、振動を抑制する制御を実施する必要がなくなり、平均的な速度制御だけでも振動が少ない状態を保つことができる。そして、平均的な速度制御だけの場合、ＤＣ側の負荷には脈動が少ない。 Here, the relationship between the compressor 301 and the load in this embodiment will be described first. In general, a reciprocating type or rolling piston type compressor 301 used in a small-sized refrigeration and air-conditioning apparatus for home use has a characteristic that required power in each of a suction stroke, a compression stroke, and a discharge stroke is significantly different. If the necessary power in each stroke is not properly supplied, the compressor 301 will vibrate and cause damage to the piping. For this reason, control which suppresses vibration by controlling the instantaneous instantaneous speed of the electric motor for driving in each stroke to be constant is performed. As a result, the load of the rectifier circuit device according to the present invention has a pulsation with a cycle of changing each stroke. In addition, the occurrence of vibration is also related to the transition cycle of each stroke, and if the cycle is shortened, it has a characteristic that it is attenuated by the inertia effect due to the moment of inertia, and when the cycle is short, that is, when the motor rotation speed is high, It is not necessary to perform control for suppressing vibration, and it is possible to maintain a state in which vibration is small even with average speed control alone. In the case of only average speed control, the load on the DC side has less pulsation.
　例えば、圧縮機３０１の回転数がある値を越える回転数領域においては、平均的な速度制御だけで駆動しても、圧縮機３０１の振動が少ない場合には、この回転数領域においては、瞬時速度制御は特に必要ではない。そして、平滑コンデンサ１０６に流入する電源電流にもその脈動の影響がなくなるので、本実施形態に係るチョッピング位相幅抽出器２１６Ａは、上記所定の回転数値を超える場合、もしくはそれ以下のどちらの回転数で圧縮機３０１を駆動しているかにより、チョッピング状態の位相幅を減算器２０４にそのまま出力するか、予め設定された一定時間又は一定周期数における最大又は平均のチョッピング状態の位相幅を抽出して減算器２０４へ出力するか、を切り替える。 For example, in the rotational speed region where the rotational speed of the compressor 301 exceeds a certain value, even when the compressor 301 is driven only by average speed control and the vibration of the compressor 301 is small, in this rotational speed region, instantaneously Speed control is not particularly necessary. Since the power supply current flowing into the smoothing capacitor 106 is not affected by the pulsation, the chopping phase width extractor 216A according to the present embodiment has either the number of rotations that exceeds or is less than the predetermined rotation number. Depending on whether or not the compressor 301 is driven, the phase width of the chopping state is output to the subtractor 204 as it is, or the phase width of the maximum or average chopping state in a predetermined time or a predetermined number of cycles is extracted. Whether to output to the subtractor 204 is switched.
　次いで、実施形態７の変形例について以下に説明する。 Next, a modification of the seventh embodiment will be described below.
　実施形態７と同様の制御方法で、圧縮機３０１の回転数が高くなると、慣性効果により、瞬時瞬時の回転速度変動が減少し、瞬時瞬時の速度制御による圧縮機３０１へ供給する電力の脈動が減少していく。このため、瞬時速度制御が常に動作している場合でも、回転数が高い領域では、ＡＣ電源１側からみて、負荷の脈動の影響がほとんど関係しなくなっていく。この場合でも、チョッピング位相幅抽出器２１６Ａが、圧縮機３０１の回転数が高い領域では、チョッピング状態の位相幅情報を減算器２０４へそのまま出力し、圧縮機３０１の回転数が低い領域では、予め設定された一定時間又は一定周期数における最大又は平均のチョッピング状態の位相幅を抽出して減算器２０４へ出力するように切り替えることで、電源高調波の低減と回路損失の両立をはかることができる。なお、これらの切り替えにおける回転数のしきい値の値は、圧縮機３０１の圧縮比や慣性モーメントなどの仕様緒元により変化する値である。例えば、チョッピング位相幅θｗＯＮもしくはチョッピングが休止状態になっている位相幅θｗＯＦＦが電源周期の毎回毎回変動する状態になるか否かで決定すればよい。 In the same control method as in the seventh embodiment, when the rotation speed of the compressor 301 increases, the instantaneous instantaneous speed fluctuation decreases due to the inertia effect, and the pulsation of the power supplied to the compressor 301 by the instantaneous instantaneous speed control is reduced. It will decrease. For this reason, even when the instantaneous speed control is always operating, in the region where the rotational speed is high, the influence of the load pulsation becomes almost irrelevant as viewed from the AC power source 1 side. Even in this case, the chopping phase width extractor 216A outputs the phase width information of the chopping state to the subtractor 204 as it is in the region where the rotation speed of the compressor 301 is high, and in advance in the region where the rotation speed of the compressor 301 is low. By switching so that the phase width of the maximum or average chopping state in a set fixed time or fixed number of cycles is extracted and output to the subtracter 204, both reduction of power supply harmonics and circuit loss can be achieved. . Note that the threshold value of the rotation speed in these switchings is a value that changes depending on the specification specifications such as the compression ratio and the moment of inertia of the compressor 301. For example, the chopping phase width θw ON or the phase width θw OFF in which the chopping is in a suspend state may be determined based on whether or not the power supply cycle changes every time.
　なお、圧縮機３０１を駆動する際の回転数に起因した振動発生の抑制が必要な場合に実行される瞬時速度制御の具体的な方法は種々提案されているが、その方法の差異は本発明には直接は関与しないので、詳細な説明は省略する。 Various specific methods of the instantaneous speed control that are executed when it is necessary to suppress the occurrence of vibration due to the rotation speed when the compressor 301 is driven have been proposed. Is not directly involved, and a detailed description is omitted.
　このようにすることで、圧縮機３０１による脈動的な負荷がある場合でも、圧縮機３０１のモータの回転数指令Ｓｒｏｔを用いることにより、脈動負荷の状況を推定できるので、脈動状況を直接検出することもなく、チョッピング状態の位相幅を抽出することができ、電源電圧の高調波の低減と回路損失の低減との両立をはかることができる。 In this way, even when there is a pulsating load due to the compressor 301, the state of the pulsating load can be estimated by using the rotation speed command Srot of the motor of the compressor 301, so the pulsating state is directly detected. Therefore, the phase width of the chopping state can be extracted, and both reduction of harmonics of the power supply voltage and reduction of circuit loss can be achieved.
　なお、本実施形態においては、駆動状況判定器２１５の入力として圧縮機３０１の駆動回転数指令Ｓｃｏｔとしたが、圧縮機３０１を駆動する際の回転数に起因した振動発生の抑制が必要な場合に実行される瞬時速度制御の有無を圧縮機制御回路３０２からの入力として、瞬時速度制御の有無に従い目標位相幅選択信号を目標位相幅選定器２１４とチョッピング位相幅抽出器２１６Ａに出力しても、同様のチョッピング制御を行うことができる。 In the present embodiment, the drive rotation speed command Scot of the compressor 301 is used as the input of the drive status determination unit 215. However, it is necessary to suppress the occurrence of vibration due to the rotation speed when the compressor 301 is driven. Whether or not the instantaneous speed control to be executed is input as input from the compressor control circuit 302, and the target phase width selection signal is output to the target phase width selector 214 and the chopping phase width extractor 216A according to the presence or absence of the instantaneous speed control. Similar chopping control can be performed.
実施形態８．
　図１２Ａは本発明の実施形態８に係る整流回路装置の制御回路１００の第１１の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。また、図１２Ｂは本発明の実施形態８に係る整流回路装置の制御回路１００の第１２の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。 Embodiment 8. FIG.
FIG. 12A is a diagram for explaining the control operation according to the eleventh operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 8 of the present invention, and shows the relationship between the AC voltage and the DC voltage after rectification. FIG. 5 is a signal waveform diagram showing a target current waveform to be controlled and an AC current after actual control. FIG. 12B is a diagram for explaining the control operation according to the twelfth operation example of the control circuit 100 of the rectifier circuit device according to the eighth embodiment of the present invention, in which the AC voltage and the DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling.
　実施形態８に係る制御回路１００は、目標電流波形を正弦波以外の波形であって、例えば三角波にすることで、さらに回路損失を低減できることを特徴としている。特に、負荷が軽いときには、波形歪みが増加しても、高調波電流そのものは少ないので、さらに損失を低減することが可能である。 The control circuit 100 according to the eighth embodiment is characterized in that the target current waveform is a waveform other than a sine wave, for example, a triangular wave, thereby further reducing circuit loss. In particular, when the load is light, even if the waveform distortion increases, the harmonic current itself is small, so that the loss can be further reduced.
　図１２Ａの第１１の動作例は、出力されるＤＣ電圧が比較的低く、半導体スイッチ１０４がチョッピングされる位相幅θｗＯＮが所望の位相幅θｗＯＮ ＊よりも小さくなっている場合である。このときにも、ＡＣ電圧がＤＣ電圧より高い位相期間が増加するので、ＡＣ電源１からリアクタ１０２とダイオードブリッジ１０５を経由してＤＣ側へと流れ込む電流が増加する。このため、ＡＣ電流の波形が先鋭になり、ＡＣ電流の高調波成分が増加する。 The eleventh operation example in FIG. 12A is a case where the output DC voltage is relatively low and the phase width θw ON where the semiconductor switch 104 is chopped is smaller than the desired phase width θw ON * . Also at this time, since the phase period in which the AC voltage is higher than the DC voltage increases, the current flowing from the AC power source 1 to the DC side via the reactor 102 and the diode bridge 105 increases. For this reason, the waveform of the AC current becomes sharp, and the harmonic component of the AC current increases.
　一方、図１２Ｂの第１２の動作例は、出力されるＤＣ電圧が第１１の動作例に比較して高く、半導体スイッチ１０４がチョッピングされる位相幅θｗＯＮが所望の位相幅θｗＯＮ ＊よりも大きくなっている場合である。このときには、ＡＣ電圧がＤＣ電圧より高い位相期間が減少するので、ＡＣ電源１からリアクタ１０２とダイオードブリッジ１０５を経由してＤＣ側へと流れ込むＡＣ電流も減少し、ＡＣ電流の高調波成分が減少する。しかし、図１２Ｂの第１２の動作例では、図３Ａ及び図３Ｂと同様に、図１２Ａでの波形に比べて、半導体スイッチ１０４のチョッピングが行われている期間（位相幅）が増加しているため、回路の損失が増加してしまう。 On the other hand, in the twelfth operation example of FIG. 12B, the output DC voltage is higher than that in the eleventh operation example, and the phase width θw ON where the semiconductor switch 104 is chopped is higher than the desired phase width θw ON *. This is the case when it is getting bigger. At this time, since the phase period in which the AC voltage is higher than the DC voltage decreases, the AC current flowing from the AC power source 1 to the DC side via the reactor 102 and the diode bridge 105 also decreases, and the harmonic component of the AC current decreases. To do. However, in the twelfth operation example of FIG. 12B, the period (phase width) during which the chopping of the semiconductor switch 104 is performed is increased compared to the waveform in FIG. 12A, as in FIGS. 3A and 3B. As a result, circuit loss increases.
　実施形態８においては、好ましくは、図１２Ａ及び図１２Ｂに示すように、目標電流波形の瞬時の絶対値は、時間経過とともに、ＡＣ電圧の０度（開始点）から１８０度（終了点）までの期間の前半の期間において、一定の傾きで単調増加した後、所定の中間点（９０度よりも小さい角度）から一定の傾きで単調減少し、その後終了点までゼロになる区間を有する三角波形を用いる。 In the eighth embodiment, preferably, as shown in FIGS. 12A and 12B, the instantaneous absolute value of the target current waveform is from 0 degree (start point) to 180 degrees (end point) of the AC voltage with time. In the first half of the period, a triangular waveform having a section that monotonously increases with a certain slope, then monotonously decreases with a certain slope from a predetermined intermediate point (an angle smaller than 90 degrees), and then becomes zero until the end point. Is used.
　なお、図１２Ａ及び図１２Ｂにおいて、ＡＣ電圧の半周期で１つのチョッピング位相幅θｗＯＮが図示されているので、ＡＣ電圧の半周期で２つのチョッピング休止位相幅が図示されていることになる。従って、上述のように、２つのチョッピング休止位相幅のいずれかの位相幅、もしくは合計の位相幅に基づいてチョッピング制御してもよい。 In FIGS. 12A and 12B, one chopping phase width θw ON is shown in the half cycle of the AC voltage, so two chopping pause phase widths are shown in the half cycle of the AC voltage. Therefore, as described above, chopping control may be performed based on one of the two chopping pause phase widths or the total phase width.
　次いで、実施形態８の変形例に係る、図１２Ａ及び図１２Ｂとは異なる別の形状を有する目標電流波形について、図１３Ａ～図１３Ｄを参照して以下に説明する。 Next, a target current waveform having another shape different from those in FIGS. 12A and 12B according to the modification of the eighth embodiment will be described below with reference to FIGS. 13A to 13D.
　図１３Ａは本発明の実施形態８に係る整流回路装置の制御回路１００の第１３の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。また、図１３Ｂは本発明の実施形態８に係る整流回路装置の制御回路１００の第１４の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。さらに、図１３Ｃは本発明の実施形態８に係る整流回路装置の制御回路１００の第１５の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。また、図１３Ｄは本発明の実施形態８に係る整流回路装置の制御回路１００の第１６の動作例に係る制御動作を説明するための図であって、ＡＣ電圧と整流後のＤＣ電圧との関係と、制御すべき目標電流波形と、実際に制御した後のＡＣ電流とを示す信号波形図である。 FIG. 13A is a diagram for explaining the control operation according to the thirteenth operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 8 of the present invention, and shows the relationship between the AC voltage and the rectified DC voltage. FIG. 5 is a signal waveform diagram showing a target current waveform to be controlled and an AC current after actual control. FIG. 13B is a diagram for explaining the control operation according to the fourteenth operation example of the control circuit 100 of the rectifier circuit device according to Embodiment 8 of the present invention, in which the AC voltage and the DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling. Further, FIG. 13C is a diagram for explaining the control operation according to the fifteenth operation example of the control circuit 100 of the rectifier circuit device according to the eighth embodiment of the present invention, in which the AC voltage and the DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling. FIG. 13D is a diagram for explaining the control operation according to the sixteenth operation example of the control circuit 100 of the rectifier circuit device according to the eighth embodiment of the present invention, in which the AC voltage and the DC voltage after rectification are calculated. It is a signal waveform diagram which shows a relationship, the target current waveform which should be controlled, and AC current after actually controlling.
　図１３Ａの第１３の動作例の目標電流波形は、図１２Ａの目標電流波形と比較して、単調減少する区間の代わりに、後半の９０度を超える所定の角度（例えば１１０度）で瞬時にゼロにする区間（ゼロで一定の区間）を有するように構成した三角波形である。 The target current waveform of the thirteenth operation example of FIG. 13A is instantaneously at a predetermined angle (for example, 110 degrees) exceeding 90 degrees in the second half, instead of the monotonously decreasing period, as compared with the target current waveform of FIG. 12A. It is the triangular waveform comprised so that it may have the area (zero and constant area) to make it zero.
　また、図１３Ｂの第１４の動作例の目標電流波形は、図１３Ａの目標電流波形と比較して、時間経過とともに、単調増加区間を正弦波状に増加させ、後半の９０度を超える所定の角度（例えば１１０度）で瞬時にゼロになる区間（ゼロで一定の区間）を有する波形である。 The target current waveform in the fourteenth operation example of FIG. 13B is a predetermined angle exceeding 90 degrees in the latter half by increasing the monotonically increasing section as a sine wave with the passage of time as compared with the target current waveform of FIG. 13A. It is a waveform having a section (for example, a constant section at zero) that instantaneously becomes zero at (eg, 110 degrees).
　さらに、図１３Ｃの第１５の動作例の目標電流波形は、図１３Ｂの目標電流波形において制約条件を設けて、前半部の正弦波波形において９０度より手前の中間点の角度（例えば７０度）で瞬時にゼロにした波形である。 Further, the target current waveform of the fifteenth operation example of FIG. 13C is provided with a constraint condition in the target current waveform of FIG. 13B, and the angle of the intermediate point before 90 degrees (for example, 70 degrees) in the sine waveform of the first half. The waveform is instantaneously zeroed.
　またさらに、図１３Ｄの第１６の動作例の目標電流波形は、図１３Ｃの目標電流波形において、時間経過とともに、０度から第１の中間点までの所定期間ゼロ（ゼロで一定の区間）にし、その後第２の中間点まで単調増加させるように構成した波形である。 Furthermore, the target current waveform of the sixteenth operation example of FIG. 13D is zero (a constant period at zero) for a predetermined period from 0 degree to the first intermediate point with time in the target current waveform of FIG. 13C. Thereafter, the waveform is configured to monotonously increase to the second intermediate point.
　図１３Ｃ及び図１３Ｄの動作例では、９０度よりも手前で目標電流をゼロにしているが、ゼロにする位相よりも手前で半導体スイッチ１０４のチョッピング動作から、チョッピングが休止になる期間になるような負荷で使用すればよい。しかも、本動作例は、ＤＣ電圧がＡＣ電圧の最高瞬時電圧よりも低いので、９０度近傍では、ＡＣ電源１からリアクタ１０２とダイオードブリッジ１０５を経由して電流が流れ込むので、目標電流がゼロになってもＡＣ電流がしばらくは流れ続けるため、高調波成分の少ない電流が高効率で実現できる。 In the operation examples of FIGS. 13C and 13D, the target current is set to zero before 90 degrees. However, the chopping operation of the semiconductor switch 104 is stopped from the chopping operation before the phase to be zero. It can be used with a heavy load. Moreover, in this operation example, since the DC voltage is lower than the maximum instantaneous voltage of the AC voltage, the current flows from the AC power source 1 through the reactor 102 and the diode bridge 105 in the vicinity of 90 degrees, so that the target current becomes zero. However, since AC current continues to flow for a while, a current with less harmonic components can be realized with high efficiency.
　以上の各実施形態において、目標電流波形の単調増加又は単調減少において、一定である期間を含んでもよく、すなわち、実質的に単調増加又は実質的に単調減少させてもよい。ここで、「実質的に単調増加」とは、目標電流波形の位相θ１＜θ２であるときに、ｆ（θ１）≦ｆ（θ２）の関係にある広義の単調増加をいい、言い換えれば、時間経過とともに、少なくとも増加し、もしくは少なくとも増加しかつ一部期間で一定であるように、実質的に単調増加することをいう。また、「実質的に単調減少」とは、目標電流波形の位相θ１＜θ２であるときに、ｆ（θ１）≧ｆ（θ２）の関係にある広義の単調減少をいい、言い換えれば、時間経過とともに、少なくとも減少し、もしくは少なくとも減少しかつ一部期間で一定であるように、実質的に単調減少することをいう。 In each of the above embodiments, the target current waveform may be monotonously increased or decreased, and a certain period may be included, that is, it may be substantially monotonically increased or substantially monotonically decreased. Here, “substantially monotonically increasing” means a monotonically increasing in a broad sense having a relationship of f (θ1) ≦ f (θ2) when the phase of the target current waveform is θ1 <θ2, in other words, time With the passage of time, it means at least increasing, or at least increasing and substantially monotonically increasing so as to be constant over a period of time. Further, “substantially monotonically decreasing” refers to a monotonic decreasing in a broad sense having a relation of f (θ1) ≧ f (θ2) when the phase θ1 <θ2 of the target current waveform, in other words, the passage of time In addition, it means to substantially decrease monotonically so as to at least decrease, or at least decrease and to be constant in a part period.
実施形態９．
　図１４は本発明の実施形態９に係る整流回路装置の構成を示す回路図である。実施形態９に係る整流回路装置は、ＡＣ電源１からのＡＣ電圧を、リアクタ６０２を介して、半導体スイッチ６０４ａ、６０４ｂ及びダイオード６０５ａ、６０５ｂ、６０５ｃ、６０５ｄで構成されたブリッジ回路で整流して、平滑コンデンサ１０６を介して負荷４を駆動することを特徴としている。本実施形態に係るチョッピング制御方法は、実施形態１に係る図１の制御回路１００と同様であり、２つの半導体スイッチ６０４ｂ、６０４ｄをチョッピング駆動信号Ｓｃｈを用いて同時に駆動する。
実施形態１０．
　図１５は本発明の実施形態１０に係る整流回路装置の構成を示す回路図である。実施形態１０に係る整流回路装置は、ＡＣ電源１からのＡＣ電圧を、リアクタ７０２を介して、半導体スイッチ７０４ａ、７０４ｂ及びダイオード７０５ａ、７０５ｂ、７０５ｃ、７０５ｄで構成されたブリッジ回路で整流して、平滑コンデンサ１０６を介して負荷４を駆動することを特徴としている。本実施形態に係るチョッピング制御方法は、ＡＣ電源１からのＡＣ電圧の極性に応じて、２つのチョッピング駆動信号Ｓｃｈ１，Ｓｃｈ２を用いて、いずれか一方の半導体スイッチ７０５ａ又は７０５ｂのみをチョッピング動作させる。例えば、ＡＣ電圧の極性がリアクタ７０２が接続されている側が高い期間であれば、チョッピング駆動信号Ｓｃｈ２を用いて半導体スイッチ７０４ｂをチョッピングし、ＡＣ電圧の極性がリアクタ７０２が接続されている側が低い期間であれば、チョッピング駆動信号Ｓｃｈ１を用いて半導体スイッチ７０４ａをチョッピングする。 Embodiment 9. FIG.
FIG. 14 is a circuit diagram showing a configuration of a rectifier circuit device according to Embodiment 9 of the present invention. The rectifier circuit device according to the ninth embodiment rectifies an AC voltage from the AC power source 1 through a reactor 602 by a bridge circuit configured by semiconductor switches 604a and 604b and diodes 605a, 605b, 605c, and 605d, The load 4 is driven through the smoothing capacitor 106. The chopping control method according to the present embodiment is the same as that of the control circuit 100 of FIG. 1 according to the first embodiment, and the two semiconductor switches 604b and 604d are simultaneously driven using the chopping drive signal Sch.
Embodiment 10 FIG.
FIG. 15 is a circuit diagram showing a configuration of a rectifier circuit device according to Embodiment 10 of the present invention. The rectifier circuit device according to the tenth embodiment rectifies the AC voltage from the AC power source 1 through the reactor 702 with a bridge circuit configured by semiconductor switches 704a and 704b and diodes 705a, 705b, 705c, and 705d, The load 4 is driven through the smoothing capacitor 106. In the chopping control method according to the present embodiment, only one of the semiconductor switches 705a or 705b is chopped using two chopping drive signals Sch1 and Sch2 in accordance with the polarity of the AC voltage from the AC power supply 1. For example, if the AC voltage polarity is high on the side where the reactor 702 is connected, the semiconductor switch 704b is chopped using the chopping drive signal Sch2, and the AC voltage polarity is low on the side where the reactor 702 is connected. If so, the semiconductor switch 704a is chopped using the chopping drive signal Sch1.
　なお、本実施形態では、半導体スイッチ７０４ａと７０４ｂを同時にオンさせると、負荷４へのＤＣ出力電圧を短絡することになるので、ＡＣ電圧の極性が反転する近傍では、どちらの半導体スイッチ７０４ａ，７０４ｂもオンしないように設定する場合がある。このような場合、図３Ａ及び図３Ｂにおいては、チョッピングが休止状態に変化する位相が、０度及び１８０度近傍でも発生しえることになる。ただし、この場合は、ＤＣ出力電圧の短絡防止として、意図的にチョッピングを休止しているので、本発明に係るチョッピングが休止状態に変化した位相としての取り扱いをしないことで、容易に実現することができる。 In this embodiment, when the semiconductor switches 704a and 704b are turned on at the same time, the DC output voltage to the load 4 is short-circuited. Therefore, which of the semiconductor switches 704a and 704b is in the vicinity where the polarity of the AC voltage is reversed. May also be set not to turn on. In such a case, in FIGS. 3A and 3B, the phase in which the chopping is changed to the resting state can occur even in the vicinity of 0 degree and 180 degrees. However, in this case, since the chopping is intentionally suspended to prevent a short circuit of the DC output voltage, it is easily realized by not handling the chopping according to the present invention as a phase that has changed to a suspended state. Can do.
　次いで、実施形態１～１０に係る整流回路装置で用いる電圧レベル比較器１０９の２値化処理について、図１６Ａ及び図１６Ｂを参照して以下に説明する。 Next, binarization processing of the voltage level comparator 109 used in the rectifier circuit devices according to Embodiments 1 to 10 will be described below with reference to FIGS. 16A and 16B.
　図１６Ａは本発明の実施形態１～１０に係る整流回路装置の電圧レベル比較器１０９の２値化処理の第１の動作例を説明するための図であって、ＡＣ電圧としきい値電圧Ｖｔｈとの関係と、電圧レベル比較器１０９からの２値信号とを示す信号波形図である。また、図１６Ｂは本発明の実施形態１～１０に係る整流回路装置の電圧レベル比較器１０９の２値化処理の第２の動作例を説明するための図であって、ＡＣ電圧としきい値電圧Ｖｔｈとの関係と、電圧レベル比較器１０９からの２値信号とを示す信号波形図である。 FIG. 16A is a diagram for explaining a first operation example of the binarization processing of the voltage level comparator 109 of the rectifier circuit device according to Embodiments 1 to 10 of the present invention, and illustrates an AC voltage and a threshold voltage Vth. And a binary waveform signal from the voltage level comparator 109. FIG. FIG. 16B is a diagram for explaining a second operation example of the binarization processing of the voltage level comparator 109 of the rectifier circuit device according to Embodiments 1 to 10 of the present invention. It is a signal waveform diagram showing the relationship with the voltage Vth and the binary signal from the voltage level comparator 109.
　すなわち、図１６Ａ及び図１６Ｂは、ＡＣ電圧が一定のレベル以上か否かの情報から電圧位相を検出する方法を示す。この情報はＡＣ電圧の瞬時電圧がしきい値を超えているか否かを２値信号として得る。すなわち、電圧レベル比較器１０９は、ＡＣ電圧をしきい値電圧Ｖｔｈと比較し、ＡＣ電圧がしきい値電圧Ｖｔｈ以上のときハイレベル信号を出力する一方、ＡＣ電圧がしきい値電圧Ｖｔｈ未満のときローレベル信号を出力する。 That is, FIGS. 16A and 16B show a method of detecting a voltage phase from information on whether or not the AC voltage is equal to or higher than a certain level. This information obtains as a binary signal whether or not the instantaneous voltage of the AC voltage exceeds the threshold value. That is, the voltage level comparator 109 compares the AC voltage with the threshold voltage Vth and outputs a high level signal when the AC voltage is equal to or higher than the threshold voltage Vth, while the AC voltage is lower than the threshold voltage Vth. When a low level signal is output.
　ここで、しきい値電圧Ｖｔｈが変動しても２値信号の周期は電源周波数と同一であり、２値信号のハイレベル側又はローレベル側の中点を求めれば、ＡＣ電圧位相の９０度又は２７０度の時間を知ることができる。また、ＡＣ電圧位相の９０度と２７０度の中点は１８０度及び０度の位相になる。このようにして得られた情報を、ＰＬＬなどを用いて逓倍すれば、瞬時瞬時の位相を正確に知ることができる。 Here, even if the threshold voltage Vth fluctuates, the cycle of the binary signal is the same as the power supply frequency. If the midpoint of the high level side or low level side of the binary signal is obtained, the AC voltage phase is 90 degrees. Or you can know the time of 270 degrees. Further, the midpoints of 90 degrees and 270 degrees of the AC voltage phase are 180 degrees and 0 degrees. If the information thus obtained is multiplied using a PLL or the like, the instantaneous instantaneous phase can be accurately known.
　例えば、３６０逓倍すれば、１つのパルスが１度相当になり、このパルスを計数すれば、単位が度の位相情報を得ることができる。そして、得られた位相情報で、その瞬時瞬時の目標電流波形を呼び出せばよい。その他のレベル比較から得られた２値情報を用いて位相を検出する方法については、例えば、本発明者が開示した特許文献４にも提案されており、特に限定されない。 For example, if it is multiplied by 360, one pulse corresponds to 1 degree, and if this pulse is counted, phase information in units of degrees can be obtained. Then, the instantaneous instantaneous target current waveform may be called from the obtained phase information. Other methods for detecting the phase using binary information obtained from level comparison have been proposed in, for example, Patent Document 4 disclosed by the present inventor, and are not particularly limited.
　本実施形態を用いることにより、ＤＣ電圧の検出精度に誤差があっても、チョッピング動作を行っている位相幅が、所望の位相幅になるようにＤＣ電圧を相対的に調整するので、同様の電流波形になり、常に損失が少なく、かつ高調波電流が少ない整流動作が実現される。 By using this embodiment, even if there is an error in the DC voltage detection accuracy, the DC voltage is relatively adjusted so that the phase width in which the chopping operation is performed becomes a desired phase width. A current waveform is obtained, and a rectification operation with always low loss and low harmonic current is realized.
実施形態１１．
　図１７は本発明の実施形態１１に係る整流回路装置の制御回路１００の詳細構成を示すブロック図である。実施形態１１に係る整流回路装置の制御回路１００は、実施形態１に係る図２の制御回路１００と比較して、ＤＣ電圧検出器１１０と減算器２０６との間に、ＡＤ変換器２３０及びＬＰＦ演算器２３１とを挿入したことを特徴とし、デジタル演算で実施する場合に特に有効な実施形態を提供する。以下、図２の制御回路１００との相違点について説明する。 Embodiment 11. FIG.
FIG. 17 is a block diagram showing a detailed configuration of the control circuit 100 of the rectifier circuit device according to Embodiment 11 of the present invention. The control circuit 100 of the rectifier circuit device according to the eleventh embodiment includes an AD converter 230 and an LPF between the DC voltage detector 110 and the subtractor 206, as compared with the control circuit 100 of FIG. The present invention is characterized in that an arithmetic unit 231 is inserted, and provides an embodiment that is particularly effective when implemented by digital computation. Hereinafter, differences from the control circuit 100 of FIG. 2 will be described.
　図１７において、ＤＣ電圧検出器１１０により検出されたＤＣ電圧を示すアナログ信号は、ＡＣ電源１の周波数よりも十分に高いサンプリング周波数でＡＤ変換するＡＤ変換器２３０により、ＡＤ変換値Ｖａｄを示すデジタル信号に変換された後、低域通過フィルタ特性を有する演算（詳細後述）を行うＬＰＦ演算器２３１によりＬＰＦ演算され、その演算結果の信号（ＬＰＦ演算値Ｖｄｃａ）は減算器２０６に出力される。ここで、例えば、ＡＣ電源１の周波数は６０Ｈｚであり、サンプリング周波数は６００ｋＨｚである。 In FIG. 17, an analog signal indicating a DC voltage detected by the DC voltage detector 110 is converted into a digital signal indicating an AD conversion value Vad by an AD converter 230 that performs AD conversion at a sampling frequency sufficiently higher than the frequency of the AC power supply 1. After being converted into a signal, an LPF operation is performed by an LPF operation unit 231 that performs an operation (described later in detail) having a low-pass filter characteristic, and a signal (LPF operation value Vdca) as a result of the operation is output to the subtracter 206. Here, for example, the frequency of the AC power source 1 is 60 Hz, and the sampling frequency is 600 kHz.
　図１８は図１７のＬＰＦ演算器２３１の詳細構成を示すブロック図である。図１８において、ＡＤ変換器２３０からのＡＤ変換値を示す信号は加算器２５３に入力される。加算器２５３は入力されるＡＤ変換値を示す信号と、定数乗算器２５１からの信号とを加算して加算結果であるＬＰＦ演算値Ｖｄｃａを示す信号を減算器２０６に出力するとともに、１つのクロック時間だけ遅延する遅延器２５２を介して定数乗算器２５１に出力する。定数乗算器２５１は入力される信号に対して所定の定数（２ｎ－１）／（２ｎ）を乗算して乗算結果を示す信号を加算器２５３に出力する。図１８のＬＰＦ演算器２３１による演算を、入力をＸ（ｊ）、出力をＹ（ｊ）とし、時系列の漸化式で表現すると、次式（１）のようになる。 FIG. 18 is a block diagram showing a detailed configuration of the LPF calculator 231 of FIG. In FIG. 18, a signal indicating the AD conversion value from the AD converter 230 is input to the adder 253. The adder 253 adds the signal indicating the input AD conversion value and the signal from the constant multiplier 251 to output a signal indicating the LPF operation value Vdca as an addition result to the subtractor 206 and one clock. The data is output to the constant multiplier 251 through a delay device 252 that is delayed by time. The constant multiplier 251 multiplies the input signal by a predetermined constant (2 n −1) / (2 n ) and outputs a signal indicating the multiplication result to the adder 253. When the calculation by the LPF calculator 231 in FIG. 18 is expressed by a time series recursion formula with an input X (j) and an output Y (j), the following formula (1) is obtained.
［数１］
Ｙ（ｊ＋１）←［（２ｎ－１）／（２ｎ）］×Ｙ（ｊ）＋Ｘ（ｊ）　　　（１） [Equation 1]
Y (j + 1) ← [(2 n −1) / (2 n )] × Y (j) + X (j) (1)
　このＬＰＦ演算処理は、演算周期の「２ｎ」倍の時定数を有する一次型の低域通過フィルタであり、かつ、振幅が「２ｎ」倍になる。したがって、この演算を実行することにより、ＡＤ変換値Ｖａｄに小数点以下のｎビットの情報が追加される。 This LPF calculation process is a first-order low-pass filter having a time constant “2 n ” times the calculation cycle, and the amplitude is “2 n ” times. Therefore, by executing this calculation, n-bit information below the decimal point is added to the AD conversion value Vad.
　図１９は図１７の整流回路装置の動作を示す図であって、ＡＣ電源１からのＡＣ電流Ｉａｃと、ＤＣ電圧Ｖｄｃと、ＡＤ変換器２３０のＡＤ変換値Ｖａｄ（上記ＤＣ電圧Ｖｄｃを点線で示す。）とを示す信号波形図である。すなわち、図１９は、単相ＡＣの整流回路で低域通過フィルタ処理を行うことにより、電圧検出精度が向上できる動作原理を示す。 FIG. 19 is a diagram illustrating the operation of the rectifier circuit device of FIG. 17, in which the AC current Iac from the AC power source 1, the DC voltage Vdc, and the AD conversion value Vad of the AD converter 230 (the DC voltage Vdc is indicated by a dotted line). FIG. That is, FIG. 19 shows an operation principle that can improve the voltage detection accuracy by performing the low-pass filter process with a single-phase AC rectifier circuit.
　単相ＡＣ電源１からのＡＣ電圧にはゼロの区間があり、瞬時瞬時の電力が一定でないため、平滑コンデンサ１０６を用いても、ＤＣ電圧には電源周波数の２倍の周波数を有する変動が残る。この変動を少なくするには、平滑コンデンサ１０６のコンデンサ容量を無限に大きくする必要があり、現実的には不可能である。 Since the AC voltage from the single-phase AC power source 1 has a zero interval and the instantaneous instantaneous power is not constant, even if the smoothing capacitor 106 is used, the DC voltage still has a fluctuation having a frequency twice the power source frequency. . In order to reduce this fluctuation, it is necessary to increase the capacitor capacity of the smoothing capacitor 106 infinitely, which is practically impossible.
　図１９（ｃ）は、ＤＣ電圧Ｖｄｃ（点線で示す。）をＡＣ電源１の周波数よりも十分に高いサンプリング周波数でＡＤ変換した場合のＡＤ変換値Ｖａｄとを示す。瞬時瞬時のＤＣ電圧Ｖｄｃに応じて、得られるＡＤ変換値Ｖａｄ（デジタル値）はＫ，Ｋ＋１，Ｋ＋２，Ｋ＋３，…の値をとる。ここで、ＡＤ変換値Ｖａｄに対して低域通過フィルタ演算を行うと、図１９の場合には、（Ｋ＋１）と（Ｋ＋２）の間の値に収束する。さらに、図１８で示したように、低域通過フィルタ演算として２ｎ倍する機能を含んでいるため、｛（Ｋ＋１）×２ｎ｝と｛（Ｋ＋２）×２ｎ｝との間の値（整数値）が得られる。つまり、ＡＤ変換器２３０の分解能に対して、小数点以下のｎビットの情報が追加されて、分解能が改善されたことになる。なお、ＤＣ電圧Ｖｄｃに電源周波数の２倍の周波数を有する変動が全く無く、図１９（ｃ）の平均値のような場合には、ＡＤ変換値Ｖａｄは常に（Ｋ＋１）になり、ＬＰＦ演算をしても、分解能を改善することはできない。すなわち、本手法は、単相ＡＣの整流回路装置により、その効果を発揮することができる。 FIG. 19C shows an AD conversion value Vad when the DC voltage Vdc (indicated by a dotted line) is AD converted at a sampling frequency sufficiently higher than the frequency of the AC power supply 1. In accordance with the instantaneous instantaneous DC voltage Vdc, the obtained AD conversion value Vad (digital value) takes values of K, K + 1, K + 2, K + 3,. Here, when the low-pass filter operation is performed on the AD conversion value Vad, the value converges to a value between (K + 1) and (K + 2) in the case of FIG. Further, as shown in FIG. 18, since it includes a function of multiplying 2 n as a low-pass filter operation, a value between {(K + 1) × 2 n } and {(K + 2) × 2 n } ( Integer value). That is, the resolution is improved by adding n bits of information after the decimal point to the resolution of the AD converter 230. When the DC voltage Vdc has no fluctuation having a frequency twice the power supply frequency and is the average value in FIG. 19C, the AD conversion value Vad is always (K + 1), and the LPF calculation is performed. However, the resolution cannot be improved. In other words, this method can exert its effect by a single-phase AC rectifier circuit device.
変形例及び補足説明．
　実施形態１に係る図２の減算器２０６において、指令電圧Ｖｄｃ＊にもＡＤ変換器２３０と同等の分解能を有する必要があるが、指令電圧Ｖｄｃ＊は情報のみであるため、上記と同様に分解能を高めておくことは、容易に実現できる。 Modifications and supplementary explanation.
In the subtractor 206 of FIG. 2 according to the first embodiment, the command voltage Vdc * needs to have the same resolution as that of the AD converter 230. However, since the command voltage Vdc * is information only, the resolution is similar to the above. It is easy to increase the value.
　また、ＬＰＦ演算では２の累乗を用いる事例で説明したが、定数乗算器２５１の定数を０から１の間の値に設定すれば、同様にＬＰＦ演算を実現することができる。また、図１９の動作原理から明らかなように、ＬＰＦ演算が図１８で示した方法以外の手法でも同様の効果を得ることができる。 In the LPF calculation, the case of using a power of 2 has been described. However, if the constant of the constant multiplier 251 is set to a value between 0 and 1, the LPF calculation can be similarly realized. Further, as apparent from the operation principle of FIG. 19, the same effect can be obtained even if the LPF calculation is a method other than the method shown in FIG.
　実施形態１１に係るＡＤ変換器２３０の分解能が粗い場合でも、きめ細かい電圧情報を得ることができるので、ＤＣ電圧Ｖｄｃを高精度に調節することができ、常に損失が少なく、かつ、高調波電流が少ない整流動作が実現される。また、本実施形態１１に係る手法は、これまで説明した実施形態１～１０を組み合わせて実施することが可能である。 Even when the resolution of the AD converter 230 according to the eleventh embodiment is rough, fine voltage information can be obtained, so that the DC voltage Vdc can be adjusted with high accuracy, the loss is always small, and the harmonic current is small. Less rectification operation is realized. Further, the technique according to the eleventh embodiment can be implemented by combining the first to tenth embodiments described so far.
　なお、全ての実施形態に共通することとして、チョッピングが休止状態からチョッピング状態に変化する際に、回路の揺らぎやノイズにより、一瞬だけ休止状態に再度変化する場合があるが、これについては、本発明でのチョッピングが休止状態に変化した位相としての取り扱いをしないことで、容易に実現することができる。 In addition, as common to all the embodiments, when chopping changes from the resting state to the chopping state, it may change again to the resting state for a moment due to circuit fluctuations or noise. The chopping in the invention can be easily realized by not handling as a phase changed to a dormant state.
　さらに、本発明に係る実施形態において、ＡＣ電圧位相検出器２０１においてＡＣ電圧の位相を検出してそれを基準としてチョッピング位相幅を検出しているが、本発明はこれに限らず、ＡＣ電源１の周波数が固定されている場合には、ＡＣ電源１のゼロクロスなどの情報に基づいてチョッピング位相幅を検出してもよい。また、チョッピング位相幅を検出するときに、チョッピング手法の一例であるＰＷＭ制御を実現するキャリア信号のパルス数で計数することでチョッピング位相幅の時間を計測してもよい。 Furthermore, in the embodiment according to the present invention, the AC voltage phase detector 201 detects the phase of the AC voltage and detects the chopping phase width based on the detected phase. However, the present invention is not limited to this, and the AC power source 1 If the frequency is fixed, the chopping phase width may be detected based on information such as zero crossing of the AC power supply 1. Further, when detecting the chopping phase width, the time of the chopping phase width may be measured by counting with the number of pulses of the carrier signal that realizes the PWM control which is an example of the chopping technique.
　以上詳述したように、本発明に係る整流回路装置は、高調波電流の抑制と回路損失の低減を両立することが可能となるので、圧縮機により冷媒を圧縮することによりヒートポンプを構成し、冷房、暖房、あるいは食品などの冷凍を行うもの等の用途にも適用できる。 As described above in detail, the rectifier circuit device according to the present invention can achieve both suppression of harmonic current and reduction of circuit loss, so that a heat pump is configured by compressing refrigerant with a compressor, The present invention can also be applied to applications such as cooling, heating, or freezing foods.
１…交流電源、
４…負荷、
１００，１１１，１１２…制御回路、
１０２，６０２，７０２…リアクタ、
１０３…電流検出器、
１０４，６０４ａ，６０４ｂ，７０４ａ，７０４ｂ…半導体スイッチ、
１０５…ダイオードブリッジ回路、
１０６…平滑コンデンサ、
１０９…電圧レベル比較器、
１１０…ＤＣ電圧検出器、
２０１…ＡＣ電圧位相検出器、
２０２…目標電流波形形成器、
２０３…目標位相幅設定器、
２０４，２０６，２０９…減算器、
２０５…位相幅補償演算器、
２０７…Ｖｄｃ補償演算器、
２０８…乗算器、
２１０…Ｉａｃ補償演算器、
２１１…パルス幅変調器、
２１２…チョッピング位相幅検出器、
２１３…入力状況判定器、
２１３ａ…入力電流変動判定値設定器、
２１４，２１４Ａ…目標位相幅選定器、
２１４ｍ，２１４Ａｍ…内蔵テーブルメモリ、
２１５…駆動状況判定器、
２１６，２１６Ａ…チョッピング位相幅抽出器、
２３０…ＡＤ変換器、
２３１…低域通過フィルタ演算器、
２５１…定数乗算器、
２５２…遅延器、
２５３…加算器、
３００…圧縮駆動部、
３０１…圧縮機、
３０２…圧縮機制御回路、
６０５ａ～６０５ｄ，７０５ａ～７０５ｄ…ダイオード。 1 ... AC power supply,
4 ... Load,
100, 111, 112 ... control circuit,
102,602,702 ... reactor,
103 ... current detector,
104, 604a, 604b, 704a, 704b ... semiconductor switch,
105. Diode bridge circuit,
106: smoothing capacitor,
109 ... voltage level comparator,
110 ... DC voltage detector,
201 ... AC voltage phase detector,
202 ... target current waveform former,
203 ... Target phase width setting device,
204, 206, 209 ... subtractor,
205 ... Phase width compensation calculator,
207 ... Vdc compensation calculator,
208 ... multiplier,
210 ... Iac compensation calculator,
211 ... pulse width modulator,
212 ... chopping phase width detector,
213... Input status determination device,
213a: Input current fluctuation judgment value setting device,
214, 214A ... Target phase width selector,
214m, 214Am ... built-in table memory,
215 ... Driving status determiner,
216, 216A ... Chopping phase width extractor,
230: AD converter,
231 ... Low-pass filter computing unit,
251 ... Constant multiplier,
252 ... delay device,
253 ... Adder,
300 ... compression drive unit,
301 ... Compressor,
302 ... compressor control circuit,
605a to 605d, 705a to 705d, diodes.

Claims (20)

  1. 　半導体スイッチをチョッピング動作させることにより、単相交流電源の出力端子をリアクタを介して短絡又は開放し、前記単相交流電源から前記リアクタを介して供給される交流電圧を直流電圧に整流して負荷に供給する整流回路装置であって、
    　前記交流電圧の波形と同一周波数の目標電流波形を形成する波形形成手段と、
    　前記単相交流電源から流れる交流電流を検出する電流検出手段と、
    　前記直流電圧を検出する電圧検出手段と、
    　前記検出された交流電流の波形が実質的に前記目標電流波形となるように前記半導体スイッチのチョッピング動作を制御する第１の制御手段と、
    　前記検出された直流電圧が実質的に所定の目標直流電圧となるように前記目標電流波形の振幅を制御する第２の制御手段と、
    　前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、もしくは、前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御する第３の制御手段とを備えたことを特徴とする整流回路装置。     By chopping the semiconductor switch, the output terminal of the single-phase AC power supply is short-circuited or opened via the reactor, and the AC voltage supplied from the single-phase AC power supply via the reactor is rectified into a DC voltage and loaded. A rectifier circuit device for supplying to
    Waveform forming means for forming a target current waveform having the same frequency as the waveform of the AC voltage;
    Current detecting means for detecting an alternating current flowing from the single-phase AC power source;
    Voltage detecting means for detecting the DC voltage;
    First control means for controlling the chopping operation of the semiconductor switch so that the waveform of the detected alternating current substantially becomes the target current waveform;
    Second control means for controlling the amplitude of the target current waveform such that the detected DC voltage is substantially a predetermined target DC voltage;
    The predetermined target DC voltage is controlled so that a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state is substantially a predetermined phase width. A rectifier circuit device comprising a third control means.
  2. 　前記所定の位相幅は、前記負荷の電気的特性に依存して変更して設定されることを特徴とする請求項１記載の整流回路装置。 The rectifier circuit device according to claim 1, wherein the predetermined phase width is changed and set depending on an electrical characteristic of the load.
  3. 　前記負荷の電気的特性は、前記交流電流の変動幅、もしくは前記負荷が圧縮機であるときの圧縮機モータへの回転数指令であることを特徴とする請求項２記載の整流回路装置。 3. The rectifier circuit device according to claim 2, wherein the electrical characteristics of the load are a fluctuation range of the alternating current or a rotational speed command to a compressor motor when the load is a compressor.
  4. 　前記第３の制御手段は、前記交流電圧の極性が固定されている期間内において、複数の前記チョッピング動作位相幅又は複数の前記チョッピング休止位相幅があるときに、当該期間内のいずれかの位相幅、もしくは、合計の位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御することを特徴とする請求項１乃至３のうちのいずれか１つに記載の整流回路装置。 When the third control means has a plurality of the chopping operation phase widths or a plurality of the chopping pause phase widths within a period in which the polarity of the AC voltage is fixed, any phase in the period is included. The rectification according to any one of claims 1 to 3, wherein the predetermined target DC voltage is controlled so that a width or a total phase width is substantially a predetermined phase width. Circuit device.
  5. 　前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、
    （ａ）当該期間の開始点から、所定の中間点までは、時間経過とともに、少なくとも増加し、もしくは少なくとも増加しかつ一部期間で一定であるように実質的に単調増加し、
    （ｂ）前記中間点から終了点までに、時間経過とともに、少なくとも減少し、もしくは少なくとも減少しかつ一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定されたことを特徴とする請求項１乃至４のうちのいずれか１つに記載の整流回路装置。     The target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
    (A) From the starting point of the period to the predetermined intermediate point, it increases at least over time, or at least increases and increases substantially at least monotonously so as to be constant over a period of time,
    (B) A period from the intermediate point to the end point that has at least decreased with time, or at least decreased and substantially monotonically decreased to be constant in a certain period, and then has a period that becomes zero. The rectifier circuit device according to any one of claims 1 to 4, wherein the rectifier circuit device is set.
  6. 　前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、
    （ａ）当該期間の開始点から、所定の第１の中間点までは、時間経過とともに、ゼロとなる期間を有し、
    （ｂ）前記第１の中間点から所定の第２の中間点までは、少なくとも増加し、もしくは少なくとも増加しかつ一部期間で一定であるように実質的に単調増加し、
    （ｃ）前記第２の中間点から終了点までに、時間経過とともに、少なくとも減少し、もしくは少なくとも減少しかつ一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定されたことを特徴とする請求項１乃至４のうちのいずれか１つに記載の整流回路装置。     The target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
    (A) From the starting point of the period to the predetermined first intermediate point, there is a period that becomes zero with time,
    (B) from the first intermediate point to the predetermined second intermediate point at least increases or at least increases and substantially monotonically increases to be constant over a period of time;
    (C) from the second intermediate point to the end point, a time period that is at least decreased with time, or at least decreased and substantially monotonically decreased so as to be constant in a certain period, and then becomes zero. The rectifier circuit device according to any one of claims 1 to 4, wherein the rectifier circuit device is set to have.
  7. 　前記交流電圧を所定のしきい値電圧と比較することにより２値信号を発生する位相検出手段をさらに備え、
    　前記波形形成手段は、前記２値信号に基づいて前記交流電圧の周期及び位相を検出し、当該検出された交流電圧の周期及び位相に基づいて、前記交流電圧の波形と同一周波数の目標電流波形を形成し、
    　前記第３の制御手段は、前記２値信号に基づいて、前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、もしくは、前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅を検出することを特徴とする請求項１乃至５のうちのいずれか１つに記載の整流回路装置。     Phase detection means for generating a binary signal by comparing the alternating voltage with a predetermined threshold voltage;
    The waveform forming means detects a period and a phase of the AC voltage based on the binary signal, and a target current waveform having the same frequency as the waveform of the AC voltage based on the detected period and phase of the AC voltage. Form the
    The third control means detects, based on the binary signal, a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state. The rectifier circuit device according to claim 1, wherein the rectifier circuit device is a rectifier circuit device.
  8. 　前記整流回路装置はさらに、
    　前記電圧検出手段と前記第２の制御手段との間に設けられ、前記検出された直流電圧をデジタル電圧にＡＤ変換するＡＤ変換手段と、
    　前記ＡＤ変換手段と前記第２の制御手段との間に設けられ、前記デジタル電圧に対して低域フィルタ演算を行った後、当該演算結果の電圧を前記第２の制御手段に前記検出された直流電圧として出力する演算手段とを備えたことを特徴とする請求項１乃至７のうちのいずれか１つに記載の整流回路装置。     The rectifier circuit device further includes
    AD conversion means provided between the voltage detection means and the second control means, and AD-converts the detected DC voltage into a digital voltage;
    Provided between the AD conversion means and the second control means, and after performing a low-pass filter operation on the digital voltage, the voltage of the calculation result is detected by the second control means The rectifier circuit device according to any one of claims 1 to 7, further comprising arithmetic means for outputting as a DC voltage.
  9. 　前記ＡＤ変換手段のサンプリング周波数は、前記単相交流電源の周波数よりも十分に高くなるように設定されたことを特徴とする請求項８記載の整流回路装置。 The rectifier circuit device according to claim 8, wherein the sampling frequency of the AD conversion means is set to be sufficiently higher than the frequency of the single-phase AC power supply.
  10. 　前記低域通過フィルタ演算は、直前の演算結果に「（２ｎ－１）／（２ｎ）」なる係数（ｎは整数である。）を乗算した後、入力されたデジタル電圧と加算し、当該加算結果の値を次の演算結果として用いて実行されることを特徴とする請求項８又は９記載の整流回路装置。 The low-pass filter operation multiplies the previous operation result by a coefficient ((2 n −1) / (2 n )) (n is an integer), and then adds the input digital voltage. The rectifier circuit device according to claim 8, wherein the rectifier circuit device is executed using the value of the addition result as a next calculation result.
  11. 　半導体スイッチをチョッピング動作させることにより、単相交流電源の出力端子をリアクタを介して短絡又は開放し、前記単相交流電源から前記リアクタを介して供給される交流電圧を直流電圧に整流して負荷に供給する整流回路装置のための制御回路において、
    　上記制御回路は、
    　前記交流電圧の波形と同一周波数の目標電流波形を形成する波形形成手段と、
    　前記単相交流電源から流れる交流電流の波形が実質的に前記目標電流波形となるように前記半導体スイッチのチョッピング動作を制御する第１の制御手段と、
    　前記直流電圧が実質的に所定の目標直流電圧となるように前記目標電流波形の振幅を制御する第２の制御手段と、
    　前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、もしくは、前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御する第３の制御手段とを備えたことを特徴とする制御回路。     By chopping the semiconductor switch, the output terminal of the single-phase AC power supply is short-circuited or opened via the reactor, and the AC voltage supplied from the single-phase AC power supply via the reactor is rectified into a DC voltage and loaded. In a control circuit for a rectifier circuit device supplied to
    The control circuit is
    Waveform forming means for forming a target current waveform having the same frequency as the waveform of the AC voltage;
    First control means for controlling a chopping operation of the semiconductor switch so that a waveform of an alternating current flowing from the single-phase alternating current power supply substantially becomes the target current waveform;
    Second control means for controlling the amplitude of the target current waveform so that the DC voltage substantially becomes a predetermined target DC voltage;
    The predetermined target DC voltage is controlled so that a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state is substantially a predetermined phase width. And a third control means.
  12. 　前記所定の位相幅は、前記負荷の電気的特性に依存して変更して設定されることを特徴とする請求項１１記載の制御回路。 12. The control circuit according to claim 11, wherein the predetermined phase width is changed and set depending on an electrical characteristic of the load.
  13. 　前記負荷の電気的特性は、前記交流電流の変動幅、もしくは前記負荷が圧縮機であるときの圧縮機モータへの回転数指令であることを特徴とする請求項１２記載の制御回路。 13. The control circuit according to claim 12, wherein the electrical characteristic of the load is a fluctuation range of the alternating current or a rotational speed command to a compressor motor when the load is a compressor.
  14. 　前記第３の制御手段は、前記交流電圧の極性が固定されている期間内において、複数の前記チョッピング動作位相幅又は複数の前記チョッピング休止位相幅があるときに、当該期間内のいずれかの位相幅、もしくは、合計の位相幅が実質的に所定の位相幅となるように前記所定の目標直流電圧を制御することを特徴とする請求項１１乃至１３のうちのいずれか１つに記載の制御回路。 When the third control means has a plurality of the chopping operation phase widths or a plurality of the chopping pause phase widths within a period in which the polarity of the AC voltage is fixed, any phase in the period is included. 14. The control according to claim 11, wherein the predetermined target DC voltage is controlled such that a width or a total phase width is substantially a predetermined phase width. circuit.
  15. 　前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、
    （ａ）当該期間の開始点から、所定の中間点までは、時間経過とともに、少なくとも増加し、もしくは少なくとも増加しかつ一部期間で一定であるように実質的に単調増加し、
    （ｂ）前記中間点から終了点までに、時間経過とともに、少なくとも減少し、もしくは少なくとも減少しかつ一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定されたことを特徴とする請求項１１乃至１４のうちのいずれか１つに記載の制御回路。     The target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
    (A) From the starting point of the period to the predetermined intermediate point, it increases at least over time, or at least increases and increases substantially at least monotonously so as to be constant over a period of time,
    (B) A period from the intermediate point to the end point that has at least decreased with time, or at least decreased and substantially monotonically decreased to be constant in a certain period, and then has a period that becomes zero. The control circuit according to claim 11, wherein the control circuit is set.
  16. 　前記目標電流波形は、前記目標電流波形の瞬時の絶対値が、前記交流電圧の極性が固定されている期間内において、
    （ａ）当該期間の開始点から、所定の第１の中間点までは、時間経過とともに、ゼロとなる期間を有し、
    （ｂ）前記第１の中間点から所定の第２の中間点までは、少なくとも増加し、もしくは少なくとも増加しかつ一部期間で一定であるように実質的に単調増加し、
    （ｃ）前記第２の中間点から終了点までに、時間経過とともに、少なくとも減少し、もしくは少なくとも減少しかつ一部期間で一定であるように実質的に単調減少した後、ゼロとなる期間を有するように設定されたことを特徴とする請求項１１乃至１４のうちのいずれか１つに記載の制御回路。     The target current waveform has an instantaneous absolute value of the target current waveform within a period in which the polarity of the AC voltage is fixed.
    (A) From the start point of the period to the predetermined first intermediate point, there is a period that becomes zero with time,
    (B) from the first intermediate point to the predetermined second intermediate point at least increases or at least increases and substantially monotonically increases to be constant over a period of time;
    (C) from the second intermediate point to the end point, a time period that is at least decreased with time, or at least decreased and substantially monotonically decreased so as to be constant in a certain period, and then becomes zero. The control circuit according to claim 11, wherein the control circuit is configured to have a control circuit.
  17. 　上記整流回路装置は、前記交流電圧を所定のしきい値電圧と比較することにより２値信号を発生する位相検出手段をさらに備え、
    　前記波形形成手段は、前記２値信号に基づいて前記交流電圧の周期及び位相を検出し、当該検出された交流電圧の周期及び位相に基づいて、前記交流電圧の波形と同一周波数の目標電流波形を形成し、
    　前記第３の制御手段は、前記２値信号に基づいて、前記半導体スイッチがチョッピング動作状態であるチョッピング動作位相幅、もしくは、前記半導体スイッチがチョッピング休止状態であるチョッピング休止位相幅を検出することを特徴とする請求項１１乃至１５のうちのいずれか１つに記載の制御回路。     The rectifier circuit device further includes phase detection means for generating a binary signal by comparing the AC voltage with a predetermined threshold voltage,
    The waveform forming means detects a period and a phase of the AC voltage based on the binary signal, and a target current waveform having the same frequency as the waveform of the AC voltage based on the detected period and phase of the AC voltage. Form the
    The third control means detects, based on the binary signal, a chopping operation phase width in which the semiconductor switch is in a chopping operation state or a chopping suspension phase width in which the semiconductor switch is in a chopping suspension state. 16. The control circuit according to claim 11, wherein the control circuit is any one of claims 11 to 15.
  18. 　前記制御回路はさらに、
    　前記電圧検出手段と前記第２の制御手段との間に設けられ、前記直流電圧をデジタル電圧にＡＤ変換するＡＤ変換手段と、
    　前記ＡＤ変換手段と前記第２の制御手段との間に設けられ、前記デジタル電圧に対して低域フィルタ演算を行った後、当該演算結果の電圧を前記第２の制御手段に前記直流電圧として出力する演算手段とを備えたことを特徴とする請求項１１乃至１７のうちのいずれか１つに記載の制御回路。     The control circuit further includes
    AD conversion means provided between the voltage detection means and the second control means, and AD-converts the DC voltage into a digital voltage;
    Provided between the AD conversion means and the second control means, and after performing a low-pass filter operation on the digital voltage, the voltage of the calculation result is sent to the second control means as the DC voltage. The control circuit according to claim 11, further comprising an arithmetic means for outputting.
  19. 　前記ＡＤ変換手段のサンプリング周波数は、前記単相交流電源の周波数よりも十分に高くなるように設定されたことを特徴とする請求項１８記載の制御回路。 19. The control circuit according to claim 18, wherein the sampling frequency of the AD conversion means is set to be sufficiently higher than the frequency of the single-phase AC power supply.
  20. 　前記低域通過フィルタ演算は、直前の演算結果に「（２ｎ－１）／（２ｎ）」なる係数（ｎは整数である。）を乗算した後、入力されたデジタル電圧と加算し、当該加算結果の値を次の演算結果として用いて実行されることを特徴とする請求項１８又は１９記載の制御回路。 The low-pass filter operation multiplies the previous operation result by a coefficient ((2 n −1) / (2 n )) (n is an integer), and then adds the input digital voltage. 20. The control circuit according to claim 18, wherein the control circuit is executed using a value of the addition result as a next calculation result.
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