WO2011101935A1 - Solid-state image pickup element and method for manufacturing same - Google Patents

Solid-state image pickup element and method for manufacturing same Download PDF

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Publication number
WO2011101935A1
WO2011101935A1 PCT/JP2010/006449 JP2010006449W WO2011101935A1 WO 2011101935 A1 WO2011101935 A1 WO 2011101935A1 JP 2010006449 W JP2010006449 W JP 2010006449W WO 2011101935 A1 WO2011101935 A1 WO 2011101935A1
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film
charge transfer
solid
photodiode
insulating film
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PCT/JP2010/006449
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French (fr)
Japanese (ja)
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教章 鈴木
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H01L27/14831—Area CCD imagers
    • H01L27/14843—Interline transfer

Definitions

  • the present invention relates to a solid-state imaging device and a manufacturing method thereof, and more particularly, to a solid-state imaging device having a charge transfer electrode having a single layer structure and a manufacturing method thereof.
  • CCD Charge-Coupled Device
  • CCD Charge-Coupled Device
  • a CCD having a single-layer electrode structure has an advantage that the interelectrode capacitance is small because there is no overlapping portion between the charge transfer electrodes.
  • a predetermined voltage such as ground potential is normally applied to the light-shielding film formed on the charge transfer electrode, but a single-layer electrode structure with almost no surface unevenness ensures a breakdown voltage between the charge transfer electrode and the light-shielding film. It also has the advantage of being easy.
  • FIG. 18 is a typical schematic plan view of a solid-state imaging device (CCD).
  • the solid-state imaging device 40 includes an imaging region 41 in which a photodiode 42 that photoelectrically converts incident light and a vertical transfer unit 43 that transfers a signal charge generated by the photodiode 42 in the vertical direction are arranged.
  • a horizontal transfer unit 44 is provided adjacent to the imaging region 41 to transfer the signal charges transferred by the vertical transfer unit 43 in the horizontal direction.
  • the plurality of photodiodes 42 are arranged in a matrix, and a vertical transfer unit 43 is disposed between each column of the photodiodes 42.
  • no charge transfer electrode is shown in FIG. 18, in the drawing, one charge transfer electrode extends in the horizontal direction from the right end region to the left end region of the imaging region 41.
  • the signal charge transferred by the horizontal transfer unit 44 is output as an electric signal via the output amplifier 45.
  • the length of the charge transfer electrode is increased because the horizontal length of the imaging region 41 is long.
  • a propagation delay occurs in the drive pulse signal applied by changing the phase from the bus line provided outside the imaging region 41 at one end of the charge transfer electrode to each of the charge transfer electrodes. Becomes a problem.
  • This propagation delay is due to the time required for the drive pulse signal to be transmitted to the vertical transfer unit 43 close to the bus line and the distance from the bus line because the charge transfer electrode is made of a silicon film having a sheet resistance value of several tens of ⁇ / ⁇ . This means that there is a difference between the time required for the drive pulse signal to be transmitted to the vertical transfer unit 43.
  • CCDs are required to have higher speed.
  • miniaturization of the charge transfer electrode has been promoted in order to reduce the ineffective region that does not contribute to the detection of incident light and increase the photodiode region. Therefore, the resistance value of the charge transfer electrode is in an increasing direction.
  • the charge transfer electrode is further miniaturized, a problem arises in that the voltage for reading the charge transfer electrode from the photodiode to the charge transfer unit increases. As such a situation progresses, the problem of the voltage drop due to the propagation delay and the wiring resistance becomes conspicuous. Therefore, it is important to reduce the resistance of the charge transfer electrode.
  • FIG. 20 is a schematic cross-sectional view of the main part showing the charge transfer electrode portion of the solid-state imaging device disclosed in Patent Document 1.
  • the charge transfer electrode is composed of a silicon-based film 101, tungsten nitride 102 and tungsten 103.
  • a silicon glass film 104, a silicon nitride film 105, and a sidewall 106 are formed on the upper surface of the charge transfer electrode, and these films serve as a hard mask when the charge transfer electrode pattern is formed by etching.
  • a narrow space between the electrodes is filled with an oxide film 107 and a silicon nitride film 108.
  • a trapezoidal pattern 100 made of a silicon-based film is provided below the both ends of the charge transfer electrode.
  • the resistance is reduced by using a refractory metal such as tungsten for the charge transfer electrode.
  • the trapezoidal pattern 100 is provided to lift the silicon-based film 101 at the end of the charge transfer electrode so that the tungsten 103 is surrounded by the silicon-based film 101. This prevents the tungsten 103 from being directly exposed to the high-temperature oxidizing atmosphere during the growth of the oxide film 107 that can be formed with a narrow electrode interval and good coverage, thereby preventing the abnormal expansion of the tungsten 103 and the resulting breakdown of the electrode gap. .
  • the charge transfer electrode when the charge transfer electrode is miniaturized, it becomes difficult to improve the S / N ratio (signal / noise ratio).
  • the area occupied by the photodiode is increased and the optical sensitivity is improved.
  • the opening area of the light shielding film is maximized, it becomes difficult to surely prevent light from entering the charge transfer portion, and noise increases. That is, in order to improve the S / N ratio, it is necessary to achieve both the maximization of the opening area and the maximization of the light shielding region.
  • the charge transfer electrode itself is made of a metal material film having a low resistance and a light shielding property so as to function as a light shielding film of the charge transfer portion (see, for example, Patent Document 2).
  • the charge transfer electrode is not only on the vertical transfer unit 43 but also directly above the photodiode 42, and a narrow region between the photodiodes 42 adjacent to each other in the vertical direction. It is necessary to pass through the top.
  • the interval between the photodiodes 42 is narrowed, and the width passing through this portion of the charge transfer electrode needs to be reduced to about 0.2 ⁇ m in the recent pixel cell size.
  • the structure of the conventional charge transfer electrode described in Patent Document 1 can be realized in the portion where the size of the electrode on the vertical transfer portion 43 may remain large, but in the extremely thin portion described above, it has a high resistance. Therefore, the tungsten 103 cannot be formed in the center of the electrode. Therefore, even if the charge transfer electrode is partially reduced in resistance by the tungsten 103, there is a problem that the effect of reducing the resistance as a whole becomes very small.
  • the insulating film disposed between the charge transfer electrode and the semiconductor substrate on which the charge transfer portion is formed is also formed on the photodiode.
  • a surface impurity layer is formed on the surface portion of the photodiode to suppress dark current, ion implantation is performed through the insulating film.
  • the saturation amount of each photodiode may be increased as much as possible to improve optical sensitivity. Desired. In order to increase the photodiode saturation amount, it is necessary to make the signal charge generation region width in the depth direction as large as possible in each photodiode.
  • the surface impurity layer is formed on the extreme surface of the photodiode. Is required.
  • ion implantation for forming the surface impurity layer is performed through the insulating film covering the photodiode, it is necessary to use implantation energy that can pass through the insulating film.
  • the distribution width of impurities in the depth direction increases. That is, as the implantation energy increases, the reverse conductivity type impurity constituting the surface impurity layer is introduced to a deeper position of the photodiode, and the saturation amount of each photodiode is reduced.
  • an antireflection film is provided on the insulating film covering the photodiode for the purpose of improving the optical sensitivity of the photodiode.
  • the antireflection effect of such an antireflection film is determined based on the refractive index and film thickness of the antireflection film, the refractive index and film thickness of the insulating film as the lower layer film, and the wavelength of the target that obtains the antireflection effect. . Therefore, when the film thickness of the lower layer film is fixed, the degree of freedom in designing the antireflection film becomes low, and a situation where the optimum antireflection effect cannot be obtained may occur.
  • the present invention has been proposed in view of the above-described conventional circumstances, and has a low-resistance charge transfer electrode made of a metal material film, and can be driven with high sensitivity and high speed even when miniaturized. It aims at providing the manufacturing method.
  • the solid-state imaging device includes, on a semiconductor substrate, a photodiode that generates a signal charge corresponding to incident light by photoelectric conversion, and a charge transfer unit that transfers the signal charge generated in the photodiode.
  • An insulating film is provided on the surface of the semiconductor substrate.
  • the insulating film includes a thin film portion that covers the photodiode and a thick film portion that covers the charge transfer portion and is thicker than the thin film portion.
  • a charge transfer electrode made of a metal material film that transfers signal charges in the charge transfer portion is provided on the thick film portion of the insulating film that covers the charge transfer portion.
  • the charge transfer electrode made of a metal material film is disposed on the thick film portion, desired threshold control can be performed.
  • the thin film portion is disposed on the photodiode, the surface impurity layer on the photodiode surface portion can be formed by shallow doping. Therefore, even when the charge transfer electrode is miniaturized, it is possible to suppress a decrease in optical sensitivity.
  • an antireflection film can be further provided on the insulating film covering the photodiode.
  • the charge transfer electrode may include a sidewall having an end that coincides with the end of the thin film portion of the insulating film.
  • the antireflection film preferably covers the sidewall.
  • the antireflection film can include, for example, a silicon nitride film.
  • the metal material film may include tungsten or aluminum, or may include a laminated structure of titanium nitride and aluminum.
  • the present invention can provide a method for manufacturing a solid-state imaging device. That is, in the method for manufacturing a solid-state imaging device according to the present invention, first, a photodiode that generates a signal charge corresponding to incident light by photoelectric conversion on a semiconductor substrate, and a charge that transfers the signal charge generated in the photodiode. A transfer unit is formed. Next, a first insulating film is formed on the semiconductor substrate on which the photodiode and the charge transfer portion are formed. Subsequently, a dummy pattern is formed on the charge transfer portion via the first insulating film. The dummy pattern has the same planar layout as the charge transfer electrode that transfers the signal charge in the charge transfer portion.
  • a second insulating film is formed on the semiconductor substrate on which the dummy pattern is formed.
  • the insulating film of the margin 2 fills the gap between the dummy patterns that are adjacent to each other along the charge transfer direction of the charge transfer portion.
  • the second insulating film on the dummy pattern and the photodiode is removed by etching, and a sidewall made of the second insulating film is formed on the dummy pattern.
  • the thickness of the first insulating film on the photodiode is reduced.
  • the dummy pattern surrounded by the second insulating film remaining on the semiconductor substrate is removed and replaced with a charge transfer electrode made of a metal material film.
  • a special process is added to an insulating film that includes a thick film portion that covers the charge transfer portion and has a charge transfer electrode formed on the upper surface, and a thin film portion that covers the photodiode. It can form without. Further, by adopting the insulating film having the thick film portion and the thin film portion, it is possible to suppress a decrease in optical sensitivity even when the charge transfer electrode is miniaturized as described above. .
  • impurities are introduced through the first insulating film having a reduced thickness, and signal charges and charges of opposite conductivity type are applied to the surface portion of the photodiode. It is preferable to form a surface impurity layer to be accumulated.
  • An antireflection film may be formed on the first insulating film covering the photodiode after the impurity is introduced through the first insulating film having a reduced thickness and before the dummy pattern is removed. preferable.
  • the dummy pattern can be composed of a silicon film.
  • a wiring or electrode made of a silicon-based film by partially replacing the dummy pattern in the solid-state imaging device, it is possible to form a wiring or electrode made of a silicon-based film.
  • the present invention it is possible to stably form a solid-state imaging device having a low-resistance charge transfer electrode made of a metal material film and capable of high sensitivity and high-speed driving even in the future further miniaturization.
  • FIG. 1 is a cross-sectional view illustrating a schematic configuration of a solid-state imaging device according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 3 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 4 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 5 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 7 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 8 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 9 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 10 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 11 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 12 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 13 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 14 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 15 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 16 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 17 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • FIG. 18 is a schematic plan configuration diagram of a solid-state imaging device.
  • FIG. 19 is a plan layout diagram showing a part of the pixel cell array of the solid-state imaging device.
  • FIG. 20 is a schematic cross-sectional view showing an example of a conventional charge transfer electrode structure of a solid-state imaging device.
  • FIG. 19 is a plan pattern layout diagram showing a part of the pixel cell array formed in the imaging region 41 of the solid-state imaging device.
  • four charge transfer electrodes 14a extend in the lateral direction, and a photodiode (not shown) is formed in a central rectangular region surrounded by the charge transfer electrodes 14a.
  • a vertical transfer portion 43 is provided to extend in the vertical direction under the wide region of the charge transfer electrode 14a.
  • description of various interlayer insulating films, planarization films, interlayer lenses, color filters, on-chip lenses, and the like formed on the pixel cell array region together with the photodiodes is omitted.
  • FIG. 1 is a cross-sectional view showing a schematic configuration of a solid-state imaging device according to an embodiment of the present invention.
  • FIG. 1 is a cross section taken along line XX shown in FIG. 19, and shows a cross-sectional structure of one pixel portion.
  • the solid-state imaging device is formed on a semiconductor substrate 1 made of a silicon single crystal substrate.
  • a photodiode 2 and a vertical transfer portion (charge transfer portion) 4 that generate signal charges corresponding to incident light are provided on the surface portion of the semiconductor substrate 1.
  • a gate insulating film 5 made of a silicon oxide film or the like is provided on the photodiode 2 and the vertical transfer portion 4.
  • the gate insulating film 5 includes a thick film portion 5a having a larger film thickness and a thin film portion 5b having a smaller film thickness than the thick film portion 5a at least in the pixel cell array region.
  • the thin film portion 5 b of the gate insulating film 5 is disposed on the photodiode 2.
  • the thick film portion 5a of the gate insulating film 5 is disposed on the vertical transfer portion 4, and the charge transfer electrode 14a made of a metal material film is disposed on the thick film portion 5a.
  • Each charge transfer electrode 14a is provided with a side wall 9a made of a silicon oxide film or the like, and the end of the side wall 9a coincides with the end of the thin film portion 5b.
  • An antireflection film 10 made of a silicon nitride film or the like is provided on the photodiode 2 and the sidewall 9a.
  • a planarizing film 11 made of a silicon oxide film or the like is provided to fill the gap. The antireflection film 10 is opened on the upper surface of the charge transfer electrode 14a, and there is no antireflection film 10 on each charge transfer electrode 14a.
  • an inner lens 17 made of a silicon nitride film (P-SiN film) deposited by a plasma CVD method through an interlayer insulating film 16 made of a silicon oxide film or the like corresponds to each photodiode 2.
  • a color filter 19 and a microlens 20 are arranged corresponding to each photodiode 2 via a filter under-flattening film 18 made of a transparent resin or the like.
  • the color filter 19 is, for example, a single color filter selected from a red filter that transmits red light, a green filter that transmits green light, and a blue filter that transmits blue light.
  • the color filters are not distinguished from each other in FIG.
  • the gate insulating film 5 includes a thick film portion 5 a disposed on the vertical transfer portion 4 and a thin film portion 5 b disposed on the photodiode 2. That is, since the charge transfer electrode 14a made of a metal material film is disposed on the thick film portion 5a, desired threshold control can be performed. Further, since the thin film portion 5b is disposed on the photodiode 2, the surface impurity layer 21 can be formed by shallow doping. Moreover, a favorable antireflection effect can be obtained by combination with the antireflection film 10.
  • the charge transfer electrode 14a is made of a low-resistance metal material film, the charge transfer electrode 14a can be thinned. As a result, even when the charge transfer electrode 14a is miniaturized, the interelectrode capacitance can be reduced and high-speed driving is possible.
  • the charge transfer electrode also serves as a light shielding film, it is possible to simultaneously increase the opening area of the light shielding film and increase the width of the vertical transfer path 4, and improve the S / N ratio. That is, high sensitivity can be achieved.
  • the charge transfer electrode 14a has a single-layer electrode structure in which there is no overlap between adjacent charge transfer electrodes, and also functions as a light shielding film. Therefore, the conventional light shielding film formed in a state of covering the charge transfer electrode is unnecessary. Therefore, the light shielding film does not rise high on the side wall of the charge transfer electrode. For example, in a configuration in which the light shielding film stands high on the side wall of the charge transfer electrode, the path of incident light needs to be sharply bent by the inner lens 17 or the like in order to guide light to the photodiode.
  • the charge transfer electrode 14a also serves as a light shielding film, the width of the charge transfer electrode 14a can be increased without sacrificing the area occupied by the photodiode 2 as compared with the case where a separate light shielding film is formed. As a result, it is possible to reduce the read voltage when reading signal charges from the photodiode 2 to the vertical transfer unit 4. Furthermore, since the charge transfer electrode 14a also serves as a light shielding film, it is possible to eliminate the parasitic capacitance between the charge transfer electrode and the light shielding film, which existed in the configuration in which the light shielding film is separately formed. As a result, further high speed driving becomes possible.
  • the photodiode 2 is covered with the silicon nitride film functioning as the antireflection film 10, there is no influence of the contamination by the metal material film, and the generation of white scratches due to the metal contamination can be avoided.
  • FIG. 19 are cross-sectional views showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention.
  • a part a cross section along the line XX in FIG. 19 (hereinafter referred to as “A part”) is shown on the left side, a cross section along the YY line in FIG.
  • the portion C a resistor made of a silicon film wiring is exemplified.
  • an N-type photodiode 2 for photoelectrically converting incident light and an individual pixel cell are electrically connected to a P-type semiconductor substrate (silicon substrate) 1.
  • a P-type isolation region 3 for isolating the signal and an N-type vertical transfer unit 4 for transferring the signal charge generated by the photodiode 2 in the vertical direction are formed.
  • a gate insulating film (first insulating film) 5 having a thickness of about 40 nm is formed on the surface of the semiconductor substrate 1, and a polysilicon film or an amorphous silicon film containing an impurity such as phosphorus is formed on the gate insulating film 5.
  • a silicon-based film 6 is formed.
  • a silicon oxide film 7 is formed on the silicon film 6.
  • the silicon-based film 6 is a material constituting a dummy pattern and a peripheral circuit wiring for forming the charge transfer electrode 14a, and the silicon oxide film 7 is a manufacturing process to be described later, in particular, an etch back process or the like. 1 has a function of preventing exposure (film reduction) of the silicon-based film 6 at a desired portion.
  • the silicon-based film 6 has a thickness of about 150 nm
  • the silicon oxide film 7 has a thickness of about 50 nm to 100 nm.
  • the silicon film 6 and the silicon oxide film 7 can be formed by using, for example, a CVD (Chemical Vapor Deposition) method.
  • a resist pattern (not shown) is formed on the silicon oxide film 7 using a known lithography technique, and the silicon oxide film 7 and the silicon-based film 6 are formed using the resist pattern as a mask. It is removed by anisotropic dry etching. Thereafter, the resist pattern is removed. As a result, a dummy pattern 6a having the same planar layout as the charge transfer electrode 14a is formed in the pixel cell array of the solid-state imaging device, and a resistor 6b is formed in the peripheral circuit formation region (C portion). Silicon oxide films 7a and 7b remain on the dummy pattern 6a and the resistor 6b, respectively.
  • a resist pattern is used to form the dummy pattern 6a and the resistor 6b.
  • a pattern is formed on the silicon oxide film 7 on the silicon-based film 6, and a side made of an insulating film such as a silicon oxide film or a silicon nitride film is formed around the pattern.
  • a pattern may be enlarged by adding a wall, and the silicon-based film 6 may be etched using the enlarged pattern as a hard mask. In this way, the gap 8 between the dummy patterns 6a can be formed very narrow in the portion B.
  • any structure may be used as long as the silicon oxide film remains on the dummy pattern 6a and the resistor 6b.
  • the resistor 6b is formed, and at the same time, the gate electrode of the MOS transistor is formed of the silicon-based film 6.
  • impurities are implanted into this region by ion implantation or the like. be introduced.
  • impurity regions such as low concentration and high concentration source / drain of the MOS transistor are formed by introducing impurities into the semiconductor substrate 1.
  • the gap 8 between the dummy patterns 6 a adjacent to each other along the charge transfer direction of the vertical transfer unit 4 is filled on the semiconductor substrate 1, and the dummy pattern 6 a and the resistor 6 b are covered.
  • An insulating film (second insulating film) 9 is formed.
  • the insulating film 9 is formed in such a film thickness that the gap 8 is embedded in the B section and a recess corresponding to the shape of the dummy pattern 6a is formed in the A section.
  • a silicon oxide film is deposited as the insulating film 9.
  • the silicon oxide film is preferably deposited by using a high-temperature LP-CVD (Low-Pressure-CVD) method exceeding 850 ° C. so as to produce a good step coverage that can fill the gap 8.
  • the entire surface of the insulating film 9 is anisotropically etched using an etch-back method, and a portion formed on the gate insulating film 5 and a portion B in the section A are shown.
  • the portion formed on the silicon oxide film 7 is removed.
  • the insulating film 9 is embedded in the gap 8 in the B portion (hereinafter referred to as an interelectrode insulating film 9b), and at the same time, a sidewall 9a made of a silicon oxide film is formed on the side surface of the dummy pattern 6a in the A portion.
  • the gate insulating film 5 covering the photodiode 2 is positively etched to form a thin film portion 5b having a desired film thickness.
  • the desired film thickness is a shallow value in ion implantation for forming a surface impurity layer for accumulating charges (here, holes) having a conductivity type opposite to that of signal charges on the surface of a photodiode 2 to be described later.
  • the thickness is such that doping can be performed and an appropriate antireflection function can be realized when the antireflection film 10 is laminated.
  • the film thickness of the thin film portion 5b is preferably 5 nm to 35 nm, and here it is 20 nm.
  • the thickness of the thin film portion 5b exceeds 35 nm, the effect of increasing the amount of photodiode saturation decreases. Also, depending on the etching apparatus and etching conditions used in the etching, combined use with wet etching, the impurity profile of the surface impurity stack, the subsequent heat treatment, etc., the etching is performed when the film thickness is less than 5 nm. This is because the dark current of the photodiode may be increased due to the damage. Furthermore, the formation of the thin film portion 5b can also have an effect of relaxing the film stress of the nitride film. From this viewpoint, the film thickness of the thin film portion 5b can also be set.
  • a portion excluding the thin film portion 5b formed by thinning the gate insulating film 5 in the process, that is, the portion of the gate insulating film 5 which is the lower layer of the dummy pattern 6a and the sidewall 9a is a thick film portion. 5a.
  • a P-type positive charge storage layer (surface impurity layer) 21 is formed by introducing P-type impurities into the surface portion of the photodiode 2 using ion implantation (see FIG. 6).
  • the charge transfer electrode 14 a made of a metal material film is disposed on the vertical transfer portion 4.
  • the thin film portion is formed on the gate insulating film 5 on the photodiode 2. 5b is formed. Therefore, it is not necessary to increase the implantation energy in order to realize ion implantation through the thick gate insulating film, and shallow doping is possible. Therefore, P-type impurities can be introduced into the extreme surface portion of the photodiode 2. Therefore, even if the gate insulating film needs to be relatively thick, it is possible to prevent the photodiode saturation from decreasing.
  • an activation heat treatment of the implanted impurities is performed using an electric furnace at a temperature exceeding 850 ° C. and not exceeding 900 ° C. for a time range of 10 minutes to 60 minutes.
  • the implanted impurities in the impurity layers such as the photodiode 2 and the vertical transfer portion 4 formed by ion implantation so far and the implanted impurities in the peripheral circuit portion are also activated simultaneously.
  • a short-time heat treatment at 1000 ° C. for about 10 seconds to 60 seconds may be used.
  • an antireflection film 10 is formed on the entire surface of the semiconductor substrate 1.
  • the antireflection film 10 a silicon nitride film is formed with a thickness of 50 nm.
  • the antireflection film 10 has a function of preventing reflection of incident light incident on the photodiode 2 on the surface of the semiconductor substrate 1.
  • the antireflection film 10 is formed of a silicon oxide film that is the gate insulating film 5. The function is created by laminating the film thickness of the thin film portion 5b and the film thickness of the silicon nitride film as the antireflection film 10 at a predetermined thickness.
  • the charge transfer electrode 14 a made of a metal material film is disposed on the vertical transfer portion 4.
  • the thin film portion is formed on the gate insulating film 5 on the photodiode 2. Since 5b is formed, the antireflection effect is not impaired due to the initial film thickness of the gate insulating film 5 (film thickness of the thick film portion 5a).
  • a planarizing film 11 made of a silicon oxide film such as BPSG (Boron Phosphor Silicate Glass) is deposited on the entire surface of the semiconductor substrate 1 to perform a reflow process, thereby forming a recess on the semiconductor substrate 1.
  • BPSG Bipolar Phosphor Silicate Glass
  • the unevenness on the semiconductor substrate 1 is a pattern made of a laminated film of the silicon-based film 6 and the silicon oxide film 7 including the dummy pattern 6a and the resistor 6b. (See FIG. 6 etc.).
  • sidewalls 9 a are formed in the pattern composed of the laminated film of the silicon-based film 6 and the silicon oxide film 7. That is, at the time when the planarizing film 11 is deposited, the convex portion on the semiconductor substrate 1 has a forward tapered shape in which the width increases from the upper surface to the lower surface of the convex portion. As a result, in the process, the planarizing film 11 can be filled in the recesses very well.
  • a resist film 12 is formed on the planarizing film 11 as shown in FIG.
  • the entire surface anisotropic etching is performed on the resist film 12 and the planarizing film 11 using the etch back method, and planarization on the semiconductor substrate 1 is achieved as shown in FIG. That is, the portion formed on the gate insulating film 5 in the section A and the portion formed on the silicon oxide film 7 in the section B are removed.
  • the antireflection film 10 deposited on the silicon oxide film 7 (7a, 7b) (on the dummy pattern 6a and the resistor 6b) is exposed to the outermost surface.
  • the same structure can be obtained even if the resist film 12 and the planarizing film 11 are polished by the CMP (Chemical Mechanical Polishing) method.
  • the material of the planarizing film 11 is not limited to BPSG, and a laminated film of a silicon oxide film and a silicon nitride film, or a silicon nitride film can also be adopted.
  • any film forming method such as atmospheric pressure CVD, low pressure CVD, plasma CVD, or the like can be adopted as long as the above-described recess filling can be realized.
  • a mask is formed in a region (for example, part C) where the silicon-based film 6 is used as a material for wiring and electrodes.
  • a resist pattern 13 made of a photoresist film is formed by a lithography technique.
  • the antireflection film 10 (here, silicon nitride film) exposed on the surface of the region not covered with the resist pattern 13 is removed by dry etching or the like on the entire surface. Thereby, as shown in FIG. 11, the silicon oxide film 7a on the dummy pattern 6a is exposed on the outermost surface. At this time, in the portion B, the space between the dummy patterns 6a is filled with the interelectrode insulating film 9b made of a silicon oxide film, so that it is avoided that this is etched.
  • the etching back process of the insulating film 9 described with reference to FIG. 5 and the etching back of the antireflection film 10 in this process are stopped when the silicon oxide film 7 is exposed.
  • the silicon oxide film 7 is initially set to a thickness that does not expose the dummy pattern 6a (and the resistor 6b) by these etchings.
  • the exposed silicon oxide film 7a is removed by etching as described above. As a result, as shown in FIG. 12, the upper surface of the dummy pattern 6a is exposed on the outermost surface.
  • the exposed dummy pattern 6a is removed by etching.
  • a technique with little etching damage for etching the dummy pattern 6 a made of a silicon-based film it is preferable to employ a technique with little etching damage for etching the dummy pattern 6 a made of a silicon-based film.
  • the dummy pattern 6a can be removed without damage by using a chemical dry etching method or a wet etching method.
  • the resist pattern 13 is removed as shown in FIG.
  • the gate oxide film 5 (a part of the thick film portion 5a) exposed to the portion where the dummy pattern 6a has been removed is slightly etched.
  • the etching amount is about 1 to 2 nm, and the thickness of the portion of the thick film portion 5a (just below the charge transfer electrode 14a) is thicker than the thickness of the thin film portion 5b.
  • the initial film thickness of the gate oxide film 5 is preferably set in consideration of the thickness reduction.
  • a metal material film 14 such as tungsten or aluminum is deposited on the entire surface.
  • the metal material film 14 is not limited to a single film, and for example, a multilayer film such as a laminated film of a refractory metal compound such as titanium nitride (lower layer) and aluminum (upper layer) may be used.
  • the metal material films exemplified above are particularly preferable materials from the viewpoint of light shielding properties, but other metal materials may be used.
  • Such metal material type and laminated structure can be determined based on the specific resistance of the metal material film, the heat resistant temperature, the wiring width of the charge transfer electrode, and the like.
  • a resist film 15 is formed on the metal material film 14, and the resist film 15 and the metal material film 14 are entirely anisotropic etched (or CMP) using an etch back method. The entire surface is polished using a method, and planarization on the semiconductor substrate 1 is achieved. As a result, the charge transfer electrode 14a made of the metal material film 14 is formed at the place where the dummy pattern 6a was present.
  • the film thickness of the charge transfer electrode 14a formed by the above process is about 150 nm.
  • the interlayer insulating film 16 made of a silicon oxide film or the like is deposited on the entire surface as shown in FIG. Is done.
  • the charge transfer electrode 14a functions as a light shielding film that prevents light from entering the vertical transfer portion 4, it is not necessary to form a light shielding film in the upper layer.
  • a light shielding film made of tungsten, aluminum, or the like may be formed on the interlayer insulating film 16 in a region that further enhances light shielding, such as an optical black pixel (optical black) region provided in the outer edge region of the imaging region. it can. As a result, a good optical black pixel can be realized, the capacitance between the charge transfer electrode and the light shielding film can be reduced, and high-speed driving is possible.
  • an inner lens 17, a color filter 19 and a microlens 20 made of a P-SiN film are formed corresponding to each photodiode 2. .
  • the thickness of the insulating film 5 is reduced using the dummy pattern 6a and the sidewall 9a as a mask to form a thin film portion 5b. That is, the gate insulating film 5 having the thick film portion 5a and the thin film portion 5b can be formed without adding a special process. Further, by adopting the gate insulating film 5 having the thick film portion 5a and the thin film portion 5b, the optical sensitivity is reduced even when the charge transfer electrode 14a is miniaturized as described above. Can be suppressed.
  • a high-quality interelectrode insulating film 9b can be formed, and a withstand voltage between charge transfer electrodes can be ensured. That is, in FIG. 19 showing the pattern layout of the pixel cell, when a solid-state imaging device having a scale in which the periodic arrangement pitch p of the charge transfer electrodes 14a is about 1.2 ⁇ m is considered, it passes over a region between adjacent photodiodes. Although the minimum width w of the charge transfer electrode 14a is reduced to 0.1 ⁇ m to 0.3 ⁇ m, according to the present invention, the charge transfer electrode 14a can be satisfactorily formed in such a portion.
  • the photodiode 2 is covered with a silicon nitride film that functions as the antireflection film 10 when the metal material film 14 is formed. That is, there is no influence of contamination by the metal material film 14, and generation of white scratches due to metal contamination can be avoided. This eliminates the need for special measures against white flaws and the heat treatment conditions and heat treatment process for that purpose. Further, in the above manufacturing method, it is not necessary to perform a high-temperature process exceeding 800 ° C. after the formation of the metal material film 14, so that the process is easy.
  • the gate insulating film directly below the charge transfer electrode 14a does not have a step and has the same film thickness. Therefore, the potential between the electrodes due to the formation of pockets and barriers is increased. Since there is no change, good transfer is possible.
  • a driving solid-state imaging device can be realized stably.
  • the present invention has a low-resistance charge transfer electrode made of a metal material film, can stably form a fine solid-state image sensor that can be driven with high sensitivity and high speed, and a solid-state image sensor and a method for manufacturing the same. Useful as.

Abstract

Disclosed is a solid-state image pickup element wherein a semiconductor substrate is provided with a photodiode, which generates signal charges corresponding to inputted light by photoelectric conversion, and a charge transfer section, which transfers the signal charges generated by the photodiode. On the surface of the semiconductor substrate, a gate insulating film is provided. The gate insulating film has a thin film portion, which covers the photodiode, and a thick film portion, which is thicker than the thin film portion, and which covers the charge transfer section. On the thick film portion of the gate insulating film, said thick film portion covering the charge transfer section, a charge transfer electrode, which transfers the signal charges in the charge transfer section, and which is composed of a metal material film, is provided.

Description

固体撮像素子とその製造方法Solid-state imaging device and manufacturing method thereof
　本発明は固体撮像素子およびその製造方法に関し、特に、単層構造の電荷転送電極を有する固体撮像装置およびその製造方法に関する。 The present invention relates to a solid-state imaging device and a manufacturing method thereof, and more particularly, to a solid-state imaging device having a charge transfer electrode having a single layer structure and a manufacturing method thereof.
　固体撮像素子のうちＣＣＤ（Charged Coupled Device）タイプの固体撮像素子（以下、ＣＣＤという。）は、入射光によって生成された画像信号電荷を転送する電荷転送電極を隣接して多数配列した構成を有している。こうした構成においては、信号電荷を効率よく転送するために互いに隣接する電荷転送電極の間隔を十分小さくすることが必要であり、以前はそのために電荷転送電極同士を薄い絶縁膜を介して互いに部分的に重なり合うよう２層構造に形成して配列するのが主流であった。 Among solid-state image sensors, a CCD (Charged-Coupled Device) type solid-state image sensor (hereinafter referred to as CCD) has a configuration in which a large number of charge transfer electrodes for transferring image signal charges generated by incident light are arranged adjacent to each other. is doing. In such a configuration, in order to efficiently transfer signal charges, it is necessary to sufficiently reduce the distance between adjacent charge transfer electrodes. For this reason, the charge transfer electrodes have previously been partially connected to each other via a thin insulating film. The mainstream was to form and arrange in a two-layer structure so as to overlap.
　しかし近年、微細加工技術の進歩に伴い０．２μｍ以下の幅を有する溝パターン形成が可能となり、ＣＣＤにおいても複数の電荷転送電極パターンを狭い間隔で、かつ相互に重なる部分を有さない１層の電極層で形成する単層電極構造が主流となってきている。単層電極構造のＣＣＤでは、電荷転送電極間に重なり部分がないことから、電極間容量が小さいという利点を有する。また、電荷転送電極の上層に形成される遮光膜は通常接地電位など所定の電圧が印加されるが、表面凹凸がほとんどない単層電極構造では、電荷転送電極と遮光膜間の耐圧が確保し易いという利点も有する。 However, in recent years, with the progress of microfabrication technology, it is possible to form a groove pattern having a width of 0.2 μm or less, and even in a CCD, a single layer having a plurality of charge transfer electrode patterns at narrow intervals and without overlapping portions. Single-layer electrode structures formed of these electrode layers have become mainstream. A CCD having a single-layer electrode structure has an advantage that the interelectrode capacitance is small because there is no overlapping portion between the charge transfer electrodes. In addition, a predetermined voltage such as ground potential is normally applied to the light-shielding film formed on the charge transfer electrode, but a single-layer electrode structure with almost no surface unevenness ensures a breakdown voltage between the charge transfer electrode and the light-shielding film. It also has the advantage of being easy.
　図１８は固体撮像素子（ＣＣＤ）の代表的な概略平面構成図である。固体撮像素子４０は、入射光を光電変換するフォトダイオード４２、フォトダイオード４２で生成された信号電荷を垂直方向に転送する垂直転送部４３が配置された撮像領域４１を備える。また、撮像領域４１に隣接して、垂直転送部４３によって転送されてきた信号電荷を水平方向に転送する水平転送部４４を備える。複数個のフォトダイオード４２はマトリックス状に配列され、フォトダイオード４２の各列間に垂直転送部４３が配置される。図１８には電荷転送電極を記載していないが、図面において、１本の電荷転送電極は撮像領域４１の右端領域から左端領域まで横方向に延びている。また、水平転送部４４で転送されてきた信号電荷は出力アンプ４５を介して電気信号として出力される。 FIG. 18 is a typical schematic plan view of a solid-state imaging device (CCD). The solid-state imaging device 40 includes an imaging region 41 in which a photodiode 42 that photoelectrically converts incident light and a vertical transfer unit 43 that transfers a signal charge generated by the photodiode 42 in the vertical direction are arranged. In addition, a horizontal transfer unit 44 is provided adjacent to the imaging region 41 to transfer the signal charges transferred by the vertical transfer unit 43 in the horizontal direction. The plurality of photodiodes 42 are arranged in a matrix, and a vertical transfer unit 43 is disposed between each column of the photodiodes 42. Although no charge transfer electrode is shown in FIG. 18, in the drawing, one charge transfer electrode extends in the horizontal direction from the right end region to the left end region of the imaging region 41. The signal charge transferred by the horizontal transfer unit 44 is output as an electric signal via the output amplifier 45.
　上記撮像領域４１がチップ上で比較的大きな面積を占めるＣＣＤでは、撮像領域４１の水平方向の長さが長いために電荷転送電極の長さも長くなる。このようなＣＣＤでは、電荷転送電極のそれぞれに、電荷転送電極の一方端の撮像領域４１の外部に設けられたバスラインから位相を変えて印加する駆動パルス信号に伝播遅延が生じ、電荷転送不良となることが問題となる。この伝播遅延は、電荷転送電極がシート抵抗値数十Ω／□のシリコン系膜などからなるため、バスラインから近い垂直転送部４３に駆動パルス信号が伝わるのに要する時間と、バスラインから遠い垂直転送部４３に駆動パルス信号が伝わるのに要する時間との間に差が生じることを意味する。 In the CCD in which the imaging region 41 occupies a relatively large area on the chip, the length of the charge transfer electrode is increased because the horizontal length of the imaging region 41 is long. In such a CCD, a propagation delay occurs in the drive pulse signal applied by changing the phase from the bus line provided outside the imaging region 41 at one end of the charge transfer electrode to each of the charge transfer electrodes. Becomes a problem. This propagation delay is due to the time required for the drive pulse signal to be transmitted to the vertical transfer unit 43 close to the bus line and the distance from the bus line because the charge transfer electrode is made of a silicon film having a sheet resistance value of several tens of Ω / □. This means that there is a difference between the time required for the drive pulse signal to be transmitted to the vertical transfer unit 43.
　また、近年は撮影機器による高速連写やＨＤ（高精細）動画に対応するため、ＣＣＤに一層の高速性が要求されるようになってきている。これに加えて固体撮像素子の高感度化という観点から入射光の検出に寄与しない無効領域を低減し、フォトダイオード領域を広く取るため、電荷転送電極の微細化も進められている。そのため、電荷転送電極の抵抗値はますます上昇する方向にある。また、電荷転送電極の微細化が進むと、フォトダイオードから電荷転送電極の電荷を電荷転送部へ読み出すための電圧が上昇するという問題も生じる。このような状況の進行に伴い上記伝播遅延や配線抵抗に起因する電圧降下の問題が顕著になるため、電荷転送電極の低抵抗化が重要視されている。 In recent years, in order to support high-speed continuous shooting by an imaging device and HD (high-definition) moving images, CCDs are required to have higher speed. In addition to this, from the viewpoint of increasing the sensitivity of the solid-state imaging device, miniaturization of the charge transfer electrode has been promoted in order to reduce the ineffective region that does not contribute to the detection of incident light and increase the photodiode region. Therefore, the resistance value of the charge transfer electrode is in an increasing direction. As the charge transfer electrode is further miniaturized, a problem arises in that the voltage for reading the charge transfer electrode from the photodiode to the charge transfer unit increases. As such a situation progresses, the problem of the voltage drop due to the propagation delay and the wiring resistance becomes conspicuous. Therefore, it is important to reduce the resistance of the charge transfer electrode.
　電荷転送電極を低抵抗化するためには、シート抵抗値が数Ω／□と従来のポリシリコンのようなシリコン系材料より１桁から２桁低い金属膜やそのシリサイド膜を用いることが考えられている。そのうち金属を主体とする低抵抗材料を用い、さらにその材料に起因する製造上の問題を解決した技術が提案されている（例えば、特許文献１等参照。）。 In order to reduce the resistance of the charge transfer electrode, it is conceivable to use a metal film having a sheet resistance value of several Ω / □, which is one to two orders of magnitude lower than a conventional silicon-based material such as polysilicon, or a silicide film thereof. ing. Among them, a technique has been proposed in which a low-resistance material mainly composed of metal is used and a manufacturing problem caused by the material is solved (see, for example, Patent Document 1).
　図２０は、特許文献１に開示されている固体撮像装置の電荷転送電極部を示す要部概略断面図である。図２０において、電荷転送電極はシリコン系膜１０１、窒化タングステン１０２およびタングステン１０３より構成されている。電荷転送電極の上面にはシリコンガラス膜１０４、シリコン窒化膜１０５、サイドウォール１０６が形成されており、これらの膜は電荷転送電極パターンをエッチング形成するときのハードマスクとなったものである。また、電極間の狭いスペースは酸化膜１０７とシリコン窒化膜１０８で埋められている。さらに、電荷転送電極の両端の下部にはシリコン系膜からなる台形パターン１００が設けられている。この固体撮像装置では、電荷転送電極にタングステンのような高融点金属を採用することによってその抵抗の低減を図っている。また、台形パターン１００を設けることによって電荷転送電極の端部のシリコン系膜１０１を持ち上げタングステン１０３がシリコン系膜１０１に囲まれるようにしている。これにより、狭い電極間隔にカバレッジよく形成できる酸化膜１０７の成長時に、タングステン１０３が高温酸化性雰囲気に直接さらされることをなくし、タングステン１０３の異常膨張およびそれによる電極間隙の破綻を防止している。 FIG. 20 is a schematic cross-sectional view of the main part showing the charge transfer electrode portion of the solid-state imaging device disclosed in Patent Document 1. In FIG. 20, the charge transfer electrode is composed of a silicon-based film 101, tungsten nitride 102 and tungsten 103. A silicon glass film 104, a silicon nitride film 105, and a sidewall 106 are formed on the upper surface of the charge transfer electrode, and these films serve as a hard mask when the charge transfer electrode pattern is formed by etching. A narrow space between the electrodes is filled with an oxide film 107 and a silicon nitride film 108. Furthermore, a trapezoidal pattern 100 made of a silicon-based film is provided below the both ends of the charge transfer electrode. In this solid-state imaging device, the resistance is reduced by using a refractory metal such as tungsten for the charge transfer electrode. Further, the trapezoidal pattern 100 is provided to lift the silicon-based film 101 at the end of the charge transfer electrode so that the tungsten 103 is surrounded by the silicon-based film 101. This prevents the tungsten 103 from being directly exposed to the high-temperature oxidizing atmosphere during the growth of the oxide film 107 that can be formed with a narrow electrode interval and good coverage, thereby preventing the abnormal expansion of the tungsten 103 and the resulting breakdown of the electrode gap. .
　一方、電荷転送電極の微細化が進行すると、Ｓ／Ｎ比（シグナル／ノイズ比）を改善することが困難になる。電荷転送電極の微細化により、フォトダイオードの占有面積が増大して光学感度が向上するが、この場合、フォトダイオードに対応して設けられる、遮光膜開口部の開口面積も大きくする必要がある。しかしながら、遮光膜の開口面積を最大化すると、電荷転送部への光の進入を確実に防止することが困難になりノイズが増大する。すなわち、Ｓ／Ｎ比を改善するためには、開口面積の最大化と、遮光領域の最大化を両立する必要があるが、電荷転送電極（電荷転送部）の微細化が進行して、位置合わせマージンの占める割合が大きくなると、このような両立は困難になる。そのため、電荷転送電極そのものを、低抵抗、かつ遮光性を有する金属材料膜により構成し、電荷転送部の遮光膜として機能させることも提案されている（例えば、特許文献２参照）。 On the other hand, when the charge transfer electrode is miniaturized, it becomes difficult to improve the S / N ratio (signal / noise ratio). By miniaturizing the charge transfer electrode, the area occupied by the photodiode is increased and the optical sensitivity is improved. In this case, it is also necessary to increase the opening area of the light shielding film opening provided corresponding to the photodiode. However, when the opening area of the light shielding film is maximized, it becomes difficult to surely prevent light from entering the charge transfer portion, and noise increases. That is, in order to improve the S / N ratio, it is necessary to achieve both the maximization of the opening area and the maximization of the light shielding region. However, as the miniaturization of the charge transfer electrode (charge transfer portion) proceeds, the position Such a balance becomes difficult as the proportion of the combined margin increases. Therefore, it has also been proposed that the charge transfer electrode itself is made of a metal material film having a low resistance and a light shielding property so as to function as a light shielding film of the charge transfer portion (see, for example, Patent Document 2).
特開２００３－６０１８９号公報JP 2003-60189 A 特開２００７－１２６７７号公報JP 2007-12677 A
　図１８に示す一般的な固体撮像素子の構成においては、電荷転送電極は、垂直転送部４３上だけでなく、フォトダイオード４２の直上を避け、互いに縦方向に隣接するフォトダイオード４２間の狭い領域上をも通す必要がある。しかしながら固体撮像素子のパターンを微細化した場合フォトダイオード４２の間隔も狭くなり、電荷転送電極のこの部分を通る幅は最近の画素セルサイズでは０．２μｍ程度にまで縮小する必要が生じてきた。 In the configuration of the general solid-state imaging device shown in FIG. 18, the charge transfer electrode is not only on the vertical transfer unit 43 but also directly above the photodiode 42, and a narrow region between the photodiodes 42 adjacent to each other in the vertical direction. It is necessary to pass through the top. However, when the pattern of the solid-state imaging device is miniaturized, the interval between the photodiodes 42 is narrowed, and the width passing through this portion of the charge transfer electrode needs to be reduced to about 0.2 μm in the recent pixel cell size.
　しかしながら、特許文献１に記載された従来の電荷転送電極の構造は、垂直転送部４３上のような電極のサイズが大きいままでよい部分では実現できるが、上に述べた極めて細い部分では高抵抗のシリコン系膜１０１のみからなる構造とならざるを得ず、電極の中央にタングステン１０３が形成できなくなる。したがって電荷転送電極がタングステン１０３によって部分的に低抵抗化されたとしても、電極全体としては低抵抗化の効果が非常に小さくなるという課題があった。 However, the structure of the conventional charge transfer electrode described in Patent Document 1 can be realized in the portion where the size of the electrode on the vertical transfer portion 43 may remain large, but in the extremely thin portion described above, it has a high resistance. Therefore, the tungsten 103 cannot be formed in the center of the electrode. Therefore, even if the charge transfer electrode is partially reduced in resistance by the tungsten 103, there is a problem that the effect of reducing the resistance as a whole becomes very small.
　一方、固体撮像装置では、電荷転送電極と、電荷転送部が形成される半導体基板との間に配置される絶縁膜は、フォトダイオード上にも形成されている。そして、暗電流抑制のためにフォトダイオードの表面部に表面不純物層を形成する際には、当該絶縁膜を通じてイオン注入が実施される。金属材料膜からなる電荷転送電極が採用されるような微細な電荷転送電極（微細な画素セル）を備える固体撮像素子では、光学感度向上のため、各フォトダイオードの飽和量をできるだけ大きくすることも求められる。このフォトダイオード飽和量を大きくするには、各フォトダイオードにおいて深さ方向の信号電荷生成領域幅をできるだけ大きくする必要があり、この観点では、上記表面不純物層をフォトダイオードの極表面に形成することが求められる。しかしながら、上述のように、表面不純物層を形成するためのイオン注入はフォトダイオードを被覆する上記絶縁膜を通じて実施されるため、当該絶縁膜を通過できる注入エネルギーを使用する必要がある。一般に、注入エネルギーが高くなるにつれて、不純物の深さ方向の分布幅は広くなる。すなわち、注入エネルギーが高くなるにつれてフォトダイオードの深い位置にまで表面不純物層構成する逆導電型の不純物が導入され、各フォトダイオード飽和量が低下することになる。 On the other hand, in the solid-state imaging device, the insulating film disposed between the charge transfer electrode and the semiconductor substrate on which the charge transfer portion is formed is also formed on the photodiode. When a surface impurity layer is formed on the surface portion of the photodiode to suppress dark current, ion implantation is performed through the insulating film. In a solid-state imaging device having a fine charge transfer electrode (fine pixel cell) in which a charge transfer electrode made of a metal material film is employed, the saturation amount of each photodiode may be increased as much as possible to improve optical sensitivity. Desired. In order to increase the photodiode saturation amount, it is necessary to make the signal charge generation region width in the depth direction as large as possible in each photodiode. From this viewpoint, the surface impurity layer is formed on the extreme surface of the photodiode. Is required. However, as described above, since ion implantation for forming the surface impurity layer is performed through the insulating film covering the photodiode, it is necessary to use implantation energy that can pass through the insulating film. In general, as the implantation energy increases, the distribution width of impurities in the depth direction increases. That is, as the implantation energy increases, the reverse conductivity type impurity constituting the surface impurity layer is introduced to a deeper position of the photodiode, and the saturation amount of each photodiode is reduced.
　また、フォトダイオードを被覆する上記絶縁膜上には、フォトダイオードの光学感度を向上させる目的で反射防止膜が設けられる。このような反射防止膜の反射防止効果は、反射防止膜の屈折率と膜厚、および下層膜である上記絶縁膜の屈折率と膜厚、並びに反射防止効果を得るターゲットの波長に基づいて定まる。そのため、下層膜の膜厚が固定であると、反射防止膜の設計自由度は低くなり、最適な反射防止効果が得られない状況も発生し得る。 Further, an antireflection film is provided on the insulating film covering the photodiode for the purpose of improving the optical sensitivity of the photodiode. The antireflection effect of such an antireflection film is determined based on the refractive index and film thickness of the antireflection film, the refractive index and film thickness of the insulating film as the lower layer film, and the wavelength of the target that obtains the antireflection effect. . Therefore, when the film thickness of the lower layer film is fixed, the degree of freedom in designing the antireflection film becomes low, and a situation where the optimum antireflection effect cannot be obtained may occur.
　特許文献２が開示する技術であっても、この種の光学感度の低下を避けることはできない。 Even with the technique disclosed in Patent Document 2, this kind of decrease in optical sensitivity cannot be avoided.
　本発明は、上記従来の事情を鑑みて提案されたものであって、金属材料膜からなる低抵抗の電荷転送電極を有し、微細化に際しても、高感度かつ高速駆動可能な固体撮像素子およびその製造方法を提供することを目的とする。 The present invention has been proposed in view of the above-described conventional circumstances, and has a low-resistance charge transfer electrode made of a metal material film, and can be driven with high sensitivity and high speed even when miniaturized. It aims at providing the manufacturing method.
　前記の目的を達成するため、本発明は、以下の技術的手段を採用する。本発明に係る固体撮像素子は、半導体基板に、光電変換により入射光に応じた信号電荷を生成するフォトダイオード、および当該フォトダイオードにおいて生成された信号電荷を転送する電荷転送部を備える。当該半導体基板表面には絶縁膜が設けられる。当該絶縁膜は、フォトダイオード上を被覆する薄膜部と、当該薄膜部よりも膜厚が厚い、電荷転送部上を被覆する厚膜部とを有する。電荷転送部上を被覆する、絶縁膜の厚膜部上には、電荷転送部内の信号電荷を転送する、金属材料膜からなる電荷転送電極が設けられる。 In order to achieve the above object, the present invention employs the following technical means. The solid-state imaging device according to the present invention includes, on a semiconductor substrate, a photodiode that generates a signal charge corresponding to incident light by photoelectric conversion, and a charge transfer unit that transfers the signal charge generated in the photodiode. An insulating film is provided on the surface of the semiconductor substrate. The insulating film includes a thin film portion that covers the photodiode and a thick film portion that covers the charge transfer portion and is thicker than the thin film portion. On the thick film portion of the insulating film that covers the charge transfer portion, a charge transfer electrode made of a metal material film that transfers signal charges in the charge transfer portion is provided.
　この固体撮像素子では、厚膜部上に金属材料膜からなる電荷転送電極が配置されるため、所望の閾値制御を行うことができる。また、フォトダイオード上に薄膜部が配置されるため、フォトダイオード表面部の表面不純物層をシャロードーピングにより形成可能である。したがって、電荷転送電極の微細化が進行した場合であっても、光学感度の低下を抑制することができる。 In this solid-state imaging device, since the charge transfer electrode made of a metal material film is disposed on the thick film portion, desired threshold control can be performed. In addition, since the thin film portion is disposed on the photodiode, the surface impurity layer on the photodiode surface portion can be formed by shallow doping. Therefore, even when the charge transfer electrode is miniaturized, it is possible to suppress a decrease in optical sensitivity.
　上記固体撮像素子において、フォトダイオード上を被覆する上記絶縁膜上に、反射防止膜をさらに備えることができる。これにより、薄膜部と反射防止膜との組み合わせにより、良好な反射防止効果を得ることができ、電荷転送電極の微細化が進行した場合であっても、光学感度の低下を抑制することができる。また、白キズの発生を防止することもできる。 In the solid-state imaging device, an antireflection film can be further provided on the insulating film covering the photodiode. Thereby, a combination of the thin film portion and the antireflection film can provide a good antireflection effect, and even when the charge transfer electrode is miniaturized, it is possible to suppress a decrease in optical sensitivity. . Moreover, generation | occurrence | production of a white flaw can also be prevented.
　また、上記電荷転送電極は、絶縁膜の薄膜部の端部に一致する端部を有するサイドウォールを備えてもよい。この場合、反射防止膜は当該サイドウォールを被覆することが好ましい。反射防止膜は、例えば、シリコン窒化膜を含むことができる。 The charge transfer electrode may include a sidewall having an end that coincides with the end of the thin film portion of the insulating film. In this case, the antireflection film preferably covers the sidewall. The antireflection film can include, for example, a silicon nitride film.
　さらに、遮光性の観点では、金属材料膜がタングステンまたはアルミニウムを含む、あるいは、窒化チタンとアルミニウムとの積層構造を含むことができる。 Furthermore, from the viewpoint of light shielding properties, the metal material film may include tungsten or aluminum, or may include a laminated structure of titanium nitride and aluminum.
　一方、他の観点では、本発明は、固体撮像素子の製造方法を提供することができる。すなわち、本発明に係る固体撮像素子の製造方法では、まず、半導体基板に、光電変換により入射光に応じた信号電荷を生成するフォトダイオード、および当該フォトダイオードにおいて生成された信号電荷を転送する電荷転送部が形成される。次いで、フォトダイオードおよび電荷転送部が形成された半導体基板上に、第１の絶縁膜が形成される。続いて、電荷転送部上に、第１の絶縁膜を介してダミーパターンが形成される。当該ダミーパターンは、電荷転送部内の信号電荷を転送する電荷転送電極と同一の平面レイアウトを有する。ダミーパターンが形成された半導体基板上には、第２の絶縁膜が形成される。当該代２の絶縁膜は、電荷転送部の電荷転送方向に沿って隣接するダミーパターン間の間隙を充填するとともに、ダミーパターンを被覆する。続いて、エッチングにより、ダミーパターン上およびフォトダイオード上の第２の絶縁膜が除去されるとともに、ダミーパターンに第２の絶縁膜からなるサイドウォールが形成される。同時に、フォトダイオード上の第１の絶縁膜の膜厚が減少される。そして、半導体基板上に残存する第２の絶縁膜で囲まれたダミーパターンが除去され、金属材料膜からなる電荷転送電極に置換される。 On the other hand, from another viewpoint, the present invention can provide a method for manufacturing a solid-state imaging device. That is, in the method for manufacturing a solid-state imaging device according to the present invention, first, a photodiode that generates a signal charge corresponding to incident light by photoelectric conversion on a semiconductor substrate, and a charge that transfers the signal charge generated in the photodiode. A transfer unit is formed. Next, a first insulating film is formed on the semiconductor substrate on which the photodiode and the charge transfer portion are formed. Subsequently, a dummy pattern is formed on the charge transfer portion via the first insulating film. The dummy pattern has the same planar layout as the charge transfer electrode that transfers the signal charge in the charge transfer portion. A second insulating film is formed on the semiconductor substrate on which the dummy pattern is formed. The insulating film of the margin 2 fills the gap between the dummy patterns that are adjacent to each other along the charge transfer direction of the charge transfer portion. Subsequently, the second insulating film on the dummy pattern and the photodiode is removed by etching, and a sidewall made of the second insulating film is formed on the dummy pattern. At the same time, the thickness of the first insulating film on the photodiode is reduced. Then, the dummy pattern surrounded by the second insulating film remaining on the semiconductor substrate is removed and replaced with a charge transfer electrode made of a metal material film.
　この固体撮像素子の製造方法では、電荷転送部を被覆し、かつ上面に電荷転送電極が形成される厚膜部と、フォトダイオードを被覆する薄膜部とを備える絶縁膜を特別な工程を追加することなく、形成することができる。また、当該厚膜部と薄膜部とを有する絶縁膜を採用することにより、上述のように、電荷転送電極の微細化が進行した場合であっても、光学感度の低下を抑制することができる。 In this solid-state imaging device manufacturing method, a special process is added to an insulating film that includes a thick film portion that covers the charge transfer portion and has a charge transfer electrode formed on the upper surface, and a thin film portion that covers the photodiode. It can form without. Further, by adopting the insulating film having the thick film portion and the thin film portion, it is possible to suppress a decrease in optical sensitivity even when the charge transfer electrode is miniaturized as described above. .
　上記固体撮像素子の製造方法において、ダミーパターンを除去する前に、膜厚を減少させた第１の絶縁膜を通じて不純物を導入し、フォトダイオードの表面部に、信号電荷と逆導電型の電荷を蓄積する表面不純物層を形成することが好ましい。また、膜厚を減少させた第１の絶縁膜を通じて不純物を導入した後、ダミーパターンを除去する前に、フォトダイオード上を被覆する第１の絶縁膜上に、反射防止膜を形成することが好ましい。 In the method of manufacturing the solid-state imaging device, before removing the dummy pattern, impurities are introduced through the first insulating film having a reduced thickness, and signal charges and charges of opposite conductivity type are applied to the surface portion of the photodiode. It is preferable to form a surface impurity layer to be accumulated. An antireflection film may be formed on the first insulating film covering the photodiode after the impurity is introduced through the first insulating film having a reduced thickness and before the dummy pattern is removed. preferable.
　なお、ダミーパターンはシリコン系膜により構成することができる。この場合、固体撮像素子内のダミーパターンを部分的に置換することで、シリコン系膜からなる配線や電極を形成することができる。 The dummy pattern can be composed of a silicon film. In this case, by partially replacing the dummy pattern in the solid-state imaging device, it is possible to form a wiring or electrode made of a silicon-based film.
　本発明によれば、今後の更なる微細化に際しても、金属材料膜からなる低抵抗な電荷転送電極を有し、高感度かつ高速駆動可能な固体撮像素子を安定して形成できる。 According to the present invention, it is possible to stably form a solid-state imaging device having a low-resistance charge transfer electrode made of a metal material film and capable of high sensitivity and high-speed driving even in the future further miniaturization.
図１は、本発明の一実施形態における固体撮像素子を示す概略構成を示す断面図である。FIG. 1 is a cross-sectional view illustrating a schematic configuration of a solid-state imaging device according to an embodiment of the present invention. 図２は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 2 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図３は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 3 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図４は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 4 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図５は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 5 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図６は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 6 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図７は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 7 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図８は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 8 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図９は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 9 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図１０は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 10 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図１１は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 11 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図１２は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 12 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図１３は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 13 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図１４は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 14 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図１５は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 15 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図１６は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 16 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図１７は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。FIG. 17 is a cross-sectional view showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. 図１８は、固体撮像素子の概略平面構成図である。FIG. 18 is a schematic plan configuration diagram of a solid-state imaging device. 図１９は、固体撮像素子の画素セルアレイの一部を示す平面レイアウト図である。FIG. 19 is a plan layout diagram showing a part of the pixel cell array of the solid-state imaging device. 図２０は、固体撮像素子の従来の電荷転送電極構造例を示す概略断面図である。FIG. 20 is a schematic cross-sectional view showing an example of a conventional charge transfer electrode structure of a solid-state imaging device.
　以下、本発明の一実施形態について、図面を参照しながら説明する。以下の実施形態では、既に説明した図１８に示す構成を有する固体撮像素子の事例について説明する。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following embodiment, an example of a solid-state imaging device having the configuration shown in FIG. 18 already described will be described.
　まず、以下で説明する、固体撮像素子の画素セルレイアウトについて説明する。図１９は、この固体撮像素子の撮像領域４１に形成された画素セルアレイの一部を示す平面パターンレイアウト図である。図１９において、４本の電荷転送電極１４ａが横方向に延び、電荷転送電極１４ａで囲まれた中央部の方形領域には、図示していないがフォトダイオードが形成されている。また、電荷転送電極１４ａの幅が広い領域の下には垂直転送部４３が縦方向に延びるように設けられている。なお、図１９では、上記のフォトダイオードと共に画素セルアレイの領域上に形成される、各種の層間絶縁膜や平坦化膜、層間レンズ、カラーフィルタ、オンチップレンズ等の記載を省略している。 First, the pixel cell layout of the solid-state image sensor described below will be described. FIG. 19 is a plan pattern layout diagram showing a part of the pixel cell array formed in the imaging region 41 of the solid-state imaging device. In FIG. 19, four charge transfer electrodes 14a extend in the lateral direction, and a photodiode (not shown) is formed in a central rectangular region surrounded by the charge transfer electrodes 14a. In addition, a vertical transfer portion 43 is provided to extend in the vertical direction under the wide region of the charge transfer electrode 14a. In FIG. 19, description of various interlayer insulating films, planarization films, interlayer lenses, color filters, on-chip lenses, and the like formed on the pixel cell array region together with the photodiodes is omitted.
　図１は、本発明の一実施形態における固体撮像素子の概略構成を示す断面図である。図１は、図１９に示すＸ－Ｘ線に沿う断面であり、１画素部分の断面構造を示している。 FIG. 1 is a cross-sectional view showing a schematic configuration of a solid-state imaging device according to an embodiment of the present invention. FIG. 1 is a cross section taken along line XX shown in FIG. 19, and shows a cross-sectional structure of one pixel portion.
　図１に示すように、固体撮像素子は、シリコン単結晶基板からなる半導体基板１に形成される。半導体基板１の表面部には、入射光に応じた信号電荷を生成するフォトダイオード２および垂直転送部（電荷転送部）４が設けられる。フォトダイオード２および垂直転送部４上には、シリコン酸化膜等からなるゲート絶縁膜５が設けられる。当該ゲート絶縁膜５は、少なくとも画素セルアレイ領域において、膜厚が厚い厚膜部５ａと、厚膜部５ａよりも膜厚が薄い薄膜部５ｂとを備える。ゲート絶縁膜５の薄膜部５ｂは、フォトダイオード２上に配置される。また、ゲート絶縁膜５の厚膜部５ａは、垂直転送部４上に配置され、当該厚膜部５ａ上に、金属材料膜からなる電荷転送電極１４ａが配置される。 As shown in FIG. 1, the solid-state imaging device is formed on a semiconductor substrate 1 made of a silicon single crystal substrate. A photodiode 2 and a vertical transfer portion (charge transfer portion) 4 that generate signal charges corresponding to incident light are provided on the surface portion of the semiconductor substrate 1. A gate insulating film 5 made of a silicon oxide film or the like is provided on the photodiode 2 and the vertical transfer portion 4. The gate insulating film 5 includes a thick film portion 5a having a larger film thickness and a thin film portion 5b having a smaller film thickness than the thick film portion 5a at least in the pixel cell array region. The thin film portion 5 b of the gate insulating film 5 is disposed on the photodiode 2. The thick film portion 5a of the gate insulating film 5 is disposed on the vertical transfer portion 4, and the charge transfer electrode 14a made of a metal material film is disposed on the thick film portion 5a.
　各電荷転送電極１４ａには、シリコン酸化膜等からなるサイドウォール９ａが設けられており、当該サイドウォール９ａの端部と、薄膜部５ｂの端部とが一致している。また、フォトダイオード２上およびサイドウォール９ａ上にわたって、シリコン窒化膜等からなる反射防止膜１０が設けられており、当該反射防止膜１０上には、各電荷転送電極１４ａ間のフォトダイオード２上の間隙を埋め込む、シリコン酸化膜等からなる平坦化膜１１が設けられる。なお、電荷転送電極１４ａの上面において、反射防止膜１０は開口されており、各電荷転送電極１４ａ上に反射防止膜１０は存在しない。 Each charge transfer electrode 14a is provided with a side wall 9a made of a silicon oxide film or the like, and the end of the side wall 9a coincides with the end of the thin film portion 5b. An antireflection film 10 made of a silicon nitride film or the like is provided on the photodiode 2 and the sidewall 9a. On the antireflection film 10, on the photodiode 2 between the charge transfer electrodes 14a. A planarizing film 11 made of a silicon oxide film or the like is provided to fill the gap. The antireflection film 10 is opened on the upper surface of the charge transfer electrode 14a, and there is no antireflection film 10 on each charge transfer electrode 14a.
　当該構造の上方には、シリコン酸化膜等からなる層間絶縁膜１６を介してプラズマＣＶＤ法により堆積されたシリコン窒化膜（Ｐ－ＳｉＮ膜）からなる層内レンズ１７が個々のフォトダイオード２に対応して配置される。当該層内レンズ１７上には、透明樹脂等からなるフィルタ下平坦化膜１８を介して、カラーフィルタ１９およびマイクロレンズ２０が個々のフォトダイオード２に対応して配置される。なお、カラーフィルタ１９は、例えば、赤色光を透過する赤色フィルタ、緑色光を透過する緑色フィルタ、青色光を透過する青色フィルタから選択された１色のフィルタが、固体撮像素子全体として所定の平面配置となるように配置されるが、図１では各色フィルタを区別していない。 Above the structure, an inner lens 17 made of a silicon nitride film (P-SiN film) deposited by a plasma CVD method through an interlayer insulating film 16 made of a silicon oxide film or the like corresponds to each photodiode 2. Arranged. On the in-layer lens 17, a color filter 19 and a microlens 20 are arranged corresponding to each photodiode 2 via a filter under-flattening film 18 made of a transparent resin or the like. The color filter 19 is, for example, a single color filter selected from a red filter that transmits red light, a green filter that transmits green light, and a blue filter that transmits blue light. The color filters are not distinguished from each other in FIG.
　この固体撮像装置は、ゲート絶縁膜５が、垂直転送部４上に配置される厚膜部５ａと、フォトダイオード２上に配置される薄膜部５ｂとを備える。すなわち、厚膜部５ａ上に金属材料膜からなる電荷転送電極１４ａが配置されるため、所望の閾値制御を行うことができる。また、フォトダイオード２上に薄膜部５ｂが配置されるため、表面不純物層２１をシャロードーピングにより形成可能である。また、反射防止膜１０との組み合わせにより、良好な反射防止効果を得ることができる。言い換えれば、従来、最適な反射防止効果を得るためにゲート絶縁膜厚を調整することは種々の弊害（ポテンシャルや閾値電圧の変動、電界分布等）が発生するため困難であったが、本構成ではこのような弊害を生じることがなく、設計自由度を高めることができる。そして、以上の結果、電荷転送電極１４ａの微細化が進行した場合であっても、光学感度の低下を抑制することができる。 In this solid-state imaging device, the gate insulating film 5 includes a thick film portion 5 a disposed on the vertical transfer portion 4 and a thin film portion 5 b disposed on the photodiode 2. That is, since the charge transfer electrode 14a made of a metal material film is disposed on the thick film portion 5a, desired threshold control can be performed. Further, since the thin film portion 5b is disposed on the photodiode 2, the surface impurity layer 21 can be formed by shallow doping. Moreover, a favorable antireflection effect can be obtained by combination with the antireflection film 10. In other words, conventionally, it has been difficult to adjust the gate insulating film thickness in order to obtain an optimal antireflection effect due to various adverse effects (potential and threshold voltage fluctuations, electric field distribution, etc.). Thus, such a harmful effect does not occur, and the degree of freedom in design can be increased. As a result, even if the charge transfer electrode 14a is miniaturized, it is possible to suppress a decrease in optical sensitivity.
　加えて、電荷転送電極１４ａは低抵抗な金属材料膜からなるため、電荷転送電極１４ａの薄膜化も可能となる。その結果、電荷転送電極１４ａの微細化が進行した場合であっても、電極間容量を低減することができ、高速駆動が可能となる。また、電荷転送電極が遮光膜を兼ねているため、遮光膜の開口面積を大きくすることと、垂直転送路４の幅を大きくすることとの両立が可能であり、Ｓ／Ｎ比の改善、すなわち、高感度化を図ることもできる。 In addition, since the charge transfer electrode 14a is made of a low-resistance metal material film, the charge transfer electrode 14a can be thinned. As a result, even when the charge transfer electrode 14a is miniaturized, the interelectrode capacitance can be reduced and high-speed driving is possible. In addition, since the charge transfer electrode also serves as a light shielding film, it is possible to simultaneously increase the opening area of the light shielding film and increase the width of the vertical transfer path 4, and improve the S / N ratio. That is, high sensitivity can be achieved.
　また、この固体撮像素子では、電荷転送電極１４ａは、互いに隣接する電荷転送電極間で重なりがない単層電極構造であり、遮光膜としても機能する。そのため、電荷転送電極を被覆する状態で形成する従来の遮光膜が不要である。したがって、遮光膜が電荷転送電極の側壁に高くそびえ立つことがない。例えば、遮光膜が電荷転送電極の側壁に高くそびえ立つ構成では、光をフォトダイオードへ導くために、層内レンズ１７等により入射光の経路を急峻に曲げる必要がある。しかしながら、このような構成では、画素セルサイズが小さくなるにつれて、層内レンズ１７等の焦点位置がフォトダイオードの手前（上方）となり、フォトダイオードに焦点を合わせることが不可能になる。すなわち、このような構成において、フォトダイオードに焦点を合わせると、入射光が電荷転送電極の側壁に高くそびえ立つ遮光膜に阻害され、光学感度が低下することになる。本実施形態の構成によれば、この種の光学感度の低下を抑制することができる。また、電荷転送電極１４ａが遮光膜を兼ねているため、別途遮光膜を形成する場合に比べて電荷転送電極１４ａの幅をフォトダイオード２の占有面積を犠牲にすることなく大きくできる。その結果、フォトダイオード２から垂直転送部４へ信号電荷を読み出す際の読出し電圧を低減することもできる。さらに、電荷転送電極１４ａが遮光膜を兼ねているため、別途遮光膜を形成する構成において存在していた、電荷転送電極と遮光膜との間の寄生容量をなくすことができる。その結果、更なる高速駆動が可能になる。 Further, in this solid-state imaging device, the charge transfer electrode 14a has a single-layer electrode structure in which there is no overlap between adjacent charge transfer electrodes, and also functions as a light shielding film. Therefore, the conventional light shielding film formed in a state of covering the charge transfer electrode is unnecessary. Therefore, the light shielding film does not rise high on the side wall of the charge transfer electrode. For example, in a configuration in which the light shielding film stands high on the side wall of the charge transfer electrode, the path of incident light needs to be sharply bent by the inner lens 17 or the like in order to guide light to the photodiode. However, in such a configuration, as the pixel cell size is reduced, the focal position of the inner layer lens 17 and the like is in front (upward) of the photodiode, and it becomes impossible to focus on the photodiode. That is, in such a configuration, when focusing on the photodiode, the incident light is hindered by the light-shielding film soaring high on the side wall of the charge transfer electrode, and the optical sensitivity is lowered. According to the configuration of the present embodiment, this type of decrease in optical sensitivity can be suppressed. Further, since the charge transfer electrode 14a also serves as a light shielding film, the width of the charge transfer electrode 14a can be increased without sacrificing the area occupied by the photodiode 2 as compared with the case where a separate light shielding film is formed. As a result, it is possible to reduce the read voltage when reading signal charges from the photodiode 2 to the vertical transfer unit 4. Furthermore, since the charge transfer electrode 14a also serves as a light shielding film, it is possible to eliminate the parasitic capacitance between the charge transfer electrode and the light shielding film, which existed in the configuration in which the light shielding film is separately formed. As a result, further high speed driving becomes possible.
　また、フォトダイオード２は、反射防止膜１０として機能するシリコン窒化膜で被覆されているので、金属材料膜による汚染の影響がなく、金属汚染に起因する白キズの発生をも回避できる。 Further, since the photodiode 2 is covered with the silicon nitride film functioning as the antireflection film 10, there is no influence of the contamination by the metal material film, and the generation of white scratches due to the metal contamination can be avoided.
　以上のように、本実施形態の固体撮像素子では、今後の更なる微細化に際しても、すなわち、電荷転送電極１４ａの更なる微細化に際しても、感度低下を招くことなく、低読出し電圧、高感度、かつ高速駆動を安定して実現することができる。 As described above, in the solid-state imaging device according to the present embodiment, even when further miniaturization is performed in the future, that is, when the charge transfer electrode 14a is further miniaturized, a low read voltage and high sensitivity are not caused. In addition, high-speed driving can be realized stably.
　続いて、上述の構造を有する固体撮像素子の製造に好適な固体撮像素子の製造方法について説明する。図２～図１７は、本発明の一実施形態における固体撮像素子の製造過程を示す断面図である。各図では、左側に図１９のＸ－Ｘ線に沿う断面（以下、Ａ部という。）、中央に図１９のＹ－Ｙ線に沿う断面（以下、Ｂ部という。）、右側に固体撮像素子の周辺回路に形成される、シリコン系膜の配線を有する素子（抵抗やヒューズ等）の断面（以下、Ｃ部という。）を同時に示している。ここでは、Ｃ部として、シリコン系膜の配線からなる抵抗体を例示する。 Subsequently, a method for manufacturing a solid-state imaging device suitable for manufacturing a solid-state imaging device having the above-described structure will be described. 2 to 17 are cross-sectional views showing the manufacturing process of the solid-state imaging device in one embodiment of the present invention. In each figure, a cross section along the line XX in FIG. 19 (hereinafter referred to as “A part”) is shown on the left side, a cross section along the YY line in FIG. A cross section (hereinafter, referred to as “C part”) of an element (resistor, fuse, etc.) having a silicon film wiring formed in the peripheral circuit of the element is shown at the same time. Here, as the portion C, a resistor made of a silicon film wiring is exemplified.
　まず、図２に示すように、イオン注入など既知の方法に従って、例えばＰ型の半導体基板（シリコン基板）１に、入射光を光電変換するためのＮ型フォトダイオード２、個々の画素セルを電気的に分離するためのＰ型分離領域３、フォトダイオード２で生成された信号電荷を垂直方向に転送するためのＮ型垂直転送部４が形成される。 First, as shown in FIG. 2, according to a known method such as ion implantation, for example, an N-type photodiode 2 for photoelectrically converting incident light and an individual pixel cell are electrically connected to a P-type semiconductor substrate (silicon substrate) 1. Thus, a P-type isolation region 3 for isolating the signal and an N-type vertical transfer unit 4 for transferring the signal charge generated by the photodiode 2 in the vertical direction are formed.
　その後、半導体基板１の表面に膜厚４０ｎｍ程度のゲート絶縁膜（第１の絶縁膜）５が形成され、当該ゲート絶縁膜５上に、リン等の不純物を含有するポリシリコン膜あるいはアモルファスシリコン膜等のシリコン系膜６が形成される。そして、当該シリコン系膜６上にシリコン酸化膜７が形成される。ここでは、当該シリコン系膜６は、電荷転送電極１４ａを形成するためのダミーパターンおよび周辺回路の配線を構成する材料であり、シリコン酸化膜７は、後述の製造過程、特に、エッチバック工程等において、所望部分のシリコン系膜６の露出（膜減り）を防止する機能を有する。本実施形態では、シリコン系膜６の膜厚は１５０ｎｍ程度であり、シリコン酸化膜７の膜厚は、５０ｎｍ～１００ｎｍ程度である。シリコン系膜６およびシリコン酸化膜７は、例えば、ＣＶＤ（Chemical Vapor Deposition）法等を用いて形成することができる。 Thereafter, a gate insulating film (first insulating film) 5 having a thickness of about 40 nm is formed on the surface of the semiconductor substrate 1, and a polysilicon film or an amorphous silicon film containing an impurity such as phosphorus is formed on the gate insulating film 5. A silicon-based film 6 is formed. Then, a silicon oxide film 7 is formed on the silicon film 6. Here, the silicon-based film 6 is a material constituting a dummy pattern and a peripheral circuit wiring for forming the charge transfer electrode 14a, and the silicon oxide film 7 is a manufacturing process to be described later, in particular, an etch back process or the like. 1 has a function of preventing exposure (film reduction) of the silicon-based film 6 at a desired portion. In this embodiment, the silicon-based film 6 has a thickness of about 150 nm, and the silicon oxide film 7 has a thickness of about 50 nm to 100 nm. The silicon film 6 and the silicon oxide film 7 can be formed by using, for example, a CVD (Chemical Vapor Deposition) method.
　次に、図３に示すようにシリコン酸化膜７上に公知のリソグラフィ技術を用いて、レジストパターン（図示せず）を形成し、このレジストパターンをマスクとしてシリコン酸化膜７およびシリコン系膜６を異方性ドライエッチングにより除去する。その後、レジストパターンが除去される。これにより、固体撮像素子の画素セルアレイには、電荷転送電極１４ａと同一の平面レイアウトを有するダミーパターン６ａが形成され、周辺回路形成領域（Ｃ部）には、抵抗体６ｂが形成される。なお、ダミーパターン６ａおよび抵抗体６ｂ上には、シリコン酸化膜７ａ、７ｂがそれぞれ残留している。なお、本実施形態ではダミーパターン６ａおよび抵抗体６ｂを形成するためにレジストパターンを用いた。しかしながら、特許文献１に記載されているように、まず、シリコン系膜６上のシリコン酸化膜７にパターンを形成し、当該パターンの周囲にシリコン酸化膜、シリコン窒化膜等の絶縁膜からなるサイドウォールを付加してパターン寸法を拡大し、当該拡大されたパターンをハードマスクとしてシリコン系膜６をエッチングしてもよい。このようにすると、Ｂ部においてダミーパターン６ａ間の間隙８を非常に狭く形成することができる。要するに、ダミーパターン６ａおよび抵抗体６ｂ上にシリコン酸化膜が残存する構成であればよい。なお、周辺回路形成領域（Ｃ部）では、上記抵抗体６ｂが形成されると同時に、ＭＯＳ型トランジスタのゲート電極もシリコン系膜６により形成される。 Next, as shown in FIG. 3, a resist pattern (not shown) is formed on the silicon oxide film 7 using a known lithography technique, and the silicon oxide film 7 and the silicon-based film 6 are formed using the resist pattern as a mask. It is removed by anisotropic dry etching. Thereafter, the resist pattern is removed. As a result, a dummy pattern 6a having the same planar layout as the charge transfer electrode 14a is formed in the pixel cell array of the solid-state imaging device, and a resistor 6b is formed in the peripheral circuit formation region (C portion). Silicon oxide films 7a and 7b remain on the dummy pattern 6a and the resistor 6b, respectively. In the present embodiment, a resist pattern is used to form the dummy pattern 6a and the resistor 6b. However, as described in Patent Document 1, first, a pattern is formed on the silicon oxide film 7 on the silicon-based film 6, and a side made of an insulating film such as a silicon oxide film or a silicon nitride film is formed around the pattern. A pattern may be enlarged by adding a wall, and the silicon-based film 6 may be etched using the enlarged pattern as a hard mask. In this way, the gap 8 between the dummy patterns 6a can be formed very narrow in the portion B. In short, any structure may be used as long as the silicon oxide film remains on the dummy pattern 6a and the resistor 6b. In the peripheral circuit formation region (C portion), the resistor 6b is formed, and at the same time, the gate electrode of the MOS transistor is formed of the silicon-based film 6.
　この後、ダミーパターン６ａ間の狭い間隙８に位置する半導体基板１の領域（Ｂ部）での、固体撮像素子の動作時における電荷転送ポテンシャルを調整するため、この領域にイオン注入などにより不純物が導入される。また、周辺回路部では、半導体基板１への不純物導入により、ＭＯＳ型トランジスタの低濃度および高濃度ソース／ドレイン等の不純物領域（図示せず）が形成される。 Thereafter, in order to adjust the charge transfer potential during the operation of the solid-state imaging device in the region (B portion) of the semiconductor substrate 1 located in the narrow gap 8 between the dummy patterns 6a, impurities are implanted into this region by ion implantation or the like. be introduced. In the peripheral circuit portion, impurity regions (not shown) such as low concentration and high concentration source / drain of the MOS transistor are formed by introducing impurities into the semiconductor substrate 1.
　次いで、図４に示すように、半導体基板１上に、垂直転送部４の電荷転送方向に沿って隣接するダミーパターン６ａ間の間隙８を充填するとともに、ダミーパターン６ａおよび抵抗体６ｂを被覆する絶縁膜（第２の絶縁膜）９が形成される。間隙８の間隔は、図１９に示す距離ｓに対応し、例えばｓ＝０．１μｍ～０．３μｍである。 Next, as shown in FIG. 4, the gap 8 between the dummy patterns 6 a adjacent to each other along the charge transfer direction of the vertical transfer unit 4 is filled on the semiconductor substrate 1, and the dummy pattern 6 a and the resistor 6 b are covered. An insulating film (second insulating film) 9 is formed. The interval of the gap 8 corresponds to the distance s shown in FIG. 19, for example, s = 0.1 μm to 0.3 μm.
　図４に示すように、絶縁膜９は、Ｂ部断面において間隙８が埋め込まれ、かつＡ部断面においてダミーパターン６ａの形状に応じた凹部ができるような膜厚で形成される。ここでは、絶縁膜９としてシリコン酸化膜を堆積している。当該シリコン酸化膜は、前記間隙８を埋め込むことができるレベルの良好な段差被覆性が生じるように８５０℃を超える高温のＬＰ－ＣＶＤ（Low Pressure-CVD）法を用いて堆積することが望ましい。 As shown in FIG. 4, the insulating film 9 is formed in such a film thickness that the gap 8 is embedded in the B section and a recess corresponding to the shape of the dummy pattern 6a is formed in the A section. Here, a silicon oxide film is deposited as the insulating film 9. The silicon oxide film is preferably deposited by using a high-temperature LP-CVD (Low-Pressure-CVD) method exceeding 850 ° C. so as to produce a good step coverage that can fill the gap 8.
　この後、図５に示すように、エッチバック法を用いて、絶縁膜９に対して全面異方性エッチングが行われ、Ａ部断面においてはゲート絶縁膜５上に形成された部分、Ｂ部断面においてはシリコン酸化膜７上に形成された部分が除去される。これによりＢ部の間隙８には絶縁膜９が埋め込まれ（以下、電極間絶縁膜９ｂという。）、同時にＡ部のダミーパターン６ａの側面にシリコン酸化膜からなるサイドウォール９ａが形成される。本実施形態では、当該エッチバック工程において、フォトダイオード２上を被覆するゲート絶縁膜５を積極的にエッチングし、所望膜厚となる薄膜部５ｂを形成する。ここで、所望膜厚とは、後述のフォトダイオード２の表面部に、信号電荷と逆導電型の電荷（ここでは、正孔）を蓄積する表面不純物層を形成するためのイオン注入において、シャロードーピングが可能となり、かつ反射防止膜１０を積層した場合に適切な反射防止機能を実現できる膜厚である。薄膜部５ｂの膜厚は、好ましくは、５ｎｍ～３５ｎｍであり、ここでは、２０ｎｍとしている。薄膜部５ｂの膜厚が３５ｎｍを超えると、フォトダイオード飽和量を大きくする効果が低下するからである。また、当該エッチングの際に使用するエッチング装置やエッチング条件、ウエットエッチングとの併用、表面不純物積層の不純物プロファイル、後続の熱処理等にも依存することになるが、膜厚が５ｎｍ未満になると、エッチングダメージによりフォトダイオードの暗電流増大が懸念されるからである。さらに、当該薄膜部５ｂの形成は、窒化膜の膜ストレスを緩和する作用も奏することができる。この観点で、薄膜部５ｂの膜厚を設定することもできる。なお、画素セルアレイ領域において、当該工程でゲート絶縁膜５の薄化により形成された薄膜部５ｂを除く部分、すなわち、ダミーパターン６ａおよびサイドウォール９ａの下層であるゲート絶縁膜５部分が厚膜部５ａになる。 Thereafter, as shown in FIG. 5, the entire surface of the insulating film 9 is anisotropically etched using an etch-back method, and a portion formed on the gate insulating film 5 and a portion B in the section A are shown. In the cross section, the portion formed on the silicon oxide film 7 is removed. As a result, the insulating film 9 is embedded in the gap 8 in the B portion (hereinafter referred to as an interelectrode insulating film 9b), and at the same time, a sidewall 9a made of a silicon oxide film is formed on the side surface of the dummy pattern 6a in the A portion. In the present embodiment, in the etch back process, the gate insulating film 5 covering the photodiode 2 is positively etched to form a thin film portion 5b having a desired film thickness. Here, the desired film thickness is a shallow value in ion implantation for forming a surface impurity layer for accumulating charges (here, holes) having a conductivity type opposite to that of signal charges on the surface of a photodiode 2 to be described later. The thickness is such that doping can be performed and an appropriate antireflection function can be realized when the antireflection film 10 is laminated. The film thickness of the thin film portion 5b is preferably 5 nm to 35 nm, and here it is 20 nm. This is because if the thickness of the thin film portion 5b exceeds 35 nm, the effect of increasing the amount of photodiode saturation decreases. Also, depending on the etching apparatus and etching conditions used in the etching, combined use with wet etching, the impurity profile of the surface impurity stack, the subsequent heat treatment, etc., the etching is performed when the film thickness is less than 5 nm. This is because the dark current of the photodiode may be increased due to the damage. Furthermore, the formation of the thin film portion 5b can also have an effect of relaxing the film stress of the nitride film. From this viewpoint, the film thickness of the thin film portion 5b can also be set. In the pixel cell array region, a portion excluding the thin film portion 5b formed by thinning the gate insulating film 5 in the process, that is, the portion of the gate insulating film 5 which is the lower layer of the dummy pattern 6a and the sidewall 9a is a thick film portion. 5a.
　この後、イオン注入を用いてフォトダイオード２の表面部にＰ型不純物を導入することにより、Ｐ型正電荷蓄積層（表面不純物層）２１が形成される（図６参照）。本実施形態では、図１に示すように、金属材料膜からなる電荷転送電極１４ａが垂直転送部４上に配置されるが、先の工程において、フォトダイオード２上のゲート絶縁膜５に薄膜部５ｂが形成されている。そのため、厚いゲート絶縁膜を通じたイオン注入を実現するために注入エネルギーを高める必要がなく、シャロードーピングが可能である。したがって、フォトダイオード２の極表面部にＰ型不純物を導入することができる。したがって、仮に、ゲート絶縁膜の膜厚を比較的厚くしなければならない状況であっても、フォトダイオード飽和量の低下を防止できる。 Thereafter, a P-type positive charge storage layer (surface impurity layer) 21 is formed by introducing P-type impurities into the surface portion of the photodiode 2 using ion implantation (see FIG. 6). In the present embodiment, as shown in FIG. 1, the charge transfer electrode 14 a made of a metal material film is disposed on the vertical transfer portion 4. In the previous step, the thin film portion is formed on the gate insulating film 5 on the photodiode 2. 5b is formed. Therefore, it is not necessary to increase the implantation energy in order to realize ion implantation through the thick gate insulating film, and shallow doping is possible. Therefore, P-type impurities can be introduced into the extreme surface portion of the photodiode 2. Therefore, even if the gate insulating film needs to be relatively thick, it is possible to prevent the photodiode saturation from decreasing.
　当該不純物導入の後、電気炉を用い、８５０℃を越え９００℃以下の温度、１０分～６０分の時間範囲で注入不純物の活性化熱処理を行う。この熱処理によって今までにイオン注入で形成したフォトダイオード２、垂直転送部４などの不純物層中の注入不純物、周辺回路部における注入不純物も同時に活性化される。不純物活性化熱処理には１０００℃で１０秒～６０秒程度の短時間熱処理（ＲＴＡ）を用いてもよい。 After the introduction of the impurities, an activation heat treatment of the implanted impurities is performed using an electric furnace at a temperature exceeding 850 ° C. and not exceeding 900 ° C. for a time range of 10 minutes to 60 minutes. By this heat treatment, the implanted impurities in the impurity layers such as the photodiode 2 and the vertical transfer portion 4 formed by ion implantation so far and the implanted impurities in the peripheral circuit portion are also activated simultaneously. For the impurity activation heat treatment, a short-time heat treatment (RTA) at 1000 ° C. for about 10 seconds to 60 seconds may be used.
　続いて、図６に示すように、半導体基板１上の全面に反射防止膜１０が形成される。ここでは、反射防止膜１０として、シリコン窒化膜を５０ｎｍの厚さで形成する。周知のように、反射防止膜１０は、フォトダイオード２へ入射する入射光の、半導体基板１表面における反射を防止する作用を有し、本実施形態では、ゲート絶縁膜５であるシリコン酸化膜の薄膜部５ｂの膜厚と、反射防止膜１０であるシリコン窒化膜の膜厚を所定厚で積層することで当該機能を創出する。本実施形態では、図１に示すように、金属材料膜からなる電荷転送電極１４ａが垂直転送部４上に配置されるが、先の工程において、フォトダイオード２上のゲート絶縁膜５に薄膜部５ｂが形成されているため、ゲート絶縁膜５の当初期膜厚（厚膜部５ａの膜厚）に起因して反射防止効果が損なわれることがない。 Subsequently, as shown in FIG. 6, an antireflection film 10 is formed on the entire surface of the semiconductor substrate 1. Here, as the antireflection film 10, a silicon nitride film is formed with a thickness of 50 nm. As is well known, the antireflection film 10 has a function of preventing reflection of incident light incident on the photodiode 2 on the surface of the semiconductor substrate 1. In this embodiment, the antireflection film 10 is formed of a silicon oxide film that is the gate insulating film 5. The function is created by laminating the film thickness of the thin film portion 5b and the film thickness of the silicon nitride film as the antireflection film 10 at a predetermined thickness. In the present embodiment, as shown in FIG. 1, the charge transfer electrode 14 a made of a metal material film is disposed on the vertical transfer portion 4. In the previous step, the thin film portion is formed on the gate insulating film 5 on the photodiode 2. Since 5b is formed, the antireflection effect is not impaired due to the initial film thickness of the gate insulating film 5 (film thickness of the thick film portion 5a).
　この後、図７に示すように、ＢＰＳＧ（Boron Phosphor Silicate Glass）等のシリコン酸化膜からなる平坦化膜１１を半導体基板１全面に堆積してリフロー処理を行うことにより、半導体基板１上の凹部（フォトダイオード２上に存在する、隣接するダミーパターン６ａ間の凹部や周辺回路部の凹部等）を充填する。なお、本実施形態では、平坦化膜１１を堆積する時点で、半導体基板１上の凹凸は、ダミーパターン６ａ、抵抗体６ｂを含む、シリコン系膜６とシリコン酸化膜７の積層膜からなるパターンに起因して構成される（図６等参照）。そして、本実施形態では、シリコン系膜６とシリコン酸化膜７の積層膜からなるパターンには、サイドウォール９ａが形成されている。すなわち、平坦化膜１１を堆積する時点で、半導体基板１上の凸部は、凸部上面から下面に向かって幅が増大する順テーパ形状になっている。その結果、当該工程において、凹部に、極めて良好に平坦化膜１１を充填することができる。 After that, as shown in FIG. 7, a planarizing film 11 made of a silicon oxide film such as BPSG (Boron Phosphor Silicate Glass) is deposited on the entire surface of the semiconductor substrate 1 to perform a reflow process, thereby forming a recess on the semiconductor substrate 1. (Recesses between adjacent dummy patterns 6a, recesses in the peripheral circuit portion, etc. existing on the photodiode 2) are filled. In the present embodiment, when the planarizing film 11 is deposited, the unevenness on the semiconductor substrate 1 is a pattern made of a laminated film of the silicon-based film 6 and the silicon oxide film 7 including the dummy pattern 6a and the resistor 6b. (See FIG. 6 etc.). In the present embodiment, sidewalls 9 a are formed in the pattern composed of the laminated film of the silicon-based film 6 and the silicon oxide film 7. That is, at the time when the planarizing film 11 is deposited, the convex portion on the semiconductor substrate 1 has a forward tapered shape in which the width increases from the upper surface to the lower surface of the convex portion. As a result, in the process, the planarizing film 11 can be filled in the recesses very well.
　当該平坦化膜１１上には、図８に示すように、レジスト膜１２が形成される。当該状態でエッチバック法を用いて、レジスト膜１２および平坦化膜１１に対して全面異方性エッチングが行われ、図９に示すように、半導体基板１上の平坦化が達成される。すなわち、Ａ部断面においてはゲート絶縁膜５上に形成された部分、Ｂ部断面においてはシリコン酸化膜７上に形成された部分が除去される。その結果、シリコン酸化膜７（７ａ、７ｂ）上（ダミーパターン６ａおよび抵抗体６ｂ上）に堆積された反射防止膜１０が最表面に露出する。 A resist film 12 is formed on the planarizing film 11 as shown in FIG. In this state, the entire surface anisotropic etching is performed on the resist film 12 and the planarizing film 11 using the etch back method, and planarization on the semiconductor substrate 1 is achieved as shown in FIG. That is, the portion formed on the gate insulating film 5 in the section A and the portion formed on the silicon oxide film 7 in the section B are removed. As a result, the antireflection film 10 deposited on the silicon oxide film 7 (7a, 7b) (on the dummy pattern 6a and the resistor 6b) is exposed to the outermost surface.
　なお、ここでは、エッチバック法を用いた手法を説明したが、ＣＭＰ（Chemical Mechanical Polishing）法により、レジスト膜１２および平坦化膜１１を研磨しても、同様の構造を得ることができる。また、平坦化膜１１の材質は、ＢＰＳＧに限定されず、シリコン酸化膜とシリコン窒化膜の積層膜、あるいはシリコン窒化膜を採用することもできる。また、これらの平坦化膜１１を形成方法も、上述の凹部の埋め込みを実現可能であれば、常圧ＣＶＤ、減圧ＣＶＤ、プラズマＣＶＤ等、任意の成膜方法を採用することができる。 In addition, although the method using the etch-back method has been described here, the same structure can be obtained even if the resist film 12 and the planarizing film 11 are polished by the CMP (Chemical Mechanical Polishing) method. The material of the planarizing film 11 is not limited to BPSG, and a laminated film of a silicon oxide film and a silicon nitride film, or a silicon nitride film can also be adopted. As the method for forming the planarizing film 11, any film forming method such as atmospheric pressure CVD, low pressure CVD, plasma CVD, or the like can be adopted as long as the above-described recess filling can be realized.
　続いて、図１０に示すように、配線、電極の材料として、シリコン系膜６を採用する領域（例えば、Ｃ部）にマスクが形成される。ここでは、マスクとして、フォトレジスト膜からなるレジストパターン１３をリソグラフィ技術により形成している。 Subsequently, as shown in FIG. 10, a mask is formed in a region (for example, part C) where the silicon-based film 6 is used as a material for wiring and electrodes. Here, as a mask, a resist pattern 13 made of a photoresist film is formed by a lithography technique.
　レジストパターン１３を形成した後、レジストパターン１３により被覆されていない領域の表面に露出している反射防止膜１０（ここでは、シリコン窒化膜）が、全面ドライエッチング等により除去される。これにより、図１１に示すように、ダミーパターン６ａ上のシリコン酸化膜７ａが最表面に露出する。このとき、Ｂ部ではダミーパターン６ａ間がシリコン酸化膜からなる電極間絶縁膜９ｂで埋め込まれているため、これがエッチングされることは回避される。 After the resist pattern 13 is formed, the antireflection film 10 (here, silicon nitride film) exposed on the surface of the region not covered with the resist pattern 13 is removed by dry etching or the like on the entire surface. Thereby, as shown in FIG. 11, the silicon oxide film 7a on the dummy pattern 6a is exposed on the outermost surface. At this time, in the portion B, the space between the dummy patterns 6a is filled with the interelectrode insulating film 9b made of a silicon oxide film, so that it is avoided that this is etched.
　なお、上述したように、図５を用いて説明した絶縁膜９のエッチバック工程、および当該工程での、反射防止膜１０のエッチバックはシリコン酸化膜７が露出した時点で停止することになるが、シリコン酸化膜７は最初からこれらのエッチングによってダミーパターン６ａ（および抵抗体６ｂ）が露出することのない膜厚に設定される。 As described above, the etching back process of the insulating film 9 described with reference to FIG. 5 and the etching back of the antireflection film 10 in this process are stopped when the silicon oxide film 7 is exposed. However, the silicon oxide film 7 is initially set to a thickness that does not expose the dummy pattern 6a (and the resistor 6b) by these etchings.
　その後、以上のようにして露出したシリコン酸化膜７ａがエッチング除去される。その結果、図１２に示すように、ダミーパターン６ａの上面が最表面に露出する。 Thereafter, the exposed silicon oxide film 7a is removed by etching as described above. As a result, as shown in FIG. 12, the upper surface of the dummy pattern 6a is exposed on the outermost surface.
　続いて、露出したダミーパターン６ａがエッチング除去される。下層の垂直転送部４における暗電流の増大を防止するため、シリコン系膜からなるダミーパターン６ａのエッチングには、エッチングダメージの少ない手法を採用することが好ましい。例えば、ケミカルドライエッチング法やウエットエッチング法を使用することによりダメージレスで、ダミーパターン６ａを除去することができる。 Subsequently, the exposed dummy pattern 6a is removed by etching. In order to prevent an increase in dark current in the lower vertical transfer section 4, it is preferable to employ a technique with little etching damage for etching the dummy pattern 6 a made of a silicon-based film. For example, the dummy pattern 6a can be removed without damage by using a chemical dry etching method or a wet etching method.
　当該エッチングの後、図１３に示すように、レジストパターン１３が除去される。当該レジスト除去に伴う、希フッ酸等を使用した洗浄の際、ダミーパターン６ａが除去された部分に露出するゲート酸化膜５（厚膜部５ａの一部）がわずかにエッチングされる。しかしながら、当該エッチング量は１～２ｎｍ程度であり、厚膜部５ａの当該部分（電荷転送電極１４ａ直下）の膜厚が、上述の薄膜部５ｂの膜厚に比べて厚い状況に変わりはない。なお、ゲート酸化膜５の当初膜厚は、当該膜厚減少分を考慮して設定することが好ましい。 After the etching, the resist pattern 13 is removed as shown in FIG. During the cleaning using dilute hydrofluoric acid or the like accompanying the removal of the resist, the gate oxide film 5 (a part of the thick film portion 5a) exposed to the portion where the dummy pattern 6a has been removed is slightly etched. However, the etching amount is about 1 to 2 nm, and the thickness of the portion of the thick film portion 5a (just below the charge transfer electrode 14a) is thicker than the thickness of the thin film portion 5b. The initial film thickness of the gate oxide film 5 is preferably set in consideration of the thickness reduction.
　次いで、図１４に示すように、タングステンやアルミニウム等の金属材料膜１４が全面に堆積される。なお、金属材料膜１４は単体膜に限らず、例えば、窒化チタン（下層）等の高融点金属化合物とアルミニウム（上層）との積層膜等の多層膜を使用してもよい。以上例示した金属材料膜は、遮光性の観点で、特に好ましい材料であるが他の金属材料を使用してもよい。このような、金属材料種、積層構造は、金属材料膜の比抵抗、耐熱温度、電荷転送電極の配線幅等に基づいて決定することができる。 Next, as shown in FIG. 14, a metal material film 14 such as tungsten or aluminum is deposited on the entire surface. The metal material film 14 is not limited to a single film, and for example, a multilayer film such as a laminated film of a refractory metal compound such as titanium nitride (lower layer) and aluminum (upper layer) may be used. The metal material films exemplified above are particularly preferable materials from the viewpoint of light shielding properties, but other metal materials may be used. Such metal material type and laminated structure can be determined based on the specific resistance of the metal material film, the heat resistant temperature, the wiring width of the charge transfer electrode, and the like.
　当該金属材料膜１４上には、図１５に示すように、レジスト膜１５が形成され、エッチバック法を用いて、レジスト膜１５および金属材料膜１４に対して全面異方性エッチング（あるいは、ＣＭＰ法を用いた全面研磨）が行われ、半導体基板１上の平坦化が達成される。その結果、ダミーパターン６ａが存在していた箇所に金属材料膜１４からなる電荷転送電極１４ａが形成される。なお、以上の工程により形成される電荷転送電極１４ａの膜厚は、１５０ｎｍ程度になる。 As shown in FIG. 15, a resist film 15 is formed on the metal material film 14, and the resist film 15 and the metal material film 14 are entirely anisotropic etched (or CMP) using an etch back method. The entire surface is polished using a method, and planarization on the semiconductor substrate 1 is achieved. As a result, the charge transfer electrode 14a made of the metal material film 14 is formed at the place where the dummy pattern 6a was present. The film thickness of the charge transfer electrode 14a formed by the above process is about 150 nm.
　以上のようにして、ダミーパターン６ａから、金属材料膜１４からなる電荷転送電極１４ａへの置換が完了すると、図１７に示すように、全面に、シリコン酸化膜等からなる層間絶縁膜１６が堆積される。 When the replacement of the dummy pattern 6a with the charge transfer electrode 14a made of the metal material film 14 is completed as described above, the interlayer insulating film 16 made of a silicon oxide film or the like is deposited on the entire surface as shown in FIG. Is done.
　なお、本実施形態では、電荷転送電極１４ａが垂直転送部４への光の進入を防止する遮光膜として機能するため、上層に遮光膜を形成する必要はない。しかしながら、撮像領域の外縁領域に設けられる光学的黒画素（オプティカルブラック）領域等、遮光をより強化する領域には、層間絶縁膜１６上に、タングステンやアルミニウム等からなる遮光膜を形成することができる。これにより、良好な光学的黒画素を実現できるとともに、電荷転送電極と遮光膜との間の容量を低減でき、高速駆動が可能となる。 In the present embodiment, since the charge transfer electrode 14a functions as a light shielding film that prevents light from entering the vertical transfer portion 4, it is not necessary to form a light shielding film in the upper layer. However, a light shielding film made of tungsten, aluminum, or the like may be formed on the interlayer insulating film 16 in a region that further enhances light shielding, such as an optical black pixel (optical black) region provided in the outer edge region of the imaging region. it can. As a result, a good optical black pixel can be realized, the capacitance between the charge transfer electrode and the light shielding film can be reduced, and high-speed driving is possible.
　以降、Ａｌを主成分とする各種配線、パッシベーション膜などを形成した後、Ｐ－ＳｉＮ膜からなる層内レンズ１７、カラーフィルタ１９およびマイクロレンズ２０が個々のフォトダイオード２に対応して形成される。 Thereafter, after forming various wirings mainly composed of Al, a passivation film, etc., an inner lens 17, a color filter 19 and a microlens 20 made of a P-SiN film are formed corresponding to each photodiode 2. .
　以上説明したように、本実施形態の固体撮像素子の製造方法では、図５に示す工程において、金属材料膜からなる電荷転送電極１４ａ形成のために、当初、半導体基板１の全面に形成したゲート絶縁膜５を、ダミーパターン６ａおよびサイドウォール９ａをマスクとして膜厚を減少させ薄膜部５ｂを形成する。すなわち、特別な工程を追加することなく、厚膜部５ａと薄膜部５ｂとを有するゲート絶縁膜５を形成することができる。また、当該厚膜部５ａと薄膜部５ｂとを有するゲート絶縁膜５を採用することにより、上述のように、電荷転送電極１４ａの微細化が進行した場合であっても、光学感度の低下を抑制することができる。 As described above, in the method of manufacturing the solid-state imaging device according to the present embodiment, the gate formed initially on the entire surface of the semiconductor substrate 1 to form the charge transfer electrode 14a made of a metal material film in the step shown in FIG. The thickness of the insulating film 5 is reduced using the dummy pattern 6a and the sidewall 9a as a mask to form a thin film portion 5b. That is, the gate insulating film 5 having the thick film portion 5a and the thin film portion 5b can be formed without adding a special process. Further, by adopting the gate insulating film 5 having the thick film portion 5a and the thin film portion 5b, the optical sensitivity is reduced even when the charge transfer electrode 14a is miniaturized as described above. Can be suppressed.
　また、本実施形態の製造方法によれば、良質な電極間絶縁膜９ｂを形成でき、電荷転送電極間耐圧を確保できる。すなわち、画素セルのパターンレイアウトを示す図１９において、電荷転送電極１４ａの周期的配列ピッチｐが１．２μｍ程度となるスケールの固体撮像素子を考えた場合、隣接するフォトダイオード間の領域上を通る電荷転送電極１４ａの最小幅ｗは０．１μｍ～０．３μｍにまで減少されることになるが、本発明によればこのような部分にも電荷転送電極１４ａを良好に形成可能である。 In addition, according to the manufacturing method of the present embodiment, a high-quality interelectrode insulating film 9b can be formed, and a withstand voltage between charge transfer electrodes can be ensured. That is, in FIG. 19 showing the pattern layout of the pixel cell, when a solid-state imaging device having a scale in which the periodic arrangement pitch p of the charge transfer electrodes 14a is about 1.2 μm is considered, it passes over a region between adjacent photodiodes. Although the minimum width w of the charge transfer electrode 14a is reduced to 0.1 μm to 0.3 μm, according to the present invention, the charge transfer electrode 14a can be satisfactorily formed in such a portion.
　また、図１４に示す工程において、金属材料膜１４形成時にフォトダイオード２は、反射防止膜１０として機能するシリコン窒化膜で被覆されている。すなわち、金属材料膜１４による汚染の影響がなく、金属汚染に起因する白キズの発生を回避できる。したがって、特別な白キズ対策、そのための熱処理条件や熱処理工程の変更が不要となる。また、上述の製造方法では、金属材料膜１４の形成後に８００℃を超えるような高温プロセスを実施する必要がないため、プロセスも容易である。 In the step shown in FIG. 14, the photodiode 2 is covered with a silicon nitride film that functions as the antireflection film 10 when the metal material film 14 is formed. That is, there is no influence of contamination by the metal material film 14, and generation of white scratches due to metal contamination can be avoided. This eliminates the need for special measures against white flaws and the heat treatment conditions and heat treatment process for that purpose. Further, in the above manufacturing method, it is not necessary to perform a high-temperature process exceeding 800 ° C. after the formation of the metal material film 14, so that the process is easy.
　さらに、上述の固体撮像素子の製造方法によれば、電荷転送電極１４ａ直下のゲート絶縁膜に段差が生じることがなく、同じ膜厚になるため、ポケットやバリアの形成による、電極間でポテンシャルが変わったりすることがないため、良好な転送が可能となる。 Furthermore, according to the above-described manufacturing method of the solid-state imaging device, the gate insulating film directly below the charge transfer electrode 14a does not have a step and has the same film thickness. Therefore, the potential between the electrodes due to the formation of pockets and barriers is increased. Since there is no change, good transfer is possible.
　以上のように、本発明によれば、今後の更なる微細化に際しても、すなわち、電荷転送電極１４の更なる微細化に際しても、感度低下を招くことなく、低読出し電圧、高感度、かつ高速駆動の固体撮像素子を安定して実現することができる。 As described above, according to the present invention, even in the future further miniaturization, that is, in further miniaturization of the charge transfer electrode 14, low read voltage, high sensitivity, and high speed without causing a decrease in sensitivity. A driving solid-state imaging device can be realized stably.
　なお、以上で説明した実施形態は本発明の技術的範囲を制限するものではなく、既に記載したもの以外でも、本発明の技術的思想を逸脱しない範囲内で種々の変形や応用が可能である。例えば、上記実施形態において例示した成膜等の各プロセスは、同一の構造を実現できる等価なプロセスに置換可能である。 The embodiment described above does not limit the technical scope of the present invention, and various modifications and applications other than those already described are possible without departing from the technical idea of the present invention. . For example, each process such as film formation exemplified in the above embodiment can be replaced with an equivalent process capable of realizing the same structure.
　以上のように本発明は、金属材料膜からなる低抵抗な電荷転送電極を有し、高感度かつ高速駆動可能な、微細な固体撮像素子を安定して形成でき、固体撮像素子およびその製造方法として有用である。 As described above, the present invention has a low-resistance charge transfer electrode made of a metal material film, can stably form a fine solid-state image sensor that can be driven with high sensitivity and high speed, and a solid-state image sensor and a method for manufacturing the same. Useful as.
　１　半導体基板（シリコン基板）
　２　フォトダイオード
　４　電荷転送部（垂直転送部）
　５　第１の絶縁膜（ゲート絶縁膜）
　５ａ　厚膜部
　５ｂ　薄膜部
　６　シリコン系膜
　６ａ　ダミーパターン
　７　シリコン酸化膜
　８　間隙
　９　第２の絶縁膜（シリコン酸化膜）
　９ａ　サイドウォール
　１０　反射防止膜（シリコン窒化膜）
　１１　平坦化膜（シリコン酸化膜）
　１２　レジスト膜
　１３　レジストパターン
　１４　金属材料膜
　１４ａ　電荷転送電極
　１５　レジスト膜
　１６　層間絶縁膜
　２１　（電荷蓄積層）表面不純物層
　４０　固体撮像素子
　４１　撮像領域
　４２　フォトダイオード
　４３　垂直転送部（転送領域）
　４４　水平転送部（転送領域） 1 Semiconductor substrate (silicon substrate)
2 Photodiode 4 Charge transfer unit (vertical transfer unit)
5 First insulating film (gate insulating film)
5a Thick film portion 5b Thin film portion 6 Silicon-based film 6a Dummy pattern 7 Silicon oxide film 8 Gap 9 Second insulating film (silicon oxide film)
9a Side wall 10 Antireflection film (silicon nitride film)
11 Planarization film (silicon oxide film)
DESCRIPTION OF SYMBOLS 12 Resist film 13 Resist pattern 14 Metal material film 14a Charge transfer electrode 15 Resist film 16 Interlayer insulation film 21 (Charge storage layer) Surface impurity layer 40 Solid-state image sensor 41 Imaging area 42 Photodiode 43 Vertical transfer part (transfer area)
44 Horizontal transfer section (transfer area)

Claims (14)

  1. 　光電変換により入射光に応じた信号電荷を生成するフォトダイオード、および前記フォトダイオードにおいて生成された信号電荷を転送する電荷転送部、を備える半導体基板と、
    　前記半導体基板表面に設けられ、前記フォトダイオード上を被覆する薄膜部と、前記電荷転送部上を被覆する、前記薄膜部よりも膜厚が厚い厚膜部とを有する絶縁膜と、
    　前記電荷転送部上を被覆する前記絶縁膜の厚膜部上に形成され、前記電荷転送部内の前記信号電荷を転送する、金属材料膜からなる電荷転送電極と、
    を備えることを特徴とする固体撮像素子。     A semiconductor substrate including a photodiode that generates signal charges according to incident light by photoelectric conversion, and a charge transfer unit that transfers the signal charges generated in the photodiode;
    An insulating film provided on the surface of the semiconductor substrate and having a thin film portion covering the photodiode and a thick film portion covering the charge transfer portion and thicker than the thin film portion;
    A charge transfer electrode formed on a thick film portion of the insulating film covering the charge transfer portion and made of a metal material film for transferring the signal charge in the charge transfer portion;
    A solid-state imaging device comprising:
  2. 　前記フォトダイオード上を被覆する前記絶縁膜上に、反射防止膜をさらに備える、請求項１記載の固体撮像素子。 The solid-state imaging device according to claim 1, further comprising an antireflection film on the insulating film covering the photodiode.
  3. 　前記電荷転送電極は、前記絶縁膜の前記薄膜部の端部に一致する端部を有するサイドウォールを備える、請求項１記載の固体撮像素子。 The solid-state imaging device according to claim 1, wherein the charge transfer electrode includes a sidewall having an end that coincides with an end of the thin film portion of the insulating film.
  4. 　前記電荷転送電極は、前記絶縁膜の前記薄膜部の端部に一致する端部を有するサイドウォールを備える、請求項２記載の固体撮像素子。 The solid-state imaging device according to claim 2, wherein the charge transfer electrode includes a sidewall having an end that coincides with an end of the thin film portion of the insulating film.
  5. 　前記反射防止膜は前記サイドウォールを被覆する、請求項３記載の固体撮像素子。 The solid-state imaging device according to claim 3, wherein the antireflection film covers the sidewall.
  6. 　前記反射防止膜は前記サイドウォールを被覆する、請求項４記載の固体撮像素子。 The solid-state imaging device according to claim 4, wherein the antireflection film covers the sidewall.
  7. 　前記反射防止膜がシリコン窒化膜を含む、請求項５記載の固体撮像素子。 The solid-state imaging device according to claim 5, wherein the antireflection film includes a silicon nitride film.
  8. 　前記反射防止膜がシリコン窒化膜を含む、請求項６記載の固体撮像素子。 The solid-state imaging device according to claim 6, wherein the antireflection film includes a silicon nitride film.
  9. 　前記金属材料膜がタングステンまたはアルミニウムを含む、請求項１から８のいずれか１項に記載の固体撮像素子。 The solid-state imaging device according to any one of claims 1 to 8, wherein the metal material film includes tungsten or aluminum.
  10. 　前記金属材料膜が窒化チタンとアルミニウムとの積層構造を含む、請求項１から８のいずれか１項に記載の固体撮像素子。 The solid-state imaging device according to any one of claims 1 to 8, wherein the metal material film includes a laminated structure of titanium nitride and aluminum.
  11. 　半導体基板に、光電変換により入射光に応じた信号電荷を生成するフォトダイオード、および前記フォトダイオードにおいて生成された信号電荷を転送する電荷転送部、を形成するステップと、
    　前記フォトダイオードおよび前記電荷転送部が形成された半導体基板上に、第１の絶縁膜を形成するステップと、
    　前記電荷転送部上に、前記第１の絶縁膜を介して、前記電荷転送部内の前記信号電荷を転送する電荷転送電極の平面レイアウトを有する、ダミーパターンを形成するステップと、
    　前記ダミーパターンが形成された半導体基板上に、前記電荷転送部の電荷転送方向に沿って隣接する前記ダミーパターン間の間隙を充填するとともに、前記ダミーパターンを被覆する、第２の絶縁膜を形成するステップと、
    　エッチングにより、前記ダミーパターン上および前記フォトダイオード上の第２の絶縁膜を除去するとともに、前記ダミーパターンに第２の絶縁膜からなるサイドウォールを形成し、かつ前記フォトダイオード上の前記第１の絶縁膜の膜厚を減少させるステップと、
    　半導体基板上に残存する前記第２の絶縁膜で囲まれたダミーパターンを除去し、金属材料膜からなる前記電荷転送電極に置換するステップと、
    を有することを特徴とする固体撮像素子の製造方法。     Forming, on a semiconductor substrate, a photodiode that generates a signal charge corresponding to incident light by photoelectric conversion, and a charge transfer unit that transfers the signal charge generated in the photodiode;
    Forming a first insulating film on the semiconductor substrate on which the photodiode and the charge transfer portion are formed;
    Forming a dummy pattern having a planar layout of a charge transfer electrode for transferring the signal charge in the charge transfer unit via the first insulating film on the charge transfer unit;
    A second insulating film is formed on the semiconductor substrate on which the dummy pattern is formed, filling a gap between the dummy patterns adjacent in the charge transfer direction of the charge transfer unit and covering the dummy pattern. And steps to
    Etching removes the second insulating film on the dummy pattern and the photodiode, forms a sidewall made of the second insulating film on the dummy pattern, and forms the first insulating film on the photodiode. Reducing the thickness of the insulating film;
    Removing the dummy pattern surrounded by the second insulating film remaining on the semiconductor substrate and replacing the charge transfer electrode made of a metal material film;
    A method for manufacturing a solid-state imaging device, comprising:
  12. 　前記ダミーパターンを除去する前に、膜厚を減少させた前記第１の絶縁膜を通じて不純物を導入し、前記フォトダイオードの表面部に、前記信号電荷と逆導電型の電荷を蓄積する表面不純物層を形成するステップを、さらに有する請求項１１記載の固体撮像素子の製造方法。 Before removing the dummy pattern, an impurity is introduced through the first insulating film having a reduced thickness, and a surface impurity layer for accumulating the charge of the opposite type to the signal charge on the surface of the photodiode. The method of manufacturing a solid-state imaging device according to claim 11, further comprising:
  13. 　膜厚を減少させた前記第１の絶縁膜を通じて不純物を導入した後、前記ダミーパターンを除去する前に、フォトダイオード上を被覆する前記第１の絶縁膜上に、反射防止膜を形成するステップを、さらに有する請求項１２記載の固体撮像素子の製造方法。 A step of forming an antireflection film on the first insulating film covering the photodiode after removing the dummy pattern after introducing impurities through the first insulating film having a reduced thickness. The manufacturing method of the solid-state image sensor of Claim 12 which further has these.
  14. 　前記ダミーパターンがシリコン系膜からなる、請求項１１から１３のいずれか１項に記載の固体撮像素子の製造方法。 14. The method for manufacturing a solid-state imaging element according to claim 11, wherein the dummy pattern is made of a silicon-based film.
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