WO2011086730A1 - Iii族窒化物系半導体素子 - Google Patents
Iii族窒化物系半導体素子 Download PDFInfo
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- WO2011086730A1 WO2011086730A1 PCT/JP2010/066443 JP2010066443W WO2011086730A1 WO 2011086730 A1 WO2011086730 A1 WO 2011086730A1 JP 2010066443 W JP2010066443 W JP 2010066443W WO 2011086730 A1 WO2011086730 A1 WO 2011086730A1
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- group iii
- iii nitride
- electrode
- semiconductor region
- nitride semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 115
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 65
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 47
- 230000007704 transition Effects 0.000 claims abstract description 36
- 239000013078 crystal Substances 0.000 claims abstract description 27
- 239000002019 doping agent Substances 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims description 17
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 72
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 39
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 38
- 229910002601 GaN Inorganic materials 0.000 description 34
- 238000000034 method Methods 0.000 description 23
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 18
- 238000001228 spectrum Methods 0.000 description 13
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 7
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- 229910052738 indium Inorganic materials 0.000 description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 6
- 238000004381 surface treatment Methods 0.000 description 6
- 238000004458 analytical method Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 101100011794 Caenorhabditis elegans epi-1 gene Proteins 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical group [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 238000003917 TEM image Methods 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
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- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000005211 surface analysis Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 229910052984 zinc sulfide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
Definitions
- the present invention relates to a group III nitride semiconductor device.
- Patent Documents 1 and 2 describe a method for forming an ohmic electrode on a p-type gallium nitride (GaN) layer grown on a (0001) plane, that is, a c-plane.
- a Ni / Au film is deposited on the p-type GaN layer, and then heat treatment is performed in an oxygen atmosphere.
- nickel absorbs the oxide film by this method.
- the oxide film is removed by the combination of oxygen atoms and nickel in the oxide film. Thereby, since Au can contact the p-type GaN crystal, an ohmic junction is formed.
- Patent Document 3 describes experimental results. In this experiment, a p-type group III nitride semiconductor layer is grown on a sapphire substrate. And after heating a board
- Patent Document 4 Pt is vapor-deposited on the p-type GaN contact layer. Then, an electrode alloying process is performed by performing a heat treatment in the range of 500 ° C. to 600 ° C. in an oxygen atmosphere.
- a group III nitride semiconductor containing indium such as InGaN or InAlGaN may be used on a group III nitride semiconductor substrate such as a GaN substrate. May grow. Since the diameter of the indium atom is larger than the diameter of the gallium atom, when the composition of indium is increased, the internal strain of the layer containing indium increases due to lattice mismatch. As a result, a large piezo electric field is induced in the layer, the recombination probability is lowered, and the light emission efficiency is suppressed.
- the present invention relates to a group III nitride semiconductor capable of reducing the contact resistance between an electrode provided on a semiconductor layer and the semiconductor layer when the surface of the group III nitride semiconductor is inclined from the c-plane. An element is provided.
- a group III nitride semiconductor device includes a semiconductor region having a nonpolar surface made of a group III nitride crystal, and a metal electrode provided on the nonpolar surface of the semiconductor region. Nonpolar surfaces are either semipolar or nonpolar.
- a p-type dopant is added to the semiconductor region.
- a transition layer is formed between the group III nitride crystal in the semiconductor region and the metal electrode, and the transition layer is formed by mutual diffusion of the metal in the metal electrode and the group III nitride in the semiconductor region.
- the present inventors have found that the contact resistance can be effectively reduced by forming a transition layer at the interface between the electrode and the group III nitride crystal. That is, in the group III nitride semiconductor region where the surface is nonpolar, the crystal state of the surface is in a state where it is easily bonded to the metal. Therefore, unlike the case where the electrode is formed on the semiconductor region having the c-plane as the surface, a transition layer can be generated between the semiconductor region and the electrode.
- the transition layer is a layer formed by interdiffusion of the metal of the electrode and the group III nitride crystal of the semiconductor region. By this transition layer, the adhesion between the semiconductor region and the electrode is improved, and the contact resistance can be kept small.
- the thickness of the transition layer may be 0.5 nm or more and 3 nm or less. Such a transition layer can more effectively reduce the contact resistance.
- the metal electrode may contain at least one of palladium (Pd) and platinum (Pt). With such a metal electrode, a transition layer can be suitably formed between the semiconductor region.
- the metal electrode may be completed without heat treatment after the metal film is formed on the nonpolar surface of the semiconductor region. Thereby, a transition layer can be suitably generated between the semiconductor region.
- the angle between the normal of the surface of the semiconductor region and the c-axis of the group III nitride crystal may be in the range of 10 degrees to 80 degrees or 100 degrees to 170 degrees. Thereby, a semipolar surface of the semiconductor region can be provided.
- the angle formed between the normal of the surface of the semiconductor region and the c-axis of the group III nitride crystal may be in the range of 63 degrees to 80 degrees or 100 degrees to 117 degrees. Thereby, a semipolar surface of the semiconductor region can be provided.
- the surface of the group III nitride semiconductor region is inclined from the c-plane, and the contact resistance between the electrode provided on the semiconductor layer and the semiconductor region is reduced.
- a small group III nitride semiconductor device is provided.
- FIG. 1 is a drawing showing major steps in a method for manufacturing a group III nitride semiconductor device according to an embodiment.
- FIG. 2 is a drawing schematically showing a product in the main process shown in FIG.
- FIG. 3 is a drawing schematically showing a product in the main process shown in FIG.
- FIG. 4A is a diagram showing the configuration of the epitaxial substrate fabricated in the first example.
- FIG. 4B is a diagram showing a Pd electrode structure including an inner electrode formed by photolithography and an outer electrode separated from the inner electrode.
- FIG. 5 is a graph showing the measurement results of contact resistance.
- FIG. 6 is a graph showing the analysis result of the epitaxial substrate in the second embodiment.
- FIG. 7 is a graph showing the analysis result of the epitaxial substrate in the second embodiment.
- FIG. 8 is a photograph of a cross section of the epitaxial substrate fabricated in the second example taken with a transmission electron microscope.
- FIG. 9 is a photograph of a cross section of the epitaxial substrate fabricated in the second example taken with a transmission electron microscope.
- FIG. 10 is a graph showing the difference in spectrum depending on the presence or absence of surface treatment in an epitaxial substrate on which a Pd electrode is formed.
- FIG. 11 is a graph showing the difference in spectrum depending on the presence or absence of surface treatment in an epitaxial substrate on which a Pd electrode is formed.
- FIG. 1 is a drawing showing main steps in a method for manufacturing a group III nitride semiconductor device according to an embodiment.
- 2 and 3 are drawings schematically showing products in the main steps shown in FIG.
- Group III nitride semiconductor devices are optical devices such as laser diodes and light emitting diodes, or electronic devices such as pn junction diodes and transistors.
- a substrate 11 shown in FIG. 2A is prepared.
- the substrate 11 has a nonpolar major surface.
- the substrate 11 is made of a group III nitride semiconductor having a wurtzite structure, for example.
- group III nitride semiconductors include AlN and gallium nitride semiconductors such as AlGaN and GaN. In these gallium nitride semiconductors, the main surface 11a of the substrate 11 exhibits nonpolarity. Nonpolar is semipolar or nonpolar.
- the normal vector NV is perpendicular to the main surface 11 a of the substrate 11.
- An angle Alpha formed by the normal vector NV of the substrate 11 and the c-axis vector VC is, for example, in the range of 10 degrees to 170 degrees.
- step S102 as shown in FIG. 2B, the substrate 11 is placed in a processing apparatus 10a such as a growth furnace. Thereafter, the semiconductor region 13 is grown on the main surface 11 a of the substrate 11.
- the semiconductor region 13 is made of a group III nitride crystal.
- the semiconductor region 13 preferably includes, for example, one or a plurality of gallium nitride based semiconductor layers.
- the semiconductor region 13 is provided by epitaxial growth on the main surface 11 a of the substrate 11. This crystal growth is performed, for example, by metal organic vapor phase epitaxy or molecular beam epitaxy.
- the surface 13a of the semiconductor region 13 has nonpolarity. This nonpolarity is also semipolar or nonpolar.
- the nonpolar surface 13a of the semiconductor region 13 is made of a p-type group III nitride semiconductor, for example, a gallium nitride semiconductor.
- a p-type dopant such as Mg is added at a high concentration to the p-type group III nitride semiconductor.
- the formation of the p-type group III nitride semiconductor is not limited to epitaxial growth. By these steps, the first substrate product P1 is produced.
- step S103 the first substrate product P1 is taken out from the processing apparatus 10a.
- the nonpolar surface 13a of the semiconductor region 13 exposed to the atmosphere is more easily oxidized than the c-plane which is a polar surface. That is, a relatively thick natural oxide film is formed on the nonpolar surface of the semiconductor region 13 exposed to the atmosphere.
- the natural oxide film is formed when the substrate product P1 is moved from the processing apparatus 10a to the film forming apparatus. As shown in FIG. 2C, the oxide 15 which is a natural oxide film exists on the surface of the first substrate product P1.
- a step of pre-processing the first substrate product P1 may be provided as step S104.
- the pretreatment solution for example, at least one of aqua regia, hydrofluoric acid, and hydrochloric acid is preferably used. With these solutions, the oxide 15 formed on the nonpolar surface 13a of the semiconductor region 13 can be removed to some extent.
- step S105 the first substrate product P1 is placed in the film forming apparatus 10b.
- a lift-off mask can be formed on the first substrate product P1 prior to placement in the film forming apparatus 10b.
- This mask includes a resist layer.
- the film forming apparatus 10b is evacuated to achieve a vacuum degree of about 1 ⁇ 10 ⁇ 6 Torr. 1 Pa is converted at 0.0075 Torr.
- the metal electrode 17 is deposited in a film shape on the surface of the first substrate product P1 using the film forming apparatus 10b.
- the metal electrode 17 can be formed using, for example, an electron beam evaporation method or a resistance heating method.
- the temperature of the substrate 11 at this time is preferably 15 ° C. or more and 100 ° C. or less, for example.
- the metal electrode 17 contains Pd.
- the metal electrode 17 comprises a Pd layer.
- the thickness of the Pd layer is preferably 10 nm or more, for example.
- a transition layer 19 is generated at the interface between the metal electrode 17 and the nonpolar surface 13 a of the semiconductor region 13.
- the transition layer 19 is a layer in which Pd and GaN are interdiffused.
- the transition layer 19 occurs simultaneously with the deposition of the metal electrode 17.
- the nonpolar surface 13a of the semiconductor region 13 is nonpolar, it is easy to bond to a metal unlike the c-plane, and thus such a transition layer 19 is expanded.
- the substrate product P ⁇ b> 2 includes a metal electrode 17 provided on the semiconductor region 13 of the substrate product P ⁇ b> 1 and a transition layer 19 generated at the interface between the semiconductor region 13 and the metal electrode 17.
- step S107 the second substrate product P2 is taken out from the film forming apparatus 10b.
- a lift-off mask is formed on the first substrate product P1
- a lift-off process is performed to form a patterned electrode.
- the lift-off process is performed using, for example, acetone.
- the second substrate product P2 is arranged in a heat treatment apparatus and heat treatment is performed at about 400 ° C.
- heat treatment is performed at about 400 ° C.
- the formation of the ohmic electrode is completed without performing such heat treatment.
- the second substrate product P2 is cut into chips. Thereby, a group III nitride semiconductor device is completed.
- Patent Documents 1 and 2 tried to form an electrode on a non-polar surface of GaN using the prior art (Patent Documents 1 and 2) for forming an ohmic electrode on the c-plane of a GaN crystal.
- Patent Documents 3 and 4 even when a Ni / Au metal film is formed on a nonpolar surface of GaN such as the (11-22) plane and this metal film is alloyed in an oxygen atmosphere, the contact resistance of the ohmic electrode cannot be lowered.
- the Pt electrode is formed on the nonpolar surface in a high temperature state as in other prior arts (Patent Documents 3 and 4), it cannot be brought into ohmic contact. That is, in these prior arts, it has become clear that a good ohmic electrode can be formed on the c-plane of the GaN crystal, but it is difficult to form a good ohmic electrode on the nonpolar plane.
- the present inventors produced a Pd electrode at a low temperature on the nonpolar surface of the GaN crystal. As a result, good ohmic contact was obtained. In order to consider the reason, surface analysis was performed using an X-ray photoelectron spectrometer (XPS). According to this analysis, in the Pd electrode formed at a low temperature on the nonpolar surface of the GaN crystal, it was possible to confirm a sub-peak that was not observed elsewhere. It is considered that a transition layer formed by interdiffusion of Pd and GaN is newly generated between the nonpolar plane of the GaN crystal and the Pd electrode, and this improves the contact resistance between the GaN crystal and the Pd electrode.
- XPS X-ray photoelectron spectrometer
- the bonding state of the crystal surface is different between the nonpolar plane and the c plane.
- GaN and Pd are likely to be bonded. Therefore, it is presumed that the transition layer as described above spreads at the interface between the GaN crystal and the Pd electrode. Such a phenomenon is considered to occur similarly in a group III nitride semiconductor other than GaN.
- the semiconductor region 13 has the nonpolar surface 13a.
- the transition layer 19 is generated by forming the metal electrode 17 containing Pd on the nonpolar surface 13a.
- the transition layer 19 improves the adhesion between the semiconductor region 13 and the metal electrode 17 and can reduce the contact resistance between them.
- the thickness of the transition layer 19 is preferably 0.5 nm or more and 3 nm or less.
- the inventors investigated the relationship between the thickness of the transition layer 19 and the electrical characteristics. As a result, good electrical characteristics could be obtained at 0.5 nm or more and 3 nm or less. That is, the contact resistance can be more effectively reduced by the transition layer 19 having such a thickness.
- the metal electrode 17 preferably contains Pd. This is because the transition layer 19 can be preferably formed between the semiconductor electrode 13 and the metal electrode 17 containing Pd.
- the metal that causes the transition layer 19 is not limited to Pd.
- the transition layer can be generated by a metal electrode containing Pt.
- the metal electrode 17 is preferably completed after a metal film is formed on the nonpolar surface 13a of the semiconductor region 13 without undergoing heat treatment. Thereby, the transition layer 19 can be suitably generated between the semiconductor region 13.
- the epitaxial substrate shown in FIG. 4A was produced by metal organic vapor phase epitaxy using an n-type semipolar GaN substrate 31.
- the main surface of the GaN substrate 31 included an m-plane.
- An n-type GaN buffer layer 32 was formed on this main surface.
- Epitaxial substrate Epi1 included Si-doped n-type GaN layer 33, Mg-doped GaN layer 34, and high-concentration Mg-doped p-type GaN layer 35.
- the thickness of the Si-doped n-type GaN layer 33 was 1 ⁇ m.
- the thickness of the Mg-doped GaN layer 34 was 0.4 ⁇ m.
- the thickness of the high-concentration Mg-doped p-type GaN layer 35 was 50 nm.
- a resist was formed by photolithography. This resist had an annular opening.
- a Pd electrode was vapor-deposited on the epitaxial substrate by an electron beam method in a vapor deposition apparatus having a vacuum of about 1 ⁇ 10 ⁇ 6 Torr. The thickness of the Pd electrode was 500 mm. The resist was lifted off using acetone. Thus, a Pd electrode structure was fabricated as shown in FIG.
- the Pd electrode structure included an inner electrode EIN formed by photolithography and an outer electrode EOUT separated from the inner electrode EIN. No heat treatment was performed on these electrode structures.
- FIG. 5 is a graph showing the measurement results of contact resistance.
- FIG. 5 also shows the contact resistance measurement results for the Ni / Au electrode structure manufactured by the same method as described above. As shown in FIG. 5, according to the Pd electrode structure of this example, the contact resistance is effectively reduced as compared with the Ni / Au electrode structure.
- An epitaxial substrate was fabricated by the same procedure as in the first example.
- the epitaxial substrate was subjected to ultrasonic organic cleaning using acetone and 2-propanol. Thereafter, washing with hydrochloric acid, aqua regia and hydrofluoric acid was performed for 5 minutes each.
- a Pd electrode was deposited on the epitaxial substrate by an electron beam method. The thickness of the Pd electrode was 100 mm. The temperature at the time of vapor deposition was room temperature.
- another epitaxial substrate prepared and cleaned by the same process as this epitaxial substrate was prepared.
- a Ni / Au electrode was deposited on the epitaxial substrate. Then, the Ni / Au electrode was subjected to heat treatment.
- Ni was deposited using the electron beam method.
- Au was deposited using a resistance heating method.
- the thickness of each of Ni and Au was 50 mm.
- different types of p-type electrodes were produced on each of the two epitaxial substrates.
- the interface between the GaN crystal and the p-type electrode was analyzed for these epitaxial substrates. For this analysis, an X-ray photoelectron spectrometer was used.
- 6 and 7 are graphs showing the analysis results of these epitaxial substrates.
- 6 (a) and 6 (b) show the Ga2p spectrum.
- FIG. 7A and FIG. 7B show N1s spectra.
- 6 and 7, graphs G1 and G2 show spectra of the epitaxial substrate on which the Pd electrode is formed.
- 6 and 7, graphs G3 and G4 show the spectra of the epitaxial substrate on which the Ni / Au electrode is formed.
- FIGS. 6A and 6B there is a sub-peak on the high energy side of the Ga2p spectrum of the epitaxial substrate on which the Pd electrode is formed.
- such a peak does not exist in the Ga2p spectrum of the epitaxial substrate on which the Ni / Au electrode is formed. Thereby, it can be confirmed that a new layer other than the GaN crystal, that is, a transition layer is generated in the epitaxial substrate on which the Pd electrode is formed.
- FIG. 8A shows a cross section of an epitaxial substrate on which a Pd electrode is formed and has not undergone heat treatment.
- FIG. 8B shows a cross section of an epitaxial substrate on which a Pd electrode is formed and subjected to heat treatment. The temperature of this heat treatment is 310 ° C., and the time is 1 minute.
- FIG. 9A and FIG. 9B show a cross section of the epitaxial substrate on which the Au / Ni electrode is formed.
- the transition layer 19 in the epitaxial substrate on which the Pd electrode is formed, a thin new layer generated between the Pd electrode and the GaN layer, that is, the transition layer 19 can be confirmed. .
- the thickness of the transition layer 19 is 0.5 nm.
- the thickness of the transition layer 19 is expanded to 2.0 nm.
- FIG. 10 and 11 are graphs showing the difference in spectrum depending on the presence or absence of surface treatment in the epitaxial substrate on which the Pd electrode is formed.
- FIG. 10A and FIG. 10B show a Ga2p spectrum.
- Fig.11 (a) and FIG.11 (b) show a N1s spectrum.
- 10 and 11 graphs G11 and G12 show spectra of an epitaxial substrate that has not been surface-treated.
- 10 and 11 to G16 show the spectra of the epitaxial substrate that has been surface-treated.
- the height of the sub-peak of the epitaxial substrate subjected to the surface treatment is slightly higher than the height of the sub-peak of the epitaxial substrate not subjected to the surface treatment.
- the transition layer is preferably formed regardless of the presence or absence of the surface treatment.
- the group III nitride semiconductor device of this embodiment is a semiconductor optical device such as a semiconductor laser or a light emitting diode.
- the group III nitride semiconductor device of this embodiment is a semiconductor device having a nonpolar surface of a group III nitride semiconductor to which a p-type dopant is added and an electrode formed on the nonpolar surface.
- the surface of the group III nitride semiconductor region is inclined from the c-plane, and the contact resistance between the electrode provided on the semiconductor layer and the semiconductor region is small.
- a group III nitride semiconductor device is provided.
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Abstract
Description
図4(a)に示されるエピタキシャル基板を、n型半極性GaN基板31を用いて有機金属気相成長法により作製した。GaN基板31の主面はm面を含んでいた。この主面上に、n型GaNバッファ層32を形成した。エピタキシャル基板Epi1は、Siドープn型GaN層33と、MgドープGaN層34と、高濃度Mgドープp型GaN層35とを含んでいた。Siドープn型GaN層33の厚さは1μmであった。MgドープGaN層34の厚さは0.4μmであった。高濃度Mgドープp型GaN層35の厚さは50nmであった。これらの窒化ガリウム系半導体層は、基板31上に順に成長された。
第1実施例と同様の手順によりエピタキシャル基板を作製した。このエピタキシャル基板に対して、アセトン及び2-プロパノールを用いて超音波有機洗浄を行った。その後、塩酸、王水、及びフッ酸による洗浄をそれぞれ5分ずつ行った。このエピタキシャル基板上に、電子ビーム法によりPd電極を蒸着した。Pd電極の厚さは100Åであった。蒸着時の温度は室温であった。一方、このエピタキシャル基板と同じ工程によって作製及び洗浄された別のエピタキシャル基板を用意した。このエピタキシャル基板上にNi/Au電極を蒸着した。そして、このNi/Au電極に対して熱処理を行った。Niは電子ビーム法を用いて蒸着された。Auは抵抗加熱法を用いて蒸着された。Ni及びAuそれぞれの厚さは50Åであった。こうして、2枚のエピタキシャル基板のそれぞれに、種類の異なるp型電極が作製された。これらのエピタキシャル基板に対し、GaN結晶とp型電極との界面の分析を行った。この分析には、X線光電子分光分析装置が用いられた。
Claims (6)
- III族窒化物結晶からなる非極性表面を有する半導体領域と、
前記半導体領域の前記非極性表面に設けられた金属電極と
を備え、
前記非極性表面は半極性及び無極性のいずれかであり、
前記半導体領域にはp型ドーパントが添加されており、
前記半導体領域のIII族窒化物結晶と前記金属電極との間に、前記金属電極の金属と前記半導体領域のIII族窒化物とが相互拡散して成る遷移層を有することを特徴とする、III族窒化物系半導体素子。 - 前記遷移層の厚さが0.5nm以上3nm以下であることを特徴とする、請求項1に記載のIII族窒化物系半導体素子。
- 前記金属電極がPd及びPtの少なくとも一方を含むことを特徴とする、請求項1または2に記載のIII族窒化物系半導体素子。
- 前記金属電極が、前記半導体領域の前記非極性表面上に金属膜が形成されたのち、熱処理を経ずに完成されたことを特徴とする、請求項1~3のいずれか一項に記載のIII族窒化物系半導体素子。
- 前記半導体領域の前記非極性表面の法線と前記半導体領域のIII族窒化物結晶のc軸との成す角度が、10度以上80度以下または100度以上170度以下の範囲内にあることを特徴とする、請求項1~4のいずれか一項に記載のIII族窒化物系半導体素子。
- 前記半導体領域の前記非極性表面の法線と前記半導体領域のIII族窒化物結晶のc軸との成す角度が、63度以上80度以下または100度以上117度以下の範囲内にあることを特徴とする、請求項1~4のいずれか一項に記載のIII族窒化物系半導体素子。
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WO2013115269A1 (ja) * | 2012-01-30 | 2013-08-08 | 独立行政法人物質・材料研究機構 | AlN単結晶ショットキーバリアダイオード及びその製造方法 |
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KR101843513B1 (ko) * | 2012-02-24 | 2018-03-29 | 서울바이오시스 주식회사 | 질화갈륨계 발광 다이오드 |
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KR20110099682A (ko) | 2011-09-08 |
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