WO2011080879A1 - アクティブマトリクス基板及びその製造方法 - Google Patents
アクティブマトリクス基板及びその製造方法 Download PDFInfo
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- WO2011080879A1 WO2011080879A1 PCT/JP2010/007102 JP2010007102W WO2011080879A1 WO 2011080879 A1 WO2011080879 A1 WO 2011080879A1 JP 2010007102 W JP2010007102 W JP 2010007102W WO 2011080879 A1 WO2011080879 A1 WO 2011080879A1
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- film
- active matrix
- layer
- wiring
- matrix substrate
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Definitions
- the present invention relates to an active matrix substrate and a manufacturing method thereof, and more particularly to an active matrix substrate using a coating type insulating film and a manufacturing method thereof.
- the active matrix substrate constituting the liquid crystal display device includes, for example, a plurality of scanning wirings provided to extend in parallel to each other, and a plurality of signal wirings provided to extend in parallel to each other in a direction orthogonal to each scanning wiring. And a plurality of thin film transistors (hereinafter also referred to as “TFTs”) provided at each intersection of each scanning wiring and each signal wiring.
- TFTs thin film transistors
- each scanning wiring and each signal wiring are coated type insulation called SOG (Spin on Glass) film.
- SOG Spin on Glass
- a multilayer insulating film covering each scanning wiring includes a lower first insulating layer obtained by patterning an SOG film formed by applying an organic SOG material, and an inorganic insulating film such as a silicon nitride film.
- An active matrix substrate is disclosed which is composed of an upper second insulating layer made of
- Patent Document 2 has an insulating film using an SOG film covering each TFT, and each signal wiring is formed of a conductive layer different from the source electrode and the drain electrode of each TFT, and is formed on the insulating film.
- An active matrix substrate connected to the source electrode of each TFT via a contact hole is disclosed.
- 14 and 15 are explanatory views showing, in cross section, a manufacturing process of a conventional active matrix substrate 120 using a coating type insulating film. 14 and 15, the cross section of the TFT portion is shown in the region A, the cross section of the contact portion of the pixel electrode is shown in the region B, and the cross section of the wiring switching portion is shown in the region C.
- the metal laminated film is patterned by using photolithography to thereby form a scanning wiring 111a and an auxiliary capacitance wiring 111b. And the signal line lead-out wiring 111c is formed.
- an organic SOG film is applied and baked on the entire substrate on which the scanning wiring 111a, the auxiliary capacitance wiring 111b, and the signal line lead-out wiring 111c are formed.
- the first insulating layer 112 is formed by patterning using photolithography.
- the second insulating layer 113, the intrinsic amorphous silicon film, and the n + amorphous material are formed on the entire substrate on which the first insulating layer 112 is formed by using a CVD (Chemical Vapor Deposition) method.
- CVD Chemical Vapor Deposition
- the intrinsic amorphous silicon film and the semiconductor laminated film of the n + amorphous silicon film are patterned using photolithography, so that the intrinsic amorphous silicon layers 114a and 114b and the n + amorphous silicon layers 115a and 115b are patterned.
- two metal films are stacked on the entire substrate on which the intrinsic amorphous silicon layers 114a and 114b and the n + amorphous silicon layers 115a and 115b are formed by using the sputtering method. After that, the metal laminated film is patterned using photolithography to form the source electrode 116a (signal wiring) and the drain electrode 116b (auxiliary capacitance electrode).
- the n + amorphous silicon layers 115a and 115b exposed from the source electrode 116a and the drain electrode 116b and the upper layer portions of the underlying intrinsic amorphous silicon layers 114a and 114b are dry-etched. by removing Te, semiconductor layer 104a having an intrinsic amorphous silicon layer 114aa and the n + amorphous silicon layer 115Aa, and to form a semiconductor layer 104b having an intrinsic amorphous silicon layer 114ba and n + amorphous silicon layer 115Ba, forming a TFT5 To do.
- FIG. 15A after forming the inorganic insulating film 117 on the entire substrate on which the TFT 5 is formed by using the CVD method, as shown in FIG. 15B, a photosensitive resin is formed.
- a fourth insulating layer 118 is formed by applying a film and patterning the photosensitive resin film.
- the third insulating layer 117a is formed by removing the inorganic insulating film 117 exposed from the fourth insulating layer 118 by using dry etching.
- the transparent conductive film is patterned using photolithography.
- the active matrix substrate 120 can be manufactured by forming the pixel electrode 119a and the transparent conductive layer 119b.
- the first insulating layer 112 formed by patterning a relatively thick organic SOG film is disposed between each scanning wiring 111a and each signal wiring (116a).
- the capacitance formed at the intersection of each scanning wiring 111a and each signal wiring 116a can be reduced, after forming the first insulating layer 112, the intrinsic amorphous silicon film and the n + amorphous silicon Since the semiconductor film is formed by the CVD method, the SOG film constituting the first insulating layer 112 is required to have high heat resistance of, for example, 300 ° C. or higher. Then, in the active matrix substrate, the degree of freedom in selecting the material of the SOG film used for reducing the capacitance at the intersection of each scanning wiring and each signal wiring is lowered.
- the present invention has been made in view of the above points, and an object of the present invention is to provide a coating type insulation used for reducing the capacitance of the intersection between each scanning wiring and each signal wiring in the active matrix substrate.
- the purpose is to improve the degree of freedom in selecting the material of the film.
- a coating type insulating layer is formed after a semiconductor layer is formed.
- an active matrix substrate includes a plurality of scanning wirings provided so as to extend in parallel to each other, and a plurality of signal wirings provided so as to extend in parallel with each other in a direction intersecting with each scanning wiring.
- a plurality of semiconductor layers and a plurality of source electrodes and drain electrodes formed on the semiconductor layer in the same layer as each of the signal lines, provided at each intersection of the scanning lines and the signal lines.
- an application-type insulating layer provided between each scanning wiring and each signal wiring, wherein the semiconductor layers are exposed in the insulating layer.
- a plurality of openings are formed, and at least a part of a peripheral edge of each opening of the insulating layer is disposed inside a peripheral edge of each semiconductor layer.
- the peripheral edge of each opening formed in the coating type insulating layer provided between each scanning wiring and each signal wiring is inside the peripheral edge of each semiconductor layer.
- a coating type insulating layer is formed.
- the coating type insulating film for forming the coating type insulating layer for example, it is not necessary to have a heat resistance of 300 ° C. or higher that can withstand the CVD process, and a spin-on glass material having a low heat resistance is applied. Since it can be used as an insulating film, in the active matrix substrate, the degree of freedom in selecting the material of the coating type insulating film used for reducing the capacitance at the intersection of each scanning wiring and each signal wiring is improved.
- Each thin film transistor may have a gate electrode formed in the same layer as each scanning wiring, and each semiconductor layer and each gate electrode may be electrically insulated via a gate insulating film.
- a relatively thick coating type insulating layer is not disposed between the semiconductor layer and the gate electrode, and the semiconductor layer and the gate electrode are interposed through the relatively thin gate insulating film. Since it is electrically insulated, a thin film transistor with low power consumption is specifically configured.
- a plurality of the gate insulating films may be provided so as to cover the upper surface of each scanning wiring and to extend in parallel with each other.
- a plurality of gate insulating films are provided so as to cover the upper surface of each scanning wiring and to extend in parallel with each other. Therefore, patterning when forming the scanning wiring and patterning when forming the semiconductor layer Can be performed by one photolithography, and the number of photomasks necessary for manufacturing is reduced.
- At least one side end of each gate insulating film may protrude from each scanning wiring.
- each gate insulating film protrudes from each scanning wiring and is formed in an overhang state, and the coating type insulating layer covers the protruding portion of the gate insulating film.
- Auxiliary capacitance wiring is provided between the scanning wirings so as to extend along the scanning wiring, and a plurality of openings are formed in the insulating layer so as to overlap the auxiliary capacitance wirings.
- Each auxiliary capacitance line and each drain electrode may be electrically insulated through a gate insulating film.
- a relatively thick coating-type insulating layer is not disposed between the auxiliary capacitor line and the drain electrode constituting the auxiliary capacitor, and the auxiliary capacitor line and the drain electrode are relatively thin. Therefore, a large capacity auxiliary capacitor is specifically configured.
- the insulating layer may be made of an organic spin-on glass material.
- the insulating layer is made of an organic spin-on glass material, for example, the insulating layer is formed by performing exposure and development on a photosensitive organic spin-on glass material.
- Each semiconductor layer may be composed of an oxide semiconductor.
- each semiconductor layer is configured by an oxide semiconductor, a high mobility thin film transistor is specifically configured.
- the active matrix substrate manufacturing method includes a plurality of scanning wirings provided so as to extend in parallel with each other and a plurality of signals provided so as to extend in parallel with each other in a direction intersecting with each scanning wiring.
- a method of manufacturing an active matrix substrate having a type insulating layer wherein a scanning wiring forming step for forming each scanning wiring on the insulating substrate, and a gate insulating film formed so as to cover each scanning wiring Thereafter, a semiconductor layer forming step for forming each semiconductor layer on the gate insulating film, and a spin-on glass material is applied so as to cover the insulating substrate on which each semiconductor layer is formed. And after baking, the spin-on glass material is patterned so that the semiconductor layers are exposed to form an insulating layer, and the signal wiring is formed on the insulating layer. And a signal wiring forming step of forming a source electrode and a drain electrode so as to face each other on each semiconductor layer.
- the degree of freedom in selecting the material of the mold insulating film is improved.
- the first photomask is used in the scanning wiring formation step
- the second photomask is used in the semiconductor layer formation step
- the third photomask is used in the insulating layer formation step.
- the fourth photomask is used in the signal wiring forming step and the subsequent steps are omitted
- the fifth photomask is used in the step of forming the interlayer insulating film as described in the embodiment described later. Since the sixth photomask is used in the step of forming the pixel electrode, the active matrix substrate is manufactured using a total of six photomasks.
- the active matrix substrate manufacturing method includes a plurality of scanning wirings provided so as to extend in parallel with each other and a plurality of signals provided so as to extend in parallel with each other in a direction intersecting with each scanning wiring.
- a plurality of thin film transistors each having a semiconductor layer, and a coating provided between each of the scanning wirings and each of the signal wirings.
- a resist pattern is formed on the semiconductor film so as to overlap the portions to be the scanning wirings and to relatively thicken the portions to be the semiconductor layers.
- Forming a gate insulating film by etching the semiconductor film exposed from the resist pattern and the inorganic insulating film under the semiconductor film, and reducing the thickness of the resist pattern.
- the semiconductor film exposed from the resist pattern is etched to form the semiconductor layers, and the metal film exposed from the gate insulating film is etched to form the scan lines.
- an insulating layer Forming an insulating layer, forming each signal wiring on the insulating layer, and forming the signal wiring on the semiconductor layer. Characterized in that it comprises a signal wire forming step of forming a source electrode and a drain electrode so as to face are.
- the semiconductor layer is formed on the gate insulating film formed in the gate insulating film forming step by using, for example, the CVD method, and then in the insulating layer forming step, the scanning is performed. Since a coating type insulating layer is formed between each scanning wiring formed in the wiring forming step and each signal wiring formed in the subsequent signal wiring forming step, the coating type insulating layer is formed. In the coating type insulating film, for example, it is not necessary to have a heat resistance of 300 ° C. or higher that can withstand the CVD process.
- a spin-on glass material with low heat resistance can be used as a coating type insulating film, so that the coating used to reduce the capacitance of the intersection between each scanning wiring and each signal wiring in the active matrix substrate.
- the degree of freedom in selecting the material of the mold insulating film is improved.
- the first photomask capable of halftone exposure is used in the gate insulating film forming step
- the second photomask is used in the insulating layer forming step
- the signal wiring forming step is used.
- a third photomask is used and subsequent steps are omitted
- a pixel electrode is formed using a fourth photomask in the step of forming an interlayer insulating film as described in the embodiments described later. Since the fifth photomask is used in the process, the active matrix substrate is manufactured using a total of five photomasks, and the manufacturing cost is reduced.
- the coating type insulating layer is formed after the semiconductor layer is formed, the capacitance at the intersection of each scanning wiring and each signal wiring is reduced in the active matrix substrate. Therefore, the degree of freedom in selecting the material of the coating type insulating film used for this purpose can be improved.
- FIG. 1 is a perspective view showing a liquid crystal display device including an active matrix substrate according to the first embodiment.
- FIG. 2 is a plan view illustrating a display unit of the active matrix substrate according to the first embodiment.
- FIG. 3 is a plan view illustrating a wiring switching unit of the active matrix substrate according to the first embodiment.
- FIG. 4 is a first explanatory view showing, in cross section, the manufacturing process of the active matrix substrate according to the first embodiment.
- FIG. 5 is a second explanatory view showing in cross section the manufacturing process of the active matrix substrate subsequent to FIG.
- FIG. 6 is a cross-sectional view illustrating a manufacturing process of the counter substrate 30 disposed to face the active matrix substrate according to the first embodiment.
- FIG. 7 is a first explanatory view showing the manufacturing process of the active matrix substrate according to the second embodiment in cross section.
- FIG. 8 is a second explanatory view showing in cross section the manufacturing process of the active matrix substrate subsequent to FIG.
- FIG. 9 is a third explanatory view showing, in cross section, the manufacturing process of the active matrix substrate subsequent to FIG.
- FIG. 10 is an explanatory view showing in cross section the manufacturing process of the active matrix substrate according to the third embodiment.
- FIG. 11 is a plan view showing a display unit of the active matrix substrate according to the fourth embodiment.
- FIG. 12 is a plan view illustrating a wiring switching unit of the active matrix substrate according to the fourth embodiment.
- FIG. 13 is a cross-sectional view illustrating a manufacturing process of the active matrix substrate according to the fourth embodiment.
- FIG. 14 is a first explanatory view showing, in cross section, a manufacturing process of a conventional active matrix substrate using a coating type insulating film.
- FIG. 15 is a second explanatory view showing the manufacturing process of the active matrix substrate subsequent to FIG. 14 in section.
- FIG. 1 is a perspective view showing a liquid crystal display device 50 including the active matrix substrate 20a of the present embodiment.
- FIG. 2 is a plan view showing the display unit of the active matrix substrate 20a, that is, each pixel which is the minimum unit of an image
- FIG. 3 is a plan view showing a wiring switching unit of the active matrix substrate 20a.
- 4 and 5 are explanatory views showing the manufacturing process of the active matrix substrate 20a in cross section
- FIG. 6 shows the manufacturing process of the counter substrate 30 arranged facing the active matrix substrate 20a in cross section. It is explanatory drawing. Note that FIG.
- 5D corresponds to a cross-sectional view of the active matrix substrate 20a, in which the region A shows a cross section taken along the line AA in FIG. 2, and the region B corresponds to the line BB in FIG. A section along the line CC in FIG. 3 is shown in the region C.
- the liquid crystal display device 50 includes an active matrix substrate 20a and a counter substrate 30 provided so as to face each other, and a sealant (not shown) between the active matrix substrate 20a and the counter substrate 30. And a liquid crystal layer (not shown) enclosed.
- a plurality of gate-side TCPs integrated IC Circuits
- a gate driver IC Integrated Circuit
- Tape Carrier Package 41 and a plurality of source-side TCPs 42 each mounted with a source driver IC are attached via ACF (AnisotropicnisConductive Film).
- the active matrix substrate 20a is provided between a plurality of scanning wirings 11a provided on the insulating substrate 10a so as to extend in parallel with each other and each scanning wiring 11a.
- a plurality of auxiliary capacitance wirings 11b extending in parallel with each other, a plurality of signal wirings 16a provided so as to extend in parallel with each other in a direction orthogonal to each scanning wiring 11a, and an intersection of each scanning wiring 11a and each signal wiring 16a
- a plurality of TFTs 5 provided for each pixel, an interlayer insulating film composed of an inorganic insulating layer 17a and an organic insulating layer 18 provided so as to cover each TFT 5, and a matrix on the interlayer insulating film
- a plurality of pixel electrodes 19a and an alignment film (not shown) provided so as to cover each pixel electrode 19a.
- the scanning wiring 11a is drawn out to the terminal region T and connected to the gate side TCP 41 as shown in FIG.
- the signal wiring 16a is drawn out to the terminal region T, and in the terminal region T, as shown in FIGS. 1, 3 and 5D, the signal wiring 16a is connected to the signal line leading wiring 11c through the transparent conductive layer 19b.
- the signal line lead-out wiring 11c is connected to the source side TCP42.
- the configuration in which the signal wiring 16a is connected to the source side TCP 42 via the signal line leading wiring 11c is exemplified. However, if necessary, the signal wiring is directly extracted and directly connected to the source side TCP. May be.
- the TFT 5 includes a gate electrode (11a) provided on the insulating substrate 10a, a gate insulating film 12 provided so as to cover the gate electrode (11a), and a gate.
- a semiconductor layer 4a provided in an island shape at a position corresponding to the gate electrode (11a) on the insulating film 12, and a source electrode 16aa and a drain electrode 16b provided on the semiconductor layer 4a so as to face each other.
- the gate electrode (11a) is a part of the scanning line 11a
- the source electrode 16aa is a part protruding to the side of the signal line 16a.
- the drain electrode 16b is connected to the pixel electrode 19a through a contact hole 18a formed in an interlayer insulating film composed of the inorganic insulating layer 17a and the organic insulating layer 18, as shown in FIGS. 2 and 5D.
- the auxiliary capacitor 6 is configured by overlapping with the auxiliary capacitor line 11 b through the gate insulating film 12.
- the semiconductor layer 4a is provided with an intrinsic amorphous silicon layer 13aa having a channel region, and the channel region exposed on the intrinsic amorphous silicon layer 13aa, and the source electrode 16aa and And an n + amorphous silicon layer 14aa connected to the drain electrode 16b.
- a coating type is provided between the scanning wiring 11a and the signal wiring 16a.
- An insulating layer 15 is provided. As shown in FIGS. 2 and 5D, the insulating layer 15 is formed with a plurality of openings 15a so that the semiconductor layers 4a are exposed, and a plurality of openings 15a are overlapped with the auxiliary capacitance lines 11b. Openings 15b are formed, and a plurality of openings 15c are formed so as to overlap each signal line lead-out wiring 11c.
- the peripheral edge of each opening part 15a of the insulating layer 15 is arrange
- the counter substrate 30 includes a black matrix 21 provided in a grid pattern on the insulating substrate 10b, and a red layer, a green layer, and a blue layer provided between the grids of the black matrix 21, respectively.
- a plurality of colored layers 22 such as a layer, a common electrode 23 provided so as to cover the black matrix 21 and each colored layer 22, a photo spacer 24 provided in a column shape on the common electrode 23, and a common electrode 23.
- An alignment film (not shown) is provided.
- the liquid crystal layer is made of a nematic liquid crystal material having electro-optical characteristics.
- the TFT 5 in each pixel, when a scanning signal is sent from the gate driver (gate side TCP 41) to the gate electrode (11a) of the TFT 5 through the scanning wiring 11a, the TFT 5 is turned on. In addition, a display signal is sent from the source driver (source side TCP 42) to the source electrode 16aa via the signal wiring 16a, and a predetermined charge is written to the pixel electrode 19a via the semiconductor layer 4a and the drain electrode 16b.
- the liquid crystal display device 50 a potential difference is generated between each pixel electrode 19a of the active matrix substrate 20a and the common electrode 23 of the counter substrate 30, and the liquid crystal layer, that is, the liquid crystal capacitance of each pixel and the liquid crystal capacitance thereof are generated.
- a predetermined voltage is applied to the auxiliary capacitors 6 connected in parallel.
- an image is displayed by adjusting the light transmittance of the liquid crystal layer in each pixel by changing the alignment state of the liquid crystal layer according to the magnitude of the voltage applied to the liquid crystal layer.
- the manufacturing method of this embodiment includes an active matrix substrate manufacturing process, a counter substrate manufacturing process, and a liquid crystal injection process.
- a titanium film (thickness of about 50 nm), an aluminum film (thickness of about 200 nm), a titanium film (thickness of about 150 nm), and the like are sequentially stacked on the entire substrate of the insulating substrate 10a such as a glass substrate. After that, by patterning the metal laminated film using photolithography, as shown in FIG. 4A, scanning wiring 11a composed of three layers of titanium layer Ga, aluminum layer Gb, and titanium layer Gc, respectively. The auxiliary capacitance line 11b and the signal line lead line 11c are formed (scanning line forming step).
- a silicon nitride film (having a thickness of about 400 nm and a relative dielectric constant of about 7.0) is formed on the entire substrate on which the scanning wiring 11a, the auxiliary capacitance wiring 11b, and the signal line drawing wiring 11c are formed by the CVD method.
- a gate insulating film 12 an intrinsic amorphous silicon film (thickness of about 50 nm to 200 nm), an n + amorphous silicon film (thickness of about 40 nm), and the like are sequentially laminated, and then an intrinsic amorphous silicon film and an n + amorphous silicon film semiconductor laminated film Is patterned using photolithography to form intrinsic amorphous silicon layers 13a and 13b and n + amorphous silicon layers 14a and 14b as shown in FIG. 4B (semiconductor layer forming step).
- an organic spin-on glass whose main component is made of, for example, polysiloxane or silicone resin is applied to the entire substrate on which the intrinsic amorphous silicon layers 13a and 13b and the n + amorphous silicon layers 14a and 14b are formed by spin coating.
- pre-baking at 150 ° C. for about 5 minutes and post-baking at 350 ° C. for about 1 hour are performed to form the organic SOG film 15s.
- the insulating layer 15 having openings 15a, 15b and 15c and having a relative dielectric constant of about 2.5.
- Insulating layer forming step For the patterning of the organic SOG film 15s, a mixed gas of carbon tetrafluoride and oxygen is used, and the mixing ratio of the gas and the high frequency power are adjusted so that the intrinsic amorphous silicon layer, the n + amorphous silicon layer, and the organic SOG film. The dry etching is performed under the condition that a high selectivity can be obtained.
- a barrier metal layer may be formed in advance on the n + amorphous silicon layer so that the intrinsic amorphous silicon layer and the n + amorphous silicon layer are not damaged.
- an organic SOG material having low heat resistance and photosensitivity may be used as the organic SOG material. In this case, the effect of improving the degree of freedom of material selection of the coating type insulating film in the present invention is effectively achieved, and the steps of photolithography and dry etching can be omitted.
- an aluminum film (thickness of about 200 nm) and a titanium film (thickness of about 100 nm) are sequentially laminated on the entire substrate on which the insulating layer 15 is formed by sputtering, and then the metal laminated film is photolithography.
- the signal wiring 16a, the source electrode 16aa, and the drain electrode 16b composed of two layers of the aluminum layer Sa and the titanium layer Sb are formed as shown in FIG. 6 is formed (signal wiring forming step). Further, as shown in FIG.
- the n + amorphous silicon layers 14a and 14b exposed from the source electrode 16aa and the drain electrode 16b and the upper layer portions of the underlying intrinsic amorphous silicon layers 13a and 13b are dry-etched.
- the TFT 5 is formed by forming the semiconductor layer 4a composed of the intrinsic amorphous silicon layer 13aa and the n + amorphous silicon layer 14aa and the semiconductor layer 4b composed of the intrinsic amorphous silicon layer 13ba and the n + amorphous silicon layer 14ba. To do.
- a silicon nitride film (thickness of about 150 nm to 700 nm) is deposited on the entire substrate on which the TFT 5 and the auxiliary capacitor 6 are formed by the CVD method, and as shown in FIG. A film 17 is formed.
- a photosensitive organic insulating film is applied to a thickness of about 1.0 ⁇ m to 3.0 ⁇ m by spin coating on the entire substrate on which the inorganic insulating film 17 is formed, and then the applied film is exposed and developed.
- the organic insulating layer 18 having the contact holes 18a and 18b is formed.
- the inorganic insulating film 17 exposed from the organic insulating layer 18 is removed by dry etching, thereby forming an inorganic insulating layer 17a as shown in FIG.
- the interlayer insulating film that electrically insulates the TFT 5 and the pixel electrode 19a a two-layered film of the inorganic insulating layer 17a and the organic insulating layer 18 is illustrated, but the inorganic insulating layer 17a or the organic insulating layer is exemplified.
- a single layer film of the layer 18 may be used.
- a transparent conductive film such as an ITO (Indium Tin Oxide) film (thickness of about 100 nm) by sputtering on the entire substrate on which the inorganic insulating layer 17a is formed.
- a transparent conductive film such as an ITO (Indium Tin Oxide) film (thickness of about 100 nm)
- the active matrix substrate 20a can be manufactured.
- a photosensitive resin colored in black for example, is applied to the entire substrate of the insulating substrate 10b such as a glass substrate by spin coating, and then the coated film is exposed and developed, thereby obtaining FIG. 6 (a). As shown, the black matrix 21 is formed to a thickness of about 1.0 ⁇ m.
- a photosensitive resin colored in red, green or blue for example, is applied to the entire substrate on which the black matrix 21 is formed by spin coating, and then the applied film is exposed and developed.
- a colored layer 22 for example, a red layer
- the other two colors to form the other two colored layers 22 (for example, a green layer and a blue layer) with a thickness of about 2.0 ⁇ m.
- the common electrode 23 has a thickness as shown in FIG. It is formed to have a thickness of about 50 nm to 200 nm.
- a photosensitive resin is applied to the entire substrate on which the common electrode 23 is formed by spin coating, and then the applied film is exposed and developed to obtain a photo spacer as shown in FIG. 24 is formed to a thickness of about 4 ⁇ m.
- the counter substrate 30 can be manufactured as described above.
- a polyimide resin film is applied to each surface of the active matrix substrate 20a manufactured in the active matrix substrate manufacturing process and the counter substrate 30 manufactured in the counter substrate manufacturing process by a printing method, and then the coating film is applied.
- An alignment film is formed by performing baking and rubbing treatment on the substrate.
- a sealing material made of UV (ultraviolet) curing and thermosetting resin is printed on the surface of the counter substrate 30 on which the alignment film is formed in a frame shape, a liquid crystal material is formed inside the sealing material. Is dripped.
- the bonded bonded body is released to atmospheric pressure. The surface and the back surface of the bonded body are pressurized.
- the bonded body in which the sealing material is cured is divided by, for example, dicing, and unnecessary portions thereof are removed. Then, the gate side TCP 41 and the source side TCP 42 are provided in the terminal region T of the active matrix substrate 20a. Implement.
- the liquid crystal display device 50 of the present embodiment can be manufactured.
- the intrinsic amorphous silicon layer 13a and the n + amorphous silicon are formed on the gate insulating film 12 using the CVD method in the semiconductor layer forming step.
- the coating type is arranged between each scanning wiring 11a formed in the scanning wiring forming step and each signal wiring 16a formed later in the signal wiring forming step. Since the insulating layer 15 is formed, the coating-type organic SOG film 15s for forming the coating-type insulating layer 15 does not need to have a heat resistance of 300 ° C. or higher that can withstand a CVD process, for example.
- an organic SOG material having low heat resistance can be used as a coating-type insulating film, so that it is used to reduce the capacitance at the intersection of each scanning wiring 11a and each signal wiring 16a in the active matrix substrate 20a.
- the degree of freedom in selecting the material for the coating type insulating film can be improved.
- each TFT 5 the relatively thick coating type insulating layer 15 is not disposed between the semiconductor layer 4a and the gate electrode (11a) due to the opening 15a.
- the semiconductor layer 4a and the gate electrode (11a) are electrically insulated via the relatively thin gate insulating film 12, the TFT 5 with low power consumption can be configured.
- the relatively thick coating type insulating layer 15 is disposed between the auxiliary capacitance line 11b and the drain electrode 16b constituting the auxiliary capacitance 6 through the opening 15b.
- the auxiliary capacitance line 11b and the drain electrode 16b are electrically insulated via the relatively thin gate insulating film 12, the large-capacity auxiliary capacitance 6 can be configured.
- the coating type organic SOG film 15s when the coating type organic SOG film 15s is baked, the surface of the gate electrode (11a) is covered with the gate insulating film 12, so that the baking is performed.
- the gate electrode (11a) is protected from heat in the atmosphere, corrosive gas (for example, oxygen), and the like (for example, aluminum, copper, or an alloy thereof) that can be easily oxidized can be used for the gate electrode (11a).
- Embodiment 2 of the Invention 7 to 9 show Embodiment 2 of the active matrix substrate and the manufacturing method thereof according to the present invention. Specifically, FIG. 7 to FIG. 9 are explanatory views showing in cross section the manufacturing process of the active matrix substrate 20b of the present embodiment. In the following embodiments, the same portions as those in FIGS. 1 to 6 are denoted by the same reference numerals, and detailed description thereof is omitted.
- a method for manufacturing an active matrix substrate using a total of six photomasks is exemplified.
- a method for manufacturing an active matrix substrate using a total of five photomasks is illustrated. To do.
- the gate insulating film 12 of the first embodiment is patterned to form gate insulating films 12a, 12b, and 12c. It is substantially the same as the active matrix substrate 20a.
- the gate insulating films 12a, 12b, and 12c are provided so as to cover the upper surfaces of the scanning wiring 11a, the auxiliary capacitance wiring 11b, and the signal line leading wiring 11c, respectively.
- the scanning line 11a, the auxiliary capacity line 11b, and the signal line lead line 11c are stacked on the scan line 11a, the auxiliary capacity line 11b, and the signal line lead line 11c so as to protrude laterally from the scanning line 11a.
- a titanium film Ga (thickness of about 50 nm), an aluminum film Gb (thickness of about 200 nm), and an aluminum substrate Gb are formed on the entire substrate of the insulating substrate 10a such as a glass substrate by sputtering.
- the titanium film Gc (thickness of about 150 nm) and the like are sequentially stacked to form the metal laminated film 11
- an inorganic material such as a silicon nitride film (thickness of about 400 nm, relative dielectric constant of about 7.0) is formed by CVD.
- an intrinsic amorphous silicon film 13 thickness of about 50 nm to 200 nm
- an n + amorphous silicon film 14 thickness of about 40 nm
- the photosensitive resin film R is formed on the entire substrate on which the n + amorphous silicon film 14 is formed by spin coating, for example, by applying a resist material to about 2 ⁇ m
- the photosensitive resin film R is half-coated.
- the semiconductor layer 4a overlaps with the portions that become the scanning wiring 11a, the auxiliary capacitance wiring 11b, and the signal line lead-out wiring 11c.
- the resist pattern Ra is formed so that the portion to be relatively thick (for example, about 2 ⁇ m and the relatively thin portion is about 1 ⁇ m).
- the halftone photomask (which can be exposed) has a transmissive part, a light-shielding part, and a semi-transmissive part made of a semi-transmissive film capable of intermediate exposure, and the transmissive part, the light-shielding part and the semi-transmissive part.
- the portion is configured to expose the photosensitive resin at three exposure levels of a completely exposed portion, an unexposed portion, and an intermediate exposed portion.
- a gray-tone photomask in which the semi-transmissive portion is configured by a plurality of slits may be used.
- n + amorphous silicon film 14 exposed from the resist pattern Ra, the underlying intrinsic amorphous silicon film 13 and the inorganic insulating film 12 are removed by using, for example, dry etching, as shown in FIG. Then, gate insulating films 12a, 12b and 12c, intrinsic amorphous silicon layers 13a and 13b, and n + amorphous silicon films 14a and 14b are formed (gate insulating film forming step).
- the resist pattern Ra is thinned by ashing with oxygen gas plasma, whereby the resist pattern Ra is transformed into the resist pattern Rb, and then the n + amorphous silicon film 14a exposed from the resist pattern Rb.
- 14b and the underlying intrinsic amorphous silicon layers 13a and 13b are etched to form intrinsic amorphous silicon layers 13ab and 13bb and n + amorphous silicon films 14ab and 14bb, as shown in FIG. (Semiconductor layer forming step).
- the metal laminated film 11 exposed from the gate insulating films 12a, 12b, and 12c is removed by wet etching, so that the scanning wiring 11a, the auxiliary capacitance wiring 11b, and the signal line as shown in FIG.
- the lead wiring 11c is formed (scanning wiring forming step).
- an organic spin-on glass (SOG) material (15 s) composed mainly of polysiloxane and silicone resin is applied to the entire substrate on which the scanning wiring 11a, the auxiliary capacitance wiring 11b, and the signal line drawing wiring 11c are formed by spin coating.
- SOG organic spin-on glass
- a thickness of about 1.5 ⁇ m followed by pre-baking at 150 ° C. for about 5 minutes and post-baking at 350 ° C. for about 1 hour to form the organic SOG film 15s. Thereafter, by patterning the organic SOG film 15s using photolithography, as shown in FIG. 8B, the insulating layer 15 having openings 15a, 15b and 15c and having a relative dielectric constant of about 2.5.
- an aluminum film (thickness of about 200 nm) and a titanium film (thickness of about 100 nm) are sequentially laminated on the entire substrate on which the insulating layer 15 is formed by sputtering, and then the metal laminated film is photolithography.
- the signal wiring 16a, the source electrode 16aa, and the drain electrode 16b composed of two layers of the aluminum layer Sa and the titanium layer Sb are formed as shown in FIG. 6 is formed (signal wiring forming step). Further, as shown in FIG.
- the n + amorphous silicon layers 14ab and 14bb exposed from the source electrode 16aa and the drain electrode 16b and the upper layers of the underlying intrinsic amorphous silicon layers 13ab and 13bb are dry-etched.
- the TFT 5 is formed by forming the semiconductor layer 4a composed of the intrinsic amorphous silicon layer 13aa and the n + amorphous silicon layer 14aa and the semiconductor layer 4b composed of the intrinsic amorphous silicon layer 13ba and the n + amorphous silicon layer 14ba. To do.
- a silicon nitride film (thickness of about 150 nm to 700 nm) is deposited on the entire substrate on which the TFT 5 and the auxiliary capacitor 6 are formed by the CVD method, and as shown in FIG. A film 17 is formed.
- a photosensitive organic insulating film is applied to a thickness of about 1.0 ⁇ m to 3.0 ⁇ m by spin coating on the entire substrate on which the inorganic insulating film 17 is formed, and then the applied film is exposed and developed. As a result, as shown in FIG. 9B, an organic insulating layer 18 having contact holes 18a and 18b is formed.
- the inorganic insulating film 17 exposed from the organic insulating layer 18 is removed by dry etching, thereby forming an inorganic insulating layer 17a as shown in FIG. 9C.
- the transparent conductive film such as an ITO film (thickness of about 100 nm), for example, by sputtering on the entire substrate on which the inorganic insulating layer 17a is formed, the transparent conductive film is patterned using photolithography. As a result, as shown in FIG. 9D, the pixel electrode 19a and the transparent conductive layer 19b are formed.
- the active matrix substrate 20b can be manufactured as described above.
- the CVD method is used on the gate insulating film 12a formed in the gate insulating film forming process in the semiconductor layer forming process.
- the semiconductor layers of the intrinsic amorphous silicon layer 13a and the n + amorphous silicon layer 14a After forming the semiconductor layers of the intrinsic amorphous silicon layer 13a and the n + amorphous silicon layer 14a, in the insulating layer forming process, each scanning wiring 11a formed in the scanning wiring forming process and each signal wiring forming process formed later. Since the coating type insulating layer 15 is formed between the signal wiring 16a and the coating type organic SOG film 15s for forming the coating type insulating layer 15, for example, at 300 ° C. or higher that can withstand the CVD process. It is not necessary to have the heat resistance.
- an organic SOG material having low heat resistance can be used as a coating-type insulating film, so that it is used to reduce the capacitance at the intersection of each scanning wiring 11a and each signal wiring 16a in the active matrix substrate 20b.
- the degree of freedom in selecting the material for the coating type insulating film can be improved. Note that, according to the manufacturing method of the active matrix substrate 20b of the present embodiment, the first photomask capable of halftone exposure in the gate insulating film forming step is used, and the second photomask in the insulating layer forming step.
- the third photomask is used in the signal wiring forming step
- the fourth photomask is used in the interlayer insulating film forming step
- the fifth photomask is used in the pixel electrode forming step.
- the active matrix substrate can be manufactured using a total of five photomasks, and the manufacturing cost can be reduced as compared with the manufacturing method of the active matrix substrate of the first embodiment.
- the gate insulating film 12a protrudes from the scanning wiring 11a, is formed in an overhang state, and is coated so as to cover the protruding portion of the gate insulating film 12a. 15 is provided, it is possible to suppress the occurrence of the disconnection of the signal wiring 16a and the short circuit between the scanning wiring 11a and the signal wiring 16a due to the overhang of the gate insulating film 12a.
- FIG. 10 is an explanatory view showing in cross section the manufacturing process of the active matrix substrate 20c of this embodiment.
- the active matrix substrate in which the color filter is provided on the counter substrate is illustrated.
- a matrix substrate is illustrated.
- the black matrix 7a and the colored layer 7b instead of the organic insulating layer 18 (see FIG. 5D) of the active matrix substrate 20a of the first embodiment, the black matrix 7a and the colored layer 7b, An inorganic insulating layer 8 and a photo spacer 9 are provided to cover them, and the other configuration is substantially the same as that of the active matrix substrate 20a.
- the signal wiring forming process in the active matrix substrate manufacturing process of the first embodiment is performed, and the entire substrate on which the TFT 5, the auxiliary capacitor 6, and the inorganic insulating film 17 are formed is colored, for example, black by spin coating. After the photosensitive resin is applied, the coating film is exposed and developed to form a black matrix 7a having a thickness of about 1.0 ⁇ m as shown in FIG.
- a photosensitive resin colored in red, green or blue for example, by spin coating on the entire substrate on which the black matrix 7a is formed, the coating film is exposed and developed, whereby As shown in FIG. 10A, a colored layer 7b (for example, a red layer) of a selected color is formed to a thickness of about 2.0 ⁇ m.
- a colored layer 7b for example, a red layer
- the other two colors for example, a green layer and a blue layer
- the inorganic insulating layer 8 having a contact hole is formed as a protective layer for the colored layer by patterning the inorganic insulating film using photolithography and dry etching.
- the transparent conductive film is patterned using photolithography.
- the pixel electrode 19a and the transparent conductive layer 19b are formed.
- the photo spacer 9 is formed to a thickness of about 4 ⁇ m.
- the active matrix substrate 20c can be manufactured as described above.
- a transparent conductive film such as an ITO film is formed to a thickness of about 50 nm to 200 nm by sputtering on the entire insulating substrate such as a glass substrate. It can be manufactured by depositing.
- the active matrix substrate 20c and the manufacturing method thereof of the present embodiment after forming the semiconductor layers of the intrinsic amorphous silicon layer 13a and the n + amorphous silicon layer 14a, as in the above embodiments, since the coating-type insulating layer 15 is formed, in the active matrix substrate 20c, the degree of freedom in selecting the material of the coating-type insulating film used for reducing the capacitance at the intersection between each scanning wiring 11a and each signal wiring 16a is increased. Can be improved.
- the color filter on array structure is applied to the active matrix substrate 20a of the first embodiment.
- the color filter on array structure is applied to the active matrix substrate 20b of the second embodiment. Also good.
- FIG. 11 is a plan view showing a display unit of the active matrix substrate 20d of this embodiment
- FIG. 12 is a plan view showing a wiring switching unit of the active matrix substrate 20d
- FIG. 13 is a cross-sectional view illustrating the manufacturing process of the active matrix substrate 20d.
- an active matrix substrate provided with an organic material layer such as the organic insulating layer 18 and the colored layer 7 as the lower layer of the pixel electrode is illustrated.
- an organic material layer is used as the lower layer of the pixel electrode.
- An active matrix substrate that is not disposed is illustrated.
- the drain electrode 16c is connected to the pixel electrode 19c through the contact hole 17ca formed in the inorganic insulating layer 17b as shown in FIGS. Since the storage capacitor 6 does not overlap with the storage capacitor 11b, the storage capacitor 6 includes the storage capacitor wiring 11b and the pixel electrode 19c, and the gate insulating film 12 and the inorganic insulating layer 17b disposed therebetween.
- the active matrix substrate 20a is substantially the same. As shown in FIGS. 12 and 13D, the transparent conductive layer 19b is connected to the signal wiring 16a and the signal line lead wiring 11c through a contact hole 17cb formed in the inorganic insulating layer 17b. .
- an insulating layer forming step in the active matrix substrate manufacturing step of the first embodiment is performed, and an aluminum film (thickness of about 200 nm) and a titanium film (with a thickness of about 200 nm) and a titanium film (with a thickness of about 200 nm) are formed on the entire substrate on which the insulating layer 15 is formed. And the like, and then, by laminating the metal laminated film using photolithography, as shown in FIG. 13A, the aluminum layer Sa and the titanium layer Sb are respectively formed. The signal wiring 16a, the source electrode 16aa, and the drain electrode 16c are formed (signal wiring forming step). Further, as shown in FIG.
- the n + amorphous silicon layers 14a and 14b exposed from the source electrode 16aa and the drain electrode 16c and upper layers of the underlying intrinsic amorphous silicon layers 13a and 13b are dry-etched.
- the semiconductor layer 4a composed of the intrinsic amorphous silicon layer 13aa and the n + amorphous silicon layer 14aa and the semiconductor layer 4b composed of the intrinsic amorphous silicon layer 13ba and the n + amorphous silicon layer 14ba are formed, and the TFT 5 is formed.
- a silicon nitride film (thickness of about 150 nm to 700 nm) is deposited on the entire substrate on which the TFT 5 is formed by a CVD method to form an inorganic insulating film 17 as shown in FIG. To do.
- the inorganic insulating layer 17b is formed by patterning the inorganic insulating film 17 using photolithography and dry etching.
- the transparent conductive film is patterned using photolithography. As a result, as shown in FIG. 13D, the pixel electrode 19c and the transparent conductive layer 19b are formed, and the auxiliary capacitor 6 is formed.
- the active matrix substrate 20d can be manufactured as described above.
- the active matrix substrate 20d and the manufacturing method thereof of the present embodiment after forming the semiconductor layers of the intrinsic amorphous silicon layer 13a and the n + amorphous silicon layer 14a, as in the above embodiments, since the coating-type insulating layer 15 is formed, in the active matrix substrate 20d, the degree of freedom in selecting the material of the coating-type insulating film used to reduce the capacitance at the intersection between each scanning wiring 11a and each signal wiring 16a is increased. Can be improved.
- the active matrix substrate 20a of the first embodiment a modification in which a structure in which the lower layer of the pixel electrode is an inorganic insulating layer is applied to the active matrix substrate 20a of the first embodiment is described.
- the active matrix substrate 20b of the second embodiment is applied to the active matrix substrate 20b.
- a structure in which the lower layer of the pixel electrode is an inorganic insulating layer may be applied.
- the scan wiring 11a is exemplified by a layered structure of titanium layer / aluminum layer / titanium layer, but the intermediate metal layer may be a copper layer, an aluminum alloy layer, or the like.
- the upper and lower metal layers may be a molybdenum layer, a molybdenum / titanium alloy layer, or the like.
- the signal wiring 16a is exemplified by a laminated structure of an aluminum layer / titanium layer, but the upper metal layer may be a copper layer, an aluminum alloy layer, or the like, and the lower layer metal The layer may be a molybdenum layer, a molybdenum / titanium alloy layer, or the like.
- an active matrix substrate using an amorphous silicon semiconductor layer has been illustrated.
- the present invention uses an oxide semiconductor layer such as ZnO or IGZO (In—Ga—Zn—O).
- the present invention can also be applied to an active matrix substrate.
- a liquid crystal display device including an active matrix substrate has been exemplified as the display device.
- the present invention includes an organic EL (Electro-Luminescence) display device, an inorganic EL display device, an electrophoretic display device, and the like.
- the present invention can also be applied to other display devices.
- an active matrix substrate in which the electrode of the TFT connected to the pixel electrode is used as the drain electrode is illustrated.
- the present invention is an active matrix in which the electrode of the TFT connected to the pixel electrode is referred to as a source electrode. It can also be applied to a substrate.
- the present invention can improve the degree of freedom in selecting the material of the coating type insulating film used for reducing the capacitance at the intersection between each scanning wiring and each signal wiring.
- the present invention is useful for an active matrix substrate used for a large-sized liquid crystal television capable of displaying a high-definition image at a rate.
- R photosensitive resin film Ra first resist pattern Rb second resist pattern 4a semiconductor layer 5 TFT 10a Insulating substrate 11 Metal laminated film (metal film) 11a Scanning wiring (gate electrode) 11b Auxiliary capacity wiring 12, 12a Gate insulating film (inorganic insulating film) 13 Intrinsic amorphous silicon film (semiconductor film) 14 n + amorphous silicon film (semiconductor film) 15 Insulating layer 15a, 15b Opening 15s Organic SOG film (spin-on glass material) 16a signal wiring 16aa source electrode 16b drain electrodes 20a to 20d active matrix substrate
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Abstract
Description
図1~図6は、本発明に係るアクティブマトリクス基板及びその製造方法の実施形態1を示している。具体的に、図1は、本実施形態のアクティブマトリクス基板20aを備えた液晶表示装置50を示す斜視図である。また、図2は、アクティブマトリクス基板20aの表示部、すなわち、画像の最小単位である各画素を示す平面図であり、図3は、アクティブマトリクス基板20aの配線切り替え部を示す平面図である。さらに、図4及び図5は、アクティブマトリクス基板20aの製造工程を断面で示す説明図であり、図6は、アクティブマトリクス基板20aに対向して配置される対向基板30の製造工程を断面で示す説明図である。なお、図5(d)は、アクティブマトリクス基板20aの断面図に相当し、領域Aが図2中のA-A線に沿った断面を示し、領域Bが図2中のB-B線に沿った断面を示し、領域Cが図3中のC-C線に沿った断面を示している。
まず、ガラス基板などの絶縁基板10aの基板全体に、スパッタリング法により、例えば、チタン膜(厚さ50nm程度)、アルミニウム膜(厚さ200nm程度)及びチタン膜(厚さ150nm程度)などを順に積層した後に、その金属積層膜をフォトリソグラフィーを用いてパターニングすることにより、図4(a)に示すように、それぞれ、チタン層Ga、アルミニウム層Gb及びチタン層Gcの3層からなる走査配線11a、補助容量配線11b及び信号線引出配線11cを形成する(走査配線形成工程)。
まず、ガラス基板などの絶縁基板10bの基板全体に、スピンコート法により、例えば、黒色に着色された感光性樹脂を塗布した後に、その塗布膜を露光及び現像することにより、図6(a)に示すように、ブラックマトリクス21を厚さ1.0μm程度に形成する。
まず、上記アクティブマトリクス基板作製工程で作製されたアクティブマトリクス基板20a、及び上記対向基板作製工程で作製された対向基板30の各表面に、印刷法によりポリイミドの樹脂膜を塗布した後に、その塗布膜に対して焼成及びラビング処理を行うことにより、配向膜を形成する。
図7~図9は、本発明に係るアクティブマトリクス基板及びその製造方法の実施形態2を示している。具体的に、図7~図9は、本実施形態のアクティブマトリクス基板20bの製造工程を断面で示す説明図である。なお、以下の各実施形態において、図1~図6と同じ部分については同じ符号を付して、その詳細な説明を省略する。
図10は、本実施形態のアクティブマトリクス基板20cの製造工程を断面で示す説明図である。
図11~図13は、本発明に係るアクティブマトリクス基板及びその製造方法の実施形態4を示している。具体的に、図11は、本実施形態のアクティブマトリクス基板20dの表示部を示す平面図であり、図12は、アクティブマトリクス基板20dの配線切り替え部を示す平面図である。また、図13は、アクティブマトリクス基板20dの製造工程を断面で示す説明図である。
Ra 第1レジストパターン
Rb 第2レジストパターン
4a 半導体層
5 TFT
10a 絶縁基板
11 金属積層膜(金属膜)
11a 走査配線(ゲート電極)
11b 補助容量配線
12,12a ゲート絶縁膜(無機絶縁膜)
13 真性アモルファスシリコン膜(半導体膜)
14 n+アモルファスシリコン膜(半導体膜)
15 絶縁層
15a,15b 開口部
15s 有機SOG膜(スピンオンガラス材料)
16a 信号配線
16aa ソース電極
16b ドレイン電極
20a~20d アクティブマトリクス基板
Claims (9)
- 互いに平行に延びるように設けられた複数の走査配線と、
上記各走査配線と交差する方向に互いに平行に延びるように設けられた複数の信号配線と、
上記各走査配線と上記各信号配線との交差部分毎にそれぞれ設けられ、各々、半導体層、並びに該半導体層上に上記各信号配線と同一層に形成されたソース電極及びドレイン電極を有する複数の薄膜トランジスタと、
上記各走査配線と上記各信号配線との間に設けられた塗布型の絶縁層とを備えたアクティブマトリクス基板であって、
上記絶縁層には、上記各半導体層が露出するように複数の開口部が形成され、
上記絶縁層の各開口部の周端の少なくとも一部は、上記各半導体層の周端よりも内側に配置されていることを特徴とするアクティブマトリクス基板。 - 請求項1に記載されたアクティブマトリクス基板において、
上記各薄膜トランジスタは、上記各走査配線と同一層に形成されたゲート電極を有し、
上記各半導体層及び各ゲート電極は、ゲート絶縁膜を介して電気的に絶縁されていることを特徴とするアクティブマトリクス基板。 - 請求項2に記載されたアクティブマトリクス基板において、
上記ゲート絶縁膜は、上記各走査配線の上面を覆うと共に互いに平行に延びるように複数設けられていることを特徴とするアクティブマトリクス基板。 - 請求項3に記載されたアクティブマトリクス基板において、
上記各ゲート絶縁膜の少なくとも一方の側端部は、上記各走査配線から突出していることを特徴とするアクティブマトリクス基板。 - 請求項1乃至4の何れか1つに記載されたアクティブマトリクス基板において、
上記各走査配線の間には、該各走査配線に沿って延びるように補助容量配線が設けられ、
上記絶縁層には、上記各補助容量配線と重なるように複数の開口部が形成され、
上記各補助容量配線及び各ドレイン電極は、ゲート絶縁膜を介して電気的に絶縁されていることを特徴とするアクティブマトリクス基板。 - 請求項1乃至5の何れか1つに記載されたアクティブマトリクス基板において、
上記絶縁層は、有機スピンオンガラス材料により構成されていることを特徴とするアクティブマトリクス基板。 - 請求項1乃至6の何れか1つに記載されたアクティブマトリクス基板において、
上記各半導体層は、酸化物半導体により構成されていることを特徴とするアクティブマトリクス基板。 - 互いに平行に延びるように設けられた複数の走査配線と、
上記各走査配線と交差する方向に互いに平行に延びるように設けられた複数の信号配線と、
上記各走査配線と上記各信号配線との交差部分毎にそれぞれ設けられ、各々、半導体層を有する複数の薄膜トランジスタと、
上記各走査配線と上記各信号配線との間に設けられた塗布型の絶縁層とを備えたアクティブマトリクス基板を製造する方法であって、
絶縁基板上に上記各走査配線を形成する走査配線形成工程と、
上記各走査配線を覆うようにゲート絶縁膜を形成した後に、該ゲート絶縁膜上に上記各半導体層を形成する半導体層形成工程と、
上記各半導体層が形成された絶縁基板を覆うようにスピンオンガラス材料を塗布及びベーキングした後に、該スピンオンガラス材料を上記各半導体層が露出するようにパターニングして、上記絶縁層を形成する絶縁層形成工程と、
上記絶縁層上に上記各信号配線を形成すると共に、上記各半導体層上に互いに対峙するようにソース電極及びドレイン電極を形成する信号配線形成工程とを備えることを特徴とするアクティブマトリクス基板の製造方法。 - 互いに平行に延びるように設けられた複数の走査配線と、
上記各走査配線と交差する方向に互いに平行に延びるように設けられた複数の信号配線と、
上記各走査配線と上記各信号配線との交差部分毎にそれぞれ設けられ、各々、半導体層を有する複数の薄膜トランジスタと、
上記各走査配線と上記各信号配線との間に設けられた塗布型の絶縁層とを備えたアクティブマトリクス基板を製造する方法であって、
絶縁基板上に、金属膜、無機絶縁膜、半導体膜及び感光性樹脂膜を順に積層し、該感光性樹脂膜をハーフトーンで露光することにより、上記半導体膜上に上記各走査配線となる部分に重なると共に上記各半導体層となる部分が相対的に厚くなるようにレジストパターンを形成した後に、該レジストパターンから露出する上記半導体膜及び該半導体膜の下層の無機絶縁膜をエッチングして、ゲート絶縁膜を形成するゲート絶縁膜形成工程と、
上記レジストパターンを薄肉化することにより該レジストパターンから露出させた上記半導体膜をエッチングして、上記各半導体層を形成する半導体層形成工程と、
上記ゲート絶縁膜から露出する上記金属膜をエッチングして、上記各走査配線を形成する走査配線形成工程と、
上記各走査配線が形成された絶縁基板を覆うようにスピンオンガラス材料を塗布及びベーキングした後に、該スピンオンガラス材料を上記各半導体層が露出するようにパターニングして、絶縁層を形成する絶縁層形成工程と、
上記絶縁層上に上記各信号配線を形成すると共に、上記各半導体層上に互いに対峙するようにソース電極及びドレイン電極を形成する信号配線形成工程とを備えることを特徴とするアクティブマトリクス基板の製造方法。
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WO2013008441A1 (ja) * | 2011-07-12 | 2013-01-17 | シャープ株式会社 | アクティブマトリクス基板及びその製造方法 |
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TW201341916A (zh) * | 2012-04-12 | 2013-10-16 | Innocom Tech Shenzhen Co Ltd | 畫素結構及應用其之液晶顯示結構 |
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JP2016085399A (ja) * | 2014-10-28 | 2016-05-19 | 株式会社ジャパンディスプレイ | 液晶表示装置 |
CN104795400B (zh) * | 2015-02-12 | 2018-10-30 | 合肥鑫晟光电科技有限公司 | 阵列基板制造方法、阵列基板和显示装置 |
US9490282B2 (en) * | 2015-03-19 | 2016-11-08 | Omnivision Technologies, Inc. | Photosensitive capacitor pixel for image sensor |
CN110741428B (zh) * | 2018-02-28 | 2021-12-21 | 京瓷株式会社 | 显示装置、玻璃基板及玻璃基板的制造方法 |
CN112054031B (zh) * | 2019-06-06 | 2023-06-27 | 夏普株式会社 | 有源矩阵基板及其制造方法 |
KR20210126839A (ko) * | 2020-04-10 | 2021-10-21 | 삼성디스플레이 주식회사 | 표시장치 및 이의 제조방법 |
KR20210148534A (ko) * | 2020-05-29 | 2021-12-08 | 삼성디스플레이 주식회사 | 표시 장치 |
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WO2013008441A1 (ja) * | 2011-07-12 | 2013-01-17 | シャープ株式会社 | アクティブマトリクス基板及びその製造方法 |
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Also Published As
Publication number | Publication date |
---|---|
EP2521180A4 (en) | 2014-06-25 |
US8729612B2 (en) | 2014-05-20 |
CN102656698B (zh) | 2015-06-17 |
JPWO2011080879A1 (ja) | 2013-05-09 |
JP5528475B2 (ja) | 2014-06-25 |
EP2521180A1 (en) | 2012-11-07 |
CN102656698A (zh) | 2012-09-05 |
US20120248443A1 (en) | 2012-10-04 |
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