WO2011026393A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2011026393A1
WO2011026393A1 PCT/CN2010/076093 CN2010076093W WO2011026393A1 WO 2011026393 A1 WO2011026393 A1 WO 2011026393A1 CN 2010076093 W CN2010076093 W CN 2010076093W WO 2011026393 A1 WO2011026393 A1 WO 2011026393A1
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Prior art keywords
drain
source
gate
fingers
semiconductor device
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PCT/CN2010/076093
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English (en)
French (fr)
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张乃千
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Zhang Naiqian
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Priority to EP10813315.8A priority Critical patent/EP2477228A4/en
Priority to US13/499,558 priority patent/US8637905B2/en
Publication of WO2011026393A1 publication Critical patent/WO2011026393A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention relates to a group III nitride semiconductor device and a method of fabricating the same, and, in particular, to a novel layout design, which is advantageous for improving a breakdown voltage of a group III nitride semiconductor device while effectively utilizing a device space on the wafer. Especially suitable for high voltage and high current devices. Background technique
  • the dielectric breakdown field of the third-generation semiconductor gallium nitride is much higher than that of the first-generation semiconductor silicon (Si) or the second-generation semiconductor gallium arsenide (GaAs), up to 3 MV/cm, making it affordable for electronic devices. Very high voltage.
  • gallium nitride can form a heterojunction structure with other gallium-based compound semiconductors (Group III nitride semiconductors). Since the Group III nitride semiconductor has strong spontaneous polarization and piezoelectric polarization effects, a two-dimensional electron gas (2DEG) channel with a very high electron concentration can be formed near the interface of the heterojunction.
  • 2DEG two-dimensional electron gas
  • This heterojunction structure also effectively reduces the scattering of ionized impurities, so the electron mobility in the channel is greatly enhanced.
  • a gallium nitride high electron mobility transistor (HEMT) fabricated on the basis of this heterojunction can conduct high current at a high frequency and has a low on-resistance. These characteristics make GaN ⁇ particularly suitable for the manufacture of high frequency, high power RF devices and high voltage and high current switching devices.
  • gallium nitride Since the electrons in the two-dimensional electron gas channel have a high mobility, the switching rate of the gallium nitride ⁇ is greatly improved with respect to the silicon device. At the same time, the high concentration of two-dimensional electron gas also makes GaN ⁇ have a high current density, which is suitable for the needs of high current power devices.
  • gallium nitride is a wide bandgap semiconductor that can operate at higher temperatures. In high-power environments, silicon devices often require additional cooling devices to ensure proper operation, while GaN does not need this or requires less cooling. Therefore, a gallium nitride power device is advantageous in saving space and cost.
  • FIG. 1 A cross-sectional view of a commonly used device structure of gallium nitride germanium is shown in FIG.
  • the bottom layer is a substrate 94 on which a nucleation layer 95, a buffer layer 96 and an isolation layer 97 are deposited.
  • a two-dimensional electron gas channel is formed near the interface of the buffer layer and the isolation layer.
  • a dielectric layer 98 is deposited over the isolation layer to reduce current collapse at high frequencies.
  • the source 91 and the drain 92 are connected to the two-dimensional electron gas. The flow of electrons in the channel can be controlled.
  • a gate 93 is located between the source and the drain for controlling the number of electrons in the channel, thereby controlling the magnitude of the current.
  • a high voltage is applied between the gate and the drain, and a strong electric field is concentrated in a space charge region near the gate.
  • the peak electric field is greater than the breakdown electric field of the material, the performance of the transistor is severely affected, and even breakdown occurs.
  • the control of the peak electric field is more stringent because it often operates at high voltages (and possibly even in kilovolts).
  • Many research institutes have proposed a number of schemes for reducing the peak electric field, which involve various improvements from the epitaxial structure of the wafer and the structure of the device. For example, the field plate structure and the floating gate structure can make the electric field distribution more uniform. For details of the field plate structure, see Chinese Patent Application Publication Nos.
  • Patent Documents 1 and 2 which are hereafter referred to as Patent Documents 1 and 2, respectively, the entire contents of which are hereby incorporated by reference.
  • Patent Document 3 For a specific detail of the floating gate structure, see Chinese Patent Application Publication No. CN101320751A, hereinafter referred to as Patent Document 3, the entire contents of which are hereby incorporated by reference.
  • the present invention provides another solution from the perspective of layout design to achieve the purpose of reducing the peak electric field and enhancing the breakdown voltage of the device.
  • the layout of conventional GaN transistors mostly uses a linear gate and drain structure, as shown in Figure 2.
  • Fig. 2 due to the termination of the gate electrode 13, the potential changes at the two end portions 13A of the gate electrode 13 are intense, and the electric field is concentrated. Therefore, the electric field at the end portion 13A of the gate electrode 13 is much larger than the electric field at the intermediate portion of the gate electrode 13, and device breakdown also occurs at the end portion 13A of the gate electrode 13.
  • the present invention provides a semiconductor device and a method of fabricating the same.
  • a semiconductor device comprising: a semiconductor layer on a substrate; an isolation layer on the semiconductor layer; a source and a drain in contact with the semiconductor layer, the source and the drain
  • Each of the poles includes a plurality of fingers, and the plurality of fingers of the source and the plurality of fingers of the drain intersect with each other; and a gate on the isolation layer, the gate is located at the source and A closed loop structure between the drains and including the plurality of fingers surrounding the source and drain electrodes is included.
  • the gate is located between the source and the drain and surrounds the source and the drain A plurality of fingers of the pole can therefore significantly increase the total length of the gates per unit area. Since the current density of the device is not affected by the layout design, the maximum carrying current per unit area is greatly increased when the total length of the gates per unit area is significantly increased. At the same time, since the gate includes a closed-loop structure, there is no beginning or end, so that the gate has no starting point and end point, which can effectively avoid the phenomenon of tip discharge and increase the breakdown voltage of the device.
  • the gate is an open-loop structure, at the start and end points of the gate, the power line is too dense at the start and end points of the gate due to the effect of the tip discharge, thereby generating a strong electric field. Further, by forming the source and the drain into a nesting structure that intersect each other, the area of the wafer can be effectively utilized, and the production cost can be reduced.
  • the ends of the gates are directly connected or connected by interconnect lines. More preferably, in the case where the head and the tail of the gate are directly connected, each corner of the gate has an arc structure, and the portions of the source and the drain corresponding to the respective corners also have an arc structure.
  • the gates of the gates are connected by interconnecting lines, a portion of the drain corresponding to the junction of the gate and the interconnecting line is formed in an arc shape, and each corner of the gate is curved.
  • the portions of the source and the drain corresponding to the respective corners described above also adopt an arc structure. More preferably, the tips of the plurality of fingers of the source and the drain have an arcuate structure, and the portion of the gate corresponding to the arcuate structure of the tips of the plurality of fingers also adopts an arc structure.
  • the variation of the gate at the corner is very gentle, unlike the linear gate 13 described above.
  • the shape of the tip at the end 13A changes so sharply. Since the shape of the gate in the curved structure changes very gently, there is no sharp shape change, so there is no case where the power line is very dense at some tips, and there is no tip discharge due to sharp edges. Since the electric field distribution is relatively uniform at these arcuate corner positions, there is no tip at the end position of the linear gate, so the tip discharge phenomenon is also avoided, the electric field at the corner of the gate is effectively reduced, and the breakdown voltage of the device is increased. .
  • the source and gate lead pads (also referred to as a lead pad) is located on one side, and the lead pad of the above drain is on the other side.
  • the drain pad of the drain is located on the other side, and device damage caused by high voltage between the gate and the drain can be avoided. This is because there is a large voltage difference between the source and the drain (possibly thousands of volts) between the gate and the drain, and the voltage difference between the source and the gate is relatively small. If the gate and drain are on the same side, high voltages between the gate and drain may result in degradation of device performance or device breakdown.
  • the lengths of the plurality of fingers of the source and the drain are different.
  • the invention does not limit the number and length of fingers of the source and drain. By making the lengths of the fingers of the source and drain different, there will be enough space in some areas of the source and drain to place the lead pads of the source and the drain pads of the drain, thereby eliminating the need for Lead pads are placed in areas other than the source and drain, and an interconnect or air bridge is taken from the source and drain to connect to the lead pads. Therefore, the space of the wafer can be saved and the production cost can be reduced.
  • a method for fabricating a semiconductor device comprising the steps of: depositing a semiconductor layer on a substrate; depositing an isolation layer on the semiconductor layer; forming a source in contact with the semiconductor layer And a drain, wherein each of the source and the drain includes a plurality of fingers, and the plurality of fingers of the source and the plurality of fingers of the drain cross each other; and on the isolation layer, at the source and Between the drains, a gate including a closed loop structure of the plurality of fingers surrounding the source and drain is formed.
  • Figure 1 shows a cross-sectional view of a device structure of a conventional gallium nitride HEMT.
  • Fig. 2 is a view showing the electric field distribution in the layout structure of a conventional gallium nitride HEMT using a linear gate.
  • FIG. 3A illustrates a layout structure of a semiconductor device in accordance with an embodiment of the present invention
  • FIG. 3B is an enlarged view of one finger of the drain and the gate at the corresponding position in FIG. 3A.
  • Fig. 4 is a cross-sectional view taken along line A-A of the layout structure of the semiconductor device of Fig. 3A.
  • Fig. 5 shows a layout structure of a semiconductor device in accordance with another embodiment of the present invention.
  • Fig. 6 shows a layout structure of a semiconductor device in accordance with another embodiment of the present invention.
  • FIG. 7 shows a layout structure of a semiconductor device in accordance with another embodiment of the present invention.
  • Fig. 8 shows a layout structure of a semiconductor device in accordance with another embodiment of the present invention.
  • Fig. 9 shows a layout structure of a semiconductor device in accordance with another embodiment of the present invention.
  • FIG. 3A shows a layout structure of a semiconductor device according to this embodiment of the present invention
  • FIG. 3B is an enlarged view of a finger of the drain of FIG. 3A and a gate at a corresponding position
  • FIG. 4 shows a view along FIG. 3A.
  • the underlayer is a substrate (also referred to as a substrate) on which a gallium nitride material is grown.
  • the substrate 54 is a sapphire, SiC, GaN, Si, or any of those known to those skilled in the art. Any other substrate or substrate suitable for growing a nitride material, the present invention is not limited thereto.
  • nucleation layer 55 for growing a semiconductor layer thereon. It should be understood that the nucleation layer 55 may not be formed, and the semiconductor layer may be formed directly on the substrate 54.
  • a semiconductor layer 56 On the nucleation layer 55 is a semiconductor layer 56, which may be any semiconductor material based on nitride, such as a Group III nitride semiconductor material, wherein the III valence atoms include indium, aluminum, gallium, or combinations thereof.
  • the semiconductor layer 56 may include gallium nitride (GaN) and other gallium-based compound semiconductor materials, such as AlGaN, InGaN, etc., or may be a stack of gallium-based compound semiconductor materials bonded to other semiconductor materials.
  • the polarity of the gallium-based semiconductor material may be Ga-polar, or may be N-polar, non-polar or semi-polar.
  • an isolation layer 57 which is any semiconductor material capable of forming a heterojunction with the underlying semiconductor layer 56, including a gallium-based compound semiconductor material or a Group III nitride semiconductor material, such as 111 1 ⁇ & ⁇ 1 ⁇ ( 0 ⁇ ⁇ 1 ). That is, the present invention does not have any limitation on the semiconductor layer 56 and the isolation layer 57 as long as a heterojunction can be formed therebetween. Since a semiconductor heterojunction is formed between the semiconductor layer 56 and the isolation layer 57, the polarized charge at the interface of the heterojunction introduces a high concentration of two-dimensional electron gas (2DEG). At the same time, since the scattering of ionized impurities is greatly reduced, electrons have a high electron mobility.
  • 2DEG two-dimensional electron gas
  • the dielectric layer 58 may be one or more dielectric layers.
  • the dielectric layer 58 may be a crystalline material deposited during growth or a process, such as GaN or AlN, etc.; or may be an amorphous material deposited during growth or a process, such as Si x N y or SiO 2 . This dielectric layer 58 helps to reduce the current collapse effect of the gallium nitride HEMT.
  • the source 41 and the drain 42 of the semiconductor device are electrically connected to the 2DEG in the semiconductor layer 56.
  • the manner in which the source 41 and the drain 42 are electrically connected to the 2DEG in the semiconductor layer 56 may be formed by, but not limited to, the following: a. high temperature annealing; b. ion implantation; c. heavy doping .
  • the electrode metal of the source 41 and the drain 42 is in contact with the semiconductor layer 56 through the isolation layer 57 to be electrically connected to the 2DEG formed in the semiconductor layer 56.
  • the source 41 and the drain 42 are composed of an ion-implanted portion or a heavily doped portion electrically connected to the 2DEG formed in the semiconductor layer 56 and an electrode thereon.
  • the gate 43 may be a metal gate or a double-layered gate structure, for example, the lower layer is an insulating medium (for example, Si0 2 ), and the upper layer is a gate metal.
  • a field plate structure and a floating gate structure may be included, and specific details of the two structures may be referred to the above-mentioned Patent Documents 1-3, and the description thereof is omitted here.
  • Fig. 3A shows a schematic plan view of the layout structure of the present embodiment.
  • the source 41 includes a plurality of fingers (also referred to as a finger) 41A drawn from the base
  • the drain 42 also includes The plurality of fingers 42B drawn from the base, and the plurality of fingers 41 A of the source 41 and the plurality of fingers 42B of the drain intersect each other, that is, staggered, whereby the source 41 and the drain 42 are nested with each other.
  • the gate 43 is located between the source 41 and the drain 42, and surrounds the plurality of fingers 41 A of the source 41 and the plurality of fingers 42B of the drain to form a closed loop structure. As shown in Fig. 3A, the gate electrode 43 is distributed in a serpentine shape, and the first gate is connected, and there is no beginning or end. The drain 42 is completely surrounded by the gate 43.
  • the source 41 is located on the periphery of the gate and includes the gate 43 except for an opening.
  • a gate 43 leads an interconnect (e.g., interconnect metal) from the source opening and is connected to the lead pad 44 of the gate. In the present embodiment, the opening may not be formed in the source 41, that is, the source 41 may completely surround the gate 43. In this case, the gate electrode may be connected to its lead pad 44 by a wiring method known to those skilled in the art, such as an air bridge.
  • the gate electrode 43 is located at the source electrode 41 and the drain electrode 42.
  • the plurality of fingers 41A, 42B between and around the source 41 and the drain 42 can thus significantly increase the total length of the gate electrode 43 per unit area. Since the current density of the device is not affected by the layout design, the maximum load current per unit area is greatly increased when the total length of the gates per unit area is significantly increased.
  • the gate 43 since the gate 43 includes a closed-loop structure, there is no beginning or end, so that the gate has no starting point and an end point, and the phenomenon of tip discharge can be effectively avoided, and the breakdown voltage of the device is increased. Further, by forming the source 41 and the drain 42 in a nested structure which intersect each other, the area of the wafer can be utilized effectively, and the production cost can be reduced.
  • each corner of the gate electrode 43 has an arc structure, and portions of the source electrode 41 and the drain electrode 42 corresponding to respective corners of the gate electrode 43 also have an arc structure. More preferably, the tips of the plurality of fingers 41A of the source 41 and the plurality of fingers 42B of the drain 42 have an arc structure, and the portion of the gate 43 corresponding to the curved structure of the tips of the plurality of fingers 41A, 42B is also employed. Curved structure.
  • a curved design is also employed at the corner 43C of the closed-loop structure of the gate electrode 43, and the source electrode 41C and the drain electrode 42C at the corresponding positions.
  • the change of the gate at the corner is very gentle, unlike the above shown in FIG. Linear gate 13
  • the shape of the tip at the end 13A changes so sharply. Since the shape of the gate in the curved structure changes very gently, there is no sharp shape change, so there is no case where the power line is very dense at some tips, and there is no tip discharge caused by sharp edges. Since the electric field distribution is relatively uniform at these arcuate corner positions, there is no tip at the end position of the linear gate, so the tip discharge phenomenon is also avoided, the electric field at the corner of the gate is effectively reduced, and the breakdown voltage of the device is increased. .
  • the tips of the plurality of fingers 41A of the source 41 adopt an arc structure
  • the portion 42A of the drain and the portion 43A of the gate corresponding to the tips of the plurality of fingers 41A of the source 41 also adopt a curved structure.
  • the tips of the plurality of fingers 42B of the drain 42 adopt an arc structure
  • the source portion 41B and the gate portion 43B corresponding to the tips of the plurality of fingers 42B of the drain 42 also adopt a curved structure.
  • the shape change is very gentle, and the electric field distribution is relatively uniform in the arc structure, avoiding the tip discharge. , helps to increase the breakdown voltage of the device.
  • Fig. 5 shows a layout structure of a semiconductor device in accordance with another embodiment of the present invention.
  • this embodiment is the same as the above-described embodiment 1 of FIG. 3A in that the source 41 and the drain 42 include a plurality of fingers 41A, 42B crossing each other, and the gate 43 is located at the source 41 and Between the drains 42, a plurality of fingers 41A surrounding the source 41 and a plurality of fingers 42B of the drain form a closed loop structure.
  • Description of the same portions of Embodiment 2 as those of Embodiment 1 is omitted here, and the differences between the two will be mainly described below.
  • Embodiment 2 differs from Embodiment 1 in two points.
  • the first point is that the gate 43 of the closed loop structure completely surrounds the source 41, and the drain 42 is located at the periphery of the gate 43.
  • the second point is that the start and end points of the gate 43 are not directly connected, but are connected by interconnects 48, which may be formed of any conductive material, such as metal, which is not limited in the present invention.
  • a sharp right angle 43D is formed at a corner where the gate 43 is connected to the interconnect 48, as shown in FIG.
  • the end point 42D that is, the position corresponding to the right angle 43D, adopts an arc structure, so that the electric field is more evenly distributed in the vicinity thereof, thereby avoiding the tip discharge phenomenon, effectively reducing the electric field at the corner of the gate, and increasing The breakdown voltage of the device.
  • the source 41 and the drain 42 include a plurality of fingers 41A, 42B crossing each other, that is, the source and the drain are nested with each other, the gate 43 is located at the source 41 and the drain.
  • the plurality of fingers 41A, 42B between the poles 42 and surrounding the source 41 and the drain 42 can thus significantly increase the total length of the gates 43 per unit area. Since the current density of the device is not affected by the layout design, the maximum carrying current per unit area is greatly increased when the total length of the gates per unit area is significantly increased.
  • the gate 43 since the gate 43 includes a closed-loop structure, there is no beginning or end, so that the gate has no starting point and an end point, and the phenomenon of tip discharge can be effectively avoided, and the breakdown voltage of the device is increased. Further, by forming the source 41 and the drain 42 in a nested structure which intersect each other, the area of the wafer can be effectively utilized, and the production cost can be reduced.
  • Fig. 6 shows a layout structure of a semiconductor device in accordance with another embodiment of the present invention.
  • this embodiment is the same as the above-described embodiment 2 of FIG. 5 in that the source 41 and the drain 42 include a plurality of fingers 41A, 42B crossing each other, and the gate 43 is located at the source 41 and the drain. Between the poles 42, a plurality of fingers 41A surrounding the source 41 and a plurality of fingers 42B of the drain form a closed loop structure, and the start and end points of the gate 43 are not directly connected, but are connected by interconnect lines.
  • the description of the same portions of Embodiment 3 as those of Embodiment 2 is omitted here, and the differences between the two will be mainly described below.
  • Embodiment 3 differs from Embodiment 2 in that the gate electrode 43 completely surrounds the drain electrode 42, and the source electrode 41 is located at the periphery of the gate electrode 43.
  • a sharp right angle 43E is formed at a corner where the gate electrode 43 is connected to the interconnection line, as shown in FIG.
  • a curved structure is adopted at a position 42E of the drain 42 corresponding to the right angle 43E, so that the electric field is more evenly distributed in the vicinity thereof, thereby avoiding the tip discharge phenomenon and effectively reducing
  • the electric field at the corner of the gate increases the breakdown voltage of the device.
  • the source 41 and the drain 42 Including a plurality of fingers 41A, 42B crossing each other, that is, a source and a drain are nested with each other, and a gate 43 is located between the source 41 and the drain 42 and surrounds the plurality of fingers 41A, 42B of the source 41 and the drain 42. Therefore, the total length of the gate electrode 43 per unit area can be significantly increased. Since the current density of the device is not affected by the layout design, the maximum carrying current per unit area is greatly increased when the total length of the gates per unit area is significantly increased.
  • the gate electrode 43 includes a closed-loop structure, there is no beginning or end, so that the gate has no starting point and an end point, and the phenomenon of tip discharge can be effectively avoided, and the breakdown voltage of the device is increased. Further, by forming the source 41 and the drain 42 in a nested structure that intersect each other, the area of the wafer can be effectively utilized, and the production cost can be reduced.
  • FIG. 7 shows a layout structure of a semiconductor device in accordance with another embodiment of the present invention.
  • this embodiment is the same as the above-described embodiment 2 of FIG. 5 in that the source 41 and the drain 42 include a plurality of fingers 41A, 42B crossing each other, and the gate 43 is located at the source 41 and the drain. Between the poles 42, a plurality of fingers 41A surrounding the source 41 and a plurality of fingers 42B of the drain form a closed loop structure, and the start and end points of the gate 43 are not directly connected, but are connected by interconnect lines.
  • the description of the same portions of Embodiment 4 as those of Embodiment 2 is omitted here, and the differences between the two will be mainly described below.
  • Embodiment 4 differs from Embodiment 2 in that the lead-out line is connected to the lead pad 44 of the gate 43 from the corner 43B of the gate 43 of the closed-loop structure. Such a design helps to lower the resistance of the gate 43 while reducing the signal phase difference between the respective fingers 43A of the gate 43.
  • the source 41 requires interconnection through the interconnect of the air bridge 45 across the gate 43.
  • the gate 43 completely surrounds the source 41
  • the gate 43 may be completely surrounded by the drain electrode 42 as shown in Fig. 6, and the source 41 may be located at the periphery of the gate electrode 43.
  • the electric field near the right angle 43D it is only necessary to adopt a curved structure at a position corresponding to the right angle 43D of the drain 42 as shown in FIG. 6, so that the electric field is more evenly distributed in the vicinity thereof. The tip discharge phenomenon is avoided, the electric field at the corner of the gate is effectively reduced, and the breakdown voltage of the device is increased.
  • the gate 43 is located.
  • the plurality of fingers 41A, 42B between the source 41 and the drain 42 and surrounding the source 41 and the drain 42 can thus significantly increase the total length of the gate 43 per unit area. Since the current density of the device is not affected by the layout design, the maximum carrying current per unit area is greatly increased when the total length of the gates per unit area is significantly increased.
  • the gate electrode 43 includes a closed-loop structure, there is no beginning or end, so that the gate has no starting point and an end point, and the phenomenon of tip discharge can be effectively avoided, and the breakdown voltage of the device is increased. Further, by forming the source 41 and the drain 42 in a nested structure that intersect each other, the area of the wafer can be effectively utilized, and the production cost can be reduced.
  • Fig. 8 shows a layout structure of a semiconductor device in accordance with another embodiment of the present invention.
  • this embodiment is the same as the above-described embodiment 2 of FIG. 5 in that the source 41 and the drain 42 include a plurality of fingers 41A, 42B crossing each other, and the gate 43 is located at the source 41 and the drain. Between the poles 42, a plurality of fingers 41A surrounding the source 41 and a plurality of fingers 42B of the drain form a closed loop structure, and the start and end points of the gate 43 are not directly connected, but are connected by interconnect lines.
  • the description of the same portions of Embodiment 5 as those of Embodiment 2 is omitted here, and the differences between the two will be mainly described below.
  • Embodiment 5 differs from Embodiment 2 in that the corner 43B of the gate 43 of the closed-loop structure is connected to the lead pad 44 of the gate 43 across the source 41 through the air bridge 49. Such a design helps to reduce the resistance of the gate 43 while reducing the signal phase difference between the respective fingers 43A of the gate 43.
  • the gate 43 completely surrounds the source 41
  • the gate 43 may be completely surrounded by the drain electrode 42 as shown in Fig. 6, and the source 41 may be located at the periphery of the gate electrode 43.
  • the electric field near the right angle 43D it is only necessary to adopt a curved structure at a position corresponding to the right angle 43D of the drain 42 as shown in FIG. 6, so that the electric field is more evenly distributed in the vicinity thereof. The tip discharge phenomenon is avoided, the electric field at the corner of the gate is effectively reduced, and the breakdown voltage of the device is increased.
  • the gate 43 is located at the source 41 and the drain A plurality of fingers 41A, 42B between the poles 42 and surrounding the source 41 and the drain 42 This can significantly increase the total length of the gate 43 per unit area. Since the current density of the device is not affected by the layout design, the maximum carrying current per unit area is greatly increased when the total length of the gates per unit area is significantly increased.
  • the gate electrode 43 includes a closed-loop structure, there is no beginning or end, so that the gate has no starting point and an end point, and the phenomenon of tip discharge can be effectively avoided, and the breakdown voltage of the device is increased. Further, by forming the source 41 and the drain 42 in a nested structure that intersect each other, the area of the wafer can be effectively utilized, and the production cost can be reduced.
  • Fig. 9 shows a layout structure of a semiconductor device in accordance with another embodiment of the present invention.
  • this embodiment is the same as the above-described embodiment 2 of FIG. 5 in that the source 41 and the drain 42 include a plurality of fingers 41A, 42B crossing each other, and the gate 43 is located at the source 41 and the drain. Between the poles 42, a plurality of fingers 41A surrounding the source 41 and a plurality of fingers 42B of the drain form a closed loop structure, and the start and end points of the gate 43 are not directly connected, but are connected by interconnect lines.
  • the description of the same portions of Embodiment 6 as those of Embodiment 2 is omitted here, and the differences between the two will be mainly described below.
  • Embodiment 6 differs from Embodiment 2 in that the lengths of the respective fingers 41A, 42B of the source 41 and the drain 42 are different, such a layout is advantageous for leaving a large area in some areas of the source 41 and the drain 42. Space, the layout and leads of the source lead pad 47 and the drain lead pad 46 are easy. Thus, it is not necessary to place the lead pads in regions other than the source and drain electrodes, and to draw interconnection lines or air bridges from the source 41 and the drain 42 to be connected to the lead pads. Therefore, the space of the wafer can be saved and the production cost can be reduced.
  • the lead pad 46 of the source 41 and the lead pad 44 of the gate 43 are disposed on one side of the layout, and the lead pad 47 of the drain 42 is disposed on the other side.
  • This can avoid device damage caused by high voltage between the gate and the drain. This is because there is a large voltage difference between the source and the drain (possibly thousands of volts) between the gate and the drain, and the voltage difference between the source and the gate is relatively small. If the gate and drain are on the same side, high voltages between the gate and drain may result in degradation of device performance or device breakdown.
  • the gate 43 completely surrounds the source 41
  • the gate 43 may be completely surrounded by the drain electrode 42 as shown in Fig. 6, and the source 41 may be located at the periphery of the gate electrode 43.
  • the electric field near the right angle 43D it is only necessary to adopt a curved structure at a position corresponding to the right angle 43D of the drain 42 as shown in FIG. 6, so that the electric field is more evenly distributed in the vicinity thereof. The tip discharge phenomenon is avoided, the electric field at the corner of the gate is effectively reduced, and the breakdown voltage of the device is increased.
  • the source 41 and the drain 42 include a plurality of fingers 41A, 42B crossing each other, that is, the source and the drain are nested with each other, the gate 43 is located at the source 41 and the drain.
  • the plurality of fingers 41A, 42B between the poles 42 and surrounding the source 41 and the drain 42 can thus significantly increase the total length of the gates 43 per unit area. Since the current density of the device is not affected by the layout design, the maximum carrying current per unit area is greatly increased when the total length of the gates per unit area is significantly increased.
  • the gate 43 since the gate 43 includes a closed-loop structure, there is no beginning or end, so that the gate has no starting point and an end point, and the phenomenon of tip discharge can be effectively avoided, and the breakdown voltage of the device is increased. Further, by forming the source 41 and the drain 42 in a nested structure which intersect each other, the area of the wafer can be effectively utilized, and the production cost can be reduced.
  • This embodiment relates to a method of manufacturing the semiconductor device of the above embodiments 1-6.
  • a deposition method known to those skilled in the art such as CVD, VPE, MOCVD, LPCVD, PECVD, pulsed laser deposition (PLD), atomic layer epitaxy, MBE, sputtering, evaporation, etc.
  • CVD chemical vapor deposition
  • VPE vacuum chemical vapor deposition
  • MOCVD MOCVD
  • LPCVD LPCVD
  • PECVD pulsed laser deposition
  • atomic layer epitaxy MBE
  • sputtering evaporation, etc.
  • a semiconductor layer on the bottom (or substrate) which may be sapphire, SiC, GaN, Si, or any other substrate or substrate suitable for growing gallium nitride materials known to those skilled in the art.
  • PLD pulsed laser deposition
  • atomic layer epitaxy MBE
  • sputtering evaporation, etc.
  • a semiconductor layer on the bottom (or substrate) which may be sapphire, SiC, GaN, Si, or any other substrate
  • an optional nucleation layer may also be deposited on the substrate using the deposition method described above prior to deposition of the semiconductor.
  • the deposited semiconductor layer can be any semiconductor material based on nitride, such as a group III nitrogen A semiconductor material, wherein the III valent atom comprises indium, aluminum, gallium or a combination thereof.
  • the semiconductor layer may include gallium nitride (GaN) and other gallium-based compound semiconductor materials, such as AlGaN, InGaN, etc., or may be a stack of gallium-based compound semiconductor materials bonded to other semiconductor materials.
  • the polarity of the gallium-based semiconductor material may be Ga-polar, or may be N-polar, non-polar or semi-polar.
  • an isolation layer is deposited on the semiconductor layer by the above deposition method, and the isolation layer may be any semiconductor material capable of forming a heterojunction with the underlying semiconductor layer, including a gallium-based compound semiconductor material or a lanthanum nitride semiconductor material, such as In x Al y Ga z N 1 -XZ ( 0 ⁇ x, y, z ⁇ l ) 0 That is, the present invention has no limitation on the deposited semiconductor layer and the spacer layer as long as a heterojunction can be formed therebetween. can. Due to the formation of a semiconductor heterojunction between the semiconductor layer and the isolation layer, the polarized charge at the interface of the heterojunction introduces a high concentration of two-dimensional electron gas (2DEG). At the same time, since the scattering of ionized impurities is greatly reduced, electrons have a high electron mobility.
  • 2DEG two-dimensional electron gas
  • an optional dielectric layer is deposited on the isolation layer using the deposition method described above, and the dielectric layer may be one or more dielectric layers.
  • the dielectric layer may be a crystalline material deposited during growth or a process, such as GaN or AlN, etc.; or may be an amorphous material deposited during growth or a process, such as Si x N y or SiO 2 . This dielectric layer helps to reduce the current collapse effect of the gallium nitride HEMT.
  • a source and a drain in contact with the semiconductor layer are formed by any method known to those skilled in the art, such as high temperature annealing, ion implantation, heavy doping, or the like.
  • a gate electrode is formed on the isolation layer between the source and the drain by the above deposition method.
  • a layout structure as shown in FIGS. 3A and 5-8 is formed by a masking method by those skilled in the art, so that it can be obtained as in the above embodiments 1-6.
  • the gate electrode may be formed as a double-layered gate structure, for example, an insulating dielectric shield (for example, Si0 2 ) is first formed, and then a gate metal is formed on the insulating medium.
  • the field plate structure and the floating gate structure may be formed in the process of forming the gate electrode.
  • the present invention increases the breakdown voltage of the semiconductor device from the viewpoint of layout design, and thus the depletion type gallium nitride HEMT described in the above embodiments 1-7 is only an example, and the present invention is not limited thereto.
  • the invention is applicable to a gallium nitride HEMT operating in a high voltage and high current environment, and can also be applied to other forms of transistors such as MOSFETs, MISFETs, DHFETs, JFETs, MESFETs, MISHFETs or other field effect transistors. Also, these devices may be either enhanced or depleted.

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Description

半导体器件及其制造方法 技术领域
本发明涉及 III族氮化物半导体器件及其制造方法， 具体来说， 涉及 一种新的版图设计方案， 有利于提高 III族氮化物半导体器件的击穿电压， 同时有效利用晶片上的器件空间， 特别适用于高电压大电流器件。 背景技术
第三代半导体氮化镓 ( GaN ) 的介质击穿电场远远高于第一代半导体 硅（Si )或第二代半导体砷化镓 ( GaAs ) ， 高达 3MV/cm， 使其电子器件 能承受很高的电压。 同时， 氮化镓可以与其他镓类化合物半导体（III族氮 化物半导体）形成异质结结构。 由于 III族氮化物半导体具有强烈的自发 极化和压电极化效应， 在异质结的界面附近， 可以形成很高电子浓度的二 维电子气（2DEG )沟道。 这种异质结结构也有效的降低了电离杂质散射， 因此沟道内的电子迁移率大大提升。 在此异质结基础上制成的氮化镓高电 子迁移率晶体管（HEMT ) 能在高频率导通高电流， 并具有 ί艮低的导通电 阻。这些特性使氮化镓 ΗΕΜΤ特别适用于制造高频的大功率射频器件和高 耐压大电流的开关器件。
由于二维电子气沟道内的电子有很高的迁移率， 所以氮化镓 ΗΕΜΤ 相对于硅器件而言， 开关速率大大提高。 同时高浓度的二维电子气也使得 氮化镓 ΗΕΜΤ具有较高的电流密度，适用于大电流功率器件的需要。另外， 氮化镓是宽禁带半导体， 能工作在较高的温度。 硅器件在大功率工作环境 下往往需要额外的降温器件来确保其正常工作， 而氮化镓无须这样， 或者 对降温要求较低。 因此氮化镓功率器件有利于节省空间和成本。
常用的氮化镓 ΗΕΜΤ的器件结构的截面图如图 1所示。 底层是基片 94， 基片 94上沉积有成核层 95, 緩冲层 96和隔离层 97。二维电子气沟道 在緩冲层和隔离层的界面附近形成。 隔离层上方沉积有一层介质层 98, 可 用于降低高频下的电流崩塌效应。 源极 91和漏极 92与二维电子气相通， 可以控制沟道内电子的流向。栅极 93位于源极和漏极之间，用于控制沟道 内电子的数目， 进而控制电流的大小。
在晶体管中， 通常， 在栅极与漏极之间承受很高的电压， 强电场在栅 极附近的空间电荷区聚集。 当峰值电场大于材料的击穿电场时， 晶体管的 性能会受到严重影响， 甚至出现击穿现象。 对于氮化镓功率器件而言， 因 为其经常要工作在大电压（甚至可能超过千伏）环境下， 所以对峰值电场 的控制的要求更加严格。 很多研究机构提出了许多降低峰值电场的方案， 涉及从晶片的外延结构和器件的结构上的种种改进， 例如， 采用场板结构 和浮栅结构， 可以使电场分布更加均匀。 场板结构的具体细节参见中国专 利申请公开 CN101232045A和 CN1954440A, 以下分别称为专利文献 1和 2,在此通过参考引入其整个内容。浮栅结构的具体细节参见中国专利申请 公开 CN101320751A, 以下称为专利文献 3， 在此通过参考引入其整个内 容。
本发明从版图设计的角度提供了另外一种方案来实现降低峰值电场， 增强器件击穿电压的目的。 传统的氮化镓晶体管的版图多采用直线型的栅 极、 漏极结构， 如图 2所示。 在图 2中， 由于栅极 13的终止， 在栅极 13 的两个端部 13A电势变化比较激烈， 电场比较集中。 因此， 栅极 13的端 部 13A处的电场要远大于栅极 13的中间区域的电场， 器件击穿也多发生 在栅极 13的端部 13A。
因此， 需要设计一种新的版图， 来有效降低栅极的端部处的电场。 发明内容
本发明为了解决上述现有技术中存在的问题， 提供了半导体器件及其 制造方法。
根据本发明的一个方面， 提供了一种半导体器件， 包括： 在衬底上的 半导体层； 在上述半导体层上的隔离层； 与上述半导体层接触的源极和漏 极， 该源极和漏极的每个包括多个指， 并且上述源极的多个指与上述漏极 的多个指相互交叉； 以及在上述隔离层上的栅极， 该栅极位于上述源极和 漏极之间并包括围绕上述源极和漏极的上述多个指的闭环结构。 通过使用本发明的这种半导体器件， 因为源极和漏极包括相互交叉的 多个指， 即源极和漏极相互嵌套， 栅极位于源极和漏极之间并围绕源极和 漏极的多个指， 因此可以显著增加单位面积内栅极的总长度。 因为器件的 电流密度不受版图设计的影响， 因此当单位面积内的栅极的总长度显著增 加后， 单位面积的最大承载电流也会大大增加。 同时， 由于栅极包括闭环 结构， 无始无终， 因此使得栅极没有起点和终点， 可以有效地避免尖端放 电的现象， 增加了器件的击穿电压。 相反， 如果栅极是开环的结构， 则在 栅极的起点和终点的位置， 由于尖端放电的效应， 电力线在栅极的起点和 终点会过于密集， 从而会产生艮强的电场。 此外， 通过使源极和漏极形成 为相互交叉的嵌套结构， 可以有效利用晶片的面积， 降低生产成本。
优选， 上述栅极的首尾直接相连或者通过互连线相连。 更优选， 在上 述栅极的首尾直接相连的情况下， 上述栅极的各个拐角都采用弧形结构， 并且上述源极和漏极的与上述各个拐角对应的部分的也采用弧形结构。 在 上述栅极的首尾通过互连线相连的情况下， 上述漏极的与上述栅极和上述 互连线的连接处对应的部分采用弧形结构， 上述栅极的各个拐角都采用弧 形结构， 并且上述源极和漏极的与上述各个拐角对应的部分也采用弧形结 构。 更优选， 上述源极和漏极的多个指的尖端采用弧形结构， 并且上述栅 极的与上述多个指的尖端的弧形结构对应的部分也采用弧形结构。
通过在栅极的各个拐角处都采用弧形结构， 并且对应位置处的源极和 漏极也采用弧形结构， 使得栅极在拐角处的变化非常平緩， 不像上述直线 型栅极 13的端部 13A处尖端的形状变化那么剧烈。 由于弧形结构中栅极 的形状变化非常平緩， 没有尖锐的形状变化， 因此不会出现电力线在某些 尖端非常密集的情况， 不会出现尖锐边缘造成的尖端放电。 由于电场分布 在这些弧形拐角位置比较均匀， 没有直线型栅极的终点位置处的尖端， 因 此也避免了尖端放电现象， 有效的降低了栅极拐角处的电场， 增加了器件 的击穿电压。
优选， 在上述半导体器件的版图结构中， 上述源极和栅极的引线烊盘 (又称为引线衬垫）位于一侧， 而上述漏极的引线烊盘位于另一侧。
通过使栅极的引线焊盘与源极的引线焊盘位于同一侧， 使漏极的引线 焊盘位于另一侧， 可以避免栅极、 漏极间的高电压造成的器件伤害。 这是 因为栅极和漏极之间， 源极和漏极之间有很大的电压差（可能上千伏） , 而源极和栅极之间的电压差比较小。 如果栅极和漏极位于同一侧， 栅极和 漏极之间的高电压可能导致的器件性能退化或器件击穿。
优选， 上述源极和漏极的多个指的长度不同。
本发明并没有限制源极和漏极的指的数目和长度。 通过使源极和漏极 的指的长度不同， 在源极和漏极内的某些区域会留有足够大的空间用来放 置源极的引线焊盘和漏极的引线焊盘， 从而无需在源极和漏极之外的区域 放置引线焊盘，并从源极和漏极引出互连线或者空气桥来连接到引线焊盘。 因此， 可以节省晶片的空间， 降低生产成本。
根据本发明的另一个方面， 提供了一种用于制造半导体器件的方法， 包括以下步骤： 在衬底上沉积半导体层； 在上述半导体层上沉积隔离层； 形成与上述半导体层接触的源极和漏极， 其中该源极和漏极的每个包括多 个指， 并且上述源极的多个指与上述漏极的多个指相互交叉； 以及在上述 隔离层上， 在上述源极和漏极之间， 形成包括围绕上述源极和漏极的上述 多个指的闭环结构的栅极。
通过本发明的上述半导体器件的制造方法， 可以获得上述相同和相应 的优点。 附图说明
相信通过以下结合附图对本发明具体实施方式的说明， 能够使人们更 好地了解本发明上述的特点、 优点和目的， 其中：
图 1示出了常规的氮化镓 HEMT的器件结构的截面图。
图 2示出了采用直线型栅极的常规氮化镓 HEMT的版图结构中电场分 布的示意图。
图 3A示出了根据本发明的一个实施例的半导体器件的版图结构， 图 3B是图 3A中的漏极的一个指和对应位置处的栅极的放大图。
图 4示出了沿图 3A的半导体器件的版图结构中 A-A线的截面图。 图 5示出了根据本发明的另一个实施例的半导体器件的版图结构。 图 6示出了根据本发明的另一个实施例的半导体器件的版图结构。 图 7示出了根据本发明的另一个实施例的半导体器件的版图结构。 图 8示出了根据本发明的另一个实施例的半导体器件的版图结构。 图 9示出了根据本发明的另一个实施例的半导体器件的版图结构。 具体实施方式
下面就结合附图对本发明的各个优选实施例进行详细的说明。
(实施例 1 )
图 3A示出了根据本发明的该实施例的半导体器件的版图结构， 图 3B 是图 3A中的漏极的一个指和对应位置处的栅极的放大图， 图 4示出了沿 图 3A的半导体器件的版图结构中 A-A线的截面图。
下面首先参照图 4说明本实施例的作为半导体器件的一个例子的增强 型氮化镓 HEMT的基本结构。
如图 4所示， 底层是生长氮化镓材料的基片 （又称为衬底） 54, 该基 片 54—般 宝石 （Sapphire ) 、 SiC、 GaN、 Si或者本领域的技术人员 公知的任何其他适合生长氮化^ "料的任何基片或衬底， 本发明对此没有 任何限制。
在基片 54上是可选的成核层 55， 用于在其上生长半导体层。 应该理 解， 也可以不形成成核层 55, 而直接在基片 54上形成半导体层。
在成核层 55上是半导体层 56， 其可以是基于氮化物的任何半导体材 料， 例如 III族氮化物半导体材料， 其中 III价原子包括铟、 铝、 镓或其组 合。 具体地， 半导体层 56可以包括氮化镓（GaN )以及其他镓类化合物半 导体材料， 例如 AlGaN、 InGaN等， 也可以是镓类化合物半导体材料与其 他半导体材料键合的叠层。 镓类半导体材料的极性可以是 Ga-极性， 也可 以是 N-极性、 非极性或者半极性。 在半导体层 56上是隔离层 57， 其是能够与下面的半导体层 56形成异 质结的任何半导体材料， 包括镓类化合物半导体材料或 III族氮化物半导 体材料， 例如111 1^&^1 ^ ( 0 <^^^ < 1 )。 也就是说， 本发明对于半 导体层 56和隔离层 57没有任何限制，只要二者之间能够形成异质结即可。 由于在半导体层 56和隔离层 57之间形成半导体异质结， 在异质结界面上 的极化电荷引入了高浓度的二维电子气（2DEG ) 。 同时由于电离杂质散 射被大大降低， 电子具有很高的电子迁移率。
在隔离层 57上是可选的介质层 58， 其可以是一层或多层介质层。 该 介质层 58可以是在生长或工艺过程中沉积的晶体材料，如 GaN或 A1N等； 也可以是在生长或工艺过程中沉积的非晶体材料， 例如 SixNy或 Si02等。 该介质层 58有助于降低氮化镓 HEMT的电流崩塌效应。
半导体器件的源极 41和漏极 42与半导体层 56中的 2DEG形成电连 接。 在本实施例中， 源极 41和漏极 42与半导体层 56中的 2DEG形成电 连接的方式可以采用但不局限于以下方式形成： a. 高温退火； b. 离子注 入； c. 重掺杂。 在进行高温退火的情况下， 源极 41和漏极 42的电极金属 穿过隔离层 57与半导体层 56接触， 从而与半导体层 56中形成的 2DEG 电连接。 在进行离子注入和重掺杂的情况下， 源极 41和漏极 42由与半导 体层 56中形成的 2DEG电连接的离子注入部分或重掺杂部分和其上的电 极构成。应该理解，这里描述形成源极 41和漏极 42的方法只是进行举例， 半导体器件的栅极 43在位于源极 41和漏极 42之间的区域。 栅极 43 可以是金属栅极，也可以双层栅极结构，例如下层是绝缘介质（例如 Si02 ), 上层是栅极金属。 可选地， 在本实施例的半导体器件中， 也可以包括场板 结构和浮栅结构，这两种结构的具体细节可以参见上述专利文献 1-3，在此 省略其说明。
下面参照附图 3A和 3B详细描 实施例的半导体器件的版图结构。 图 3A示出了本实施例的版图结构的俯视示意图。如图 3A所示， 源极 41包括从基部引出的多个指（finger , 又称为节指） 41A, 漏极 42也包括 从基部引出的多个指 42B，并且源极 41的多个指 41 A和漏极的多个指 42B 相互交叉， 即交错排列， 由此， 源极 41和漏极 42互相嵌套。
栅极 43位于源极 41和漏极 42之间， 并且围绕源极 41的多个指 41 A 和漏极的多个指 42B, 形成一个闭环结构。 如图 3A所示， 栅极 43呈蛇状 分布， 首^目连， 无始无终。 漏极 42被栅极 43完全包围。 源极 41位于栅 极的***， 除了一个开口外将栅极 43包含在内。 栅极 43从该源极开口处 引出互连线（例如互连金属），与栅极的引线焊盘 44相连。在本实施例中， 也可以不在源极 41中形成开口，也就是说源极 41也可以完全包围栅极 43。 在这种情况下， 可以通过本领域的技术人员公知的布线方法， 例如空气桥 等将栅极与其引线焊盘 44相连。
通过使用本实施例的上述半导体器件， 因为源极 41和漏极 42包括相 互交叉的多个指 41A、 42B, 即源极和漏极相互嵌套， 栅极 43位于源极 41 和漏极 42之间并围绕源极 41和漏极 42的多个指 41A、 42B, 因此可以显 著增加单位面积内栅极 43的总长度。因为器件的电流密度不受版图设计的 影响， 因此当单位面积内的栅极的总长度显著增加后， 单位面积的最大承 载电流也会大大增加。 同时， 由于栅极 43包括闭环结构， 无始无终， 因此 使得栅极没有起点和终点， 可以有效地避免尖端放电的现象， 增加了器件 的击穿电压。此外，通过使源极 41和漏极 42形成为相互交叉的嵌套结构， 可以有效利用晶片的面积， 降低生产成本。
此外， 在本实施例中， 优选， 栅极 43的各个拐角都采用弧形结构， 并 且源极 41和漏极 42的与栅极 43的各个拐角对应的部分的也采用弧形结 构。 更优选， 源极 41的多个指 41A和漏极 42的多个指 42B的尖端采用弧 形结构， 并且栅极 43的与多个指 41A、 42B的尖端的弧形结构对应的部分 也采用弧形结构。
具体地， 如图 3A所示， 在栅极 43的闭环结构的拐角 43C处， 以及对 应位置处的源极 41C和漏极 42C也采用了弧形设计。通过在栅极的各个拐 角处都采用弧形结构， 并且对应位置处的源极和漏极也采用弧形结构， 使 得栅极在拐角处的变化非常平緩， 不像上述图 2 中示出的直线型栅极 13 的端部 13A处尖端的形状变化那么剧烈。 由于弧形结构中栅极的形状变化 非常平緩， 没有尖锐的形状变化， 因此不会出现电力线在某些尖端非常密 集的情况， 不会出现尖锐边缘造成的尖端放电。 由于电场分布在这些弧形 拐角位置比较均匀， 没有直线型栅极的终点位置处的尖端， 因此也避免了 尖端放电现象，有效的降低了栅极拐角处的电场，增加了器件的击穿电压。
进而， 源极 41的多个指 41A的尖端采用了弧形结构， 并且与源极 41 的多个指 41A的尖端对应的漏极的部分 42A和栅极的部分 43A,也采用了 弧形结构。 此外， 漏极 42的多个指 42B的尖端采用了弧形结构， 并且与 漏极 42的多个指 42B的尖端对应的源极的部分 41B和栅极的部分 43B， 也采用了弧形结构。 如图 3B的放大图所示， 由于漏极 42的指的尖端和栅 极 43的对应部分采用弧形结构， 因此其形状变化非常平緩，在弧形结构中 电场分布比较均匀， 避免了尖端放电， 有助于提高器件的击穿电压。
应该理解， 尽管在图 3A中示出了栅极 43将漏极 42完全包围的结构， 但是很显然可以将源极 41和漏极 42互换， 而形成栅极 43将源极 41完全 包围， 漏极 42位于栅极 43的***的结构。
(实施例 2 )
图 5示出了根据本发明的另一个实施例的半导体器件的版图结构。 如图 5所示， 该实施例与上述图 3 A的实施例 1的相同之处在于源极 41和漏极 42包括互相交叉的多个指 41A、 42B, 并且栅极 43位于源极 41 和漏极 42之间， 围绕源极 41的多个指 41A和漏极的多个指 42B, 形成一 个闭环结构。 在此省略对实施例 2的与实施例 1相同的部分的描述， 下面 着重描述二者的不同之处。
实施例 2与实施例 1的不同之处在于两点。 第一点为闭环结构的栅极 43将源极 41完全包围， 而漏极 42位于栅极 43的***。 第二点为栅极 43 的起点和终点没有直接连接， 而是通过互连线 48相连接， 互连线 48可以 由任何导电的材料， 例如金属形成， 本发明对此没有任何限制。
在本实施例中， 在栅极 43与互连线 48相连接的拐角处， 形成尖锐的 直角 43D, 如图 5所示。 为了降低处直角 43D附近的电场， 在漏极 42终 止的端点 42D， 即与直角 43D相对应的位置， 采用了弧形结构， 使得电场 在其附近位置的分布更加均匀， 从而避免了尖端放电现象， 有效的降低了 栅极拐角处的电场， 增加了器件的击穿电压。
同样， 通过使用本实施例的上述半导体器件， 因为源极 41和漏极 42 包括相互交叉的多个指 41A、 42B, 即源极和漏极相互嵌套， 栅极 43位于 源极 41和漏极 42之间并围绕源极 41和漏极 42的多个指 41A、 42B, 因 此可以显著增加单位面积内栅极 43的总长度。因为器件的电流密度不受版 图设计的影响， 因此当单位面积内的栅极的总长度显著增加后， 单位面积 的最大承载电流也会大大增加。 同时， 由于栅极 43包括闭环结构， 无始无 终， 因此使得栅极没有起点和终点， 可以有效地避免尖端放电的现象， 增 加了器件的击穿电压。 此外， 通过使源极 41和漏极 42形成为相互交叉的 嵌套结构， 可以有效利用晶片的面积， 降低生产成本。
(实施例 3 )
图 6示出了根据本发明的另一个实施例的半导体器件的版图结构。 如图 6所示， 该实施例与上述图 5的实施例 2的相同之处在于源极 41 和漏极 42包括互相交叉的多个指 41A、 42B, 并且栅极 43位于源极 41和 漏极 42之间， 围绕源极 41的多个指 41A和漏极的多个指 42B, 形成一个 闭环结构， 以及栅极 43的起点和终点没有直接连接， 而是通过互连线相连 接。 在此省略对实施例 3的与实施例 2相同的部分的描述， 下面着重描述 二者的不同之处。
实施例 3与实施例 2的不同之处在于栅极 43完全包围漏极 42, 源极 41位于栅极 43的***。
在本实施例中，在栅极 43与互连线相连接的拐角处，形成尖锐的直角 43E, 如图 6所示。 为了降低处直角 43E附近的电场， 在漏极 42的与直角 43E相对应的位置 42E, 采用了弧形结构， 使得电场在其附近位置的分布 更加均匀， 从而避免了尖端放电现象， 有效的降低了栅极拐角处的电场， 增加了器件的击穿电压。
同样， 通过使用本实施例的上述半导体器件， 因为源极 41和漏极 42 包括相互交叉的多个指 41A、 42B, 即源极和漏极相互嵌套， 栅极 43位于 源极 41和漏极 42之间并围绕源极 41和漏极 42的多个指 41A、 42B, 因 此可以显著增加单位面积内栅极 43的总长度。因为器件的电流密度不受版 图设计的影响， 因此当单位面积内的栅极的总长度显著增加后， 单位面积 的最大承载电流也会大大增加。 同时， 由于栅极 43包括闭环结构， 无始无 终， 因此使得栅极没有起点和终点， 可以有效地避免尖端放电的现象， 增 加了器件的击穿电压。 此外， 通过使源极 41和漏极 42形成为相互交叉的 嵌套结构， 可以有效利用晶片的面积， 降低生产成本。
(实施例 4 )
图 7示出了根据本发明的另一个实施例的半导体器件的版图结构。 如图 7所示， 该实施例与上述图 5的实施例 2的相同之处在于源极 41 和漏极 42包括互相交叉的多个指 41A、 42B, 并且栅极 43位于源极 41和 漏极 42之间， 围绕源极 41的多个指 41A和漏极的多个指 42B, 形成一个 闭环结构， 以及栅极 43的起点和终点没有直接连接， 而是通过互连线相连 接。 在此省略对实施例 4的与实施例 2相同的部分的描述， 下面着重描述 二者的不同之处。
实施例 4与实施例 2的不同之处在于从闭环结构的栅极 43的拐角处 43B, 引出互连线与栅极 43的引线烊盘 44相连接。 这样的设计有助于降 低栅极 43的电阻， 同时降低栅极 43的各个指 43A之间的信号相位差。 在 该实施例中，源极 41需要通过空气桥 45跨越栅极 43的互连线来实现互连。
此外， 尽管在该实施例中， 栅极 43将源极 41完全包围， 但是也可以 如图 6那样， 使栅极 43将漏极 42完全包围， 而使源极 41位于栅极 43的 ***。 此时， 为了降低处直角 43D附近的电场， 只需要如图 6那样， 在漏 极 42的与直角 43D相对应的位置， 采用了弧形结构， 使得电场在其附近 位置的分布更加均匀， 从而避免了尖端放电现象， 有效的降低了栅极拐角 处的电场， 增加了器件的击穿电压。
同样， 通过使用本实施例的上述半导体器件， 因为源极 41和漏极 42 包括相互交叉的多个指 41A、 42B, 即源极和漏极相互嵌套， 栅极 43位于 源极 41和漏极 42之间并围绕源极 41和漏极 42的多个指 41A、 42B, 因 此可以显著增加单位面积内栅极 43的总长度。因为器件的电流密度不受版 图设计的影响， 因此当单位面积内的栅极的总长度显著增加后， 单位面积 的最大承载电流也会大大增加。 同时， 由于栅极 43包括闭环结构， 无始无 终， 因此使得栅极没有起点和终点， 可以有效地避免尖端放电的现象， 增 加了器件的击穿电压。 此外， 通过使源极 41和漏极 42形成为相互交叉的 嵌套结构， 可以有效利用晶片的面积， 降低生产成本。
(实施例 5 )
图 8示出了根据本发明的另一个实施例的半导体器件的版图结构。 如图 8所示， 该实施例与上述图 5的实施例 2的相同之处在于源极 41 和漏极 42包括互相交叉的多个指 41A、 42B, 并且栅极 43位于源极 41和 漏极 42之间， 围绕源极 41的多个指 41A和漏极的多个指 42B， 形成一个 闭环结构， 以及栅极 43的起点和终点没有直接连接， 而是通过互连线相连 接。 在此省略对实施例 5的与实施例 2相同的部分的描述， 下面着重描述 二者的不同之处。
实施例 5与实施例 2的不同之处在于将闭环结构的栅极 43的拐角 43B， 通过空气桥 49跨越源极 41与栅极 43的引线烊盘 44相连接。 这样的设计 有助于降低栅极 43的电阻， 同时降低栅极 43的各个指 43A之间的信号相 位差。
此外， 尽管在该实施例中， 栅极 43将源极 41完全包围， 但是也可以 如图 6那样， 使栅极 43将漏极 42完全包围， 而使源极 41位于栅极 43的 ***。 此时， 为了降低处直角 43D附近的电场， 只需要如图 6那样， 在漏 极 42的与直角 43D相对应的位置， 采用了弧形结构， 使得电场在其附近 位置的分布更加均匀， 从而避免了尖端放电现象， 有效的降低了栅极拐角 处的电场， 增加了器件的击穿电压。
同样， 通过使用本实施例的上述半导体器件， 因为源极 41和漏极 42 包括相互交叉的多个指 41A、 42B, 即源极和漏极相互嵌套， 栅极 43位于 源极 41和漏极 42之间并围绕源极 41和漏极 42的多个指 41A、 42B, 因 此可以显著增加单位面积内栅极 43的总长度。因为器件的电流密度不受版 图设计的影响， 因此当单位面积内的栅极的总长度显著增加后， 单位面积 的最大承载电流也会大大增加。 同时， 由于栅极 43包括闭环结构， 无始无 终， 因此使得栅极没有起点和终点， 可以有效地避免尖端放电的现象， 增 加了器件的击穿电压。 此外， 通过使源极 41和漏极 42形成为相互交叉的 嵌套结构， 可以有效利用晶片的面积， 降低生产成本。
(实施例 6 )
图 9示出了根据本发明的另一个实施例的半导体器件的版图结构。 如图 9所示， 该实施例与上述图 5的实施例 2的相同之处在于源极 41 和漏极 42包括互相交叉的多个指 41A、 42B, 并且栅极 43位于源极 41和 漏极 42之间， 围绕源极 41的多个指 41A和漏极的多个指 42B, 形成一个 闭环结构， 以及栅极 43的起点和终点没有直接连接， 而是通过互连线相连 接。 在此省略对实施例 6的与实施例 2相同的部分的描述， 下面着重描述 二者的不同之处。
实施例 6与实施例 2的不同之处在于源极 41和漏极 42的各个指 41A、 42B的长度不同， 这样的布局有利于在源极 41和漏极 42的某些区域留下 较大空间， 易于源极引线焊盘 47和漏极引线嬋盘 46的布局和引线。 从而 无需在源极和漏极之外的区¾^置引线焊盘， 并从源极 41和漏极 42引出 互连线或者空气桥来连接到引线焊盘。 因此， 可以节省晶片的空间， 降低 生产成本
优选，在本实施例中，将源极 41的引线嬋盘 46和栅极 43的引线焊盘 44设置在版图的一侧， 而将漏极 42的引线絆盘 47设置在另一侧， 由此可 以避免栅极、漏极间的高电压造成的器件伤害。这是因为栅极和漏极之间， 源极和漏极之间有很大的电压差（可能上千伏） ， 而源极和栅极之间的电 压差比较小。 如果栅极和漏极位于同一侧， 栅极和漏极之间的高电压可能 导致的器件性能退化或器件击穿。
应该理解， 尽管在本实施例中将源极 41和栅极 43的引线焊盘与漏极 42的引线焊盘设置在不同侧， 但是在与上述图 3A、 5-8对应的实施例 1-5 中， 同样也可以采用这种结构， 来避免栅极、 漏极间的高电压造成的器件 伤害。
此外， 尽管在该实施例中， 栅极 43将源极 41完全包围， 但是也可以 如图 6那样， 使栅极 43将漏极 42完全包围， 而使源极 41位于栅极 43的 ***。 此时， 为了降低处直角 43D附近的电场， 只需要如图 6那样， 在漏 极 42的与直角 43D相对应的位置， 采用了弧形结构， 使得电场在其附近 位置的分布更加均匀， 从而避免了尖端放电现象， 有效的降低了栅极拐角 处的电场， 增加了器件的击穿电压。
同样， 通过使用本实施例的上述半导体器件， 因为源极 41和漏极 42 包括相互交叉的多个指 41A、 42B, 即源极和漏极相互嵌套， 栅极 43位于 源极 41和漏极 42之间并围绕源极 41和漏极 42的多个指 41A、 42B, 因 此可以显著增加单位面积内栅极 43的总长度。因为器件的电流密度不受版 图设计的影响， 因此当单位面积内的栅极的总长度显著增加后， 单位面积 的最大承载电流也会大大增加。 同时， 由于栅极 43包括闭环结构， 无始无 终， 因此使得栅极没有起点和终点， 可以有效地避免尖端放电的现象， 增 加了器件的击穿电压。 此外， 通过使源极 41和漏极 42形成为相互交叉的 嵌套结构， 可以有效利用晶片的面积， 降低生产成本。
(实施例 7 )
本实施例涉及上述实施例 1-6的半导体器件的制造方法。
在本实施例中， 首先利用本领域的技术人员公知的沉积方法， 例如 CVD、 VPE、 MOCVD、 LPCVD、 PECVD、 脉冲激光沉积（ PLD ) 、 原 子层外延、 MBE、 溅射、 蒸发等， 在衬底（或基片）上沉积半导体层， 该 衬底可以是蓝宝石（Sapphire ) 、 SiC、 GaN、 Si或者本领域的技术人员公 知的任何其他适合生长氮化镓材料的任何基片或衬底， 本发明对此没有任 何限制。
可选地， 也可以在沉积半导体之前， 在衬底上利用上述沉积方法沉积 可选的成核层。
沉积的半导体层可以是基于氮化物的任何半导体材料， 例如 III族氮 化物半导体材料， 其中 III价原子包括铟、 铝、 镓或其组合。 具体地， 半 导体层可以包括氮化镓（GaN ) 以及其他镓类化合物半导体材料， 例如 AlGaN、 InGaN等， 也可以是镓类化合物半导体材料与其他半导体材料键 合的叠层。 镓类半导体材料的极性可以是 Ga-极性， 也可以是 N-极性、 非 极性或者半极性。
接着， 在半导体层上利用上述沉积方法沉积隔离层， 该隔离层可以是 能够与下面的半导体层形成异质结的任何半导体材料， 包括镓类化合物半 导体材料或 ΙΠ族氮化物半导体材料，例如 InxAlyGazN1 -X Z( 0 < x, y, z < l )0 也就是说， 本发明对于沉积的半导体层和隔离层没有任何限制， 只要二者 之间能够形成异质结即可。 由于在半导体层和隔离层之间形成半导体异质 结， 在异质结界面上的极化电荷引入了高浓度的二维电子气（2DEG ) 。 同时由于电离杂质散射被大大降低， 电子具有很高的电子迁移率。
接着， 可选地， 在隔离层上利用上述沉积方法沉积可选的介质层， 该 介质层可以是一层或多层介质层。 该介质层可以是在生长或工艺过程中沉 积的晶体材料， 如 GaN或 A1N等； 也可以是在生长或工艺过程中沉积的 非晶体材料，例如 SixNy或 Si02等。该介质层有助于降低氮化镓 HEMT的 电流崩塌效应。
接着， 利用本领域的技术人员公知的任何方法， 例如高温退火、 离子 注入、 重掺杂等， 形成与半导体层接触的源极和漏极。
接着， 在隔离层上、 在源极和漏极之间通过上述沉积方法形成栅极。 在形成源极、 漏极和栅极的过程中， 利用本领域的技术人员 的掩 蔽方法， 形成如图 3A、 5-8所示的版图结构， 从而可以得到如上述实施例 1-6中所述的半导体器件。
此外，也可以将栅极形成为双层栅极结构，例如首先形成绝缘介盾（例 如 Si02 ) ， 接着在绝缘介质上形成栅极金属。 可选地， 在本实施例中， 也 可以在形成栅极的过程中形成场板结构和浮栅结构， 具体细节可以参见上 述专利文献 1-3， 在此省略其说明。
通过使用本实施例的形成半导体器件的方法,可以获得上述实施例 1-6 中描述的所有优点。
应该理解，本发明是从版图设计的角度来增加半导体器件的击穿电压， 因此上述实施例 1-7中描述的耗尽型的氮化镓 HEMT只是一个例子，本发 明并不限于此。 本发明既适用于工作在高电压大电流环境下的氮化镓 HEMT , 也可以适用于其他形式的晶体管， 如 MOSFET、 MISFET、 DHFET、 JFET、 MESFET、 MISHFET或者其他场效应晶体管。 并且， 这些器件可以是增强型的， 也可以是耗尽型的。
以上虽然通过一些示例性的实施例对本发明的半导体器件以及用于制 造半导体器件的方法进行了详细的描述， 但是以上这些实施例并不是穷举 的， 本领域技术人员可以在本发明的精神和范围内实现各种变化和修改。 因此， 本发明并不限于这些实施例， 本发明的范围仅以所附权利要求书为 准。

Claims

权 利 要 求
1. 一种半导体器件， 包括：
在衬底上的半导体层；
在上述半导体层上的隔离层；
与上述半导体层接触的源极和漏极，该源极和漏极的每个包括多个指， 并且上述源极的多个指与上述漏极的多个指相互交叉； 以及
在上述隔离层上的栅极， 该栅极位于上述源极和漏极之间并包括围绕 上述源极和漏极的上述多个指的闭环结构。
2. 根据权利要求 1所述的半导体器件， 其中， 上述栅极的首尾直接 相连或者通过互连线相连。
3. 根据权利要求 2所述的半导体器件， 其中， 在上述栅极的首尾直 接相连的情况下， 上述栅极的各个拐角都采用弧形结构， 并且上述源极和 漏极的与上述各个拐角对应的部分也采用弧形结构。
4. 根据权利要求 2所述的半导体器件， 其中， 在上述栅极的首尾通 过互连线相连的情况下， 上述漏极的与上述栅极和上述互连线的连接处对 应的部分采用弧形结构。
5. 根据权利要求 1所述的半导体器件， 其中， 上述闭环结构将上述 源极和漏极中的一个完全包围。
6. 根据权利要求 5所述的半导体器件， 其中， 上述源极和漏极中的 另一个位于上述栅极的***。
7. 根据权利要求 1所述的半导体器件， 其中， 上述源极和漏极的多 个指的尖端采用弧形结构， 并且上述栅极的与上述多个指的尖端的弧形结 构对应的部分也采用弧形结构。
8. 根据权利要求 1-7中任何一项所述的半导体器件， 还包括在上述 源极和漏极之间的上述隔离层上的介质层。
9. 根据权利要求 1-7中任何一项所述的半导体器件， 还包括场板结 构和 /或浮栅结构。
10. 根据权利要求 1-7中任何一项所述的半导体器件， 其中， 上述半 导体层和上述隔离层包括 III族氮化物半导体材料，其中 III价原子包括铟、 铝、 镓或其组合。
11. 根据权利要求 1-7中任何一项所述的半导体器件， 其中， 上述栅 极通过空气桥跨越上述源极或漏极连接到栅极引线焊盘， 或者通过互连线 连接到栅极引线烊盘。
12. 根据权利要求 1-7中任何一项所述的半导体器件， 其中， 上述源 极和栅极的引线详盘位于一侧， 而上述漏极的引线烊盘位于另一侧。
13. 根据权利要求 1-7中任何一项所述的半导体器件， 其中， 上述源 极和漏极的多个指的长度不同。
14. 一种用于制造半导体器件的方法， 包括以下步骤：
在衬底上沉积半导体层；
在上述半导体层上沉积隔离层；
形成与上述半导体层接触的源极和漏极， 其中该源极和漏极的每个包 括多个指， 并且上述源极的多个指与上述漏极的多个指相互交叉； 以及 在上述隔离层上， 在上述源极和漏极之间， 形成包括围绕上述源极和 漏极的上述多个指的闭环结构的栅极。
15. 根据权利要求 14所述的方法， 其中， 上述栅极的首尾直接相连 或者通过互连线相连以形成上述闭环结构。
16. 根据权利要求 15所述的方法， 其中， 在上述栅极的首尾直接相 连的情况下， 将上述栅极的各个拐角形成为弧形结构， 并且将上述源极和 漏极的与上述各个拐角对应的部分也形成为弧形结构。
17. 根据权利要求 15所述的方法， 其中， 在上述栅极的首尾通过互 连线相连的情况下， 将上述漏极的与上述栅极和上述互连线的连接处对应 的部分形成为弧形结构。
18. 根据权利要求 14所述的方法， 其中， 将上述源极和漏极的多个 指的尖端形成为弧形结构， 并且将上述栅极的与上述多个指的尖端的弧形 结构对应的部分也形成为弧形结构。
19. 根据权利要求 14-18中任何一项所述的方法， 其中， 将上述源极 和栅极的 3 ]线焊盘形成于一侧， 而将上述漏极的 I线焊盘形成于另一侧。
20. 根据权利要求 14-18中任何一项所述的方法， 其中， 将上述源极 和漏极的多个指形成为不同的长度。
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