WO2010090262A1 - エピタキシャルウエハ、窒化ガリウム系半導体デバイスを作製する方法、窒化ガリウム系半導体デバイス、及び酸化ガリウムウエハ - Google Patents
エピタキシャルウエハ、窒化ガリウム系半導体デバイスを作製する方法、窒化ガリウム系半導体デバイス、及び酸化ガリウムウエハ Download PDFInfo
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- WO2010090262A1 WO2010090262A1 PCT/JP2010/051617 JP2010051617W WO2010090262A1 WO 2010090262 A1 WO2010090262 A1 WO 2010090262A1 JP 2010051617 W JP2010051617 W JP 2010051617W WO 2010090262 A1 WO2010090262 A1 WO 2010090262A1
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- gallium oxide
- wafer
- gallium
- epitaxial
- gallium nitride
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 200
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 169
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 169
- 239000004065 semiconductor Substances 0.000 title claims abstract description 161
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 124
- 238000000034 method Methods 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title description 19
- 150000004767 nitrides Chemical class 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 72
- 230000003746 surface roughness Effects 0.000 claims description 31
- 239000013078 crystal Substances 0.000 claims description 13
- 229910002704 AlGaN Inorganic materials 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 10
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 144
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 10
- 239000013598 vector Substances 0.000 description 10
- -1 InGaN Inorganic materials 0.000 description 7
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 238000002441 X-ray diffraction Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000001000 micrograph Methods 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- MHYQBXJRURFKIN-UHFFFAOYSA-N C1(C=CC=C1)[Mg] Chemical compound C1(C=CC=C1)[Mg] MHYQBXJRURFKIN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000000295 emission spectrum Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
- C30B29/403—AIII-nitrides
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
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- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
Definitions
- the present invention relates to an epitaxial wafer, a method for producing a gallium nitride based semiconductor device, a gallium nitride based semiconductor device, and a gallium oxide wafer.
- Non-Patent Document 1 describes that a GaN layer is epitaxially grown on the (100) plane of a ⁇ -Ga 2 O 3 substrate. Further, a light emitting diode is fabricated on the (100) plane of the ⁇ -Ga 2 O 3 substrate, and this light emitting diode is In 0.12 Ga 0.88 N / In 0.03 Ga 0.97 N multiple quantum. Includes well structure.
- Kiyoshi SHIMAMURA et al. Japanese. Journal of Applied Physics, Vol.44, No. 1 2005, pp L7-L8
- Non-Patent Document 1 after a GaN buffer layer is grown at 600 degrees Celsius on the (100) plane of a ⁇ -Ga 2 O 3 substrate, a 1000 nm GaN layer is grown at 1070 degrees Celsius.
- the epitaxial wafer includes (a) a gallium oxide wafer having a main surface made of monoclinic gallium oxide, and (b) a buffer layer made of a group III nitride provided on the main surface of the gallium oxide wafer, (C) a first epitaxial layer provided on the buffer layer and made of a first gallium nitride semiconductor.
- the main surface of the gallium oxide wafer is inclined at an angle of 2 degrees or more and at an angle of 4 degrees or less with respect to the (100) plane of the monoclinic gallium oxide.
- the main surface of the gallium oxide wafer is inclined at an angle of 2 degrees or more and 4 degrees or less with respect to the (100) plane of monoclinic gallium oxide.
- the above inclination provides an epitaxial layer having a flat surface.
- the direction of inclination of the principal surface of the gallium oxide wafer may be the direction of the [001] axis of the monoclinic gallium oxide.
- gallium oxide is monoclinic, an epitaxial layer having a good morphology is provided by tilting toward the [001] axis.
- the crystal structure of the first gallium nitride semiconductor is a hexagonal crystal, and the normal of the main surface of the first epitaxial layer is the c-axis of the first gallium nitride semiconductor.
- An angle of 1 degree or less can be made.
- the surface of the epitaxial layer is provided with an inclination of an angle of 1 degree or less with respect to the c-axis of the gallium nitride semiconductor of the epitaxial layer.
- the surface roughness (RMS) on the main surface of the first epitaxial layer may be 0.5 nm or less in a 5 ⁇ m square area.
- the flatness of the main surface of the epitaxial layer is reduced to a surface roughness (RMS) of 0.5 nm or less in an area of 5 micrometers square.
- the first gallium nitride based semiconductor can be made of any one of GaN, AlGaN, InGaN, and AlN.
- This epitaxial wafer can be applied to a gallium nitride based semiconductor device using the semiconductor described above.
- the buffer layer may be made of GaN.
- a binary group III nitride semiconductor such as GaN can be used as a material for the buffer layer.
- the inclination angle is distributed in the main surface of the gallium oxide substrate, and is in an angle range of 2 degrees to 4 degrees over the entire main surface of the gallium oxide wafer. Can do.
- an epitaxial film having a good morphology can be provided over the entire main surface of the wafer.
- the main surface of the gallium oxide wafer is inclined at an angle of 2.5 degrees or more with respect to the (100) plane of the monoclinic gallium oxide and 3.5 degrees or less. Can be tilted at an angle.
- This gallium nitride semiconductor device includes (a) a gallium oxide supporting base having a main surface made of monoclinic gallium oxide, and (b) a laminated structure made of group III nitride.
- the laminated structure includes a buffer layer made of a group III nitride provided on the main surface of the gallium oxide support base, a first epitaxial layer made of a first gallium nitride semiconductor provided on the buffer layer, including.
- the main surface of the gallium oxide wafer is inclined at an angle of 2 degrees or more and at an angle of 4 degrees or less with respect to the (100) plane of the monoclinic gallium oxide.
- This gallium nitride based semiconductor device includes a laminated structure provided on a gallium oxide supporting base.
- a laminated structure is formed on a gallium oxide supporting substrate having a principal surface inclined at the above angle, this inclination provides an epitaxial layer having a flat surface. Therefore, the characteristics of the gallium nitride based semiconductor device are not bothered by poor flatness of the epitaxial surface.
- the stacked structure includes a second epitaxial layer formed on the buffer layer and made of a second gallium nitride based semiconductor, the first epitaxial layer, and the second epitaxial layer.
- An active layer provided between the first and second layers, wherein the gallium oxide wafer has conductivity, the first epitaxial layer has first conductivity, and the second epitaxial layer has a conductivity.
- the layer has a second conductivity opposite to the first conductivity, the active layer has a quantum well structure, and the gallium nitride based semiconductor device is a semiconductor light emitting device.
- This gallium nitride based semiconductor device includes a laminated structure for a light emitting device provided on a gallium oxide supporting base. Therefore, a gallium nitride based semiconductor light emitting device having good characteristics is provided without the characteristics of the gallium nitride based semiconductor device being bothered by poor flatness of the epitaxial surface.
- the stacked structure further includes a second epitaxial layer provided on the gallium oxide wafer, and the second epitaxial layer has a heterojunction with the first epitaxial layer.
- the band gap of the second gallium nitride based semiconductor is larger than the band gap of the first gallium nitride based semiconductor, and the heterojunction causes the first epitaxial layer and the second epitaxial layer to A two-dimensional electron gas is generated at the interface, and the gallium nitride based semiconductor device is a two-dimensional electron gas transistor.
- This gallium nitride based semiconductor device includes a laminated structure for a two-dimensional electron gas transistor provided on a gallium oxide support base. Therefore, there is provided a two-dimensional electron gas transistor having good characteristics without bothering the characteristics of the gallium nitride based semiconductor device due to poor flatness of the epitaxial surface.
- the gallium nitride based semiconductor device of the present invention comprises a source region composed of a first conductive gallium nitride based semiconductor region and a second conductive gallium nitride based semiconductor region, and the source region is separated from the first epitaxial layer.
- the gallium oxide wafer has conductivity
- the first epitaxial layer has first conductivity
- the gallium nitride based semiconductor device has a vertical electric field. It is an effect transistor.
- This gallium nitride based semiconductor device includes a structure for a vertical field effect transistor provided on a gallium oxide support substrate. Therefore, there is provided a vertical field effect transistor having good characteristics without bothering the characteristics of the gallium nitride based semiconductor device due to poor flatness of the epitaxial surface.
- the surface roughness (RMS) on the main surface of the uppermost layer of the laminated structure can be 0.5 nm or less in an area of 5 micrometers square.
- the main surface of the epitaxial layer exhibits good flatness.
- Still another aspect of the present invention is a method of manufacturing a gallium nitride based semiconductor device.
- This method includes (a) a step of preparing a gallium oxide wafer having a main surface made of monoclinic gallium oxide, and (b) a buffer layer made of a group III nitride on the main surface of the gallium oxide wafer. A step of growing; and (c) a step of growing a first epitaxial layer made of a first gallium nitride based semiconductor on the buffer layer.
- the main surface of the gallium oxide wafer is inclined at an angle of 2 degrees or more and at an angle of 4 degrees or less with respect to the (100) plane of the monoclinic gallium oxide.
- the main surface of the gallium oxide wafer is inclined at an angle of 2 degrees or more and 4 degrees or less with respect to the (100) plane of monoclinic gallium oxide.
- This tilt provides an epitaxial layer having a flat surface. Therefore, the characteristics of the gallium nitride based semiconductor device are not bothered by poor flatness of the epitaxial surface.
- the growth temperature of the buffer layer may be 400 degrees Celsius or more and 600 degrees Celsius or less.
- Still another aspect of the present invention is a gallium oxide wafer having a main surface made of monoclinic gallium oxide, wherein the main surface of the gallium oxide wafer is made of the monoclinic gallium oxide (100 ) Inclined with respect to the surface at an angle of 2 degrees or more and at an angle of 4 degrees or less.
- the main surface of the gallium oxide wafer is inclined at an angle of 2 degrees or more and 4 degrees or less with respect to the (100) plane of the monoclinic gallium oxide. Due to this inclination, the gallium nitride semiconductor epitaxially grown on the main surface of the gallium oxide wafer has a flat surface.
- the direction of inclination of the main surface of the gallium oxide wafer may be the direction of the [001] axis of the monoclinic gallium oxide.
- gallium oxide is monoclinic, an epitaxial layer having a good morphology is provided by tilting toward the [001] axis.
- an epitaxial wafer including a gallium nitride based semiconductor film provided on a gallium oxide wafer and having a flat surface.
- a gallium nitride based semiconductor device including a gallium nitride based semiconductor film provided on a gallium oxide wafer is provided.
- a method for producing this gallium nitride based semiconductor device is provided.
- an epitaxial wafer, a gallium nitride based semiconductor device, and a gallium oxide wafer for a method of making the epitaxial wafer and the gallium nitride based semiconductor device.
- FIG. 1 is a drawing showing main steps of a method for producing a gallium nitride based semiconductor device and an epitaxial wafer according to the present embodiment.
- FIG. 2 is a drawing showing a monoclinic gallium oxide wafer and a crystal lattice of monoclinic gallium oxide.
- FIG. 3 is a drawing schematically showing a gallium nitride based semiconductor device manufactured through steps S101 to S103.
- FIG. 4 is a drawing showing the relationship between the inclination angle (off angle) of the main surface of the gallium oxide substrate and the morphology of the surface of the GaN epitaxial film.
- FIG. 1 is a drawing showing main steps of a method for producing a gallium nitride based semiconductor device and an epitaxial wafer according to the present embodiment.
- FIG. 2 is a drawing showing a monoclinic gallium oxide wafer and a crystal lattice of monoclinic gallium oxide.
- FIG. 3 is a drawing schematically showing
- FIG. 5 is a drawing showing a scanning electron microscope image representing the surface of an epitaxial wafer using a gallium oxide substrate having a zero off angle.
- FIG. 6 is a drawing showing the main steps of a method for producing a gallium nitride based semiconductor device and an epitaxial wafer according to the present embodiment.
- FIG. 7 is a drawing showing the structure of a light emitting diode in Example 2.
- FIG. 8 is a drawing showing the relationship between the off-angle of the main surface of the gallium oxide substrate, the surface roughness and off-angle of the semiconductor layer serving as the foundation for active layer growth, and the light output of the LED structure.
- FIG. 9 is a drawing showing the main steps of a method for manufacturing a high electron mobility transistor and an epitaxial wafer according to the present embodiment.
- FIG. 10 is a drawing schematically showing a high electron mobility transistor and an epitaxial wafer manufactured according to the process flow of FIG.
- FIG. 11 is a drawing showing the main steps of a method for producing a vertical field effect transistor and an epitaxial wafer according to the present embodiment.
- FIG. 12 is a drawing schematically showing a vertical field effect transistor and an epitaxial wafer manufactured according to the process flow of FIG.
- FIG. 1 is a drawing showing main steps of a method for producing a gallium nitride based semiconductor device and an epitaxial wafer according to the present embodiment.
- step S101 of the process flow shown in FIG. 1A a gallium oxide wafer 11 having a main surface made of monoclinic gallium oxide is prepared.
- a gallium oxide wafer 11 is shown.
- the wafer 11 is made of, for example, ⁇ -Ga 2 O 3 single crystal.
- the wafer 11 includes a main surface 11a and a back surface 11b, and the main surface 11a and the back surface 11b are parallel to each other.
- the main surface 11a of the wafer 11 is inclined at an angle of 2 degrees or more with respect to the (100) plane of monoclinic gallium oxide and at an angle A OFF of 4 degrees or less.
- the main surface 11a of the wafer 11 is inclined at an angle of 2 degrees or more and 4 degrees or less with respect to the (100) plane of monoclinic gallium oxide. Due to this inclination, the gallium nitride based semiconductor epitaxially grown on the gallium oxide wafer main surface 11a has a flat surface.
- the angle A OFF of the main surface of the gallium oxide wafer can be distributed over the entire main surface 11a.
- the surface of the gallium nitride semiconductor epitaxially grown on the gallium oxide wafer main surface 11a has a good morphology over the entire wafer main surface 11a.
- the crystal coordinate system CR is a shaft, b axis And c-axis.
- FIG. 2 (b) a crystal lattice of monoclinic gallium oxide is shown.
- the lattice constants of the a-axis, b-axis, and c-axis of the monoclinic gallium oxide crystal lattice are 1.223 nm, 0.304 nm, and 0.58 nm, respectively.
- Vectors Va, Vb, and Vc indicate the directions of the a-axis, b-axis, and c-axis, respectively.
- the vectors Va and Vb define the (001) plane
- the vectors Vb and Vc define the (100) plane
- the vectors Vc and Va define the (010) plane.
- the angle ⁇ formed by the vectors Va and Vb and the angle ⁇ formed by the vectors Vb and Vc are 90 degrees
- the angle ⁇ formed by the vectors Vc and Va is 103.7 degrees.
- the wafer main surface 11a is shown by a one-dot chain line in FIG. According to this wafer 11, since gallium oxide is monoclinic, an epitaxial layer having a good morphology can be grown on the wafer main surface 11a by tilting toward the [001] axis.
- step S102 shown in FIG. 1 a laminated structure including a plurality of group III nitride films is formed to produce an epitaxial wafer.
- the group III nitride film is grown by, for example, a metal organic chemical vapor deposition (MOVPE) method.
- MOVPE metal organic chemical vapor deposition
- the buffer layer 13 is grown on the main surface 11 a of the wafer 11.
- the buffer layer 13 is made of a group III nitride such as GaN.
- the growth reactor 10 is supplied with a source gas G0 containing trimethylgallium (TMG) and ammonia (NH 3 ).
- TMG trimethylgallium
- NH 3 ammonia
- the growth temperature T1 of the buffer layer 13 is in the range of, for example, 400 degrees Celsius or more and 600 degrees Celsius or less, and the buffer layer 13 is called a so-called low temperature buffer layer.
- the film thickness of the buffer layer 13 can be in the range of 10 nanometers or more and 50 nanometers or less, for example. Subsequently, after raising the temperature of the growth furnace 10 to a temperature T2 higher than the growth temperature T1, as shown in FIG. 1D, the first gallium nitride based semiconductor is formed on the main surface 13a of the buffer layer 13. An epitaxial layer 15 is grown.
- the epitaxial layer 15 is made of hexagonal group III nitride such as GaN, AlGaN, InGaN, AlN, or the like.
- the film thickness of the epitaxial layer 15 can be in the range of not less than 300 nanometers and not more than 10 micrometers, for example.
- the growth reactor 10 is supplied with a source gas G1 containing trimethylgallium (TMG) and ammonia (NH 3 ).
- TMG trimethylgallium
- NH 3 ammonia
- the growth temperature T2 of the epitaxial layer 15 is in a range of 900 degrees Celsius or more and 1200 degrees Celsius or less
- the epitaxial layer 15 is a semiconductor layer constituting a gallium nitride based semiconductor device, and is an undoped, p-type dopant. Addition and can be an n-type dopant.
- a dopant gas is supplied in addition to the source gas when the epitaxial layer 15 is grown.
- the dopant for example, cyclopentadienyl magnesium (Cp 2 Mg) can be used for p-type conductivity, and for example, silane (SiH 4 ) can be used for n-type conductivity.
- Epitaxial wafer E is obtained by the conventional deposition of gallium nitride semiconductor.
- the epitaxial wafer E includes a gallium oxide wafer 11, a buffer layer 13, and an epitaxial layer 15.
- the flatness of the main surface 15a of the epitaxial layer 15 is reduced to a surface roughness (RMS) of 0.5 nm or less in a 5 micrometer square area.
- RMS surface roughness
- This surface roughness is measured using an atomic force microscope (AFM).
- a plurality of electrodes are formed on the epitaxial wafer E.
- the first electrode 17 a is formed on the epitaxial layer main surface 15 a of the epitaxial wafer E.
- the first electrode 17a is, for example, a Schottky electrode, and the Schottky electrode is made of, for example, gold (Au).
- the first electrode 17a forms a Schottky junction 19 in the epitaxial layer.
- the second electrode 17b is formed on the gallium oxide substrate back surface 11b of the epitaxial wafer E.
- the second electrode 17b is, for example, an ohmic electrode.
- the epitaxial wafer E can include one or a plurality of gallium nitride based semiconductor layers grown in order on the epitaxial layer 15. These gallium nitride based semiconductor layers are grown, for example, by metal organic vapor phase epitaxy in step S102.
- the epitaxial wafer E can include another epitaxial layer 23 grown on the epitaxial layer 15, for example.
- the epitaxial layer 15 exhibits undoped or n-type conductivity
- the epitaxial layer 23 is made of a p-type gallium nitride semiconductor layer.
- the epitaxial layer 23 forms a pn junction 25 with the epitaxial layer 15.
- the first electrode 27 a is formed on the epitaxial layer main surface 23 a of the epitaxial wafer E.
- the first electrode 27a is, for example, a p ohmic electrode.
- the second electrode 17b is formed on the gallium oxide substrate back surface 11b of the epitaxial wafer E.
- steps S101 to S103 the gallium nitride based semiconductor device shown in FIG. 3B is manufactured. This gallium nitride based semiconductor device is a pn junction diode.
- the epitaxial wafer according to the present embodiment can provide a gallium nitride based semiconductor multilayer structure for a light emitting element, a transistor, etc., as will be described later, in addition to a pn junction diode.
- Example 1 Eleven monoclinic gallium oxide substrates were prepared. The main surfaces of these gallium oxide substrates were inclined in the range of 0 ° to 5 ° with respect to the (100) plane of the single crystal of the gallium oxide substrate. The pitch of the inclination angle was 0.5 degrees. The direction of inclination was the [001] axis direction of the single crystal of the gallium oxide substrate. The tilt angle and direction of tilt were determined by X-ray diffraction.
- the GaN film is formed on these gallium oxide substrates using MOVPE as follows.
- a buffer layer and a GaN epitaxial film were deposited.
- a source gas containing NH 3 , TMG and SiH 4 was supplied to the growth furnace, and a low temperature GaN buffer layer was grown on the gallium oxide substrate at a temperature of 500 degrees Celsius.
- the thickness of the GaN buffer layer was 25 nanometers.
- a source gas containing NH 3 , TMG and SiH 4 was supplied to the growth furnace to grow a GaN epitaxial layer on the buffer layer.
- the thickness of the GaN epitaxial layer was 3 micrometers.
- FIG. 4 is a drawing showing the relationship between the inclination angle (off angle) of the main surface of the gallium oxide substrate and the morphology of the surface of the GaN epitaxial film.
- FIG. 5 is a drawing showing a scanning electron microscope image representing the surface of an epitaxial wafer using a gallium oxide substrate having a zero off angle.
- the scale shown in FIG. 5 is 10 ⁇ m.
- a step difference of about several micrometers is formed in the GaN epitaxial film on the gallium oxide substrate having a zero off angle or a small off angle, and therefore, the surface roughness of the GaN epitaxial film. Is big.
- a terrace-like flat region is formed between the steps.
- the surface morphology shows a so-called terraced field appearance. For this reason, when measuring the surface roughness (RMS) using an atomic force microscope, the surface roughness was measured at different positions on the surface of the GaN epitaxial film, and then the maximum value of these measured values was obtained. .
- RMS surface roughness
- the GaN epitaxial layer is formed on the low-temperature GaN buffer layer under the film formation conditions described above. Grew up. All of these epitaxial wafers showed a morphology similar to the waved morphology shown in FIG. Therefore, the scanning electron microscope image of the epitaxial film at an off angle of zero degrees is considered not to be caused by the film formation temperature of the buffer layer but by the zero off angle of the main surface of the gallium oxide substrate. In the fabrication of the epitaxial wafer shown in FIG. 4, a low temperature GaN buffer layer was formed at 500 degrees Celsius.
- the surface roughness was measured in an area of 5 micrometers square using an atomic force microscope. Referring to FIG. 4, the surface roughness and the off angle of the epitaxial film once decrease as the off angle of the main surface of the gallium oxide substrate increases from the just (100) plane. However, the surface roughness and the off angle of the epitaxial film increase as the off angle of the main surface of the gallium oxide substrate increases in the range of the off angle exceeding 3 degrees. The surface roughness and surface morphology were greatly improved in the angle range near the off angle of 3 degrees.
- the surface roughness was 1.3 or less within the range of an off angle of 1.5 degrees to 4.5 degrees on the substrate surface. Further, the surface roughness was less than 0.5 (0.47 or less) in the range of the off angle of 2.0 degrees or more and 4.0 degrees or less on the substrate surface. Further, the surface roughness was 0.35 or less in the range of the off angle of 2.5 degrees to 3.5 degrees on the substrate surface. According to the study by the inventors, the surface roughness in the range of the off angle of 2.0 degrees or more and 4.0 degrees or less is the surface roughness of the GaN epitaxial film on the sapphire substrate in the production of a semiconductor light emitting device or a semiconductor electronic device. This is a sufficiently acceptable value as compared to 0.20 nanometer. When the off angle is in the range of 2.5 degrees or more and 3.5 degrees or less, device characteristic deterioration due to the surface morphology is reduced.
- the angle formed between the c-axis direction of the GaN epitaxial film and the normal axis of the GaN epitaxial film surface was estimated using an X-ray diffraction method.
- the off-angle of the GaN film was 1.5 degrees or less in the range of the off-angle of 1.5 degrees or more and 4.5 degrees or less on the substrate surface. Further, the off angle of the GaN film was less than 1 degree (0.9 degrees or less) in the range of the off angle of 2.0 degrees or more and 4.0 degrees or less on the substrate surface. Furthermore, the off angle of the GaN film was 0.6 degrees or less in the range of the off angle of 2.5 degrees or more and 3.5 degrees or less of the substrate surface. According to the study by the inventors, when the off-angle of the gallium oxide substrate is 2 to 4 degrees, the off-angle of the GaN epitaxial film is less than 1 degree, and epitaxial growth with good surface flatness is possible.
- the epitaxial wafer E is good over the entire main surface of the epitaxial wafer E when it is in the angle range of 2 degrees to 4 degrees over the entire main surface of the gallium oxide substrate.
- a morphology epitaxial film is provided.
- the inclination angle of the main surface of the gallium oxide wafer is inclined at an angle of 2.5 degrees or more and an angle of 3.5 degrees or less with respect to the (100) plane of monoclinic gallium oxide, A higher planar epitaxial layer main surface can be obtained.
- an epitaxial wafer including a GaN film has been described.
- the off-angle contribution in the gallium oxide substrate main surface is not limited to GaN, but on the gallium oxide substrate main surface.
- the epitaxial film can be made of AlGaN, InGaN, InAlGaN, AlN, or the like. Therefore, this epitaxial wafer E can be applied to a gallium nitride based semiconductor device.
- FIG. 6 is a drawing showing the main steps of a method for producing a gallium nitride based semiconductor device and an epitaxial wafer according to the present embodiment.
- step S101 of the flowchart shown in FIG. 6 a gallium oxide wafer 11 having a main surface made of monoclinic gallium oxide is prepared.
- step S102 a laminated structure including a plurality of group III nitride films is formed to produce an epitaxial wafer.
- the group III nitride film is grown by, for example, a metal organic chemical vapor deposition (MOVPE) method.
- MOVPE metal organic chemical vapor deposition
- step S105 the wafer 11 is placed on the susceptor of the growth reactor 10.
- the buffer layer 13 is grown on the main surface 11 a of the wafer 11.
- a first conductivity type epitaxial layer is grown on the main surface 13a of the buffer layer 13 in step S106.
- This epitaxial layer is made of a gallium nitride based semiconductor.
- the first conductivity type epitaxial layer is made of hexagonal group III nitride such as n-type GaN, n-type AlGaN, n-type InAlGaN, n-type InAlN, and the like.
- a source gas containing TMG, NH 3 and SiH 4 is supplied to the growth reactor 10 to grow an n-type GaN film.
- the growth temperature T2 of the first conductivity type epitaxial layer is, for example, in the range of 900 degrees Celsius or more and 1200 degrees Celsius or less, and the first conductivity type epitaxial layer is a gallium nitride based semiconductor device. It is a semiconductor layer which comprises.
- an active layer is formed on the first conductivity type epitaxial layer.
- the active layer includes well layers and barrier layers arranged alternately.
- the well layer is made of, for example, GaN, InGaN, InAlGaN, or the like.
- the barrier layer is made of, for example, GaN, InGaN, InAlGaN, or the like.
- the growth temperature of the well layer is, for example, in the range of 500 degrees Celsius or more and 900 degrees Celsius, and the growth temperature of the barrier layer is, for example, in the range of 550 degrees Celsius or more and 950 degrees Celsius or less.
- a second conductivity type epitaxial layer is formed on the active layer.
- the second conductivity type epitaxial layer can include, for example, a p-type electron block layer and a p-type contact layer.
- An epitaxial wafer can be obtained by depositing a conventional gallium nitride based semiconductor.
- the epitaxial wafer includes a gallium oxide wafer 11 and a semiconductor stack grown on the gallium oxide wafer 11.
- the semiconductor stack includes a first conductivity type epitaxial layer, a second conductivity type epitaxial layer, and an active layer, and the active layer is provided between the first conductivity type epitaxial layer and the second conductivity type epitaxial layer.
- step S109 the epitaxial wafer is etched to form a semiconductor mesa.
- a part of the semiconductor stack is removed, and a part of the first conductivity type epitaxial layer in the semiconductor stack is exposed.
- a first electrode is formed on the exposed portion of the conductive epitaxial layer, and a second electrode is formed on the upper surface of the semiconductor mesa.
- FIG. 7 is a drawing showing the structure of a light emitting diode in Example 2.
- the light emitting diode LED includes a gallium oxide supporting base 31 having a main surface made of monoclinic gallium oxide and a laminated structure 33 made of group III nitride.
- the laminated structure 33 has a semiconductor mesa shape.
- the semiconductor mesa includes a low-temperature GaN buffer layer 35, an n-type GaN layer 37, an active layer 39 having a quantum well structure, and a p-type gallium nitride based semiconductor layer 41.
- the p-type gallium nitride based semiconductor layer 41 includes, for example, a p-type AlGAn electron block layer and a p-type GaN contact layer.
- An example LED structure is as follows. Low temperature GaN buffer layer 35: 25 nanometers; n-type GaN layer 37: 3 micrometers; Active layer 39: MQW of 6 well layers, Barrier layer 39a: GaN layer, thickness 15 nm; Well layer 39b: InGaN layer, thickness 3 nm; P-type AlGAn electron blocking layer of the gallium nitride based semiconductor layer 41: 20 nm; P-type GaN contact layer of the gallium nitride based semiconductor layer 41: 50 nm.
- Example 1 eleven monoclinic gallium oxide substrates were prepared.
- the main surfaces of these gallium oxide substrates were 0 degrees or more and 5 degrees with respect to the (100) plane of the single crystal of the gallium oxide substrate. It was inclined in the following range.
- the pitch of the inclination angle was 0.5 degrees.
- the direction of inclination was the [001] axis direction of the single crystal of the gallium oxide substrate.
- the tilt angle and direction of tilt were determined by X-ray diffraction.
- the MOVPE method is used on these gallium oxide substrates as described above.
- an LED structure was formed.
- a p-side electrode was formed on the upper surface of the semiconductor mesa having this LED structure, and an n-side electrode was formed in the exposed region of the n-type semiconductor.
- the surface roughness was measured in an area of 5 micrometers square using an atomic force microscope. Referring to FIG. 8, the surface roughness and the off angle of the semiconductor layer serving as a base for the active layer growth once decrease as the off angle of the main surface of the gallium oxide substrate increases from the just (100) plane. However, the surface roughness and the off angle of the epitaxial film increase as the off angle of the main surface of the gallium oxide substrate increases in the range of the off angle exceeding 3 degrees. The surface roughness and morphology were greatly improved in the angle range near the off angle of 3 degrees.
- the surface roughness was 1.3 or less within the range of an off angle of 1.5 degrees to 4.5 degrees on the substrate surface.
- the surface roughness was less than 0.5 (for example, 0.47 or less) in the range of the off angle of 2.0 degrees or more and 4.0 degrees or less on the substrate surface.
- the surface roughness was 0.35 or less in the range of the off angle of 2.5 degrees to 3.5 degrees on the substrate surface.
- the surface roughness in the range of the off angle of 2.0 degrees to 4.0 degrees is that the surface roughness of the GaN epitaxial film on the sapphire substrate is 0.20 nanometers. In comparison, the values are sufficiently acceptable in the production of light emitting diodes.
- the off angle is in the range of 2.0 degrees or more and 4.0 degrees or less, deterioration of light emission characteristics due to morphology is reduced.
- the angle formed between the c-axis direction in the epitaxial film serving as the base for the active layer growth and the normal axis on the surface of the GaN epitaxial film was estimated using the X-ray diffraction method.
- the off-angle of the GaN film was 1.5 degrees or less in the range of the off-angle of 1.5 degrees or more and 4.5 degrees or less on the substrate surface. Further, the off angle of the GaN film was less than 1 degree (for example, 0.9 degree or less) in the range of the off angle of the substrate surface of 2.0 degrees or more and 4.0 degrees or less. Furthermore, the off angle of the GaN film was 0.6 degrees or less in the range of the off angle of 2.5 degrees or more and 3.5 degrees or less of the substrate surface. According to the study by the inventors, when the off-angle of the gallium oxide substrate is 2 to 4 degrees, the off-angle of the GaN epitaxial film is less than 1 degree, and epitaxial growth with good surface flatness is possible.
- a power source is connected between one of the p-side electrodes (electrode size: for example, 0.4 mm ⁇ 0.4 mm) arranged on the substrate product and the n-side electrode, and a forward bias is applied to the light emitting diode LED.
- the light-emitting diode LED includes a laminated structure 33 for a light-emitting device provided on a gallium oxide support base 31 separated from a gallium oxide substrate 32. Therefore, a light emitting diode LED having good light emitting characteristics is provided without the characteristics of the light emitting diode LED being bothered by poor flatness of the epitaxial surface.
- FIG. 9 is a drawing showing the main steps of a method of manufacturing a high electron mobility transistor and an epitaxial wafer for this device according to the present embodiment.
- FIG. 10 is a drawing schematically showing a high electron mobility transistor and an epitaxial wafer manufactured according to the process flow of FIG.
- step S101 of the flowchart shown in FIG. 9 a gallium oxide wafer 51 having a main surface made of monoclinic gallium oxide is prepared.
- step S105 as in FIG. 2B, the wafer 51 is placed on the susceptor of the growth reactor.
- a low temperature buffer layer 53 is grown on the main surface 51 a of the wafer 51.
- an epitaxial layer 55 is grown on the main surface 53a of the buffer layer 53 in step S110.
- the epitaxial layer 55 is made of a gallium nitride based semiconductor.
- the epitaxial layer 55 is made of hexagonal group III nitride such as undoped GaN, undoped AlGaN, undoped InAlGaN, undoped InGaN, or the like.
- a source gas containing TMG and NH 3 is supplied to the growth furnace to grow an undoped GaN film.
- the growth temperature T2 of the epitaxial layer 55 is, for example, in the range of not less than 900 degrees Celsius and not more than 1200 degrees Celsius.
- another epitaxial layer 57 is grown on the main surface 55a of the epitaxial layer 55.
- the epitaxial layer 57 is made of a gallium nitride based semiconductor, and the band gap of the epitaxial layer 57 is larger than the band gap of the epitaxial layer 55.
- the epitaxial layer 57 is made of hexagonal group III nitride such as undoped GaN, undoped AlGaN, undoped InAlGaN, undoped InAlN, or the like.
- the epitaxial layer 57 is made of AlGaN
- a raw material gas containing trimethylaluminum (TMA), TMG and NH 3 is supplied to the growth furnace to grow an undoped AlGaN film.
- TMA trimethylaluminum
- the growth temperature of the epitaxial layer 57 is, for example, in the range of not less than 900 degrees Celsius and not more than 1300 degrees Celsius.
- the epitaxial layer 57 forms a heterojunction 61a with the epitaxial layer 55, and a two-dimensional electron gas layer 61b is generated in the epitaxial layer 55 along the heterojunction 61a.
- the gate electrode 63a, the source electrode 63b, and the drain electrode 63c are formed on the epitaxial wafer E HEMT .
- the gate electrode 63a is a Schottky electrode, and the source electrode 63b and the drain electrode 63c are ohmic electrodes.
- the gate electrode 63a controls the current flowing from the drain electrode 63c to the source electrode 63b by changing the electron density of the channel along the heterojunction 61a according to the gate voltage.
- the high electron mobility transistor HEMT includes a laminated structure 59 provided on a gallium oxide support base 52 separated from the gallium oxide substrate 51. Since the main surface 52a of the gallium oxide support base 52 is inclined at the above angle, the inclination provides the epitaxial layer 57 having a flat surface. For this reason, the characteristics of the high electron mobility transistor HEMT made of a gallium nitride semiconductor are not bothered by poor flatness of the epitaxial surface.
- FIG. 11 is a drawing showing the main steps of a method for producing a vertical field effect transistor and an epitaxial wafer according to the present embodiment.
- FIG. 12 is a drawing schematically showing a vertical field effect transistor and an epitaxial wafer manufactured according to the process flow of FIG.
- step S101 of the flowchart shown in FIG. 11 a gallium oxide wafer 51 having a main surface made of monoclinic gallium oxide is prepared.
- step S105 as in FIG. 2B, the wafer 51 is placed on the susceptor of the growth reactor.
- a low temperature buffer layer 53 is grown on the main surface 51 a of the wafer 51.
- an epitaxial layer 65 is grown on the main surface 53a of the buffer layer 53 in step S110.
- the epitaxial layer 65 is made of a gallium nitride semiconductor.
- the epitaxial layer 65 is made of hexagonal group III nitride such as n-type GaN, n-type AlGaN, n-type InAlGaN, n-type InAlN, and the like.
- a source gas containing TMG, NH 3 and SiH 4 is supplied to the growth furnace to grow an n-type GaN film.
- the majority carriers of the n-type GaN film are electrons.
- the growth temperature of the epitaxial layer 65 is, for example, in the range of not less than 900 degrees Celsius and not more than 1200 degrees Celsius.
- an n-type source semiconductor region 67 and a p-type well semiconductor region 69 are formed on the surface of the epitaxial layer 65.
- the n-type source semiconductor region 67 and the p-type wafer semiconductor region 69 can be made of a gallium nitride-based semiconductor such as GaN, for example, by using photolithography, etching, and selective growth.
- the n-type source semiconductor region 67 is isolated from the epitaxial layer 65 by the p-type well semiconductor region 69.
- One end of the p-type well semiconductor region 69 appears on the surface of the semiconductor stack 71.
- a gate electrode 75 a is formed on one end of the p-type wafer semiconductor region 69 via an insulating film 73, and a source electrode 75 b is formed on the n-type source semiconductor region 67.
- a drain electrode 75c is formed.
- the gate electrode 75a forms a surface inversion layer 77 at one end of the p-type wafer semiconductor region 69 via the insulating film 73 in accordance with the gate voltage, and the epitaxial layer 65 in the n-type drift layer region and the n-type source semiconductor region 67 to control the electrical path between.
- This vertical field effect transistor FET includes a laminated structure 59 provided on a gallium oxide support base 52 separated from the gallium oxide substrate 51. Since the main surface 52a of the gallium oxide support base 52 is inclined at the above angle, the inclination provides the epitaxial layer 65 having a flat surface. Therefore, the characteristics of the vertical field effect transistor FET made of a gallium nitride semiconductor are not bothered by the poor flatness of the epitaxial surface.
- barrier layer 39b ... well layer, 41 ... gallium nitride based semiconductor layer, 51 ... wafer, 52 ... oxidation Gallium support base, 53 ... buffer layer, 55 ... epitaxial layer, 57 ... epitaxial layer, 61a ... heterojunction, 61b
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Abstract
Description
11枚の単斜晶系酸化ガリウム基板を準備した。これらの酸化ガリウム基板の主面は、酸化ガリウム基板の単結晶の(100)面に対して0度以上5度以下の範囲で傾斜していた。傾斜角度のピッチは0.5度であった。傾斜の方向は、酸化ガリウム基板の単結晶の[001]軸方向であった。傾斜角及び傾斜の方向は、X線回折法によって決定された。
図7は、実施例2における発光ダイオードの構造を示す図面である。発光ダイオードLEDは、単斜晶系酸化ガリウムからなる主面を有する酸化ガリウム支持基体31と、III族窒化物からなる積層構造33とを備える。積層構造33は、半導体メサの形状を成している。半導体メサは、低温GaNバッファ層35と、n型GaN層37と、量子井戸構造の活性層39と、p型窒化ガリウム系半導体層41とを含む。p型窒化ガリウム系半導体層41は、例えばp型AlGAn電子ブロック層及びp型GaNコンタクト層を含む。
低温GaNバッファ層35:25ナノメートル;
n型GaN層37:3マイクロメートル;
活性層39:6つの井戸層のMQW、
障壁層39a:GaN層、厚さ15nm;
井戸層39b:InGaN層、厚さ3nm;
窒化ガリウム系半導体層41のp型AlGAn電子ブロック層:20nm;
窒化ガリウム系半導体層41のp型GaNコンタクト層:50nm。
Claims (20)
- 窒化ガリウム系半導体デバイスのためのエピタキシャルウエハであって、
単斜晶系酸化ガリウムからなる主面を有する酸化ガリウムウエハと、
前記酸化ガリウムウエハの前記主面上に設けられIII族窒化物からなるバッファ層と、
前記バッファ層上に設けられ第1の窒化ガリウム系半導体からなる第1のエピタキシャル層と
を備え、
前記酸化ガリウムウエハの前記主面は、前記単斜晶系酸化ガリウムの(100)面に対して2度以上の角度で傾斜すると共に4度以下の角度で傾斜する、ことを特徴とするエピタキシャルウエハ。 - 前記酸化ガリウムウエハの前記主面おける傾斜の方向は、前記単斜晶系酸化ガリウムの[001]軸の方向である、ことを特徴とする請求項1に記載されたエピタキシャルウエハ。
- 前記第1の窒化ガリウム系半導体の結晶構造は六方晶であり、
前記第1のエピタキシャル層の主面の法線は、前記第1の窒化ガリウム系半導体のc軸に対して1度以下の角度を成す、ことを特徴とする請求項1又は請求項2に記載されたエピタキシャルウエハ。 - 前記第1のエピタキシャル層の主面における表面粗さ(RMS)は5マイクロメートル角のエリアにおいて0.5nm以下である、ことを特徴とする請求項1~請求項3のいずれか一項に記載されたエピタキシャルウエハ。
- 前記第1の窒化ガリウム系半導体はGaNからなる、ことを特徴とする請求項1~請求項4のいずれか一項に記載されたエピタキシャルウエハ。
- 前記第1の窒化ガリウム系半導体はAlGaNからなる、ことを特徴とする請求項1~請求項4のいずれか一項に記載されたエピタキシャルウエハ。
- 前記第1の窒化ガリウム系半導体はInGaNからなる、ことを特徴とする請求項1~請求項4のいずれか一項に記載されたエピタキシャルウエハ。
- 前記第1の窒化ガリウム系半導体はAlNからなる、ことを特徴とする請求項1~請求項4のいずれか一項に記載されたエピタキシャルウエハ。
- 前記バッファ層は、GaNからなる、ことを特徴とする請求項1~請求項8のいずれか一項に記載されたエピタキシャルウエハ。
- 前記傾斜の角度は前記酸化ガリウム基板の前記主面において分布しており、前記酸化ガリウム基板の前記主面の全体にわたって2度以上4度以下の角度範囲にある、ことを特徴とする請求項1~請求項9のいずれか一項に記載されたエピタキシャルウエハ。
- 前記酸化ガリウムウエハの前記主面は、前記単斜晶系酸化ガリウムの(100)面に対して2.5度以上の角度で傾斜すると共に3.5度以下の角度で傾斜する、ことを特徴とする請求項1~請求項10のいずれか一項に記載されたエピタキシャルウエハ。
- 窒化ガリウム系半導体デバイスであって、
単斜晶系酸化ガリウムからなる主面を有する酸化ガリウム支持基体と、
III族窒化物からなる積層構造と
を備え、
前記積層構造は、前記酸化ガリウム支持基体の前記主面上に設けられIII族窒化物からなるバッファ層と、前記バッファ層上に設けられ第1の窒化ガリウム系半導体からなる第1のエピタキシャル層とを含み、
前記酸化ガリウム支持基体の前記主面は、前記単斜晶系酸化ガリウムの(100)面に対して2度以上の角度で傾斜すると共に4度以下の角度で傾斜する、ことを特徴とする窒化ガリウム系半導体デバイス。 - 前記積層構造は、前記バッファ層上に設けられ第2の窒化ガリウム系半導体からなる第2のエピタキシャル層と、前記第1のエピタキシャル層と前記第2のエピタキシャル層との間に設けられた活性層とを更に含み、
前記酸化ガリウムウエハは導電性を有しており、
前記第1のエピタキシャル層は第1導電性を有しており、
前記第2のエピタキシャル層は前記第1導電性と反対の第2導電性を有しており、
前記活性層は量子井戸構造を有しており、
当該窒化ガリウム系半導体デバイスは半導体発光素子である、ことを特徴とする請求項12に記載された窒化ガリウム系半導体デバイス。 - 前記積層構造は、前記酸化ガリウム支持基体上に設けられた第2のエピタキシャル層を更に含み、
前記第2のエピタキシャル層は前記第1のエピタキシャル層にヘテロ接合を成し、
前記第2の窒化ガリウム系半導体のバンドギャップは前記第1の窒化ガリウム系半導体のバンドギャップよりも大きく、
前記ヘテロ接合により、前記第1のエピタキシャル層と前記第2のエピタキシャル層との界面に二次元電子ガスが生成され、
当該窒化ガリウム系半導体デバイスは二次元電子ガストランジスタである、ことを特徴とする請求項12に記載された窒化ガリウム系半導体デバイス。 - 第1導電性の窒化ガリウム系半導体領域からなるソース領域と、
第2導電性の窒化ガリウム系半導体領域からなり前記ソース領域を前記第1のエピタキシャル層から隔てるウエル領域と
を更に備え、
前記酸化ガリウム支持基体は導電性を有しており、
前記第1のエピタキシャル層は第1導電性を有しており、
当該窒化ガリウム系半導体デバイスは縦型電界効果トランジスタである、ことを特徴とする請求項12に記載された窒化ガリウム系半導体デバイス。 - 前記積層構造の最上層の主面における表面粗さ(RMS)は5マイクロメートル平方において0.5nm以下である、ことを特徴とする請求項12~請求項15のいずれか一項に記載された窒化ガリウム系半導体デバイス。
- 窒化ガリウム系半導体デバイスを作製する方法であって、
単斜晶系酸化ガリウムからなる主面を有する酸化ガリウムウエハを準備する工程と、
前記酸化ガリウムウエハの前記主面上にIII族窒化物からなるバッファ層を成長する工程と、
第1の窒化ガリウム系半導体からなる第1のエピタキシャル層を前記バッファ層上に成長する工程と
を備え、
前記酸化ガリウムウエハの前記主面は、前記単斜晶系酸化ガリウムの(100)面に対して2度以上の角度で傾斜すると共に4度以下の角度で傾斜する、ことを特徴とする方法。 - 前記バッファ層の成長温度は、摂氏400度以上であり、摂氏600度以下である、ことを特徴とする請求項17に記載された方法。
- 単斜晶系酸化ガリウムからなる主面を有する酸化ガリウムウエハであって、
前記酸化ガリウムウエハの前記主面は、前記単斜晶系酸化ガリウムの(100)面に対して2度以上の角度で傾斜すると共に4度以下の角度で傾斜する、ことを特徴とする酸化ガリウムウエハ。 - 前記酸化ガリウムウエハの前記主面おける傾斜の方向は、前記単斜晶系酸化ガリウムの[001]軸の方向である、ことを特徴とする請求項19に記載された酸化ガリウムウエハ。
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