WO2010084533A1 - 半導体集積回路の電源配線構造 - Google Patents
半導体集積回路の電源配線構造 Download PDFInfo
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- WO2010084533A1 WO2010084533A1 PCT/JP2009/004119 JP2009004119W WO2010084533A1 WO 2010084533 A1 WO2010084533 A1 WO 2010084533A1 JP 2009004119 W JP2009004119 W JP 2009004119W WO 2010084533 A1 WO2010084533 A1 WO 2010084533A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000000926 separation method Methods 0.000 claims description 11
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- 230000003071 parasitic effect Effects 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a power supply wiring structure of a semiconductor integrated circuit in which power supply wirings arranged in mutually different wiring layers are electrically connected by vias.
- a power supply wiring structure using a multi-stack via is known as a structure for electrically connecting two power supply wirings arranged in two different wiring layers with vias. .
- the conventional power supply wiring structure will be described below with reference to FIG.
- FIG. 11 is a cross-sectional view of the LSI wiring layer
- FIG. 13 is a plan view thereof.
- L1 to L4 are first to fourth wiring layers
- 51 is a first power supply wiring arranged in the first wiring layer L1
- 52 is arranged in the fourth wiring layer L4.
- the second and third wiring layers L2 and L3 are connected to connect both the power supply lines 51 and 52.
- the second wiring 53 and the third wiring 54 are arranged, and the first to third vias 56, 57, and 58 are arranged in the three insulating layers I1 to I3, respectively.
- the second and third wirings 53 and 54 and the first to third vias 56 to 58 have the shape shown in the top view of FIG. 13, and the vias 56 to 58 are close to two in the vertical direction of FIG.
- the multiple vias (double in the figure) that are arranged side by side, and the wirings 53 and 54 connected to the multiple vias are formed wide in the vertical and horizontal directions so as to include the double vias inward when viewed from above.
- the first via 56, the second wiring 53, the second via 57, the third wiring 54, and the third via 58 on one vertical line are on the same vertical line.
- a multi-stack via having a stacked shape is formed, and this multi-stack via is used as one unit, and five units are formed in the same figure, whereby the first power supply wiring 51 and the fourth power supply wiring are formed.
- 52 is connected to be electrically connected to one power supply wiring.
- Patent Document 1 the amount of current flowing between the first and second power supply wirings 51 and 52 is calculated, the minimum number of units is calculated from the amount of current, and unnecessary vias are deleted. Thus, the wiring resources are increased, and the signal wiring 62 of the second wiring layer L2 is arranged between the five units as illustrated in FIG. 11 to increase the wiring efficiency and improve the wiring property. .
- Non-Patent Document 1 a borderless via has been developed as a signal wiring connection structure apart from the power supply wiring structure described above.
- This borderless via is a via that does not have a pad portion that is an extra wide wiring region that is mainstream in DFM (Design For Manufacturing) like the multi via shown in FIG. Since vias and wirings can be formed more precisely at predetermined positions, the vertical and horizontal lengths of the vias are set to be approximately equal to the vertical and horizontal lengths of the wirings connected thereto.
- the reason why a large number of multi-stack vias are arranged in the power supply wiring structure of the semiconductor integrated circuit is for IR-DROP countermeasures and electromigration (hereinafter referred to as EM) countermeasures, and reduces the voltage drop to the target cell. This is to eliminate the disconnection at the via portion.
- EM electromigration
- the multi-stack vias may still be insufficient to maximize and optimize the wiring efficiency around the vias. is there. This will be described in detail with reference to FIG.
- FIG. 12 is a partially enlarged view of the multi-stack via and the wiring in the region surrounded by a circle in FIG.
- reference numeral 60 denotes a wiring track.
- four wiring tracks 60 are shown, and there are wide pad portions 61 and 61 protruding from the wiring portion even though the two wiring tracks 60 are located between the multi-stack vias. Therefore, in order to observe a separation rule equivalent to the wiring width, only one wiring 62 can pass between the multi-stack vias.
- the separation width to adjacent vertical and horizontal wiring tracks is essentially the distance So to the via 58 in the vicinity of the multi (double) stack via.
- the distance Sx is shorter than the distance So by the length of the pad portion.
- the horizontal track cannot be routed to the tracks B and E that can be originally wired, and as a result, the wiring resources that can be used for signal wiring can be secured in the vertical direction and in the vertical direction, the vertical length is 0.
- the number of books is limited to two.
- the present inventors have focused on the borderless via employed in the signal wiring as the power supply wiring structure of the semiconductor integrated circuit, and studied to use a single power supply wiring via and a stack borderless via.
- this power supply wiring structure with a single borderless stack via there is no pad part of the multi-stack via, so that the wiring efficiency is improved and the wiring performance is improved.
- IR-DROP countermeasures and EM countermeasures there are concerns about IR-DROP countermeasures and EM countermeasures.
- the power supply wiring length to the target cell 40 is long and the parasitic resistance increases, but the single borderless stack shown in FIG.
- the single borderless stacked vias are arranged in the form of scattered dots having a wider via interval than in FIG. 5B, and the single borderless stacked via is located near the target cell 40.
- the wiring length can be shortened, and IR-DROP is reduced compared to the multi-stack via structure.
- the EM that is regulated by the via portion if the number of vias is the same, the EM characteristics are considered to be the same for both single and multi vias. Therefore, it has been known that even if a single borderless stacked via structure is adopted as the power supply wiring structure, it is possible to improve the wiring efficiency by improving the wiring efficiency while satisfactorily securing the IR-DROP countermeasure and the EM countermeasure.
- the present invention adopts a single borderless stack via structure as a power supply wiring structure of a semiconductor integrated circuit to connect power supply wirings of different wiring layers to each other, thereby taking measures against IR-DROP and EM.
- the wiring efficiency is improved by improving the wiring efficiency while ensuring good.
- the power supply wiring structure of the semiconductor integrated circuit according to the present invention includes a power supply wiring arranged in two mutually different wiring layers sandwiching at least one intermediate wiring layer, and a power supply arranged in the two wiring layers.
- a single borderless stack via that electrically connects the wirings to form a wiring connection portion is provided.
- the single borderless stack vias constituting the wiring connection portion are single vias respectively disposed in two or more insulating layers positioned between the two wiring layers.
- a wiring having the same cross-sectional shape as a single via of each insulating layer disposed in the intermediate wiring layer, and each single via of each insulating layer and the wiring of the intermediate wiring layer are on the same vertical line A unit is configured by being electrically connected in an alternately stacked state.
- the single borderless stack via unit in the power supply wiring structure of the semiconductor integrated circuit, includes a single via disposed in each of three insulating layers and two intermediate layers sandwiched between the three insulating layers. It is characterized by comprising one wiring arranged in each wiring layer.
- the present invention is characterized in that, in the power supply wiring structure of the semiconductor integrated circuit, a plurality of the single borderless stack via units are formed, and the intervals between the units are equally spaced.
- a plurality of the single borderless stack via units are formed, and the intervals between the units are a mixture of equal intervals and unequal intervals. .
- a plurality of the single borderless stack via units are formed, and a signal wiring is provided in an area between any two adjacent units of the plurality of units. Is arranged.
- a distance between the single borderless stack via and the signal wiring is equal to a distance between the signal wiring and another signal wiring adjacent to the signal wiring.
- the power supply wirings arranged in the two wiring layers are electrically connected to each other.
- a multi-stack via constituting the connecting portion is provided.
- the multi-stack via in the power supply wiring structure of the semiconductor integrated circuit, includes a plurality of vias arranged in two or more insulating layers positioned between the two wiring layers, and the intermediate wiring layer And a wiring having a pad portion so as to include a plurality of vias in each insulating layer in an inward direction when viewed from above, a plurality of vias in each insulating layer and a wiring in the intermediate wiring layer Are electrically connected in a state of being alternately stacked on the same vertical line.
- the single borderless stack via constituting the wiring connection portion is disposed in a signal wiring region, and the multi-stack via constituting the other wiring connection portion is It is arranged in a non-wiring area where signals are not wired.
- the multi-stack via constituting the other wiring connection portion is disposed in a region having a predetermined signal wiring density in the signal wiring region, and the wiring connection portion
- the single borderless stacked via constituting the signal wiring region is arranged in a wiring region having a signal wiring density higher than the predetermined density in the signal wiring region.
- the single borderless stack vias are arranged at a plurality of locations, and the plurality of single borderless stack vias are separated from each other within the same insulating layer of the multistack vias. It is characterized by being wider than the separation between individual vias.
- the wiring efficiency can be higher than the multi-stack via having a wide pad portion as in the prior art, The wiring property can be improved. As a result, the chip area can be effectively reduced, and IR-DROP and EM can be maintained or improved well.
- the present invention since there are two types of single borderless stack vias and multi-stack vias as wiring connection portions for connecting two power supply wirings, the combined resistance of the entire power supply wirings even when an OPEN failure of the vias occurs.
- the increase in value can be effectively suppressed, and the yield can be improved.
- the wiring efficiency can be improved and the wiring property can be improved, and the chip area can be reduced.
- IR-DROP and EM can be maintained or improved well, and the affinity with the EDA tool is increased and TAT (Turn Around Time) can be shortened.
- a multi-stack via is also provided as a wiring connection portion, an increase in the combined resistance value of the entire power supply wiring when an OPEN failure of the via occurs can be effectively suppressed, and the yield is improved. Can do.
- FIG. 1 is a cross-sectional view of the main part of the power supply wiring structure of the semiconductor integrated circuit according to the first embodiment of the present invention.
- FIG. 2 is a top view of the power supply wiring structure.
- FIG. 3 is an enlarged view of a portion surrounded by a circle in the power supply wiring structure of FIG.
- FIG. 4A is an explanatory diagram showing that IR-DROP is improved in the same power supply wiring structure
- FIG. 4B is an explanatory diagram of IR-DROP in the conventional power supply wiring structure.
- FIG. 5 is a top view in which a semiconductor integrated circuit having the same power supply wiring structure is constituted by one chip.
- FIG. 6 is a top view in which a semiconductor integrated circuit having a conventional power supply wiring structure is constituted by one chip.
- FIG. 7 is a top view in which a semiconductor integrated circuit having a power supply wiring structure according to the second embodiment of the present invention is constituted by one chip.
- FIG. 8A is a diagram showing a change in resistance value when an OPEN failure occurs in the single stack via structure provided in the power supply wiring structure
- FIG. 8B is a multi-stack via structure provided in the power supply wiring structure. It is a figure which shows the change of resistance value when the OPEN defect
- FIG. 9 is a flowchart showing the creation of the power supply wiring structure.
- FIG. 10A is a layout diagram in a wiring region having a low signal wiring density of the semiconductor integrated circuit having the power supply wiring structure of the third embodiment of the present invention, and FIG.
- FIG. 10B is a signal wiring density of the semiconductor integrated circuit.
- FIG. 6 is a layout diagram in a high wiring area.
- FIG. 11 is a cross-sectional view of a main part of a power supply wiring structure of a conventional semiconductor integrated circuit.
- 12 is an enlarged view of a portion surrounded by a circle in the power supply wiring structure of FIG.
- FIG. 13 is a top view of the power supply wiring structure.
- FIG. 1 shows a cross-sectional view of a power supply wiring structure of a semiconductor integrated circuit according to the present invention
- FIG. 2 shows a top view thereof, and illustrates a four-layer wiring structure.
- L1 is the first wiring layer
- L4 is the fourth wiring layer
- L2 and L3 are the second and third wiring layers arranged between the first and fourth wiring layers L1 and L4. This is an intermediate wiring layer.
- Numeral 1 is a first power supply wiring arranged in the first wiring layer L1
- 4 is a fourth power supply wiring arranged in the fourth wiring layer L4.
- first power supply line 1 and the fourth power supply line 4 are connected as one power supply line
- both the power supply lines 1 and 4 are connected to the second and third intermediate wiring layers L2 and L3.
- the second wiring 2 and the third wiring 3 are arranged, and the first to third vias 5, 6 and 7 are arranged in the three insulating layers I1 to I3, respectively.
- the first to third vias 5 to 7 are each a single via
- the second and third wirings 2 and 3 connected to the single via are as follows:
- the single vias have the same vertical and horizontal lengths and the same cross-sectional shape. That is, each of the single vias 5 to 7 is constituted by a borderless via having no wide pad portion as shown in FIG.
- the first single via 5, the second wiring 2, the second single via 6, the third wiring 3, and the third single via 7 on one vertical line One single borderless stack via 8 having a shape stacked on the same vertical line is formed, and this single borderless stack via 8 is a wiring connection for electrically connecting the first and fourth power supply wires 1 and 4. Parts.
- the unit is composed of one single via 5 to 7 for each of the three insulating layers I1 to I3 and one wiring 2 and 3 for the two intermediate wiring layers L2 and L3. In order to form a via, it may be configured by each single via of at least two insulating layers and wiring of one intermediate wiring layer.
- FIG. 3 is an enlarged view of a portion surrounded by a circle in FIG. Even if they are arranged at the same interval as in FIG. 12, the borderless vias 5 to 7 do not have the pad portion 61 shown in FIG. Even if the wiring separation rule is taken into consideration, the wiring property is improved as compared with the case where only one signal wiring 62 in FIG.
- the wiring resources that can be used for signal wiring are 4 for the vertical track and 2 for the horizontal track, and 0 for the vertical track in the conventional example shown in FIG. It is obvious that the wiring property is better than the case of two.
- the signal wiring 10 adjacent to the wiring 2 of the single borderless stack via 8 when the signal wiring 10 adjacent to the wiring 2 of the single borderless stack via 8 is disposed, the signal wiring 10 is disposed on the wiring track 12. Therefore, the separation between the signal wiring 10 and the wiring 2 of the single borderless stack via 8 is equal to the separation between the signal wiring 10 and another signal wiring 10 adjacent to the signal wiring 10.
- this signal wiring 62 even if one signal wiring 62 can be arranged between two multi-vias having a pad portion 61 as shown in FIG. 12 showing the conventional example, this signal wiring 62 is connected between two wiring tracks 60. And cannot be placed on the wiring track 60. Therefore, in the present embodiment, the signal wiring 10 around the single borderless stack via 8 can be arranged on the wiring track 12, and the compatibility with the EDA tool is good.
- two single vias 6 are arranged within a predetermined area occupied by six vertical tracks and three horizontal tracks, and a multi (double) within the same area shown in FIG.
- the number of stacked vias is the same as two vias.
- EM electromigration
- the EM characteristics are considered to be the same for both single and multi vias. Therefore, even in the single borderless stacked via structure of the present embodiment, the EM characteristics are maintained well, and occurrence of disconnection in the via portion is effectively reduced.
- two single vias 6 are arranged in the predetermined area.
- two single vias 6 are arranged in the predetermined area.
- both the single vias 6 may be arranged such that only one signal wiring 10 is arranged between the vias 6, It is also possible to arrange so that three or four signal wirings 10 are arranged.
- the single borderless stacked via 8 is highly arbitrary in the arrangement position. Therefore, in this embodiment, as shown in FIG. 4A, for example, four single vias 6 can be arranged at positions where their mutual separation is wide. As a result, as shown in FIG. 4B, the power supply to the target standard cell 40 that receives power supply is provided as compared with the case where the four vias 58 constituting the conventional multi-stack via are arranged close to each other. The wiring length can be shortened, the parasitic resistance can be reduced accordingly, and IR-DROP can be reduced and improved.
- FIG. 5 shows a schematic diagram in which a semiconductor integrated circuit having a single borderless stacked via structure of this embodiment is integrated on one chip.
- all vias are constituted by single borderless stacked vias 20 and the number thereof is 24.
- FIG. 6 shows a conventional semiconductor integrated circuit in which six multi-stack vias including four vias 70 are arranged to constitute one chip. The total number of vias 70 is 24 as in FIG.
- the vias 20 are arranged evenly over the entire chip surface as compared to FIG. Accordingly, it can be seen that the power wiring length to the target cell (not shown in FIGS. 5 and 6) that receives power supply can be shortened, and the IR-DROP can be reduced and improved.
- FIG. 7 shows a power supply wiring structure of the semiconductor integrated circuit of this embodiment.
- a power supply wiring structure in which single borderless stacked vias 20 are arranged in a scattered manner at a plurality of predetermined locations, and a multi (double) stacked via 75 including a plurality of (two in the figure) vias 71 are provided.
- 2 shows a semiconductor integrated circuit provided with two types of power supply wiring structures, including a plurality of power supply wiring structures provided as wiring connection portions.
- the detailed structure of the multi-stack via 75 is the same as the structure shown in FIGS. 11 to 13 and has already been described, and the description thereof will be omitted. However, as can be seen from FIG.
- the separation between the less stack vias 20 is naturally set wider than the separation between the two vias 71 of the multi stack via 75.
- the arrangement area of the single borderless stack via 20 is a signal wiring area 30, and the arrangement area of the multi-stack via 75 is a non-wiring area 31 where no signal is wired.
- the reason for this is that when the OPEN defect of the via occurs, it is considered that the power wiring structure having the single borderless stacked via 20 has a larger increase in resistance value.
- the resistance value of one via is R
- the combined resistance of the entire two units is 2R.
- the wiring having the pad portion between the two vias plays a role of insurance, and the combined resistance is 3 / 2R and there is little drop in resistance. Therefore, a single power supply wiring is provided with two types, a single borderless stack via structure and a multi-stack via structure, and the combined resistance value of the entire power supply wiring is kept low even when an open failure of the via occurs. Thus, it is possible to suppress power supply wiring defects and improve the wiring property in the signal wiring region 30 while improving the yield.
- FIG. 9 shows a flow of creating the two types of power supply wiring structures shown in FIG. 7.
- step S1 the number of single stack vias 20 determined by design is arranged in the signal wiring region 30, and then in step S2.
- wiring layout processing (wiring processing) is performed.
- step S3 the presence / absence of wiring near the single stacked via 20 is determined. If no wiring exists, it is determined as a non-wiring area, and the multi-stack via 75 is set in step S4. Deploy.
- the steps S3 and S4 are repeated for all the single stack vias 20 and the determination of the presence / absence of wiring for all the single stack vias 20 is completed, the wiring is completed in step S5.
- FIG. 10 shows a power supply wiring structure of the semiconductor integrated circuit of this embodiment.
- FIG. 7 showing the second embodiment, only the single borderless stack via 20 is arranged in the signal wiring region 30, but in this embodiment, a single signal is formed in the signal wiring region 30 according to the signal wiring density. Borderless stack vias and multi-stack vias are arranged and sorted.
- FIGS. 10A and 10B show a part of the signal wiring region, and FIG. 10A shows the signal wirings 43 and 44 arranged in the signal wiring region, but the signal wiring density is low.
- the wiring area is a high-density wiring area and has many empty areas.
- a multi-stack via 75 is arranged in the empty area.
- the multi-stack via 75 illustrates a configuration having two vias (double vias) 71 in FIG.
- the signal wiring area shown in FIG. 5B a large number of signal wirings 45 to 49 are arranged, and there are few empty areas, and the signal wiring density in the wiring area shown in FIG. This is a wiring area of wiring density.
- a single borderless stack via 20 is disposed in the wiring region having a high signal wiring density.
- the single borderless stack via 20 is disposed in the wiring region having a high signal wiring density shown in FIG. 4B, a large number of signal wirings 45 to 49 can be wired efficiently.
- the signal wirings 47 and 49 can be wired with a short wiring length without wastefully bypassing the vicinity of the single borderless stacked via 20.
- the multi-stack via 75 is arranged in the wiring region having a low signal wiring density shown in FIG. 5A.
- the number of the signal wirings 43 and 44 is small and there are many free regions, There is no hindrance in the selection of the wiring route, and the wiring efficiency is secured high.
- the single borderless stack via 20 and the multi-stack via 75 are connected in parallel to the power supply wiring (first and fourth power supply wirings 1 and 4 shown in FIG. 1), an OPEN defect of the via has occurred. Even in this case, as described in detail in the second embodiment, the resistance value of the power supply wiring can be kept low, and the yield of the chip can be improved.
- a single borderless stack via is provided as a wiring connection part for electrically connecting wirings of different wiring layers
- a multi-stack of double or more having a wide pad part is provided.
- Wiring performance is better than vias, chip area can be reduced, IR-DROP can also be improved, and signal wiring around single borderless stack vias must be securely placed on wiring tracks Therefore, the compatibility with the EDA tool can be improved, which is useful as a power supply wiring structure for various semiconductor integrated circuits.
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Abstract
Description
以下、本発明の第1の実施形態について図面を参照しながら説明する。
次に、本発明の第2の実施形態について図面を参照しながら説明する。
続いて、本発明の第3の実施形態について図面を参照しながら説明する。
2 第2の配線
3 第3の配線
4 第4の電源配線
5 第1のビア
6 第2のビア
7 第3のビア
8、20 シングルボーダレススタックビア
10、11 信号配線
12 配線トラック
30 信号配線領域
31 非配線領域
40 目的スタンダードセル
61 パッド部
71 ビア
75 マルチスタックビア
Claims (12)
- 少なくとも1つの中間配線層を間に挟んだ2つの相互に異なる配線層に配置された電源配線と、
前記2つの配線層に配置された電源配線同士を電気的に接続して配線接続部を構成するシングルボーダレススタックビアとを備えた
ことを特徴とする半導体集積回路の電源配線構造。 - 前記請求項1記載の半導体集積回路の電源配線構造において、
前記配線接続部を構成するシングルボーダレススタックビアは、
前記2つの配線層の間に位置する2つ以上の絶縁層に各々配置されるシングルビアと、
前記中間配線層に配置され、前記各絶縁層のシングルビアと同一断面形状を有する配線とを有し、
前記各絶縁層の各シングルビアと前記中間配線層の配線とが同一垂直線上に交互に重ねられた状態で電気的に接続されてユニットを構成する
ことを特徴とする半導体集積回路の電源配線構造。 - 前記請求項2記載の半導体集積回路の電源配線構造において、
前記シングルボーダレススタックビアのユニットは、
3つの絶縁層に各々1つ配置されたシングルビアと、
前記3つの絶縁層に挟まれた2つの中間配線層に各々1本配置された配線とにより構成される
ことを特徴とする半導体集積回路の電源配線構造。 - 前記請求項2記載の半導体集積回路の電源配線構造において、
前記シングルボーダレススタックビアのユニットは複数本形成され、
前記各ユニット間の離隔は、等間隔である
ことを特徴とする半導体集積回路の電源配線構造。 - 前記請求項2記載の半導体集積回路の電源配線構造において、
前記シングルボーダレススタックビアのユニットは複数本形成され、
前記各ユニット間の離隔は、等間隔と不等間隔とが混在する
ことを特徴とする半導体集積回路の電源配線構造。 - 前記請求項2記載の半導体集積回路の電源配線構造において、
前記シングルボーダレススタックビアのユニットは複数本形成され、
前記複数本のユニットのうち隣接する何れか2本のユニット間の領域には、信号配線が配置される
ことを特徴とする半導体集積回路の電源配線構造。 - 前記請求項6記載の半導体集積回路の電源配線構造において、
前記シングルボーダレススタックビアと前記信号配線との離隔は、前記信号配線とこの信号配線に隣接する他の信号配線との離隔に等しい
ことを特徴とする半導体集積回路の電源配線構造。 - 前記請求項1又は2記載の半導体集積回路の電源配線構造において、
前記配線接続部を構成する前記シングルボーダレススタックビアと共に、
前記2つの配線層に配置された電源配線同士を電気的に接続して他の配線接続部を構成するマルチスタックビアを備えた
ことを特徴とする半導体集積回路の電源配線構造。 - 前記請求項8記載の半導体集積回路の電源配線構造において、
前記マルチスタックビアは、
前記2つの配線層の間に位置する2つ以上の絶縁層に各々複数個配置されるビアと、
前記中間配線層に配置され、前記各絶縁層の複数個のビアを平面から見て内方に含むようにパッド部を有する配線とを有し、
前記各絶縁層の複数個のビアと前記中間配線層の配線とが同一垂直線上に交互に重ねられた状態で電気的に接続される
ことを特徴とする半導体集積回路の電源配線構造。 - 前記請求項8又は9記載の半導体集積回路の電源配線構造において、
前記配線接続部を構成する前記シングルボーダレススタックビアは、信号配線領域に配置され、
前記他の配線接続部を構成する前記マルチスタックビアは、信号が配線されない非配線領域に配置される
ことを特徴とする半導体集積回路の電源配線構造。 - 前記請求項8又は9記載の半導体集積回路の電源配線構造において、
前記他の配線接続部を構成する前記マルチスタックビアは、信号配線領域のうち信号配線密度が所定密度の領域に配置され、
前記配線接続部を構成する前記シングルボーダレススタックビアは、前記信号配線領域のうち信号配線密度が前記所定密度よりも高い配線領域に配置される
ことを特徴とする半導体集積回路の電源配線構造。 - 前記請求項10又は11記載の半導体集積回路の電源配線構造において、
前記シングルボーダレススタックビアは複数箇所に配置され、
前記複数箇所のシングルボーダレススタックビア間の離隔は、前記マルチスタックビアの同一絶縁層内の複数個のビア間の離隔よりも広い
ことを特徴とする半導体集積回路の電源配線構造。
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CN2009801549066A CN102282667A (zh) | 2009-01-20 | 2009-08-26 | 半导体集成电路的电源布线构造 |
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US10032674B2 (en) | 2015-12-07 | 2018-07-24 | International Business Machines Corporation | Middle of the line subtractive self-aligned contacts |
US10410934B2 (en) * | 2017-12-07 | 2019-09-10 | Micron Technology, Inc. | Apparatuses having an interconnect extending from an upper conductive structure, through a hole in another conductive structure, and to an underlying structure |
CN110349947A (zh) * | 2018-04-02 | 2019-10-18 | 台湾积体电路制造股份有限公司 | 半导体装置、其设计方法及包括其的*** |
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US6225211B1 (en) * | 1999-04-29 | 2001-05-01 | Industrial Technology Research Institute | Method for making stacked and borderless via structures on semiconductor substrates for integrated circuits |
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US5891799A (en) * | 1997-08-18 | 1999-04-06 | Industrial Technology Research Institute | Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates |
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