WO2010057941A1 - Procédé de production d’une hétérostructure de type silicium sur saphir - Google Patents

Procédé de production d’une hétérostructure de type silicium sur saphir Download PDF

Info

Publication number
WO2010057941A1
WO2010057941A1 PCT/EP2009/065440 EP2009065440W WO2010057941A1 WO 2010057941 A1 WO2010057941 A1 WO 2010057941A1 EP 2009065440 W EP2009065440 W EP 2009065440W WO 2010057941 A1 WO2010057941 A1 WO 2010057941A1
Authority
WO
WIPO (PCT)
Prior art keywords
grinding
bonding
carried out
substrate
silicon
Prior art date
Application number
PCT/EP2009/065440
Other languages
English (en)
Inventor
Gweltaz Gaudin
Alexandre Vaufredaz
Fleur Guittard
Original Assignee
S.O.I.Tec Silicon On Insulator Technologies
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by S.O.I.Tec Silicon On Insulator Technologies filed Critical S.O.I.Tec Silicon On Insulator Technologies
Priority to US13/123,180 priority Critical patent/US20110195560A1/en
Publication of WO2010057941A1 publication Critical patent/WO2010057941A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Definitions

  • the present invention relates to the production of heterogeneous structures formed by bonding at least one substrate of semiconductor material, such as silicon, on a sapphire (AI 2 O 3 ) substrate.
  • the invention is applicable to the fabrication of silicon-on- sapphire type heterostructures known by the acronym SOS (for silicon-on-sapphire).
  • Heterostructures comprising a layer of silicon on a sapphire substrate have particular advantages.
  • SOS structures can produce high-frequency, low-energy- consumption devices.
  • the use of sapphire substrates can also mean that very good heat dissipation can be achieved that is superior to that obtained with quartz substrates, for example.
  • SOS structures were initially produced by growing a layer of silicon epitaxially from a sapphire substrate.
  • a layer of silicon epitaxially from a sapphire substrate it is difficult to obtain layers or films of silicon with a low crystal defect density due to the large differences between the lattice parameters and the thermal expansion coefficients of the two materials.
  • SOS structures can be produced by assembling an SOI (silicon-on- insulator) structure on a sapphire substrate.
  • production of an SOS structure comprises bonding the SOI structure onto the sapphire substrate by direct wafer bonding or fusion bonding (also known as molecular adhesion) , a reinforcing anneal or bonding stabilization anneal, and thinning the SOI structure to form a transferred layer of silicon on the sapphire substrate. Thinning is typically carried out in two steps, namely a first, grinding, step that removes the major portion of the support substrate of the SOI structure, followed by a second step of chemical etching up to the oxide layer of the SOI structure that acts as a stop layer.
  • TMAH tetramethylammonium hydroxide
  • the heterostructure may have crosswise crack type defects disposed along the crystalline axes of the superficial silicon layer.
  • chemical etching may result in delamination of the transferred silicon layer, as can be seen in Figure 2 where it should be observed that the superficial silicon layer and the subjacent sapphire substrate have delaminated when a shear force is applied to the silicon layer.
  • edge loss defects broadening of the ring due to delamination
  • Edge loss type defects are due to delamination during bonding reinforcement annealing; the greater the thickness of the silicon at the moment of bonding reinforcement annealing, the wider are the edge loss defects .
  • the presence of said defects and of delamination are principally due to the fact that direct wafer bonding between the sapphire substrate and the transferred silicon layer is not strong enough to prevent the etching solution from infiltrating into the bonding interface. Because of the large difference between the expansion coefficient of silicon and that of sapphire (3.6 x 10 ⁇ 6 /°C for silicon and 5 x 10 ⁇ 6 /°C for sapphire) , large thermomechanical stresses are produced in the structure during post-bonding heat treatments such as reinforcing annealing, which causes cracks to appear and propagate in the silicon.
  • the temperature thereof is limited ( ⁇ 300 0 C) compared with the temperatures normally used during such anneals (700 0 C to 800 0 C) .
  • This limitation in temperature means that large bonding energy between the silicon and the sapphire cannot be obtained.
  • the document US-A-5 395 788 describes a method of producing a heterostructure, comprising bonding a silicon substrate onto a quartz substrate.
  • that document recommends carrying out thinning of the silicon substrate in several steps with heat treatments before and after each of those steps. The temperature of the heat treatments is raised continually as the treatments proceed.
  • One of the aims of the invention is to overcome the above-mentioned disadvantages by proposing a solution that can produce an SOS type heterostructure by bonding and thinning of an SOI substrate or structure on a sapphire substrate, thereby limiting the appearance of defects and the risk of delamination as described above.
  • the present invention proposes a method of producing such a heterostructure, in which thinning of the SOI substrate or structure is carried out by grinding followed by an etch, the method being characterized in that grinding is carried out using a wheel with a grinding surface that comprises abrasive particles having a mean dimension of more than 6.7 microns (or less than 2000 mesh), and in that said method comprises, after grinding and before etching, a step of post-grinding annealing of the heterostructure carried out at a temperature in the range 150 0 C to 170 0 C.
  • a wheel or grinder for grinding that comprises abrasive particles having a mean dimension of more than 6.7 microns ( ⁇ m) means that coarse grinding can be carried out, as opposed to fine grinding that is carried out with a wheel comprising abrasive particles having a mean dimension of less than 6.7 ⁇ m.
  • the Applicant has elected to use such coarse grinding since it means that the SOI substrate can be thinned, thereby minimizing the risks of delamination between the SOI substrate and the sapphire substrate during grinding. Because the bond between these two elements is weak (limitation on the temperature of the reinforcement anneal), it is not possible to apply a very high load with the wheel during grinding without risking delamination. To this end, grinding carried out with abrasive particles having a mean dimension greater than at least 6.7 ⁇ m means that a large quantity of material can be removed without having to apply too high a load. During grinding, the load of the wheel on the SOI substrate does not exceed 222.5 newtons (N) .
  • the surface area ratio between the fine wheel and the material is higher than between the coarse wheel and that same material , which has the effect of increasing the load of the wheel on the SOI substrate and, as a result, of increasing the risks of delamination.
  • the SOI substrate has a work-hardened surface that is the origin of the appearance of crack type defects during subsequent heat treatments.
  • the post-grinding annealing temperature By limiting the post-grinding annealing temperature to a temperature in the range 15O 0 C to 170 0 C, the appearance of such defects is prevented.
  • Post-grinding annealing can also reinforce the bond between the sapphire substrate and the SOI substrate and thereby prevent infiltration of the etching solution into the bonding interface during the second thinning step.
  • a step of pre-grinding annealing of the heterostructure may also be carried out in order to reinforce bonding and further reduce the risks of delamination during grinding.
  • the pre-grinding anneal is carried out at a temperature that is preferably in the range 150 0 C to 180 0 C.
  • the boat-in temperature of the heterostructure during pre-grinding annealing is less than 80 0 C.
  • the temperature ramp-up is of the order of I 0 C per minute (°C/min) .
  • Figure 1 is a photograph showing edge loss type defects and showing crack type crosswise defects in a silicon-on-sapphire heterostructure after chemical etching;
  • Figure 2 is a photograph showing the delamination of a silicon-on-sapphire heterostructure
  • Figure 3 is a photograph showing edge loss type defects and crosswise crack type defects in a silicon-on- sapphire heterostructure following grinding
  • Figure 4 illustrates the deformation undergone by a silicon-on-sapphire heterostructure during heat treatment ;
  • Figures 5A to 5G are diagrammatic views showing the production of a heterostructure employing a method in accordance with the invention
  • Figure 6 is a flow chart of the steps carried out during production of the heterostructure illustrated in Figures 5A to 5G.
  • the method of the present invention is of general application to the production of an SOS type heterostructure formed from an assembly between a first substrate formed of sapphire and a second substrate, or
  • the substrates may in particular have diameters of 150 millimeters (mm) .
  • the initial substrate 110 is constituted by an SOI type structure comprising a layer of silicon 111 on a support 113, also of silicon, with a buried oxide layer 112, formed of SiO 2 , for example, being disposed between the layer 111 and the support 113.
  • the support substrate 120 is constituted by a wafer of sapphire ( Figure 5A) .
  • the bonding surface 120a of the sapphire support substrate that has been polished may be prepared (step Sl) .
  • This preparation may in particular consist of chemical cleaning, in particular by RCA cleaning (namely a combination of an SCl bath (NH 4 OH, H 2 O2, H 2 O) , suitable for removing particles and hydrocarbons, and an SC2 bath (HCl, H 2 O 2 , H 2 O) suitable for removing metallic contaminants), a Caro's type clean or Piranhaclean type clean (H 2 SO 4 : H 2 O 2 ), or even cleaning with an ozone/water (0 3 /H 2 O) solution. Cleaning may be followed by scrubbing.
  • the surface 120a of the substrate 120 may be activated using a plasma treatment (step S2) .
  • the surface Ilia of the silicon layer 111 of the initial substrate 110 may be covered with a layer of thermal oxide 114 formed, for example, by oxidizing the surface of the substrate ( Figure 5B, step S3) .
  • the surface Ilia of the initial substrate 110 which may optionally be covered with a layer of oxide, may also be activated by plasma treatment (step S4) .
  • the bonding surfaces of the substrates 110 and 120 may be activated by exposing them to a plasma based on oxygen, nitrogen, argon, or other.
  • the equipment used for this purpose may, inter alia, have initially been provided for capacitatively coupled reactive ionic etching (RIE) , or for etching using inductively coupled plasma (ICP) .
  • RIE reactive ionic etching
  • ICP inductively coupled plasma
  • Said plasma may also be immersed in a magnetic field, in particular to prevent electrically charged species from diffusing towards the walls of the reactor, using magnetically enhanced reactive ion etching (MERIE) type equipment .
  • MIE magnetically enhanced reactive ion etching
  • the plasma density may be selected so as to be low, medium or high (or HDP, high density plasma) .
  • plasma bonding activation in general comprises an initial chemical cleaning such as a RCA clean (namely a combination of an SCl bath (NH4OH, H 2 O 2 , H 2 O) suitable for removing particles and hydrocarbons, and an SC2 bath (HCl, H 2 O 2 , H 2 O) suitable for removing metallic contaminants) , followed by exposing the surface to a plasma for a few seconds to a few minutes .
  • a RCA clean namely a combination of an SCl bath (NH4OH, H 2 O 2 , H 2 O) suitable for removing particles and hydrocarbons, and an SC2 bath (HCl, H 2 O 2 , H 2 O) suitable for removing metallic contaminants
  • One or more cleaning steps following plasma exposure may be carried out, in particular in order to remove contaminants introduced during exposure, such as rinsing with water and/or SCl cleaning, optionally followed by drying by centrifuging.
  • said cleaning may be replaced by scrubbing in order to eliminate a large proportion of these contaminants .
  • Activation of a bonding surface by plasma treatment is well known to the skilled person and for the purposes of simplification is not described here in any further detail .
  • the surfaces Ilia and 120a are brought Into intimate contact and a pressure is applied to one of the two substrates in order to initiate propagation of a bonding wave between the surfaces In contact (step S5, Figure 3C) .
  • direct wafer bonding also known as direct bonding, or molecular adhesion
  • molecular adhesion is based on bringing two surfaces Into direct contact, I.e. without using a specific material (adhesive, wax, solder, etc) .
  • Such an operation requires that the surfaces for bonding together be sufficiently smooth, free of particles or contamination, and that they come sufficiently close to allow contact to be initiated, typically at a distance of less than a few nanometers.
  • the attractive forces between the two surfaces are high enough to cause molecular adhesion (bonding induced by the various attractive forces (Van der Waals forces) of electronic interaction between atoms or molecules of the two surfaces for bonding together) .
  • the bond is reinforced a first time by carrying out a pre-grinding anneal (step S6) .
  • the pre-grinding anneal is carried out at a treatment temperature that is preferably in the range 150 0 C to 180 0 C for a period in the range 30 minutes to 4 hours . This anneal can reduce ring type defects (non-transferred peripheral zone) and prevent delamination of the two substrates during the grinding step.
  • the boat-in temperature of the assembly constituted by bonding the initial substrate 110 to the support substrate 120 is preferably less than 80 0 C, for example 50 0 C.
  • the temperature ramp-up i.e. the rate of increase of temperature used to bring the temperature of the furnace from the boat-in temperature to the temperature proper of the pre-grinding annealing treatment (preferably in the range 150 0 C to 180 0 C) is preferably of the order of l°C/min.
  • Such control of the boat-in temperature and the temperature ramp-up can reduce the thermal stresses applied to the assembly during the pre-grinding anneal.
  • Production of the heterostructure continues by thinning the initial substrate 110 in order to form a transferred layer corresponding to a portion of the silicon layer 111.
  • Thinning is initially carried out by grinding a major proportion of the support 113 (step S7, Figure 3D) .
  • grinding is carried out using a "coarse" wheel or grinder 210, i.e. a wheel the surface or active grinding portion 211 of which comprises abrasive particles having a mean dimension of more than 6.7 p (or 2000 mesh), preferably of more than 15 ⁇ m (or 1000 mesh) , and more preferably 31 um (or 500 mesh) or more.
  • the abrasive particles may in particular be diamond particles.
  • the reference number of a wheel model marketed by Saint-Gobain and comprising abrasive diamond type particles with a mean dimension of 6.7 ⁇ m (or 2000 mesh) is: FINE WHEEL STD - 301017 :18BB-ll-306-B65JP-5MM 11,100x1,197x9,002 MC176261 69014113064 POLISH#3JPl , 28BX623D-5MM.
  • the reference number of a wheel model marketed by Saint-Gobain and comprising abrasive diamond type particles with a mean dimension of 44 microns (or 325 mesh) is: COARSE WHEEL STD - 223599: 18BB-11-32B69S 11,034 X 1-1/8 X 9,001 MD15219669014111620 COARSE #3R7B69 - 1/8
  • a support 220 also termed a chuck, comprising a platen 222 that can hold the substrate 120 by suction or by an electrostatic system, for example.
  • the support 220 may be stationary while the wheel 210 is driven in rotation about its axis 212.
  • the support 220 may also be movable in rotation about an axis 221, the wheel 210 being either driven or not driven in rotation.
  • the post- grinding annealing temperature is limited to a temperature in the range 150 0 C to 170 0 C. Post-grinding annealing is carried out over a period in the range 30 minutes (min) to 4 hours (h) .
  • Thinning of the initial substrate is continued by etching the remaining portion 113a (step S9, Figure 5E).
  • This portion may be removed by chemical etching, also termed wet etching, for example using a TMAH
  • the remaining portion 113a may also be removed by means of reactive ion etching, also termed plasma etching or dry etching.
  • reactive ion etching also termed plasma etching or dry etching.
  • This etching technique is well known to the skilled person. It should be recalled that it is a physico-chemical etching employing both ion bombardment and a chemical reaction between the ionized gas and the surface of the wafer or the layer to be etched. The atoms of the gas react with the atoms of the layer or the wafer to form a new volatile species that is evacuated by a pumping device.
  • the oxide layer 112 is used as a stop layer for etching.
  • the layer 112 may be removed (step SlO, Figure 5G), for example by HF deoxidation, in order to leave a transferred layer 115 corresponding to at least a portion of the silicon layer 111. However, if required, the oxide layer 112 may be conserved.
  • the structure may be trimmed in order to remove chamfers or edge roll-off present at the periphery of the substrates (step SIl).
  • trimming may be carried out on the silicon substrate directly after assembling it with the sapphire substrate, and before the grinding step.
  • a heterostructure comprising the sapphire support substrate 120 and the transferred layer 115 is thus obtained, with an interposed buried oxide layer 114.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

L’invention concerne un procédé de production d’une hétérostructure de type silicium sur saphir, consistant à lier un substrat en SOI (110) sur un substrat de saphir (120), et à amincir le substrat en SOI, l’amincissement étant réalisé par un broyage suivi d’une gravure du substrat en SOI (110). Selon le procédé, le broyage est réalisé au moyen d’une roue (210) avec une surface de broyage (211) qui comprend des particules abrasives dont la dimension moyenne est supérieure à 6,7 µm; en outre, après le broyage et avant la gravure, ledit procédé comprend une étape consistant à une recuisson post-broyage de l’hétérostructure réalisée à une température comprise entre 150 °C et 170 °C.
PCT/EP2009/065440 2008-11-24 2009-11-19 Procédé de production d’une hétérostructure de type silicium sur saphir WO2010057941A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/123,180 US20110195560A1 (en) 2008-11-24 2009-11-19 Method of producing a silicon-on-sapphire type heterostructure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0857954A FR2938975B1 (fr) 2008-11-24 2008-11-24 Procede de realisation d'une heterostructure de type silicium sur saphir
FR0857954 2008-11-24

Publications (1)

Publication Number Publication Date
WO2010057941A1 true WO2010057941A1 (fr) 2010-05-27

Family

ID=40522243

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2009/065440 WO2010057941A1 (fr) 2008-11-24 2009-11-19 Procédé de production d’une hétérostructure de type silicium sur saphir

Country Status (3)

Country Link
US (1) US20110195560A1 (fr)
FR (1) FR2938975B1 (fr)
WO (1) WO2010057941A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8778737B2 (en) 2011-10-31 2014-07-15 International Business Machines Corporation Flattened substrate surface for substrate bonding
CN106409650A (zh) * 2015-08-03 2017-02-15 沈阳硅基科技有限公司 一种硅片直接键合方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9190269B2 (en) * 2010-03-10 2015-11-17 Purdue Research Foundation Silicon-on-insulator high power amplifiers
JP5859742B2 (ja) * 2011-04-28 2016-02-16 京セラ株式会社 複合基板
JP5976999B2 (ja) * 2011-05-30 2016-08-24 京セラ株式会社 複合基板
US10052848B2 (en) 2012-03-06 2018-08-21 Apple Inc. Sapphire laminates
US9221289B2 (en) 2012-07-27 2015-12-29 Apple Inc. Sapphire window
US9232672B2 (en) 2013-01-10 2016-01-05 Apple Inc. Ceramic insert control mechanism
WO2014178356A1 (fr) * 2013-05-01 2014-11-06 信越化学工業株式会社 Procédé de production de substrat hybride et substrat hybride
US9632537B2 (en) 2013-09-23 2017-04-25 Apple Inc. Electronic component embedded in ceramic material
US9678540B2 (en) 2013-09-23 2017-06-13 Apple Inc. Electronic component embedded in ceramic material
US9154678B2 (en) 2013-12-11 2015-10-06 Apple Inc. Cover glass arrangement for an electronic device
JP2015126052A (ja) * 2013-12-26 2015-07-06 京セラ株式会社 複合基板の製造方法
US9225056B2 (en) 2014-02-12 2015-12-29 Apple Inc. Antenna on sapphire structure
US10406634B2 (en) 2015-07-01 2019-09-10 Apple Inc. Enhancing strength in laser cutting of ceramic components
CN110085510B (zh) * 2018-01-26 2021-06-04 沈阳硅基科技有限公司 一种多层单晶硅薄膜的制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5441591A (en) * 1993-06-07 1995-08-15 The United States Of America As Represented By The Secretary Of The Navy Silicon to sapphire bond
US20030089950A1 (en) * 2001-11-15 2003-05-15 Kuech Thomas F. Bonding of silicon and silicon-germanium to insulating substrates

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6670259B1 (en) * 2001-02-21 2003-12-30 Advanced Micro Devices, Inc. Inert atom implantation method for SOI gettering

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5441591A (en) * 1993-06-07 1995-08-15 The United States Of America As Represented By The Secretary Of The Navy Silicon to sapphire bond
US20030089950A1 (en) * 2001-11-15 2003-05-15 Kuech Thomas F. Bonding of silicon and silicon-germanium to insulating substrates

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ABE T ET AL: "DISLOCATION-FREE SILICON ON SAPPHIRE BY WAFER BONDING", JAPANESE JOURNAL OF APPLIED PHYSICS, JAPAN SOCIETY OF APPLIED PHYSICS, TOKYO,JP, vol. 33, 1 January 1994 (1994-01-01), pages 514 - 518, XP000749264, ISSN: 0021-4922 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8778737B2 (en) 2011-10-31 2014-07-15 International Business Machines Corporation Flattened substrate surface for substrate bonding
US9355936B2 (en) 2011-10-31 2016-05-31 Globalfoundries Inc. Flattened substrate surface for substrate bonding
CN106409650A (zh) * 2015-08-03 2017-02-15 沈阳硅基科技有限公司 一种硅片直接键合方法

Also Published As

Publication number Publication date
FR2938975B1 (fr) 2010-12-31
US20110195560A1 (en) 2011-08-11
FR2938975A1 (fr) 2010-05-28

Similar Documents

Publication Publication Date Title
US20110195560A1 (en) Method of producing a silicon-on-sapphire type heterostructure
US8314007B2 (en) Process for fabricating a heterostructure with minimized stress
US20120015497A1 (en) Preparing a Surface of a Sapphire Substrate for Fabricating Heterostructures
US6146979A (en) Pressurized microbubble thin film separation process using a reusable substrate
KR100709689B1 (ko) 에피택셜 공정을 사용한 ｓｏｉ 기판의 표면 마무리 방법
US8202785B2 (en) Surface treatment for molecular bonding
KR100796249B1 (ko) 접합 웨이퍼의 제조방법
US7790565B2 (en) Semiconductor on glass insulator made using improved thinning process
KR101469282B1 (ko) Ｓｏｉ 웨이퍼의 제조 방법
US20070029043A1 (en) Pre-made cleavable substrate method and structure of fabricating devices using one or more films provided by a layer transfer process
KR100796831B1 (ko) 빈 자리 클러스터를 가지는 기판에서 형성된 박층 이송방법
US8951887B2 (en) Process for fabricating a semiconductor structure employing a temporary bond
US20090061593A1 (en) Semiconductor Wafer Re-Use in an Exfoliation Process Using Heat Treatment
JP2008021971A (ja) 電子工学、光学または光電子工学に使用される２つの基板を直接接合する方法
KR20110052456A (ko) 웨이퍼 접합 방법
KR20180016394A (ko) Soi웨이퍼의 제조방법
EP1542275A1 (fr) Méthode d'amélioration de la qualité d'une structure hétérogène
JP2004128389A (ja) 貼り合わせｓｏｉウエーハの製造方法
JP5368000B2 (ja) Ｓｏｉ基板の製造方法
KR20070019697A (ko) 반도체 층의 열처리 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09756730

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 13123180

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09756730

Country of ref document: EP

Kind code of ref document: A1