FR2938975B1 - Procede de realisation d'une heterostructure de type silicium sur saphir - Google Patents
Procede de realisation d'une heterostructure de type silicium sur saphirInfo
- Publication number
- FR2938975B1 FR2938975B1 FR0857954A FR0857954A FR2938975B1 FR 2938975 B1 FR2938975 B1 FR 2938975B1 FR 0857954 A FR0857954 A FR 0857954A FR 0857954 A FR0857954 A FR 0857954A FR 2938975 B1 FR2938975 B1 FR 2938975B1
- Authority
- FR
- France
- Prior art keywords
- sapphire
- silicon
- producing
- type heterostructure
- heterostructure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 229910052594 sapphire Inorganic materials 0.000 title 1
- 239000010980 sapphire Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0857954A FR2938975B1 (fr) | 2008-11-24 | 2008-11-24 | Procede de realisation d'une heterostructure de type silicium sur saphir |
US13/123,180 US20110195560A1 (en) | 2008-11-24 | 2009-11-19 | Method of producing a silicon-on-sapphire type heterostructure |
PCT/EP2009/065440 WO2010057941A1 (fr) | 2008-11-24 | 2009-11-19 | Procédé de production d’une hétérostructure de type silicium sur saphir |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0857954A FR2938975B1 (fr) | 2008-11-24 | 2008-11-24 | Procede de realisation d'une heterostructure de type silicium sur saphir |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2938975A1 FR2938975A1 (fr) | 2010-05-28 |
FR2938975B1 true FR2938975B1 (fr) | 2010-12-31 |
Family
ID=40522243
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0857954A Expired - Fee Related FR2938975B1 (fr) | 2008-11-24 | 2008-11-24 | Procede de realisation d'une heterostructure de type silicium sur saphir |
Country Status (3)
Country | Link |
---|---|
US (1) | US20110195560A1 (fr) |
FR (1) | FR2938975B1 (fr) |
WO (1) | WO2010057941A1 (fr) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9190269B2 (en) * | 2010-03-10 | 2015-11-17 | Purdue Research Foundation | Silicon-on-insulator high power amplifiers |
JP5859742B2 (ja) * | 2011-04-28 | 2016-02-16 | 京セラ株式会社 | 複合基板 |
JP5976999B2 (ja) * | 2011-05-30 | 2016-08-24 | 京セラ株式会社 | 複合基板 |
US8778737B2 (en) | 2011-10-31 | 2014-07-15 | International Business Machines Corporation | Flattened substrate surface for substrate bonding |
US10052848B2 (en) | 2012-03-06 | 2018-08-21 | Apple Inc. | Sapphire laminates |
US9221289B2 (en) | 2012-07-27 | 2015-12-29 | Apple Inc. | Sapphire window |
US9232672B2 (en) | 2013-01-10 | 2016-01-05 | Apple Inc. | Ceramic insert control mechanism |
WO2014178356A1 (fr) * | 2013-05-01 | 2014-11-06 | 信越化学工業株式会社 | Procédé de production de substrat hybride et substrat hybride |
US9632537B2 (en) | 2013-09-23 | 2017-04-25 | Apple Inc. | Electronic component embedded in ceramic material |
US9678540B2 (en) | 2013-09-23 | 2017-06-13 | Apple Inc. | Electronic component embedded in ceramic material |
US9154678B2 (en) | 2013-12-11 | 2015-10-06 | Apple Inc. | Cover glass arrangement for an electronic device |
JP2015126052A (ja) * | 2013-12-26 | 2015-07-06 | 京セラ株式会社 | 複合基板の製造方法 |
US9225056B2 (en) | 2014-02-12 | 2015-12-29 | Apple Inc. | Antenna on sapphire structure |
US10406634B2 (en) | 2015-07-01 | 2019-09-10 | Apple Inc. | Enhancing strength in laser cutting of ceramic components |
CN106409650B (zh) * | 2015-08-03 | 2019-01-29 | 沈阳硅基科技有限公司 | 一种硅片直接键合方法 |
CN110085510B (zh) * | 2018-01-26 | 2021-06-04 | 沈阳硅基科技有限公司 | 一种多层单晶硅薄膜的制备方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5441591A (en) * | 1993-06-07 | 1995-08-15 | The United States Of America As Represented By The Secretary Of The Navy | Silicon to sapphire bond |
US6670259B1 (en) * | 2001-02-21 | 2003-12-30 | Advanced Micro Devices, Inc. | Inert atom implantation method for SOI gettering |
US20030089950A1 (en) * | 2001-11-15 | 2003-05-15 | Kuech Thomas F. | Bonding of silicon and silicon-germanium to insulating substrates |
-
2008
- 2008-11-24 FR FR0857954A patent/FR2938975B1/fr not_active Expired - Fee Related
-
2009
- 2009-11-19 WO PCT/EP2009/065440 patent/WO2010057941A1/fr active Application Filing
- 2009-11-19 US US13/123,180 patent/US20110195560A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20110195560A1 (en) | 2011-08-11 |
FR2938975A1 (fr) | 2010-05-28 |
WO2010057941A1 (fr) | 2010-05-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
CD | Change of name or company name |
Owner name: SOITEC, FR Effective date: 20120907 |
|
ST | Notification of lapse |
Effective date: 20140731 |