WO2010052963A1 - アクティブマトリクス基板、液晶パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機 - Google Patents
アクティブマトリクス基板、液晶パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機 Download PDFInfo
- Publication number
- WO2010052963A1 WO2010052963A1 PCT/JP2009/064508 JP2009064508W WO2010052963A1 WO 2010052963 A1 WO2010052963 A1 WO 2010052963A1 JP 2009064508 W JP2009064508 W JP 2009064508W WO 2010052963 A1 WO2010052963 A1 WO 2010052963A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electrode
- capacitor
- pixel electrode
- insulating film
- liquid crystal
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
- G02F1/134354—Subdivided pixels, e.g. for grey scale or redundancy the sub-pixels being capacitively coupled
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
Definitions
- the present invention relates to an active matrix substrate in which a plurality of pixel electrodes are provided in one pixel region, and a liquid crystal display device (pixel division method) using the same.
- a plurality of subpixels provided in one pixel are controlled to have different luminances, and the area level of these subpixels.
- a liquid crystal display device pixel division method, for example, see Patent Document 1 that displays a halftone by a tone.
- two pixel electrodes 190a and 190b are arranged in one pixel region, the source electrode 178 of the transistor is connected to the data line 171 and the drain electrode 175 is in contact.
- the pixel electrode 190a is connected through a hole 185.
- the coupling electrode 176 is connected to the drain electrode 175 of the transistor through the extension portion 177.
- the coupling electrode 176 and the pixel electrode 190b overlap with each other via a protective film (channel protective film), and the pixel electrode 109a connected to the transistor via a capacitor (coupling capacitance) formed in the overlapping portion;
- the pixel electrode 109b that is electrically floating is connected (capacitive coupling type pixel division method).
- the sub-pixel corresponding to the pixel electrode 190a can be a bright sub-pixel
- the sub-pixel corresponding to the pixel electrode 190b can be a dark sub-pixel.
- a halftone can be displayed according to the area gradation of the pixel.
- the coupling electrode 176 and the pixel electrode 190b are easily short-circuited at the overlapping portion.
- an electrically floating pixel electrode (a pixel electrode corresponding to a dark sub-pixel) is connected to a lower layer capacitor electrode formed in the same layer (on the substrate) as the scanning signal line,
- the pixel electrode connected to the transistor is connected to the upper capacitor electrode formed on the same layer (on the gate insulating film) as the data signal line, and the upper capacitor electrode and the lower capacitor electrode overlap through the gate insulating film.
- a configuration in which a coupling capacitance is formed in the portion is disclosed.
- Japanese Patent Publication Japanese Patent Laid-Open No. 2006-221174 (Publication Date: August 24, 2006)”
- the pixel electrode corresponding to the dark sub-pixel is burned in because the lower-layer capacitor electrode formed in the same layer as the scanning signal line is electrically floating.
- the inventors of the present application have found that it is easy.
- An object of the present invention is to alleviate burn-in of a pixel electrode corresponding to a dark sub-pixel while suppressing a short circuit of a coupling capacitance portion in a capacitively coupled pixel-divided active matrix substrate.
- An active matrix substrate of the present invention includes a scanning signal line and a data signal line, a first pixel electrode connected to the data signal line via a transistor in one pixel region, and a capacitor connected to the first pixel electrode.
- a first capacitor electrode formed in the same layer as the scanning signal line and electrically connected to the first pixel electrode, and a scanning signal line.
- a second insulating film formed in a layer between the first insulating film and the second pixel electrode, wherein the first capacitor electrode and the second pixel electrode are the first and second electrodes.
- a capacitor is formed between the first capacitor electrode and the second pixel electrode by overlapping with each other through the insulating film.
- a first capacitor electrode and a second pixel electrode that form a coupling capacitor overlap with each other via a first insulating film (for example, a gate insulating film) and a second insulating film (for example, a channel protective film). Therefore, it is possible to suppress a short circuit between the two (the first capacitor electrode and the second pixel electrode).
- a first insulating film for example, a gate insulating film
- a second insulating film for example, a channel protective film. Therefore, it is possible to suppress a short circuit between the two (the first capacitor electrode and the second pixel electrode).
- the first capacitor electrode is connected to the first pixel electrode connected to the transistor, it is possible to reduce burn-in of the second pixel electrode (pixel electrode corresponding to the dark subpixel) that is electrically floating.
- the thickness of the second insulating film may be equal to or less than the thickness of the first insulating film.
- the second insulating film may be configured such that the thickness of the portion overlapping the first capacitor electrode and the second pixel electrode is smaller than the surrounding area.
- An active matrix substrate of the present invention includes a scanning signal line and a data signal line, a first pixel electrode connected to the data signal line via a transistor in one pixel region, and a capacitor connected to the first pixel electrode.
- a first capacitor electrode formed in the same layer as the scanning signal line and electrically connected to the first pixel electrode, and a scanning signal line.
- a second capacitor electrode formed in the same layer as the data signal line and electrically connected to the second pixel electrode, wherein the first capacitor electrode and the second capacitor electrode are the first capacitor electrode.
- a capacitor is formed between the first capacitor electrode and the second capacitor electrode by overlapping with each other through the insulating film.
- the first capacitor electrode and the second pixel electrode forming the coupling capacitor overlap with each other via the first insulating film (for example, the gate insulating film). Short circuit of the two pixel electrodes) can be suppressed.
- the first capacitor electrode is connected to the first pixel electrode connected to the transistor, it is possible to reduce burn-in of the second pixel electrode (pixel electrode corresponding to the dark subpixel) that is electrically floating.
- a second insulating film thicker than the first insulating film may be formed in a layer between the second capacitor electrode and the second pixel electrode.
- the second insulating film may include an organic insulating film.
- the first capacitor electrode has two parallel edges
- the second capacitor electrode also has two parallel edges.
- both of the second capacitor electrodes It is also possible to adopt a configuration in which both edges of the first capacitor electrode are positioned inside the edge, or both edges of the second capacitor electrode are positioned inside both edges of the first capacitor electrode.
- the first insulating film may be a gate insulating film.
- the second insulating film may be an interlayer insulating film that covers the channel of the transistor.
- the first pixel electrode and the first capacitor electrode may be connected by a contact hole penetrating the first and second insulating films.
- the present active matrix substrate may be configured to include a storage capacitor line that is formed in the same layer as the scanning signal line and forms a capacitor with at least one of the first and second pixel electrodes.
- the present active matrix substrate may have a configuration in which correction electrodes are provided in the same layer as the data signal line, and overlap each of the storage capacitor line and the first capacitor electrode.
- the liquid crystal panel includes the active matrix substrate and a counter substrate having a linear protrusion for regulating alignment, and at least a part of the first capacitor electrode is disposed below the linear protrusion. To do.
- the active matrix substrate is disposed in one pixel region in a lower layer than the first pixel electrode, the second pixel electrode, and the first and second pixel electrodes connected to the transistor.
- the first capacitor electrode and the second capacitor electrode are disposed on the lower layer than the first and second pixel electrodes, and the first capacitor electrode and the second capacitor electrode overlap with each other via the first insulating film. A capacitor is formed between the two.
- the above configuration may include a third capacitance electrode connected to the second capacitance electrode in the same layer, and a storage capacitor wiring that forms a capacitance with the third capacitance electrode.
- the liquid crystal panel includes the active matrix substrate and a counter substrate having a common electrode.
- the counter electrode is provided with an alignment regulating slit, and at least a part of the first capacitor electrode is disposed below the slit. It is characterized by being.
- This liquid crystal display unit includes the liquid crystal panel and a driver.
- the present liquid crystal display device includes the liquid crystal display unit and a light source device.
- a television receiver includes the liquid crystal display device and a tuner unit that receives a television broadcast.
- the second pixel electrode (pixel electrode corresponding to the dark subpixel) is burned in while suppressing a short circuit between the first capacitor electrode and the second pixel electrode forming the coupling capacitor. Can be relaxed.
- FIG. 2 is an equivalent circuit diagram of the liquid crystal panel of FIG. 1.
- FIG. 2 is a cross-sectional view of the liquid crystal panel of FIG. 3 is a timing chart illustrating a driving method of a liquid crystal display device including the liquid crystal panel of FIG. 1.
- FIG. 5 is a schematic diagram showing a display state for each frame when the driving method of FIG. 4 is used.
- FIG. 7 is a cross-sectional view of the liquid crystal panel of FIG.
- FIG. 9 is a cross-sectional view of the liquid crystal panel shown in FIG.
- FIG. 16 is a plan view illustrating a modification of the liquid crystal panel illustrated in FIG. 14.
- FIG. 16 is a plan view illustrating a modification example of the liquid crystal panel illustrated in FIG. 15. It is a top view which shows the modification of the liquid crystal panel shown in FIG. It is a top view which shows the modification of the liquid crystal panel shown in FIG.
- FIG. 20 is a plan view illustrating a modification of the liquid crystal panel illustrated in FIG. 19.
- FIG. 20 is a plan view illustrating still another modification of the liquid crystal panel illustrated in FIG. 19.
- (A) is a schematic diagram which shows the structure of this liquid crystal display unit
- (b) is a schematic diagram which shows the structure of this liquid crystal display device. It is a block diagram explaining the whole structure of this liquid crystal display device. It is a block diagram explaining the function of this liquid crystal display device.
- FIG. 26 is a block diagram illustrating functions of the present television receiver. It is a disassembled perspective view which shows the structure of this television receiver. It is a top view which shows the other structural example of this liquid crystal panel.
- FIG. 30 is a cross-sectional view of the liquid crystal panel of FIG. 29 as viewed from the direction of the arrows. It is a top view which shows the structure of the conventional liquid crystal panel.
- the extending direction of the scanning signal lines is hereinafter referred to as the row direction.
- the scanning signal line may extend in the horizontal direction or in the vertical direction. Needless to say, it is good.
- alignment regulating structures for example, slits formed on the pixel electrodes of the active matrix substrate and ribs formed on the color filter substrate
- FIG. 2 is an equivalent circuit diagram showing a part of the liquid crystal panel (for example, normally black mode) according to the present embodiment.
- this liquid crystal panel includes data signal lines 15x and 15y extending in the column direction (up and down direction in the figure), scanning signal lines 16x and 16y extending in the row direction (left and right direction in the figure), rows, and
- Each pixel includes the pixels (101 to 104) arranged in the column direction, the storage capacitor lines 18p and 18q, and the common electrode (counter electrode) com, and the structure of each pixel is the same.
- the pixel column including the pixels 101 and 102 and the pixel column including the pixels 103 and 104 are adjacent to each other, and the pixel row including the pixels 101 and 103 and the pixel row including the pixels 102 and 104 are adjacent to each other. is doing.
- one data signal line, one scanning signal line, and one storage capacitor line are provided corresponding to one pixel, and two pixel electrodes are arranged in the column direction in one pixel. It has been.
- the pixel electrode 17a is connected to the data signal line 15x via the transistor 12a connected to the scanning signal line 16x, and the pixel electrode 17a and the pixel electrode 17b are connected via the coupling capacitor Cab.
- a storage capacitor Cha is formed between the electrode 17a and the storage capacitor line 18p
- a liquid crystal capacitor Cla is formed between the pixel electrode 17a and the common electrode com
- a liquid crystal capacitor Clb is formed between the pixel electrode 17b and the common electrode com. Is formed.
- the pixel electrode 17a is connected to the data signal line 15x (via the transistor 12a).
- the potential of the pixel electrode 17a after the transistor 12a is turned off is Va
- for example,
- means a potential difference between Vb and com potential Vcom
- the subpixel including the pixel electrode 17a is a bright subpixel.
- the subpixel including the pixel and the pixel electrode 17b is a dark subpixel, and halftone display can be performed by the area gradation of the bright subpixel and the dark subpixel. Thereby, the viewing angle characteristic of this liquid crystal display device can be improved.
- FIG. 1 shows a specific example of the pixel 101 in FIG.
- members on the color filter substrate (counter substrate) side are omitted, and only members of the active matrix substrate are shown.
- a transistor 12a is arranged near the intersection of the data signal line 15x and the scanning signal line 16x, the source electrode 8 of the transistor 12a is connected to the data signal line 15x, and the gate electrode of the transistor 12a is scanned.
- the signal electrode 16x also serves as the drain electrode 9 of the transistor 12a is connected to the drain lead electrode 27, and the pixel electrode 17a (first pixel electrode) adjacent to the transistor 12a is formed in the pixel region defined by both signal lines (15x and 16x).
- the pixel electrode 17b (second pixel electrode) are arranged in the column direction.
- the drain lead electrode 27 is connected to the pixel electrode 17a through the contact hole 11a, and the lower layer capacitor electrode 87 (first capacitor electrode) connected to the pixel electrode 17a through the contact hole 11g is connected to the pixel electrode 17b. It extends so that it may overlap.
- the lower layer capacitive electrode 87 is formed in the same layer as the scanning signal line 16x, and in the overlapping portion of the lower layer capacitive electrode 87 and the pixel electrode 17b, a gate insulating film and interlayer insulation are provided between the lower layer capacitive electrode 87 and the pixel electrode 17b. A membrane is arranged. As a result, a coupling capacitor Cab (see FIG. 2) is formed in the overlapping portion between the lower layer capacitor electrode 87 and the pixel electrode 17b.
- the storage capacitor line 18p is disposed close to the scanning signal line 16x, and the storage capacitor line 18p overlaps only the pixel electrode 17a.
- the drain lead electrode 27 is extended in the row direction so as to overlap the storage capacitor wiring 18p. In this case, the storage capacitor line 18p and the drain lead electrode 27 overlap with each other only through the gate insulating film, and a large part of the storage capacitor Cha between the storage capacitor line 18p and the pixel electrode 17a is formed in this overlapping portion.
- FIG. 3 is a cross-sectional view taken along the line XY in FIG.
- the present liquid crystal panel includes an active matrix substrate 3, a color filter substrate 30 facing the active matrix substrate 3, and a liquid crystal layer 40 disposed between both substrates (3, 30).
- the scanning signal line 16x, the storage capacitor line 18p, and the lower layer capacitor electrode 87 are formed on the glass substrate 31, and the gate insulating film 22 is formed so as to cover them.
- a drain extraction electrode 27 is formed on the upper layer of the gate insulating film 22 .
- a semiconductor layer i layer and n + layer
- a source electrode 8 and a drain electrode 9 in contact with the n + layer, and a data signal line 15x are formed in the upper layer of the gate insulating film 22.
- an interlayer insulating film 25 (inorganic interlayer insulating film) is formed so as to cover the metal layer.
- Pixel electrodes 17a and 17b are formed on the interlayer insulating film 25, and an alignment film 7 is formed so as to cover the pixel electrodes.
- the contact hole 11a the interlayer insulating film 25 is penetrated, whereby the pixel electrode 17a and the drain extraction electrode 27 are connected.
- the gate insulating film 22 and the interlayer insulating film 25 are penetrated, and thereby the pixel electrode 17b and the lower layer capacitor electrode 87 are connected.
- the lower-layer capacitor electrode 87 overlaps the pixel electrode 17b via the gate insulating film 22 and the interlayer insulating film 25, and a coupling capacitor Cab (see FIG. 2) is formed at the overlapping portion of both (87 and 17b).
- the storage capacitor line 18p overlaps the drain lead electrode 27 through the gate insulating film 22, and most of the storage capacitor Cha (see FIG. 2) is formed in the overlapping portion of both (18p ⁇ 27).
- the material and thickness of the gate insulating film 22 and the material and thickness of the interlayer insulating film 25 are the function of the gate insulating film 22 as a gate insulating film, the function of the interlayer insulating film 25 as a channel protective film of the transistor, and It may be determined in consideration of the value of the required coupling capacity.
- silicon nitride (SiNx) is used for each of the gate insulating film 22 and the interlayer insulating film 25, and the interlayer insulating film 25 is formed thinner than the gate insulating film 22.
- a colored layer (color filter layer) 14 is formed on a glass substrate 32, a common electrode (com) 28 is formed thereon, and an alignment film 19 is formed so as to cover this. ing.
- FIG. 4 is a timing chart showing a driving method of the present liquid crystal display device (normally black mode liquid crystal display device) provided with the liquid crystal panel shown in FIGS.
- Sv and SV indicate signal potentials supplied to the data signal lines 15x and 15y (see FIG. 2)
- Gx and Gy indicate gate-on pulse signals supplied to the scanning signal lines 16x and 16y
- Va Vd represents the potentials of the pixel electrodes 17a to 17d
- VA and AB represent the potentials of the pixel electrodes 17A and 17B, respectively.
- the scanning signal lines are sequentially selected, the polarity of the signal potential supplied to the data signal lines is inverted every horizontal scanning period (1H), and the same number in each frame.
- the polarity of the signal potential supplied in the horizontal scanning period is inverted in units of one frame, and in the same horizontal scanning period, a signal potential having a reverse polarity is supplied to two adjacent data signal lines.
- scanning signal lines are sequentially selected, and one of the two adjacent data signal lines has a first horizontal scanning period (for example, the pixel electrode 17a).
- a positive polarity signal potential is supplied during the second horizontal scanning period, a negative polarity signal potential is supplied during the second horizontal scanning period, and the other of the two data signal lines is negative during the first horizontal scanning period.
- a polar signal potential is supplied, and a positive polarity signal potential is supplied in the second horizontal scanning period.
- As a result, as shown in FIG. 4,
- the subpixel including the pixel electrode 17a is a bright subpixel (hereinafter, “bright”).
- a sub-pixel including the pixel electrode 17b (positive polarity) includes a dark sub-pixel (hereinafter “dark”)
- a sub-pixel including the pixel electrode 17c (negative polarity) includes “bright” and a pixel electrode 17d (negative polarity).
- the sub-pixel is “dark”, and the whole is as shown in FIG.
- the scanning signal line is sequentially selected, and a negative polarity signal potential is applied to one of the two adjacent data signal lines in the first horizontal scanning period (for example, the writing period of the pixel electrode 17a).
- a positive polarity signal potential is supplied during the second horizontal scanning period, and a positive polarity signal potential is supplied during the first horizontal scanning period to the other of the two data signal lines.
- a negative-polarity signal potential is supplied during the horizontal scanning period. Accordingly, as shown in FIG.
- each pixel electrode is provided with an alignment regulating slit, and a color filter
- the substrate is provided with orientation regulating ribs.
- an orientation regulating slit may be provided in the common electrode of the color filter substrate.
- the method for manufacturing a liquid crystal panel includes an active matrix substrate manufacturing process, a color filter substrate manufacturing process, and an assembly process in which both substrates are bonded to each other and filled with liquid crystal.
- a metal film such as titanium, chromium, aluminum, molybdenum, tantalum, tungsten, or copper, an alloy film thereof, or a laminated film thereof (thickness: 1000 mm to 3000 mm) is sputtered onto a substrate such as glass or plastic.
- patterning is performed by photolithography technology (Photo Engraving Process, hereinafter referred to as “PEP technology”) to form scanning signal lines (transistor gate electrodes), storage capacitor wires, and lower layer capacitor electrodes To do.
- PEP technology Photo Engraving Process
- an inorganic insulating film such as silicon nitride or silicon oxide is formed on the entire substrate on which the scanning signal lines and the like are formed by a CVD (Chemical Vapor Deposition) method to form a gate insulating film (
- the substrate temperature at the time of film formation is, for example, 350 ° C.).
- an intrinsic amorphous silicon film (thickness 1000 to 3000 mm) and an n + amorphous silicon film (thickness 400 to 700 mm) doped with phosphorus are continuously formed on the gate insulating film (whole substrate) by CVD.
- patterning is performed by the PEP technique, and a silicon laminated body including an intrinsic amorphous silicon layer and an n + amorphous silicon layer is formed in an island shape on the gate electrode.
- a metal film such as titanium, chromium, aluminum, molybdenum, tantalum, tungsten, or copper, an alloy film thereof, or a stacked film thereof (thickness 1000 to 3000 mm) is formed on the entire substrate on which the silicon laminate is formed. Then, patterning is performed by a PEP technique to form data signal lines, transistor source / drain electrodes, and drain lead electrodes (formation of a metal layer).
- the n + amorphous silicon layer constituting the silicon stacked body is removed by etching to form a transistor channel.
- the semiconductor layer may be formed of an amorphous silicon film as described above.
- a polysilicon film may be formed, or a laser annealing treatment is performed on the amorphous silicon film and the polysilicon film to form a crystal. May be improved. Thereby, the moving speed of the electrons in the semiconductor layer is increased, and the characteristics of the transistor (TFT) can be improved.
- an inorganic insulating film such as silicon nitride or silicon oxide is formed by CVD on the entire substrate on which the data signal lines and the like are formed, and an interlayer insulating film is formed (at the time of film formation).
- the substrate temperature is, for example, 250 ° C.).
- the PEP technique is used to etch away the interlayer insulating film or the interlayer insulating film and the gate insulating film to form a contact hole.
- the interlayer insulating film is removed at the position where the contact hole 11a is formed in FIGS. 1 and 3, and the interlayer insulating film and the gate insulating film are removed at the position where the contact hole 11g is formed.
- a transparent conductive film (thickness 1000 to 2000 mm) made of ITO (Indium / Tin / Oxide), IZO (Indium / Zinc / Oxide), zinc oxide, tin oxide or the like is formed on the entire substrate on the interlayer insulating film in which the contact holes are formed Is formed by sputtering, and then patterned by PEP technology to form each pixel electrode.
- polyimide resin is printed on the entire substrate on the pixel electrode with a thickness of 500 to 1000 mm, and then fired and rubbed in one direction with a rotating cloth to form an alignment film.
- the active matrix substrate is manufactured as described above.
- the color filter substrate manufacturing process will be described below.
- a chromium thin film or a resin containing a black pigment is formed on a glass or plastic substrate (entire substrate), and then patterned by PEP technology to form a black matrix.
- red, green and blue color filter layers are formed in a pattern in the gap of the black matrix by using a pigment dispersion method or the like.
- a transparent conductive film made of ITO, IZO, zinc oxide, tin oxide or the like is formed on the entire substrate on the color filter layer to form a common electrode (com).
- polyimide resin is printed on the entire substrate on the common electrode with a thickness of 500 to 1000 mm, and then fired and rubbed in one direction with a rotating cloth to form an alignment film.
- a color filter substrate can be manufactured as described above.
- a seal material made of a thermosetting epoxy resin or the like is applied to one of the active matrix substrate and the color filter substrate by screen printing in a frame-like pattern lacking the liquid crystal inlet portion, and the liquid crystal layer is applied to the other substrate.
- a spherical spacer having a diameter corresponding to the thickness and made of plastic or silica is dispersed.
- the active matrix substrate and the color filter substrate are bonded together, and the sealing material is cured.
- the liquid crystal panel is manufactured.
- the gate insulating film 22 with high density exists in addition to the interlayer insulating film 25 between the lower layer capacitive electrode 87 and the pixel electrode 17b that form the coupling capacitance Cab, Short circuit generation can be suppressed.
- the interlayer insulating film 25 that is a channel protective film is generally less dense than the gate insulating film 22 (in general, the interlayer insulating film is formed at a lower temperature than the gate insulating film. Therefore, in the configuration in which the coupling electrode 176 and the pixel electrode 190b overlap with each other only through the interlayer insulating film as shown in FIG. 31, both are easily short-circuited.
- the burn-in of the pixel electrode 17b corresponding to the dark sub-pixel can be reduced.
- the coupling electrode 176 and the pixel electrode 190b overlap with each other only through the interlayer insulating film as shown in FIG. 31, the coupling electrode 176 and the pixel electrode 190b are too close to each other, so that the finished width of the coupling electrode 176 varies. In this case, the variation in the value of the coupling capacitance increases.
- the lower layer capacitive electrode 87 and the pixel electrode 17b are not too close to each other, variation in the value of the coupling capacitance when the line width of the lower layer capacitive electrode 87 varies can be suppressed.
- silicon nitride (SiNx) is used for each of the gate insulating film 22 and the interlayer insulating film 25, and the interlayer insulating film 25 is formed thinner than the gate insulating film 22.
- SiNx silicon nitride
- the thickness of the gate insulating film 22 has a great influence on the transistor characteristics, and it is not preferable to greatly change the thickness in order to increase the value of the coupling capacitance.
- the thickness of the interlayer insulating film 25 (channel protective film) has a relatively small influence on the transistor characteristics.
- the thickness of the interlayer insulating film 25 for example, to set the thickness of the interlayer insulating film 25 to be equal to or less than the thickness of the gate insulating film 22.
- an organic interlayer insulating film 26 thicker than this is provided on the interlayer insulating film (inorganic interlayer insulating film) 25 of FIG. 3, and as shown in FIG. ) Structure.
- effects such as reduction of various parasitic capacitances, prevention of short-circuiting between wirings, and reduction of pixel electrode tearing due to planarization can be obtained.
- the organic interlayer insulating film 26 penetrates the portion K that overlaps the lower layer capacitive electrode 87. In this way, the above effect can be obtained while sufficiently securing the value of the coupling capacitance.
- the pixel electrode is connected to the data signal line or the scanning signal line as shown in FIGS. It is possible to increase the aperture ratio.
- the inorganic interlayer insulating film 25, the organic interlayer insulating film 26 and the contact holes 11a and 11g in FIG. 7 can be formed as follows, for example. That is, after forming transistors and data signal lines, a mixed gas of SiH 4 gas, NH 3 gas, and N 2 gas is used to cover the entire surface of the substrate, and an interlayer insulating film 25 made of SiNx having a thickness of about 3000 mm ( A passivation film) is formed by CVD. Thereafter, an organic interlayer insulating film 26 made of a positive photosensitive acrylic resin having a thickness of about 3 ⁇ m is formed by spin coating or die coating.
- photolithography is performed to form a penetrating portion of the organic interlayer insulating film 26 and various contact patterns. Further, using the patterned organic interlayer insulating film 26 as a mask, CF 4 gas and O 2 gas are mixed.
- the interlayer insulating film 25 is dry etched using a mixed gas. Specifically, for example, the penetration portion of the organic interlayer insulating film is half-exposed in the photolithography process so that the organic interlayer insulating film remains thin when development is completed, while the contact hole portion is By performing full exposure in the photolithography process, an organic interlayer insulating film is not left when development is completed.
- the remaining film (of the organic interlayer insulating film) is removed from the penetrated portion of the organic interlayer insulating film, and the contact hole 11a portion is removed.
- the inorganic interlayer insulating film under the organic interlayer insulating film is removed, and the inorganic interlayer insulating film and the gate insulating film under the organic interlayer insulating film are removed from the contact hole 11g. That is, the interlayer insulating film 25 is removed in the contact hole 11a portion and the surface of the drain lead electrode 27 (for example, an Al film) is exposed to stop the etching.
- the interlayer insulating film 25 and the gate insulating film are removed. Etching stops when the film 22 is removed and the surface of the lower capacitive electrode 87 (for example, an Al film) is exposed.
- the organic interlayer insulating film 26 may be, for example, an insulating film made of an SOG (spin-on glass) material, and the organic interlayer insulating film 26 may be an acrylic resin, an epoxy resin, a polyimide resin, a polyurethane resin, or a novolac resin. , And at least one of siloxane resins may be included.
- an upper layer capacitive electrode 47 is provided so as to overlap the lower layer capacitive electrode 87 and the pixel electrode 17b.
- the upper capacitor electrode 47 is formed on the gate insulating film 22 (same layer as the drain lead electrode 27) and is connected to the pixel electrode 17b through the contact hole 11j.
- the lower layer capacitive electrode 87 and the upper layer capacitive electrode 47 overlap with each other only through the gate insulating film 22, and a coupling capacitance is formed at this overlapping portion, so that the value of the coupling capacitance Cab is sufficiently ensured. be able to. Since the gate insulating film 22 is denser than the interlayer insulating film 25 as described above, it is possible to suppress a short circuit at the capacitive coupling formation portion as compared with the configuration shown in FIG.
- both edges of the lower layer capacitive electrode 87 are positioned inside both edges of the upper layer capacitive electrode 47, the alignment of the lower layer capacitive electrode 87 and the upper layer capacitive electrode 47 is shifted in the row direction.
- the coupling capacitance value hardly fluctuates (strong against misalignment). It should be noted that it may be configured such that both edges of the upper capacitor electrode 47 are positioned inside both edges of the lower capacitor electrode 87.
- the liquid crystal panel shown in FIG. 1 can also be configured as shown in FIG. That is, although not shown in FIG. 1, in the MVA liquid crystal panel, as shown in FIG. 11, the pixel electrode of the active matrix substrate is provided with a slit SL for alignment control, and the color filter substrate is for alignment control. Ribs Li (linear protrusions) are provided.
- the aperture ratio can be increased by disposing the lower capacitor electrode 87 of the active matrix substrate under the rib Li.
- a slit may be provided in the common electrode of the CF (color filter) substrate instead of the rib Li.
- FIG. 12 shows another specific example of the present liquid crystal display device.
- a transistor 12a is disposed near the intersection of the data signal line 15x and the scanning signal line 16x, the source electrode 8 of the transistor 12a is connected to the data signal line 15x, and the scanning signal line 16x is connected to the gate electrode of the transistor 12a.
- the drain electrode 9 of the transistor 12a is connected to the drain lead electrode 27.
- the pixel electrode 17a first pixel electrode
- the pixel Electrodes 17b second pixel electrodes
- the upper capacitor electrode 47 connected to the pixel electrode 17b through the contact hole 11j extends so as to overlap the pixel electrode 17a, and the lower capacitor electrode 87 so as to overlap the upper capacitor electrode 47 and the pixel electrode 17a.
- the lower capacitor electrode 87 and the pixel electrode 17a are connected via a contact hole 11g.
- the upper layer capacitive electrode 47 has two edges along the column direction below the pixel electrode 17a, and the lower layer capacitive electrode 87 also has two edges along the column direction below the pixel electrode 17a. When viewed in plan, both edges of the lower layer capacitive electrode 87 are located inside both edges of the upper layer capacitive electrode 47.
- the lower layer capacitor electrode 87 is formed in the same layer as the scanning signal line 16x
- the upper layer capacitor electrode 47 is formed in the same layer as the data signal line 15x
- the lower layer capacitor electrode 87, the upper layer capacitor electrode 47, and the pixel electrode 17a In the overlapping portion, a gate insulating film is disposed between the lower capacitive electrode 87 and the upper capacitive electrode 47, and an interlayer insulating film is disposed between the upper capacitive electrode 47 and the pixel electrode 17a.
- a first coupling capacitor formed in an overlapping portion with the upper layer capacitive electrode 47 and a second coupling capacitor formed in an overlapping portion between the upper layer capacitive electrode 47 and the pixel electrode 17a are arranged in parallel.
- a storage capacitor line 18p is arranged so as to cross the pixel region, and the storage capacitor line 18p overlaps with the pixel electrode 17a and the pixel electrode 17b through the gate insulating film and the interlayer insulating film. As a result, a storage capacitor is formed at the overlapping portion of the storage capacitor wiring 18p and the pixel electrode 17a, and a storage capacitor is formed at the overlapping portion of the storage capacitor wiring 18p and the pixel electrode 17b.
- FIG. 13 is a cross-sectional view taken along the line XY in FIG.
- the storage capacitor wiring 18p and the lower layer capacitor electrode 87 are formed on the glass substrate 31, and the gate insulating film 22 is formed so as to cover them.
- An upper capacitor electrode 47 and a drain lead electrode 27 are formed on the gate insulating film 22.
- an interlayer insulating film 25 is formed so as to cover the metal layer.
- Pixel electrodes 17a and 17b are formed on the interlayer insulating film 25, and an alignment film 7 is formed so as to cover the pixel electrodes.
- the contact hole 11j the interlayer insulating film 25 is penetrated, whereby the pixel electrode 17b and the upper capacitor electrode 47 are connected.
- the interlayer insulating film 25 and the gate insulating film 22 are penetrated, whereby the lower-layer capacitor electrode 87 and the pixel electrode 17a are connected.
- the lower capacitive electrode 87 overlaps the upper capacitive electrode 47 with the gate insulating film 22 interposed therebetween, and a first coupling capacitance is formed in the overlapping portion (87, 47).
- the upper capacitor electrode 47 overlaps the pixel electrode 17a with the interlayer insulating film 25 interposed therebetween, and a second coupling capacitor is formed at the overlapping portion of both (47, 17a).
- the storage capacitor line 18p overlaps the pixel electrode 17a via the gate insulating film 22 and the interlayer insulating film 25, and a storage capacitor is formed at the overlapping portion of both (18p, 17a).
- the storage capacitor line 18p overlaps with the pixel electrode 17b through the gate insulating film 22 and the interlayer insulating film 25, and a storage capacitor is formed at the overlapping portion of both (18p and 17b).
- the first coupling capacitance (the coupling capacitance of the overlapping portion of the lower layer capacitance electrode 87 and the upper layer capacitance electrode 47) and the second coupling capacitance (the coupling of the overlapping portion of the upper layer capacitance electrode 47 and the pixel electrode 17a) in the thickness direction of the substrate.
- the first and second coupling capacitors are formed in parallel, and the pixel electrodes 17a and 17b can be connected via the paralleled first and second coupling capacitors.
- the burn-in of the pixel electrode corresponding to the dark subpixel can be reduced while suppressing a short circuit in the coupling capacitance forming portion
- the area of the upper capacitor electrode 47 can be reduced without changing the value of the coupling capacitance.
- the coupling capacity can be increased without reducing the aperture ratio and increasing the aperture ratio, or without changing the area of the upper capacitive electrode 47 (without changing the aperture ratio).
- silicon nitride SiNx
- the interlayer insulating film 25 is formed thinner than the gate insulating film 22.
- the thickness of the gate insulating film 22 has a great influence on the transistor characteristics, and it is not preferable to greatly change the thickness because of the above effects such as improving the aperture ratio or increasing the value of the coupling capacitance.
- the thickness of the interlayer insulating film 25 channel protective film
- the thickness of the interlayer insulating film 25 is set to be equal to or less than the thickness of the gate insulating film 22 as in the present liquid crystal panel. It is preferable to do.
- both edges of the lower layer capacitive electrode 87 are positioned inside both edges of the upper layer capacitive electrode 47, and therefore the lower layer capacitive electrode 87 and the upper layer capacitive electrode 47 are aligned. Even if it deviates in the direction, the coupling capacitance value hardly changes (strong against misalignment).
- both edges of the upper capacitor electrode 47 may be positioned inside both edges of the lower capacitor electrode 87. However, as shown in FIG. If the width of the upper capacitor electrode 47 that forms the coupling capacitance with both the pixel electrode 17a is increased, the above-described effect of improving the aperture ratio or increasing the value of the coupling capacitance can be further enhanced.
- both edges of the lower layer capacitive electrode 87 are positioned inside both edges of the upper layer capacitive electrode 47, the alignment of the lower layer capacitive electrode 87 and the upper layer capacitive electrode 47 is shifted in the row direction.
- the coupling capacitance value hardly fluctuates (strong against misalignment). From the viewpoint of being resistant to misalignment, it can be configured such that both edges of the upper capacitive electrode 47 are positioned inside both edges of the lower capacitive electrode 87, but the former (see FIG. 12 configuration) is more desirable.
- the pixel electrode 17b is formed in a V shape when viewed in the row direction, and the pixel electrode 17a is configured to surround the pixel electrode 17b.
- the pixel electrode 17b includes two edges E1 and E2 that form 45 degrees with respect to the row direction, and two edges E3 and E4 that form 315 degrees with respect to the row direction.
- Each of the gaps between the pixel electrode 17a and the edge of the pixel electrode 17a is parallel to the alignment regulating slits SL1 to SL4.
- the drain lead electrode 27 is connected to the pixel electrode 17a through the contact hole 11a, and the lower-layer capacitor electrode 87 connected to the pixel electrode 17a through the contact hole 11g extends so as to pass under the slit SL3. It overlaps with the pixel electrode 17b. In this configuration, a coupling capacitor is formed at the overlapping portion of the lower layer capacitor electrode 87 and the pixel electrode 17b.
- a storage capacitor line 18p is arranged so as to cross the pixel region, and the storage capacitor line 18p overlaps with the pixel electrode 17a and the pixel electrode 17b through the gate insulating film and the interlayer insulating film. As a result, a storage capacitor is formed at the overlapping portion of the storage capacitor wiring 18p and the pixel electrode 17a, and a storage capacitor is formed at the overlapping portion of the storage capacitor wiring 18p and the pixel electrode 17b.
- the storage capacitor line 18p and the lower layer capacitor electrode 87 are brought close to each other so as not to be short-circuited, and the correction electrode 44 overlapping each of the storage capacitor line 18p and the lower layer capacitor electrode 87 is connected to the data signal line 15x. And in the same layer.
- a defect for example, source / drain short-circuit
- the drain lead electrode 27 is cut and the lower-layer capacitor electrode 87 and the correction electrode 44 are melt-connected and the lower-layer capacitor electrode
- the pixel electrode 17a can be connected to the storage capacitor wiring 18p by melt-connecting 87 and the storage capacitor wiring 18p (see FIG. 16). Thereby, the pixel electrodes 17a and 17b can be black spots.
- an upper layer capacitor electrode 47 is provided so as to overlap the lower layer capacitor electrode 87 and the pixel electrode 17b.
- the upper capacitor electrode 47 is formed on the gate insulating film 22 (same layer as the drain lead electrode 27), and is connected to the pixel electrode 17b through the contact hole 11j.
- the lower-layer capacitor electrode 87 and the upper-layer capacitor electrode 47 overlap with each other only through the gate insulating film 22, and a coupling capacitance is formed in this overlapping portion, so that a sufficient coupling capacitance value can be secured. . Since the gate insulating film 22 is denser than the interlayer insulating film 25, it is possible to suppress the occurrence of a short circuit at the capacitive coupling formation portion as compared with the conventional case.
- both edges of the lower layer capacitive electrode 87 are positioned inside both edges of the upper layer capacitive electrode 47, the alignment of the lower layer capacitive electrode 87 and the upper layer capacitive electrode 47 is shifted in the row direction.
- the coupling capacitance value hardly fluctuates (strong against misalignment). Note that the both edges of the upper capacitor electrode 47 may be positioned inside both edges of the lower capacitor electrode 87.
- the value of the coupling capacitance can be determined almost regardless of the thickness of the interlayer insulating film, so that it can be said that it is more suitable for the case where the channel protective film is formed thick.
- the pixel electrode 17a is formed in a triangular shape when viewed in the row direction, and the pixel electrode 17b is configured to surround the pixel electrode 17a.
- the pixel electrode 17a includes an edge E1 that forms 45 degrees with respect to the row direction and an edge E2 that forms 315 degrees with respect to the row direction, and the pixel electrode 17b that is parallel to the edge E1.
- Each of the gap between the edge E2 and the gap between the edge E2 and the edge of the pixel electrode 17b parallel to the edge E2 is an alignment regulating slit SL1 and SL2.
- the drain lead wiring 57 led out from the drain electrode 9 is connected to the pixel electrode 17a through the contact hole 11a, and the upper capacitor electrode 47 connected to the pixel electrode 17b through the contact hole 11j is below the slit SL2.
- a lower capacitor electrode 87 is provided so as to overlap the upper capacitor electrode 47 and the pixel electrode 17a, and the lower capacitor electrode 87 is connected to the pixel electrode 17a through a contact hole 11g.
- the upper capacitor electrode 47 has two edges that form 45 degrees with respect to the row direction under the pixel electrode 17a, and the lower capacitor electrode 87 also has 45 degrees with respect to the row direction under the pixel electrode 17a. When viewed in plan, both edges of the lower layer capacitor electrode 87 are located inside the both edges of the upper layer capacitor electrode 47.
- annular storage capacitor extending portion 18px that extends over the outer periphery of the pixel electrode 17a extends from the storage capacitor wiring 18p, and the storage capacitor extending portion 18px extends through the gate insulating film and the interlayer insulating film to form the pixel electrode 17a. And the pixel electrode 17b.
- a storage capacitor is formed at an overlapping portion between the storage capacitor extending portion 18px and the pixel electrode 17a, and a storage capacitor is formed at an overlapping portion between the storage capacitor extending portion 18px and the pixel electrode 17b.
- the retention capacity extending portion 18px is overlapped on the outer periphery of the pixel electrode 17a, so that the aperture ratio can be increased while the retention capacity is secured, and the alignment regulating force can be further enhanced.
- This liquid crystal panel can also be configured as shown in FIG.
- a transistor 12a is disposed in the vicinity of the intersection of the data signal line 15x and the scanning signal line 16x, the source electrode 8 of the transistor 12a is connected to the data signal line 15x, and the gate electrode of the transistor 12a is scanned with the scanning signal.
- the line 16x also serves as the drain electrode 9 of the transistor 12a is connected to the drain lead electrode 27.
- the pixel electrode 17au adjacent to the transistor 12a, the pixel electrode 17b, A pixel electrode 17av having the same shape as the pixel electrode 17au is provided.
- the pixel electrode 17au is an isosceles trapezoidal shape having an edge E1 forming 315 degrees with respect to the row direction and an edge E2 forming 45 degrees with respect to the row direction and having a base along the column direction.
- the pixel electrode 17av includes The leg E is an isosceles trapezoidal shape having a base along the column direction, with an edge E3 forming 45 degrees with respect to the row direction and an edge E4 forming 315 degrees with respect to the row direction.
- the pixel electrodes 17au and 17av are arranged so as to coincide with the pixel electrode 17av when the pixel electrode 17au is rotated 180 degrees around the center of the pixel region, and the pixel electrode 17b fits with the pixel electrodes 17au and 17av.
- a gap between the edge of the pixel electrode 17b parallel to the edge and a gap between the edge E4 of the pixel electrode 17av and the edge of the pixel electrode 17b parallel to the edge are slits SL1 to SL4 for regulating the orientation.
- the drain extraction electrode 27 is connected to the pixel electrode 17au through the contact hole 11a, and is connected to the pixel electrode 17au through the contact hole 11u, and is formed in the same layer as the scanning signal line 16x. However, it extends in the column direction, passes under the slit SL2, and then changes its direction by 90 degrees under the pixel electrode 17b to reach under the pixel electrode 17av. The end of the lower capacitive electrode 87 and the pixel electrode 17av are contact holes. 11v. Further, an upper capacitor electrode 47 is formed on the gate insulating film (same layer as the data signal line 15x) so as to overlap the lower capacitor electrode 87 and the pixel electrode 17b. The upper capacitor electrode 47 is connected to the pixel via the contact hole 11j.
- the upper capacitor electrode 47 has two edges along the column direction below the pixel electrode 17b
- the lower capacitor electrode 87 also has two edges along the column direction below the pixel electrode 17b.
- both edges of the lower layer capacitive electrode 87 are located inside both edges of the upper layer capacitive electrode 47.
- the lower layer capacitive electrode 87 and the upper layer capacitive electrode 47 overlap only through the gate insulating film 22, and a coupling capacitance is formed in this overlapping portion, so that a sufficient coupling capacitance value can be secured. . Since the gate insulating film 22 is denser than the interlayer insulating film 25, it is possible to suppress the occurrence of a short circuit at the capacitive coupling formation portion as compared with the conventional case.
- both edges of the lower layer capacitive electrode 87 are positioned inside both edges of the upper layer capacitive electrode 47, the alignment of the lower layer capacitive electrode 87 and the upper layer capacitive electrode 47 is shifted in the row direction.
- the coupling capacitance value hardly fluctuates (strong against misalignment). Note that the both edges of the upper capacitor electrode 47 may be positioned inside both edges of the lower capacitor electrode 87.
- the channel protective film is formed thick (including the organic interlayer insulating film in the channel protective film). It can be said that it is preferable in some cases.
- an annular storage capacitor extending portion 18px extending over the outer periphery of the pixel region extends, and the storage capacitor extending portion 18px is connected to the pixel electrode 17a and the interlayer insulating film via the gate insulating film and the interlayer insulating film. It overlaps with each pixel electrode 17b.
- a storage capacitor is formed at an overlapping portion between the storage capacitor extending portion 18px and the pixel electrode 17a, and a storage capacitor is formed at an overlapping portion between the storage capacitor extending portion 18px and the pixel electrode 17b.
- FIG. 19 by overlapping the storage capacitor extension portion 18px on the outer periphery of the pixel region, it is possible to suppress seizing of the pixel electrode 17b that is electrically floating while securing the storage capacitor.
- the storage capacitor extending portion 18px is overlaid on the outer periphery of the pixel electrode 17b, and the lower layer capacitor electrode 87 is extended in the row direction.
- the lower-layer capacitor electrode 87 connected to the pixel electrode 17au through the contact hole 11u extends in the row direction in the center of the pixel, first passes under the slit SL2, reaches below the pixel electrode 17b, and further passes through the slit SL3. It reaches under the pixel electrode 17av, and the end of the lower capacitive electrode 87 and the pixel electrode 17av are connected via the contact hole 11v.
- an upper layer capacitive electrode 47 is provided so as to overlap the lower layer capacitive electrode 87 and the pixel electrode 17b, and the upper layer capacitive electrode 47 is connected to the pixel electrode 17b through the contact hole 11j.
- the aperture ratio can be increased while the storage capacitor is secured, and the alignment regulating force can be further increased.
- a lower layer capacitor electrode 87 formed in the same layer as the scanning signal line 16x and connected to the pixel electrode 17au via the contact hole 11u extends in the row direction and is divided into two under the pixel electrode 17b.
- One of them extends from the edges E2 and E3 of the pixel electrode 17b so as to form 315 degrees with respect to the row direction in plan view so as to crawl under the rib Li formed on the color filter substrate, and the other Passes through the slit SL3 and reaches the lower side of the pixel electrode 17av, and the other end is connected to the pixel electrode 17av through the contact hole 11v.
- An electrode 47 is formed, and the upper capacitor electrode 47 is connected to the pixel electrode 17b through the contact hole 11j.
- a storage capacitor line 18p is arranged so as to cross the pixel region, a storage capacitor electrode 67b is provided so as to overlap the storage capacitor line 18p and the pixel electrode 17b, and a storage capacitor is overlapped with the storage capacitor line 18p and the pixel electrode 17av.
- An electrode 67av is provided.
- the storage capacitor electrodes 67b and 67av are both formed in the same layer as the data signal line 15x, the pixel electrode 17b and the storage capacitor electrode 67b are connected through the contact hole 11i, and the pixel electrode 17av and the storage capacitor electrode 67av. Are connected via a contact hole 11v.
- the lower-layer capacitor electrode 87 As shown in FIG. 21, by setting the lower-layer capacitor electrode 87 so as to crawl under the rib Li, it is possible to improve the aperture ratio and the alignment regulating force.
- a slit may be provided in the common electrode of the CF substrate instead of the rib Li.
- the storage capacitor electrodes 67b and 67av the storage capacitor between the storage capacitor line 18p and the pixel electrodes 17au and 17av and the storage capacitor between the storage capacitor line 18p and the pixel electrode 17b can be increased. it can.
- FIG. 27 shows another configuration of the present liquid crystal panel
- FIG. 28 shows a cross-sectional view of FIG.
- the active matrix substrate of the liquid crystal panel shown in FIG. 27 includes transistors 12a and 12b connected to the scanning signal line 16x, and a transistor 112 connected to the scanning signal line 16y that is the next stage of the scanning signal line 16x, and data In the pixel region defined by the signal line 15x and the scanning signal line 16x, the pixel electrodes 17au, 17av, and 17b, the storage capacitor electrodes 67b and 67av, and the upper capacitor electrodes 87 and 97 that are formed in the same layer as the data signal line 15x.
- connection wiring 57 and a lower layer capacitor electrode 77 formed in the same layer as the scanning signal line 16x are provided.
- the shape and arrangement of the pixel electrodes 17au, 17av, and 17b are the same as those in FIG.
- the pixel electrode 17au and the pixel electrode 17av are connected through the contact holes 11u and 11v and the connection wiring 57
- the storage capacitor electrode 67b is connected to the pixel electrode 17b through the contact hole 11i
- the storage capacitor electrode 67av is
- the contact hole 11j is connected to the pixel electrode 17av
- the lower capacitor electrode 77 is connected to the pixel electrode 17b via the contact hole 11f.
- the common source electrode 8 of the transistors 12a and 12b is connected to the data signal line 15x, the drain electrode 9a of the transistor 12a is connected to the pixel electrode 17au via the contact hole 11a, and the drain electrode 9b of the transistor 12b is connected to the contact hole 11b.
- the source electrode 108 of the transistor 112 is connected to the storage capacitor electrode 67av (connected in the same layer)
- the drain electrode 109 of the transistor 112 is connected to the upper capacitor electrode 87 (connected in the same layer)
- the upper capacitor electrode 87 is connected.
- the storage capacitor electrode 67 b overlaps the storage capacitor wiring 18 p through the gate insulating film 22, and the storage capacitor electrode 67 av is connected to the storage capacitor wiring 18 p through the gate insulating film 22.
- the upper capacitor electrode 97 overlaps with the storage capacitor wiring 18p through the gate insulating film 22, and the pixel through the channel protective film (a laminated film of the inorganic interlayer insulating film 25 and the organic interlayer insulating film 26 thicker than this).
- the upper capacitor electrode 87 overlaps with the pixel electrode 17b via a channel protective film (a laminated film of the inorganic interlayer insulating film 25 and the organic interlayer insulating film 26 thicker than this), and the lower capacitor electrode 77 is gated. It overlaps with the upper capacitive electrode 87 through the insulating film 22.
- a storage capacitor between the pixel electrode 17av and the storage capacitor line 18p is formed in an overlapping part between the storage capacitor electrode 67av and the storage capacitor line 18p
- a pixel electrode 17b is formed in an overlap part between the storage capacitor electrode 67b and the storage capacitor line 18p.
- a storage capacitor between the storage capacitor wiring 18p is formed, and most of the coupling capacitance between the pixel electrodes 17au and 17av and the pixel electrode 17b is formed at the overlapping portion of the lower layer capacitor electrode 77 and the upper layer capacitor electrode 87, and the remainder of the coupling capacitor Are formed at the overlapping portion of the upper-layer capacitor electrode 87 and the pixel electrode 17b and the overlapping portion of the upper-layer capacitor electrode 97 and the pixel electrode 17b.
- the same data signal potential is written to the pixel electrodes 17au, 17av, and 17b during scanning of the scanning signal line 16x, but the pixel electrode 17av is scanned during (next stage) scanning of the scanning signal line 16y.
- 17au and the pixel electrode 17b are connected via the coupling capacitance.
- dark subpixels formed by the pixel electrodes 17au and 17av and bright subpixels formed by the pixel electrode 17b are formed.
- the lower layer capacitor electrode 77 and the upper layer capacitor electrode 87 overlap the pixel electrode 17b, but the present invention is not limited to this.
- the lower layer capacitive electrode 77 and the upper layer capacitive electrode 87 may overlap the pixel electrode 17av.
- the lower-layer capacitor electrode 77 and the upper-layer capacitor electrode 87 overlap with each other via the gate insulating film 22, and a coupling capacitor between the pixel electrodes 17au and 17av and the pixel electrode 17b is formed in these overlapping portions.
- the present liquid crystal display unit and the liquid crystal display device are configured as follows. That is, the two polarizing plates A and B are attached to both surfaces of the liquid crystal panel so that the polarizing axis of the polarizing plate A and the polarizing axis of the polarizing plate B are orthogonal to each other. In addition, you may laminate
- drivers gate driver 202, source driver 201 are connected.
- ACF is temporarily pressure-bonded to the terminal portion of the liquid crystal panel.
- the TCP on which the driver is placed is punched out of the carrier tape, aligned with the panel terminal electrode, and heated and pressed.
- the circuit board 209 (PWB) for connecting the driver TCPs and the input terminal of the TCP are connected by ACF.
- the display control circuit 209 is connected to each driver (201, 202) of the liquid crystal display unit via the circuit board 201, and integrated with the lighting device (backlight unit) 204.
- the liquid crystal display device 210 is obtained.
- FIG. 23 is a block diagram showing a configuration of the present liquid crystal display device.
- the liquid crystal display device includes a display unit (liquid crystal panel), a source driver (SD), a gate driver (GD), and a display control circuit.
- the source driver drives the data signal line
- the gate driver drives the scanning signal line
- the display control circuit controls the source driver and the gate driver.
- the display control circuit controls a display operation from a digital video signal Dv representing an image to be displayed, a horizontal synchronization signal HSY and a vertical synchronization signal VSY corresponding to the digital video signal Dv from an external signal source (for example, a tuner). For receiving the control signal Dc. Further, the display control circuit, based on the received signals Dv, HSY, VSY, and Dc, uses a data start pulse signal SSP and a data clock as signals for displaying an image represented by the digital video signal Dv on the display unit.
- Signal SCK digital image signal DA (signal corresponding to video signal Dv) representing an image to be displayed
- gate start pulse signal GSP gate start pulse signal GSP
- gate clock signal GCK gate driver output control signal (scanning signal output control signal) GOE is generated and these are output.
- the video signal Dv is output as a digital image signal DA from the display control circuit, and a pulse corresponding to each pixel of the image represented by the digital image signal DA.
- a data clock signal SCK is generated as a signal consisting of the above, a data start pulse signal SSP is generated as a signal that becomes high level (H level) for a predetermined period every horizontal scanning period based on the horizontal synchronization signal HSY, and the vertical synchronization signal VSY
- the gate start pulse signal GSP is generated as a signal that becomes H level only for a predetermined period every one frame period (one vertical scanning period), and the gate clock signal GCK is generated based on the horizontal synchronization signal HSY, and the horizontal synchronization signal HSY and
- a gate driver output control signal GOE is generated based on the control signal Dc.
- the digital image signal DA the polarity inversion signal POL for controlling the polarity of the signal potential (data signal potential)
- the data start pulse signal SSP the data start pulse signal SSP
- the data clock signal SCK the data clock signal SCK
- the gate start pulse signal GSP, the gate clock signal GCK, and the gate driver output control signal GOE are input to the gate driver.
- the source driver is based on the digital image signal DA, the data clock signal SCK, the data start pulse signal SSP, and the polarity inversion signal POL, and an analog potential (signal corresponding to the pixel value in each scanning signal line of the image represented by the digital image signal DA. Potential) is sequentially generated every horizontal scanning period, and these data signals are output to the data signal lines.
- the gate driver generates a gate-on pulse signal based on the gate start pulse signal GSP, the gate clock signal GCK, and the gate driver output control signal GOE, and outputs them to the scanning signal line, thereby selecting the scanning signal line. Drive.
- the data signal line and the scanning signal line of the display unit are driven by the source driver and the gate driver, so that the data is transmitted through the transistor (TFT) connected to the selected scanning signal line.
- TFT transistor
- a signal potential is written from the signal line to the pixel electrode.
- a voltage is applied to the liquid crystal layer of each subpixel, whereby the amount of light transmitted from the backlight is controlled, and an image indicated by the digital video signal Dv is displayed on each subpixel.
- FIG. 24 is a block diagram showing a configuration of a liquid crystal display device 800 for a television receiver.
- the liquid crystal display device 800 includes a liquid crystal display unit 84, a Y / C separation circuit 80, a video chroma circuit 81, an A / D converter 82, a liquid crystal controller 83, a backlight drive circuit 85, a backlight 86, A microcomputer 87 and a gradation circuit 88 are provided.
- the liquid crystal display unit 84 includes a liquid crystal panel and a source driver and a gate driver for driving the liquid crystal panel.
- a composite color video signal Scv as a television signal is input from the outside to the Y / C separation circuit 80, where it is separated into a luminance signal and a color signal.
- These luminance signals and color signals are converted into analog RGB signals corresponding to the three primary colors of light by the video chroma circuit 81, and further, the analog RGB signals are converted into digital RGB signals by the A / D converter 82. .
- This digital RGB signal is input to the liquid crystal controller 83.
- the Y / C separation circuit 80 also extracts horizontal and vertical synchronization signals from the composite color video signal Scv input from the outside, and these synchronization signals are also input to the liquid crystal controller 83 via the microcomputer 87.
- the liquid crystal display unit 84 receives a digital RGB signal from the liquid crystal controller 83 at a predetermined timing together with a timing signal based on the synchronization signal.
- the gradation circuit 88 generates gradation potentials for the three primary colors R, G, and B for color display, and these gradation potentials are also supplied to the liquid crystal display unit 84.
- the backlight drive is performed under the control of the microcomputer 87.
- the circuit 85 drives the backlight 86, so that light is irradiated to the back surface of the liquid crystal panel.
- the microcomputer 87 controls the entire system including the above processing.
- the video signal (composite color video signal) input from the outside includes not only a video signal based on television broadcasting but also a video signal captured by a camera, a video signal supplied via an Internet line, and the like.
- the liquid crystal display device 800 can display images based on various video signals.
- a tuner unit 90 is connected to the liquid crystal display device 800, whereby the present television receiver 601 is configured.
- the tuner unit 90 extracts a signal of a channel to be received from a received wave (high frequency signal) received by an antenna (not shown), converts the signal to an intermediate frequency signal, and detects the intermediate frequency signal, thereby detecting the television.
- a composite color video signal Scv as a signal is taken out.
- the composite color video signal Scv is input to the liquid crystal display device 800 as described above, and an image based on the composite color video signal Scv is displayed by the liquid crystal display device 800.
- FIG. 26 is an exploded perspective view showing a configuration example of the present television receiver.
- the present television receiver 601 includes a first casing 801 and a second casing 806 in addition to the liquid crystal display device 800 as its constituent elements. It is configured to be sandwiched between one housing 801 and a second housing 806.
- the first housing 801 is formed with an opening 801a through which an image displayed on the liquid crystal display device 800 is transmitted.
- the second housing 806 covers the back side of the liquid crystal display device 800, is provided with an operation circuit 805 for operating the display device 800, and a support member 808 is attached below. Yes.
- the present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on common general technical knowledge and those obtained by combining them are also included in the embodiments of the present invention.
- the active matrix substrate of the present invention and the liquid crystal panel provided with the active matrix substrate are suitable for, for example, a liquid crystal television.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
12a トランジスタ
15x データ信号線
16x 走査信号線
17a 画素電極(第1画素電極)
17b 画素電極(第2画素電極)
18p 保持容量配線
22 ゲート絶縁膜
25 層間絶縁膜
47 上層容量電極(第2容量電極)
87 下層容量電極(第1容量電極)
84 液晶表示ユニット
601 テレビジョン受像機
800 液晶表示装置
Claims (20)
- 走査信号線とデータ信号線を備え、1つの画素領域に、データ信号線にトランジスタを介して接続された第1画素電極と、該第1画素電極に容量を介して接続された第2画素電極とが設けられたアクティブマトリクス基板であって、
走査信号線と同層に形成され、第1画素電極に電気的に接続された第1容量電極と、走査信号線を覆う第1絶縁膜と、該第1絶縁膜および第2画素電極の間の層に形成された第2絶縁膜とを備え、
第1容量電極と第2画素電極とが第1および第2絶縁膜を介して重なることで、第1容量電極と第2画素電極との間に容量が形成されていることを特徴とするアクティブマトリクス基板。 - 第2絶縁膜の厚さは第1絶縁膜の厚さ以下であることを特徴とする請求項1記載のアクティブマトリクス基板。
- 上記第2絶縁膜は、第1容量電極および第2画素電極と重なる部分の厚みが、周囲よりも小さくなっていることを特徴とする請求項1記載のアクティブマトリクス基板。
- 走査信号線とデータ信号線を備え、1つの画素領域に、データ信号線にトランジスタを介して接続された第1画素電極と、該第1画素電極に容量を介して接続された第2画素電極とが設けられたアクティブマトリクス基板であって、
走査信号線と同層に形成され、第1画素電極に電気的に接続された第1容量電極と、走査信号線を覆う第1絶縁膜と、データ信号線と同層に形成され、第2画素電極に電気的に接続された第2容量電極とを備え、
第1容量電極と第2容量電極とが第1絶縁膜を介して重なることで、第1容量電極と第2容量電極との間に容量が形成されていることを特徴とするアクティブマトリクス基板。 - 第2容量電極および第2画素電極の間の層に、第1絶縁膜よりも厚い第2絶縁膜が形成されていることを特徴とする請求項4に記載のアクティブマトリクス基板。
- 上記第2絶縁膜は、有機絶縁膜を含んで構成されていることを特徴とする請求項5に記載のアクティブマトリクス基板。
- 第1容量電極が平行な2本のエッジを有するとともに、第2容量電極も平行な2本のエッジを有し、平面的に視たときに、第2容量電極の両エッジの内側に第1容量電極の両エッジが位置しているか、あるいは、第1容量電極の両エッジの内側に第2容量電極の両エッジが位置していることを特徴とする請求項4または5に記載のアクティブマトリクス基板。
- 第1絶縁膜はゲート絶縁膜であることを特徴とする請求項1~7のいずれか1項に記載のアクティブマトリクス基板。
- 第2絶縁膜はトランジスタのチャネルを覆う層間絶縁膜であることを特徴とする請求項1~3および請求項5~6のいずれか1項に記載のアクティブマトリクス基板。
- 第1画素電極と第1容量電極とが、第1および第2絶縁膜を貫くコンタクトホールによって接続されていることを特徴とする請求項1~3および請求項5~6のいずれか1項に記載のアクティブマトリクス基板。
- 上記走査信号線と同層に形成され、第1および第2画素電極の少なくとも一方と容量を形成する保持容量配線を備えることを特徴とする請求項1~10のいずれか1項に記載のアクティブマトリクス基板。
- 上記データ信号線と同層に、保持容量配線および第1容量電極それぞれに重なる修正用電極が設けられていることを特徴とする請求項11に記載のアクティブマトリクス基板。
- 1つの画素領域に、トランジスタに接続された第1画素電極と、第2画素電極と、第1画素電極にコンタクトホールを介して接続された第1容量電極と、上記トランジスタとは別のトランジスタを介して第2画素電極に接続された第2容量電極とを備え、
上記第2容量電極は、第1容量電極よりも上層で第1および第2画素電極よりも下層に配され、
上記第1容量電極と第2容量電極とが第1絶縁膜を介して重なることで、第1容量電極と第2容量電極との間に容量が形成されていることを特徴とするアクティブマトリクス基板。 - 上記第2容量電極に同層にて接続された第3容量電極と、該第3容量電極と容量を形成する保持容量配線とを備えることを特徴とする請求項13記載のアクティブマトリクス基板。
- 請求項1~14のいずれか1項に記載のアクティブマトリクス基板を備えることを特徴とする液晶パネル。
- 請求項1~14のいずれか1項に記載のアクティブマトリクス基板と、配向規制用の線状突起を有する対向基板とを備え、
第1容量電極の少なくとも一部がこの線状突起の下に配されていることを特徴とする液晶パネル。 - 請求項1~14のいずれか1項に記載のアクティブマトリクス基板と、共通電極を有する対向基板とを備え、上記対向電極には配向規制用のスリットが設けられ、
第1容量電極の少なくとも一部がこのスリットの下に配されていることを特徴とする液晶パネル。 - 請求項15~17のいずれか1項に記載の液晶パネルとドライバとを備えることを特徴とする液晶表示ユニット。
- 請求項18記載の液晶表示ユニットと光源装置とを備えることを特徴とする液晶表示装置。
- 請求項19記載の液晶表示装置と、テレビジョン放送を受信するチューナー部とを備えることを特徴とするテレビジョン受像機。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
RU2011122685/28A RU2475790C2 (ru) | 2008-11-05 | 2009-08-19 | Подложка активной матрицы, жидкокристаллическая панель, модуль жидкокристаллического дисплея, устройство жидкокристаллического дисплея и телевизионный приемник |
JP2010536718A JP5323856B2 (ja) | 2008-11-05 | 2009-08-19 | アクティブマトリクス基板、液晶パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機 |
US13/126,237 US8514339B2 (en) | 2008-11-05 | 2009-08-19 | Active matrix substrate, liquid crystal panel, liquid crystal display unit, liquid crystal display device, and television receiver |
CN2009801426494A CN102203663A (zh) | 2008-11-05 | 2009-08-19 | 有源矩阵基板、液晶面板、液晶显示单元、液晶显示装置、电视接收机 |
BRPI0921745A BRPI0921745A2 (pt) | 2008-11-05 | 2009-08-19 | substrato de matriz ativa, painel de cristal líquido, unidade de exibição de cristal líquido, dispositivo de exibição de cristal líquido e receptor de televisão |
EP09824663A EP2352063A4 (en) | 2008-11-05 | 2009-08-19 | ACTIVE MATRIX SUBSTRATE, LIQUID CRYSTAL PANEL, LIQUID CRYSTAL DISPLAY UNIT, LIQUID CRYSTAL DISPLAY DEVICE AND TV RECEIVER |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008-284805 | 2008-11-05 | ||
JP2008284805 | 2008-11-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2010052963A1 true WO2010052963A1 (ja) | 2010-05-14 |
Family
ID=42152773
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2009/064508 WO2010052963A1 (ja) | 2008-11-05 | 2009-08-19 | アクティブマトリクス基板、液晶パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機 |
Country Status (7)
Country | Link |
---|---|
US (1) | US8514339B2 (ja) |
EP (1) | EP2352063A4 (ja) |
JP (1) | JP5323856B2 (ja) |
CN (1) | CN102203663A (ja) |
BR (1) | BRPI0921745A2 (ja) |
RU (1) | RU2475790C2 (ja) |
WO (1) | WO2010052963A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2022113679A (ja) * | 2010-01-24 | 2022-08-04 | 株式会社半導体エネルギー研究所 | 表示装置 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011039903A1 (ja) * | 2009-09-30 | 2011-04-07 | シャープ株式会社 | 液晶表示装置 |
TWI446079B (zh) * | 2011-06-29 | 2014-07-21 | Au Optronics Corp | 畫素結構及其驅動方法 |
CN202339463U (zh) * | 2011-11-29 | 2012-07-18 | 北京京东方光电科技有限公司 | 薄膜晶体管液晶显示器像素结构及液晶显示器 |
KR102011985B1 (ko) | 2012-07-23 | 2019-08-20 | 삼성디스플레이 주식회사 | 표시 장치 및 그 구동 방법 |
JP2015225150A (ja) * | 2014-05-27 | 2015-12-14 | ソニー株式会社 | 表示装置及び電子機器 |
CN104536578B (zh) * | 2015-01-13 | 2018-02-16 | 京东方科技集团股份有限公司 | 裸眼3d显示装置的控制方法及装置、裸眼3d显示装置 |
KR102509111B1 (ko) * | 2018-05-17 | 2023-03-13 | 삼성디스플레이 주식회사 | 표시 장치 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005346082A (ja) | 2004-06-03 | 2005-12-15 | Samsung Electronics Co Ltd | 液晶表示装置及びそれに使用される薄膜トランジスタ表示板 |
JP2006023744A (ja) * | 2004-07-07 | 2006-01-26 | Samsung Electronics Co Ltd | 多重ドメイン液晶表示装置及びそれに用いられる表示板 |
JP2006039290A (ja) * | 2004-07-28 | 2006-02-09 | Fujitsu Display Technologies Corp | 液晶表示装置及びその焼き付き防止方法 |
JP2006091890A (ja) * | 2004-09-24 | 2006-04-06 | Samsung Electronics Co Ltd | 液晶表示装置 |
JP2006221174A (ja) | 2005-02-07 | 2006-08-24 | Samsung Electronics Co Ltd | 液晶表示装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6922183B2 (en) * | 2002-11-01 | 2005-07-26 | Chin-Lung Ting | Multi-domain vertical alignment liquid crystal display and driving method thereof |
JP4627081B2 (ja) * | 2004-01-28 | 2011-02-09 | シャープ株式会社 | アクティブマトリクス基板及び表示装置 |
KR20060069080A (ko) | 2004-12-17 | 2006-06-21 | 삼성전자주식회사 | 박막 트랜지스터 표시판 및 이를 포함하는 액정 표시 장치 |
JP5170985B2 (ja) * | 2006-06-09 | 2013-03-27 | 株式会社ジャパンディスプレイイースト | 液晶表示装置 |
JP5128091B2 (ja) * | 2006-08-04 | 2013-01-23 | 三菱電機株式会社 | 表示装置及びその製造方法 |
-
2009
- 2009-08-19 JP JP2010536718A patent/JP5323856B2/ja not_active Expired - Fee Related
- 2009-08-19 US US13/126,237 patent/US8514339B2/en not_active Expired - Fee Related
- 2009-08-19 CN CN2009801426494A patent/CN102203663A/zh active Pending
- 2009-08-19 RU RU2011122685/28A patent/RU2475790C2/ru not_active IP Right Cessation
- 2009-08-19 EP EP09824663A patent/EP2352063A4/en not_active Withdrawn
- 2009-08-19 BR BRPI0921745A patent/BRPI0921745A2/pt not_active IP Right Cessation
- 2009-08-19 WO PCT/JP2009/064508 patent/WO2010052963A1/ja active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005346082A (ja) | 2004-06-03 | 2005-12-15 | Samsung Electronics Co Ltd | 液晶表示装置及びそれに使用される薄膜トランジスタ表示板 |
JP2006023744A (ja) * | 2004-07-07 | 2006-01-26 | Samsung Electronics Co Ltd | 多重ドメイン液晶表示装置及びそれに用いられる表示板 |
JP2006039290A (ja) * | 2004-07-28 | 2006-02-09 | Fujitsu Display Technologies Corp | 液晶表示装置及びその焼き付き防止方法 |
JP2006091890A (ja) * | 2004-09-24 | 2006-04-06 | Samsung Electronics Co Ltd | 液晶表示装置 |
JP2006221174A (ja) | 2005-02-07 | 2006-08-24 | Samsung Electronics Co Ltd | 液晶表示装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP2352063A4 * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2022113679A (ja) * | 2010-01-24 | 2022-08-04 | 株式会社半導体エネルギー研究所 | 表示装置 |
JP7443415B2 (ja) | 2010-01-24 | 2024-03-05 | 株式会社半導体エネルギー研究所 | 液晶表示装置 |
US11935896B2 (en) | 2010-01-24 | 2024-03-19 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
US20110216249A1 (en) | 2011-09-08 |
RU2011122685A (ru) | 2012-12-20 |
RU2475790C2 (ru) | 2013-02-20 |
EP2352063A4 (en) | 2012-08-22 |
EP2352063A1 (en) | 2011-08-03 |
CN102203663A (zh) | 2011-09-28 |
JPWO2010052963A1 (ja) | 2012-04-05 |
US8514339B2 (en) | 2013-08-20 |
JP5323856B2 (ja) | 2013-10-23 |
BRPI0921745A2 (pt) | 2016-01-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5431335B2 (ja) | アクティブマトリクス基板、液晶パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機、アクティブマトリクス基板の製造方法 | |
JP5220863B2 (ja) | アクティブマトリクス基板、液晶パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機 | |
JP5107439B2 (ja) | アクティブマトリクス基板、液晶パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機 | |
JP5323856B2 (ja) | アクティブマトリクス基板、液晶パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機 | |
WO2010100788A1 (ja) | アクティブマトリクス基板、液晶パネル、液晶表示装置、液晶表示ユニット、テレビジョン受像機 | |
WO2010100789A1 (ja) | アクティブマトリクス基板、アクティブマトリクス基板の製造方法、液晶パネル、液晶パネルの製造方法、液晶表示装置、液晶表示ユニット、テレビジョン受像機 | |
JP5179670B2 (ja) | 液晶表示装置 | |
WO2010089820A1 (ja) | アクティブマトリクス基板、液晶パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機 | |
WO2010100790A1 (ja) | アクティブマトリクス基板、アクティブマトリクス基板の製造方法、液晶パネル、液晶パネルの製造方法、液晶表示装置、液晶表示ユニット、テレビジョン受像機 | |
JP5107437B2 (ja) | アクティブマトリクス基板、アクティブマトリクス基板の製造方法、液晶パネル、液晶パネルの製造方法、液晶表示装置、液晶表示ユニット、テレビジョン受像機 | |
JP5318888B2 (ja) | 液晶パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機 | |
JP5143905B2 (ja) | アクティブマトリクス基板、液晶パネル、液晶表示装置、液晶表示ユニット、テレビジョン受像機 | |
JP5301567B2 (ja) | アクティブマトリクス基板、アクティブマトリクス基板の製造方法、液晶パネル、液晶パネルの製造方法、液晶表示装置、液晶表示ユニット、テレビジョン受像機 | |
WO2010089922A1 (ja) | アクティブマトリクス基板、液晶パネル、液晶表示装置、液晶表示ユニット、テレビジョン受像機 | |
WO2009144966A1 (ja) | アクティブマトリクス基板、アクティブマトリクス基板の製造方法、液晶パネル、液晶パネルの製造方法、液晶表示装置、液晶表示ユニット、テレビジョン受像機 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200980142649.4 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 09824663 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2010536718 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13126237 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 3569/CHENP/2011 Country of ref document: IN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2009824663 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2011122685 Country of ref document: RU |
|
ENP | Entry into the national phase |
Ref document number: PI0921745 Country of ref document: BR Kind code of ref document: A2 Effective date: 20110429 |