WO2009133919A1 - 接合方法及び接合装置 - Google Patents
接合方法及び接合装置 Download PDFInfo
- Publication number
- WO2009133919A1 WO2009133919A1 PCT/JP2009/058459 JP2009058459W WO2009133919A1 WO 2009133919 A1 WO2009133919 A1 WO 2009133919A1 JP 2009058459 W JP2009058459 W JP 2009058459W WO 2009133919 A1 WO2009133919 A1 WO 2009133919A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- bonded
- oxide film
- substrates
- substrate
- electrode
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3489—Composition of fluxes; Methods of application thereof; Other methods of activating the contact surfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29109—Indium [In] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/751—Means for controlling the bonding environment, e.g. valves, vacuum pumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
- H01L2224/81011—Chemical cleaning, e.g. etching, flux
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/81022—Cleaning the bonding area, e.g. oxide removal step, desmearing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1163—Chemical reaction, e.g. heating solder by exothermic reaction
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Definitions
- the present invention relates to a method for bonding substrates and an apparatus used for this method.
- Flip chip connection is a method of eliminating lead wires from a semiconductor chip corresponding to one substrate to another substrate (such as a printed circuit board or an interposer), and passing the semiconductor chip through bump electrodes called bumps arranged two-dimensionally. And connecting to another board. That is, in the flip chip connection, the semiconductor chip and the protruding electrodes on the surface of another substrate are connected to each other, or the protruding electrode on one surface of the semiconductor chip and the other substrate and the extraction electrode on the other surface are connected. Connect it.
- flux is mainly used to join the protruding electrode onto the extraction electrode.
- Flux is used for the purpose of reducing and removing oxides on the surface of the bump electrode and internal oxides, and preventing oxidation of the bump electrode surface.
- the flux is deposited on the substrate. If it remains, it will affect the reliability of the semiconductor. Therefore, it is necessary to clean and remove the flux residue remaining in the gap so that the flux does not remain in the gap between the semiconductor chip and the substrate.
- Patent Document 2 discloses a technique of performing an oxide film reduction process on the electrode surface, aligning it in the air, and melting it in an atmosphere having a low oxygen concentration.
- the protruding electrode must be heated to the melting temperature or higher by performing a heat treatment after the oxide film reduction process. Such heating is not preferable for the semiconductor chip.
- the present invention has been made in view of such problems, and an object of the present invention is to provide a bonding method and apparatus that can be easily bonded at low temperatures without deteriorating the electrical contact between objects to be bonded. There is to do.
- the bonding method includes a process of performing oxide film reduction treatment with hydrogen radicals on the surfaces of the non-bonded materials of the first and second substrates each having a non-bonded material on the surface;
- the non-bonded material subjected to the reduction treatment is aligned, and then a load is applied to the first and second substrates to bond the non-bonded materials to each other.
- the object to be bonded to the first substrate can be an electrode provided on the surface of the first substrate.
- the object to be bonded to the second substrate is a protruding electrode provided on the surface of the electrode provided on the surface of the second substrate, and the first and second substrates are placed in the atmosphere after the oxide film reduction process. Taking out and joining by the said load is performed under high temperature.
- Either the alignment or heating order may be first.
- the article to be joined is tin or a tin alloy
- t exposure time (min)
- T Heating temperature (K)
- the objects to be joined of the first and second substrates can be planar bodies provided on the surfaces of the first and second substrates, or linear bodies provided on the surfaces of the first and second substrates. Is a joining method.
- a bonding apparatus comprising: means for performing an oxide film reduction treatment with hydrogen radicals on surfaces of the non-bonded materials of the first and second substrates each having a non-bonded material on a surface thereof; Means for aligning the non-bonded material subjected to film reduction treatment, and means for bonding the non-bonded materials by applying a load to the first and second substrates after the alignment. It is.
- 1 is a diagram showing a semiconductor device 1 manufactured according to a first embodiment of the present invention.
- 2 is a flowchart showing a flow of a manufacturing method of the semiconductor device of FIG. It is a figure which shows the oxide film removal apparatus used for manufacture of the semiconductor device 1 of FIG. It is a figure which shows the other semiconductor device which can be manufactured by 1st Embodiment of this invention. It is a figure which shows another semiconductor device which can be manufactured by 1st Embodiment of this invention. It is a figure which shows the relationship between temperature and time in the modification of 1st Embodiment of this invention. It is a figure which shows the board
- FIG. 1 shows a semiconductor device 1 manufactured according to the first embodiment of the present invention.
- FIG. 2 shows a flow of a manufacturing method of the semiconductor device 1 of FIG.
- a first substrate for example, a semiconductor chip 2 is bonded to a second substrate, for example, an intermediate substrate 3.
- the semiconductor chip 2 has a semiconductor element 4, an external extraction electrode 5, and a protruding electrode 6.
- the semiconductor element 4 has an integrated circuit (not shown) incorporated therein, for example.
- the external extraction electrode 5 is formed on the surface of the semiconductor element 4 and is connected to, for example, one end of the integrated circuit.
- the protruding electrode 6 is formed on the surface of the external extraction electrode 5.
- the intermediate substrate 3 electrically connects, for example, the external extraction electrode 5 of the semiconductor chip 2 and an electrode pad (not shown) provided on the surface of a printed board (not shown) for mounting the semiconductor device 1.
- An interposer for connection having an insulating substrate 7, a via (not shown) penetrating through the insulating substrate 7, and an external extraction electrode 8 connected to the via and formed on the surface of the intermediate substrate 3 ing.
- the surfaces of the external extraction electrodes 5 and 8 are, for example, Al (aluminum), Ni (nickel), Cu (copper), Au (gold), Pd (palladium), Ag (silver), In (indium). Or it is comprised with the metal containing Sn (tin).
- the protruding electrode 6 may be, for example, Sn (tin) containing no impurities, Ag (silver), Cu (copper), Bi (bismuth), In (indium), Ni (nickel), Au (gold), P ( It is made of tin containing at least one impurity of phosphorus and Pb (lead), and is formed by, for example, plating, printing, ball, or vapor deposition.
- the oxide film removing apparatus 10 used when carrying out the method for manufacturing the semiconductor device 1 will be described.
- the oxide film removing apparatus 10 is an apparatus for removing the oxide film covering the surfaces of the external extraction electrodes 5 and 8 and the protruding electrode 6. As shown in FIG. 3, the oxide film removing apparatus 10 includes a chamber 11 including a plasma generation chamber 11A and a processing chamber 11B that are spatially separated from each other.
- a microwave generator 14 that generates a microwave W is disposed via a waveguide 13 and a microwave introduction window 12, and a hydrogen gas source 16 that generates hydrogen gas is supplied. It is arranged via a tube 15.
- the plasma generation chamber 11A converts the hydrogen gas supplied from the hydrogen gas source 16 into plasma by the microwave W generated by the microwave generator 14, and generates hydrogen radicals (free radical gas). .
- a shield 17 is further provided on the processing chamber 11B side than the plasma generation region P.
- the shield 17 is made of, for example, a metal mesh, collects unnecessary charged particles present in the plasma as much as possible, and introduces a gas contained in the plasma generated in the plasma generation chamber 11A into the processing chamber 11B. It has become. As a result, the plasma generation chamber 11A introduces a gas containing hydrogen radicals into the processing chamber 11B through the shield 17.
- the processing chamber 11B is provided with a support base 18 on which a processing object (semiconductor chip 2 and intermediate substrate 3) is placed.
- the support base 18 includes a heater 19 and a cooler 20 in a portion that supports the semiconductor chip 2 and the intermediate substrate 3, and can heat and cool the semiconductor chip 2 and the intermediate substrate 3 in a predetermined procedure. It has become.
- a vacuum pump 22 is provided on the bottom surface via an exhaust port 21, and a pressure gauge 23 is provided on the bottom surface.
- the vacuum pump 22 is for exhausting the gas in the chamber 11 to reduce the pressure in the chamber 11.
- the pressure gauge 23 is for measuring the pressure in the chamber 11.
- the processing chamber 11B is further provided with a nitrogen gas source 25 via a supply pipe 24.
- the nitrogen gas source 25 may be provided on the plasma generation chamber 11A side.
- the measurement value of the pressure gauge 23 is transmitted to the control unit 26, and the control unit 26 controls the hydrogen gas source 15, the vacuum pump 22, and the nitrogen gas source 25 based on the measurement value. Thereby, a process target object can be exposed to the gas containing a hydrogen radical.
- the oxide film covering the surfaces of the external extraction electrodes 5 and 8 and the protruding electrode 6 is removed using the oxide film removing apparatus 10 having the above-described configuration.
- step S1 the chamber 11 is opened, and the semiconductor chip 2 and the intermediate substrate 3 are placed on the support base 18 with the external extraction electrodes 5 and 8 and the protruding electrodes 6 facing up (step S1).
- FIG. 3 illustrates the case where the semiconductor chip 2 is placed on the support base 18.
- the vacuum pump 22 is operated to exhaust the gas in the chamber 11 and reduce the pressure (step S2).
- the microwave generator 14 is operated to generate the microwave W
- the hydrogen gas source 16 is operated to generate hydrogen gas.
- the hydrogen gas is turned into plasma by the microwave W, and hydrogen radicals (free radical gas) are generated (step S3).
- the semiconductor chip 2 placed on the support base 18 and the external extraction electrodes 5 and 8 and the protruding electrode 6 of the intermediate substrate 3 are exposed to a gas containing hydrogen radicals supplied from the nozzle 18.
- the oxide films covering the surfaces of the external extraction electrodes 5 and 8 and the protruding electrode 6 are chemically reacted with hydrogen radicals to be vaporized and removed from the surface (step S4).
- step S5 After the semiconductor chip 2 and the intermediate substrate 3 are taken out into the atmosphere (step S5), both are bonded by a flip chip bonding machine (step S6).
- step S6 the environment to which the surfaces to be joined before pressurization are exposed is set to the following conditions of temperature and time.
- T Heating temperature (K)
- Equation (1) The process of obtaining equation (1) will be briefly described. Solder balls (ball diameter 760 ⁇ m) of Sn-3.5% Ag component are subjected to surface oxide film reduction by hydrogen radical treatment, and after the oxide film is completely removed, a constant heating temperature (T) with a hot plate in the atmosphere The film was allowed to cool at time (t), and the thickness of the surface oxide film was measured by Auger analysis. As a result, it was found that at a constant temperature, the oxide film thickness does not increase until a certain time, but increases rapidly from a certain time determined by the temperature. As a result of formulating the relationship between the temperature (T) and the time (t) at which the temperature starts to increase, formula (1) can be obtained.
- Table 1 lists a plurality of combinations (materials A1 to A33) of materials (Sn, Ag, Cu, Bi, In, Ni, Au, P, and Pb) that can be considered as the material of the protruding electrode 6.
- the value in Table 1 is the content rate (%).
- “remaining” in the Sn column means a value obtained by subtracting the ratio of the contained elements from 100, where 100 is the whole. Since the materials B1 and B2 contain Zn (zinc), the ratio of ZnO contained in the oxide film is large, and it is difficult to chemically remove the oxide film compared to the case of SnO. Since the material of the bump electrode 6 of this embodiment is an inappropriate material, it is listed as a comparative example.
- Table 2 uses the above-described materials A1 to A35, B1, and B2 as the material of the protruding electrode 6, and uses (Cu (material C1), Au (material C2) as the material of the external extraction electrodes 5 and 8,
- a chemical treatment an oxide film reduction treatment is carried out by any of hydrogen radicals, a mixture of hydrogen and Ar gas, an organic acid vaporized gas containing formic acid, hydrogen and nitrogen gas, and the bonding temperature (heating temperature T), bonding load, heating time ( This shows the die shear strength when the time t) during which the heating temperature is exposed to the atmosphere before the load is applied, where the double circle in Table 2 indicates that the die shear strength after joining is 2 MPa.
- the protruding electrode 6 and the external extraction electrode 8 are bonded, but the protruding electrodes may be bonded to each other.
- the semiconductor chip 2 and the intermediate substrate 3 are bonded.
- the semiconductor chip 2 and the printed circuit board may be bonded to each other.
- the present invention is not limited to this, for example, as shown in FIG.
- the present invention is also applicable to a semiconductor device in which a semiconductor chip 9 having an external extraction electrode 5 on the upper surface of the semiconductor element 4 is provided between the semiconductor chip 2 and the intermediate substrate 3.
- the semiconductor element including the semiconductor chip 2 and one or a plurality of semiconductor chips 9 corresponds to an example of the “first substrate” in the present invention.
- the present invention can be similarly applied to a semiconductor device in which a plurality of semiconductor chips 2 are provided on an intermediate substrate 3 as shown in FIG.
- the plurality of semiconductor chips 2 correspond to an example of the “first substrate” in the present invention.
- the planar bodies formed on the first substrate 2a and the second substrate 3a for example, copper films 5a and 8a are bonded.
- the bonding is performed by performing oxide film reduction treatment on the films 5a and 8a by the oxide film removing apparatus 10 in the same manner as in the first embodiment.
- the second substrates 2a and 3a are taken out, and the first and second substrates 3a and 5a are aligned by the known alignment apparatus 100 so that the positions of the films 5a and 8a are aligned.
- the films 5a and 8a are joined by heating and pressurizing at a temperature lower than the melting point of copper (1085 degrees Celsius).
- the films 5a and 8a were not joined, but when heated to 200 degrees Celsius and pressurized at 0.3 MPa, 250 degrees Celsius.
- the films 5a and 8a were bonded to each other. Note that the films 5a and 8a were bonded even when heated and pressurized after being left in the atmosphere for 60 seconds after the oxide film reduction treatment.
- linear bodies formed on the first substrate 2b and the second substrate 3b for example, tin indium solder having a melting point of 120 degrees centigrade.
- the thin frames 5b and 8b are joined to seal the inside of the frames 5b and 8b.
- the bonding is performed by performing an oxide film reduction process on the frames 5b and 8b by the oxide film removing apparatus 10 in the same manner as in the first embodiment, and then performing the first and first processes from the oxide film removing apparatus.
- the second substrates 2b and 3b are taken out, and the first and second substrates 2b and 2b are aligned so that the positions of the frames 5b and 8b are aligned by the known alignment device 100, and then the melting point is heated by the heating and pressing device 102.
- the frames 5b and 8b are joined by heating to a temperature lower than the temperature and applying pressure.
- the frames 5b and 8b were not joined, but when heated to 80 degrees Celsius and pressurized at 15 MPa, heated to 80 degrees Celsius
- pressurized at 30 MPa when heated to 100 degrees Celsius and pressurized at 15 MPa, when heated to 100 degrees Celsius and pressurized at 30 MPa, the frames 5b and 8b were joined. Note that the frames 5b and 8b were bonded even when heated and pressurized after being left in the atmosphere for 60 minutes after the oxide film reduction treatment.
- the films 5a and 8a and the frames 5b and 8b are metals other than tin or an alloy of tin
- the films 5a and 8a and the frames 5b and 8b are applied from the oxide film reduction treatment to the pressurization. From the above experimental results, it is desirable that the environment exposed to the temperature and time be as follows. Log (t) ⁇ 3 (1000 / T-3) (3) t: exposure time (min) T: Heating temperature (K) This equation (3) was also derived in the same process as equations (1) and (2).
- the alignment device 100 and the bonding device 102 are individually used, but a bonding device including the alignment device can also be used. Further, as shown in FIG. 10, it is also possible to use a single bonding apparatus that functions as an oxide film removing apparatus, a positioning apparatus, and a heating and pressing apparatus.
- the oxide film removing apparatus 10 shown in FIG. 3 is arranged in a state rotated by 90 degrees. Parts corresponding to the constituent elements of the oxide film removing apparatus 10 are denoted by the same reference numerals, and description thereof is omitted.
- the processing chamber 11B is provided with a support base 18a for mounting the first substrate 2a or 2b and a support base 18b for mounting the second substrate 3a or 3b.
- the support base 18a has a heater and a cooler (not shown) in the same manner as the support base 18 of the oxide film removing apparatus 10 at a portion that supports the first substrate 2a or 2b.
- the support base 18b also has a heater and a cooler (not shown) in a portion that supports the second substrate 3a or 3b.
- These support bases 18a and 18b are respectively coupled to elevating devices 180a and 180b provided outside the processing chamber 11B.
- the support bases 18a and 18b can be moved up and down as indicated by arrows, and the support base 18a is lowered.
- the film 5a or frame 5b of the first substrate 8a or 8b on the support table 18a and the film 8a or frame 8b of the second substrate 3a or 3b on the support table 18b are added by raising the support table 18b. Can be joined by pressing. During the pressurization, the film 5a, 5b or the frame 8a, 8b is heated to a temperature below the melting point of the film 5a, 5b or the frame 8a, 8b by the heater in the support bases 18a, 18b. Also, the support base 18b is provided with a pin 200 for aligning the first and second substrates 2a or 2b and 3a or 3b, and a hole (not shown) through which the pin 200 is inserted has a support base 18a. Is provided. The pin 200 and the hole function as an alignment device.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
Log(t)≦3(1000/T-2) (1)
t;曝露時間(min)
T;加熱温度(K)
図6に示すように、2段階以上の加熱カーブで加熱される場合は、曝露時間と加熱温度とは、以下の条件を満足することが望ましい。
Σ(log(tn)/{3(1000/Tn-2)}≦1(2)
tn,Tn;n段目の時間、温度
さて、上記した構成の酸化膜除去装置10を用いて、外部引出電極5,8や突起電極6の表面を覆っている酸化膜の除去を行う。
次に、半導体チップ2および中間基板3を大気中に取り出した後(ステップS5)、フリップチップ接合機で両者の接合をおこなう(ステップS6)。その際、加圧前の接合されるべき面が曝される環境は温度、時間を以下の条件とする。
Log(t)≦3(1000/T-2) (1)
t;曝露時間(min)
T;加熱温度(K)
また、酸化膜還元処理を実施することにより、上記の酸化膜が急激に増加する加熱時間前であれば、酸化膜はほとんど存在せず、大気中に加熱しても接合することができた。もし、酸化膜還元処理を実施していなければ、この加熱条件よりずっと低温、短時間で酸化膜が成長する。
Log(t)≦3(1000/T-3) (3)
t;曝露時間(min)
T;加熱温度(K)
この式(3)も、式(1)、(2)と同様な過程で導出した。
Claims (6)
- 表面に非接合物をそれぞれ有する第1及び第2基板の前記非接合物の表面に対して、水素ラジカルによる酸化膜還元処理を行う過程と、
前記酸化膜還元処理を行った前記非接合物の位置あわせを行い、その後に前記第1及び第2の基板に荷重を加えて前記非接合物同士を接合する過程とを、
具備する接合方法。 - 請求項1記載の接合方法において、前記第1基板の被接合物は、前記第1基板の表面に設けた電極であり、前記第2基板の被接合物は、第2基板の表面に設けた電極の表面に設けた突起電極であり、前記第1及び第2の基板を前記酸化膜還元処理後に大気中に取り出し、前記荷重による接合を高温下で行う接合方法。
- 請求項2記載の接合方法において、前記接合の荷重を付加する前の電極の大気中に放置される時間、温度は以下に示す範囲内に留める
接合方法。
Log(t)≦3(1000/T-2) (1)
t;曝露時間(min)
T;加熱温度(K) - 請求項1記載の接合方法において、前記第1及び第2基板の被接合物は、前記第1及び第2基板の表面に設けた面状体である接合方法。
- 請求項1記載の接合方法において、前記第1及び第2基板の被接合物は、前記第1及び第2基板の表面に設けた線状体である接合方法。
- 表面に非接合物をそれぞれ有する第1及び第2基板の前記非接合物の表面に対して、水素ラジカルによる酸化膜還元処理を行う手段と、
前記酸化膜還元処理を行った前記非接合物の位置あわせを行う手段と、
前記位置あわせ後に前記第1及び第2の基板に荷重を加えて前記非接合物同士を接合する手段とを、
具備する接合装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200980115842.9A CN102017819B (zh) | 2008-05-02 | 2009-04-30 | 接合方法以及接合装置 |
US12/990,608 US8318585B2 (en) | 2008-05-02 | 2009-04-30 | Bonding method and bonding apparatus |
JP2010510161A JP5449145B2 (ja) | 2008-05-02 | 2009-04-30 | 接合方法及び接合装置 |
KR1020107023927A KR101233282B1 (ko) | 2008-05-02 | 2009-04-30 | 접합 방법 및 접합 장치 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008-120291 | 2008-05-02 | ||
JP2008120291 | 2008-05-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009133919A1 true WO2009133919A1 (ja) | 2009-11-05 |
Family
ID=41255135
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2009/058459 WO2009133919A1 (ja) | 2008-05-02 | 2009-04-30 | 接合方法及び接合装置 |
Country Status (7)
Country | Link |
---|---|
US (1) | US8318585B2 (ja) |
JP (1) | JP5449145B2 (ja) |
KR (1) | KR101233282B1 (ja) |
CN (1) | CN102017819B (ja) |
MY (1) | MY155481A (ja) |
TW (1) | TWI500092B (ja) |
WO (1) | WO2009133919A1 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011181631A (ja) * | 2010-02-26 | 2011-09-15 | Tokyo Electron Ltd | 表面活性化方法、プログラム、コンピュータ記憶媒体及び表面活性化装置 |
JP2011200930A (ja) * | 2010-03-26 | 2011-10-13 | Gunma Univ | 金属部材の接合方法 |
JP2012038790A (ja) * | 2010-08-04 | 2012-02-23 | Hitachi Ltd | 電子部材ならびに電子部品とその製造方法 |
JP2012204523A (ja) * | 2011-03-24 | 2012-10-22 | Fujitsu Ltd | 半導体装置の製造方法 |
WO2013183560A1 (ja) * | 2012-06-05 | 2013-12-12 | 国立大学法人群馬大学 | 金属部材の接合方法 |
JP2016117092A (ja) * | 2014-12-22 | 2016-06-30 | ボンドテック株式会社 | 接合方法、接合装置及び接合物を含む構造体 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5314607B2 (ja) * | 2010-01-20 | 2013-10-16 | 東京エレクトロン株式会社 | 接合装置、接合方法、プログラム及びコンピュータ記憶媒体 |
JP5183659B2 (ja) * | 2010-03-23 | 2013-04-17 | 東京エレクトロン株式会社 | 基板処理装置、基板処理方法、プログラム及びコンピュータ記憶媒体 |
JP6011074B2 (ja) * | 2012-01-20 | 2016-10-19 | 富士通株式会社 | 電子装置の製造方法及び電子装置の製造装置 |
CN104395999B (zh) * | 2012-05-30 | 2017-03-08 | Ev 集团 E·索尔纳有限责任公司 | 用于接合基片的装置以及方法 |
US9446467B2 (en) | 2013-03-14 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrate rinse module in hybrid bonding platform |
US9780065B2 (en) | 2013-10-08 | 2017-10-03 | Kulicke And Soffa Industries, Inc. | Systems and methods for bonding semiconductor elements |
US9779965B2 (en) * | 2013-10-08 | 2017-10-03 | Kulicke And Soffa Industries, Inc. | Systems and methods for bonding semiconductor elements |
US11205633B2 (en) * | 2019-01-09 | 2021-12-21 | Kulicke And Soffa Industries, Inc. | Methods of bonding of semiconductor elements to substrates, and related bonding systems |
US11515286B2 (en) | 2019-01-09 | 2022-11-29 | Kulicke And Soffa Industries, Inc. | Methods of bonding of semiconductor elements to substrates, and related bonding systems |
CN117976564A (zh) * | 2023-12-29 | 2024-05-03 | 上海捷策创电子科技有限公司 | 一种多层基板与测试载板的无缝接合方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001308144A (ja) * | 2000-04-25 | 2001-11-02 | Tamura Seisakusho Co Ltd | フリップチップ実装方法 |
JP2008041980A (ja) * | 2006-08-08 | 2008-02-21 | Shinko Seiki Co Ltd | はんだ付け方法およびはんだ付け装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3407275B2 (ja) * | 1998-10-28 | 2003-05-19 | インターナショナル・ビジネス・マシーンズ・コーポレーション | バンプ及びその形成方法 |
DE10164502B4 (de) * | 2001-12-28 | 2013-07-04 | Epcos Ag | Verfahren zur hermetischen Verkapselung eines Bauelements |
US6935553B2 (en) * | 2002-04-16 | 2005-08-30 | Senju Metal Industry Co., Ltd. | Reflow soldering method |
KR100521081B1 (ko) * | 2002-10-12 | 2005-10-14 | 삼성전자주식회사 | 플립 칩의 제조 및 실장 방법 |
JP4732699B2 (ja) | 2004-02-17 | 2011-07-27 | 神港精機株式会社 | はんだ付け方法 |
JP4742844B2 (ja) * | 2005-12-15 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP5210496B2 (ja) | 2006-03-27 | 2013-06-12 | 神港精機株式会社 | 半導体装置の製造方法 |
-
2009
- 2009-04-30 KR KR1020107023927A patent/KR101233282B1/ko active IP Right Grant
- 2009-04-30 WO PCT/JP2009/058459 patent/WO2009133919A1/ja active Application Filing
- 2009-04-30 CN CN200980115842.9A patent/CN102017819B/zh active Active
- 2009-04-30 US US12/990,608 patent/US8318585B2/en active Active
- 2009-04-30 JP JP2010510161A patent/JP5449145B2/ja active Active
- 2009-04-30 MY MYPI2010005181A patent/MY155481A/en unknown
- 2009-05-01 TW TW098114595A patent/TWI500092B/zh active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001308144A (ja) * | 2000-04-25 | 2001-11-02 | Tamura Seisakusho Co Ltd | フリップチップ実装方法 |
JP2008041980A (ja) * | 2006-08-08 | 2008-02-21 | Shinko Seiki Co Ltd | はんだ付け方法およびはんだ付け装置 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011181631A (ja) * | 2010-02-26 | 2011-09-15 | Tokyo Electron Ltd | 表面活性化方法、プログラム、コンピュータ記憶媒体及び表面活性化装置 |
JP2011200930A (ja) * | 2010-03-26 | 2011-10-13 | Gunma Univ | 金属部材の接合方法 |
JP2012038790A (ja) * | 2010-08-04 | 2012-02-23 | Hitachi Ltd | 電子部材ならびに電子部品とその製造方法 |
JP2012204523A (ja) * | 2011-03-24 | 2012-10-22 | Fujitsu Ltd | 半導体装置の製造方法 |
WO2013183560A1 (ja) * | 2012-06-05 | 2013-12-12 | 国立大学法人群馬大学 | 金属部材の接合方法 |
JPWO2013183560A1 (ja) * | 2012-06-05 | 2016-01-28 | 国立大学法人群馬大学 | 金属部材の接合方法 |
JP2016117092A (ja) * | 2014-12-22 | 2016-06-30 | ボンドテック株式会社 | 接合方法、接合装置及び接合物を含む構造体 |
Also Published As
Publication number | Publication date |
---|---|
TWI500092B (zh) | 2015-09-11 |
US8318585B2 (en) | 2012-11-27 |
CN102017819B (zh) | 2016-05-11 |
KR20100126561A (ko) | 2010-12-01 |
MY155481A (en) | 2015-10-30 |
TW201003809A (en) | 2010-01-16 |
JP5449145B2 (ja) | 2014-03-19 |
JPWO2009133919A1 (ja) | 2011-09-01 |
KR101233282B1 (ko) | 2013-02-14 |
CN102017819A (zh) | 2011-04-13 |
US20110045653A1 (en) | 2011-02-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5449145B2 (ja) | 接合方法及び接合装置 | |
TWI428967B (zh) | 熱機械倒裝晶片接合法 | |
US9860989B2 (en) | Electronic component module and method for manufacturing electronic component module | |
EP2006895A1 (en) | Electronic component module | |
US8409919B2 (en) | Method for manufacturing semiconductor device | |
US20070170227A1 (en) | Soldering method | |
US20150123263A1 (en) | Two-step method for joining a semiconductor to a substrate with connecting material based on silver | |
JP2007019360A (ja) | 電子部品の実装方法 | |
US20140374775A1 (en) | Electronic component and manufacturing method for electronic component | |
WO2000019514A1 (fr) | Boitier de semiconducteur et procede correspondant de soudage de puce | |
TWI723424B (zh) | 半導體裝置之製造方法 | |
JP4136844B2 (ja) | 電子部品の実装方法 | |
Zhang et al. | Shear performance and accelerated reliability of solder interconnects for fan-out wafer-level package | |
JP2007266054A (ja) | 半導体装置の製造方法 | |
WO2005086221A1 (ja) | 電子部品の実装方法 | |
JP2007184408A (ja) | 電極接合方法 | |
CN114043122B (zh) | 一种含有Cu@Sn核壳双金属粉高温钎料及其制备方法和应用 | |
JP2000138255A (ja) | 半導体装置の製造方法と製造装置 | |
CN112151400B (zh) | 一种解决smd管壳键合点金铝***的方法 | |
WO2005086218A1 (ja) | 半導体モジュールの製造方法 | |
EP3754701B1 (en) | Copper/titanium/aluminum joint, insulating circuit board, insulating circuit board with heat sink, power module, led module, and thermoelectric module | |
CN110770884A (zh) | 由两个器件和位于其间的焊料构成的稳固的夹层配置的制造方法 | |
JP5434087B2 (ja) | 半導体装置とその半導体装置のハンダ付け方法 | |
Zheng | Processing and Properties of Die-attachment on Copper Surface by Low-temperature Sintering of Nanosilver Paste | |
JPS63280428A (ja) | 接合方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200980115842.9 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 09738856 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 20107023927 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2010510161 Country of ref document: JP Ref document number: 12990608 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 09738856 Country of ref document: EP Kind code of ref document: A1 |