WO2009104688A1 - 不揮発性記憶装置およびその製造方法 - Google Patents
不揮発性記憶装置およびその製造方法 Download PDFInfo
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- WO2009104688A1 WO2009104688A1 PCT/JP2009/052913 JP2009052913W WO2009104688A1 WO 2009104688 A1 WO2009104688 A1 WO 2009104688A1 JP 2009052913 W JP2009052913 W JP 2009052913W WO 2009104688 A1 WO2009104688 A1 WO 2009104688A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
Definitions
- the present invention relates to a nonvolatile memory device and a manufacturing method thereof.
- FIGS. 1A to 1D are explanatory diagrams of a nonvolatile memory device related to the present invention.
- FIG. 1A shows a trap memory having the simplest planar structure (a structure related to the present invention, hereinafter referred to as “related structure I”).
- a laminated film 7 including a first insulating film 4, a charge storage layer 5, and a second insulating film 6, and a memory gate electrode 8 are further provided on the laminated film 7.
- a source region 2 and a drain region 3 are formed on both sides of the memory substrate 8 in the silicon substrate 1 so as to partially overlap the memory gate electrode 8.
- Data is written in a high energy state by applying a positive voltage to the memory gate electrode 8 and the drain 3 and a strong lateral electric field generated at the boundary with the inversion channel region 9 as shown in FIG. It is utilized that channel hot electrons are injected into the charge storage layer 5 in the laminated film 7.
- data can be erased by applying a negative voltage to the memory gate electrode 8 and using the Fowler-Nordheim (FN) tunnel phenomenon to pull out the electrons trapped in the charge storage layer 5 or By applying a positive voltage to the drain 3 in addition to the negative voltage to the electrode 8 to generate an interband tunnel hot hole and injecting it into the charge storage layer 5, the electrons trapped in the charge storage layer 5 and the medium To sum up. Since the change in the amount of charge stored in the charge storage layer 5 changes the threshold value of the memory gate electrode 8, information (data) related to the charge storage amount is read out by the change in the threshold value.
- FN Fowler-Nordheim
- the problem with the related structure I shown in FIG. 1A is that it is difficult to improve the writing efficiency.
- a high electric field is applied to the memory gate electrode 8 and the vertical electric field from the gate crossing the charge storage layer 5 to the silicon substrate 1 is strengthened so that channel hot electrons are easily injected into the charge storage layer 5, the resistance in the channel direction is increased. This is because the channel current flowing from the source to the drain increases due to the decrease.
- the writing efficiency (the value obtained by dividing the amount of channel hot electrons injected into the charge storage layer per unit time by the channel current flowing from the source to the drain) does not increase greatly even if the gate voltage is increased. It can even decrease.
- a trap memory having a split gate structure (hereinafter referred to as “related structure II”) has been proposed.
- a first insulating film 4, a charge storage layer 5, a laminated film 7 composed of a second insulating film 6, and a memory gate electrode 8 are provided on a silicon substrate 1 in this order.
- a word gate electrode 13 is provided via insulating films 10 and 11 so as to contact both one side of the memory gate electrode 8 and one main surface (upper surface in the drawing) of the silicon substrate 1.
- the source region 2 and the drain region 3 are formed in the silicon substrate 1 on both sides of the gate electrodes 8 and 13 so as to partially overlap the gate electrodes 8 and 13.
- the split gate structure excellent in write efficiency is a particularly important structure in a logic LSI with a built-in memory that has a large effect of reducing the chip cost by reducing the area of the peripheral circuit.
- the partial doping (related structure II ′) described above in the split gate type structure (related structure II) has the merit of improving the write efficiency, but on the other hand, when the memory cell is actually arranged in an array, It has been found that the disturb resistance to adjacent cells is worse than the related structure II before improvement.
- FIGS. 3A to 3C are explanatory diagrams of a nonvolatile memory device related to the present invention.
- 4A and 4B are characteristics explanatory diagrams of the nonvolatile memory device related to the present invention.
- FIG. 4A shows the relationship between the time of each cell and the voltage change
- FIG. 4B shows the relationship between the threshold value of each cell and the voltage change. Therefore, when a voltage is applied to the write cell (FIG.
- the voltage is also applied to each electrode of the adjacent cell (non-selected cell) through the common wiring as shown in FIG. 3B.
- the erasure level (threshold) rises particularly when the non-selected cell is in the erased state, and the memory way The dough is constricted (this is called the disturb problem).
- the voltage arrangement applied to the non-selected cells can be classified into three from A to C in FIG.
- the time during which stress is applied in each voltage arrangement is, for example, A and B (write time) ⁇ assuming that a write operation is performed on almost all cells in a 16 ⁇ 16 array.
- 15 and C write time
- the voltage difference between the source and drain (V3-V2 *) is small, and the voltage above the threshold formed by the inversion layer is applied to the word gate (V13) and memory gate (V8)). Therefore, there is no steep electric field drop in the channel, and almost no hot electrons are generated. For this reason, the threshold fluctuation amount within the disturb time in the voltage arrangement of A is so small that it can be ignored.
- the channel voltage does not flow due to the negative voltage applied to the word gate (this is called the inhibit voltage ⁇ Vinh), but a high electric field drop in the substrate under the word gate in the vicinity of the memory gate.
- a subthreshold current such as a punch-through current or a band current (between a valence band and a conduction band) tunnel current, and electrons flow into the charge storage layer 5.
- the subthreshold current increases more and more as the memory cell becomes finer, and the threshold fluctuation within the disturb time is not negligible under the voltage stress of B and C (FIG. 4 (a)).
- the disturb will be described in more detail with a focus on B and C.
- the main factor that fluctuates the threshold value of the cell having the voltage arrangement B is a punch-through current flowing inside the substrate. Therefore, as shown in FIG. 4B, when the inhibit negative voltage applied to the word gate is reduced, the threshold fluctuation amount of the cell having the voltage arrangement A increases.
- the inhibit voltage in writing is set so that the sum of the threshold fluctuation amount due to the voltage arrangement of B and C is minimized. .
- This minimum value is used as an index of disturbance resistance, and the smaller the value, the higher the disturbance resistance.
- FIG. 5 shows the disturbance resistance of the related structure II ′ in which the channel doping concentration in the region ⁇ in contact with the laminated film in the word gate is increased to improve the write efficiency, as compared with the related structure II.
- the horizontal axis indicates the threshold value ⁇ Vinh, and the horizontal axis indicates the voltage change of each cell.
- the threshold fluctuation amount due to the stress voltage arrangement of A in the related structure II ′ is limited in the reduction of the punch-through current because the doping amount in the vicinity of the source region or in the deep position in the substrate does not change, and even if it changes.
- the in-substrate electric field strength in the vicinity of the memory gate under the word gate increases due to the influence of channel doping on the region ⁇ , and the band-to-band tunneling current generated in the vicinity of the memory gate under the word gate increases greatly.
- the threshold fluctuation amount due to the stress voltage arrangement of C greatly increases.
- the minimum value of the total disturbance fluctuation amount of the cell arrangement B and the cell arrangement C of the related structure II ′ is larger than that of the related structure II (that is, the disturb tolerance is deteriorated). ).
- the nonvolatile semiconductor memory device of Patent Document 1 has a floating gate formed on a silicon substrate of one conductivity type, an insulating film that covers the floating gate, and a region that overlaps the floating gate via the insulating film.
- a control gate formed in this manner, a floating gate and a reverse conductivity type diffusion region formed on the surface of the silicon substrate adjacent to the control gate, and a metal wiring connected to the diffusion region through an interlayer insulating film
- the metal wiring is formed on the surface of one diffusion region through the silicide film, and the metal wiring is formed on the surface of the other diffusion region without the silicide film.
- a silicon film is formed and silicided by forming a titanium film in a state where a silicidation protective film made of an LPTEOS film is formed on a portion that is not to be silicided, thereby forming a base Si (source region). It is said that the reaction between titanium and the titanium film can be suppressed.
- the split gate nonvolatile semiconductor memory device of Patent Document 2 includes a floating gate having an acute angle portion formed by a side surface and an upper portion, a control gate provided so as to face the acute angle portion, and an upper portion of the floating gate.
- a split gate type nonvolatile semiconductor memory device including the insulating region formed on the substrate, wherein the side surface of the insulating region corresponding to the control gate side is separated from the control gate with respect to the normal direction of the substrate It is inclined in the direction.
- the split gate type nonvolatile semiconductor memory device in the split gate type nonvolatile memory in which data is erased by extracting electrons from the floating gate to the control gate, the data erasing operation can be performed appropriately and stably. It is said that it is possible to configure a non-volatile memory that can be performed.
- the nonvolatile semiconductor memory device of Patent Document 3 includes a floating gate formed on a silicon substrate of one conductivity type via a gate oxide film, a tunnel oxide film covering the floating gate, and one end of the floating gate via the tunnel oxide film.
- a nonvolatile semiconductor memory device comprising a control gate formed so as to overlap with a floating gate and a source / drain region of a reverse conductivity type formed on a surface of a semiconductor substrate adjacent to the control gate, a tunnel oxide film A side wall insulating film is formed only in a portion covering the vicinity of the lower portion of the floating gate.
- the side wall insulating film is formed on the portion of the tunnel oxide film covering the floating gate on the silicon substrate that covers the vicinity of the lower portion of the floating gate and then on one end of the floating gate. Since the control gate is formed so as to overlap, the control gate corner does not sharply enter the floating gate even at the lower corner of the floating gate where reverse tunneling is likely to occur. The gap between the floating gate and the floating gate is not reduced, and the occurrence of reverse tunneling failure can be suppressed.
- an object of the present invention is to provide a structure of a non-volatile memory device and a method for manufacturing the same that can improve the write efficiency and the disturb tolerance in the split gate type trap memory.
- the device of the present invention includes a laminated film that is formed on a substrate and accumulates charges, a first gate electrode formed on the laminated film, and first and second insulating layers on the first gate electrode and the substrate, respectively.
- a second gate electrode formed so as to be in contact with the film, and first and second impurity diffusion layers formed in the substrate so as to sandwich the first gate electrode and the second gate electrode.
- At least a part of the part in contact with the laminated film of the second insulating film has a larger equivalent oxide film thickness than the part of the part not in contact with the laminated film of the second insulating film.
- the equivalent oxide thickness refers to a thickness required for a certain insulating film to obtain a capacitance equivalent to that of a silicon oxide film.
- the first method of the present invention includes a step of preparing a semiconductor substrate, a step of sequentially depositing a tunnel insulating film material, a charge storage layer material and a gate electrode material on one main surface of the semiconductor substrate, a gate electrode material, a charge Removing a part of the storage layer material and tunnel insulating film material to expose the semiconductor substrate; depositing an insulating film material on one main surface side of the semiconductor substrate; and on one main surface side of the semiconductor substrate After depositing the gate electrode material, etch back is performed to leave the gate electrode material on the side surface of the previously formed gate electrode, and the dielectric constant of the insulating film material formed on the substrate without being etched back.
- a step of depositing a gate electrode material on one main surface side of the semiconductor substrate a step of exposing an upper portion of each gate electrode by etching, a predetermined gate electrode material, an insulating film material, an electrode Storage layer material, removing the tunnel insulating film material, characterized in that it comprises a step of exposing the semiconductor substrate, and forming a diffusion layer in a semiconductor substrate.
- the second method of the present invention includes a step of preparing a semiconductor substrate, a step of depositing an insulating film material and a gate electrode material on one main surface of the semiconductor substrate, and a part of the insulating film material and the gate electrode material.
- a step of removing and exposing the semiconductor substrate; a step of introducing bird's beaks into a region of the insulating film sandwiched between the gate electrode and the semiconductor substrate by oxidation; and tunnel insulation in order on one main surface side of the semiconductor substrate A step of depositing a film material, a charge storage layer material, and a gate electrode material; a step of exposing an upper portion of each gate electrode by etching; and a predetermined gate material, an insulating film material, a charge storage layer material, and a tunnel insulating film material And a step of exposing the semiconductor substrate and a step of forming a diffusion layer in the semiconductor substrate.
- the third method of the present invention includes a step of preparing a semiconductor substrate, a step of sequentially depositing a tunnel insulating film material, a charge storage layer material and a gate electrode material on one main surface of the semiconductor substrate, and a predetermined gate electrode material Removing the charge storage layer material and the tunnel insulating film material, performing a continuous etching to partially remove one main surface side of the semiconductor substrate material to make the semiconductor substrate convex, and After depositing an insulating film material on one main surface side, etching back to leave the insulating film material on the side surface of the gate electrode and the convex substrate; and an insulating film material on one main surface side of the semiconductor substrate After depositing the gate electrode material, etching back to leave the gate electrode material on the side surface of the previously formed gate electrode, and to remove the predetermined gate electrode material, charge storage layer material, and tunnel insulating film material. And characterized in that it comprises a step of exposing the semiconductor substrate, and forming a diffusion layer in a semiconductor substrate.
- the threshold value of the region under the insulating film By becoming larger than the threshold value of the region under the film, it is possible to improve the writing efficiency and the disturb resistance.
- a nonvolatile memory device includes a stacked film formed on a semiconductor substrate and having a function of accumulating charges, a first gate electrode formed on the stacked film, a first gate electrode, and a semiconductor substrate A second gate electrode formed so as to be in contact with each other via the first and second insulating films, and a first gate formed in the semiconductor substrate so as to sandwich the first gate electrode and the second gate electrode.
- at least the second diffusion layer is included, and a part in contact with the stacked film of the second insulating film has a larger equivalent oxide film thickness than a part not in contact.
- the nonvolatile memory device includes a substrate, first and second impurity diffusion layers formed so as to face each other in the vicinity of one main surface in the substrate, and the first impurity diffusion layer on the substrate.
- Oxide film equivalent film thickness is larger than the part that is not in contact with the laminated film of other insulating films And said that no.
- FIG. 6 shows a top view of one embodiment of a nonvolatile memory device according to the present invention.
- the trap-type memory as the nonvolatile memory device according to the present invention has a line-shaped element isolation region 15 arranged in a plurality of predetermined regions of a semiconductor substrate 1 to form an active region (first impurity).
- the diffusion region, the second impurity diffusion region, the channel region, etc.) are insulated and separated.
- the semiconductor substrate may be an N-type semiconductor (N well) or a P-type semiconductor (P well).
- a plurality of line electrodes are provided on the semiconductor substrate 1 so as to extend in a predetermined direction 16.
- One line-shaped electrode is further composed of two electrodes, that is, an electrode 8 and an electrode 13 that are in contact with each other on the side surface with the insulating film 10 interposed therebetween.
- a laminated film 7 including an insulating film (tunnel insulating film) 4, a charge storage layer 5, and an insulating film 6 is provided between the line-shaped electrode 8 and the semiconductor substrate 1 from the semiconductor substrate 1 side.
- An insulating film 11 and an insulating film 12 are provided between the line electrode 13 and the semiconductor substrate 1 so as to be adjacent to each other with respect to a predetermined direction 16. Note that the insulating film 12 is in contact with the laminated film 7.
- a conductor having a desired conductivity and work function can be used as a material for the gate electrode.
- impurities such as polycrystalline silicon, polycrystalline SiGe, polycrystalline Ge, and polycrystalline SiC introduced with impurities are introduced.
- semiconductors metals such as Mo, W, Ta, Ti, Hf, Re, and Ru, metal nitrides such as TiN, TaN, HfN, and WN, and silicide compounds such as cobalt silicide, nickel silicide, platinum silicide, and erbium silicide.
- the gate electrode may have a stacked structure such as a stacked film of a semiconductor and a metal film, a stacked film of metal films, or a stacked film of a semiconductor and a silicide film.
- a pair of source / drain regions are formed on both sides of the semiconductor substrate 1 sandwiched in a direction 17 orthogonal to a direction 16 in which each line-shaped electrode composed of the gate electrode 8 and the gate electrode 13 extends. Diffusion regions and second impurity diffusion regions) 2 and 3 are provided so as to face each other. Either an N-type impurity or a P-type impurity may be implanted into the source / drain regions 2 and 3, depending on whether the portion of the semiconductor substrate constituting the device of the present invention is an N well or a P well. Select as appropriate.
- the source / drain regions provided so as to sandwich each line-shaped electrode are arranged in a straight line in a direction 17 orthogonal to the extending direction 16 of the line-shaped electrodes, and such source / drain regions are arranged.
- a plurality of straight lines are provided so as to be parallel to each other.
- Source / drain contacts 14 are arranged in the source / drain regions provided on both sides of each on-line electrode so that a voltage can be applied, and the contacts 14 are electrically connected to the wiring layer.
- FIG. 7A is a cross-sectional view taken along the line Ia-Ia of the embodiment of the nonvolatile memory device according to the present invention shown in FIG. 6, and FIG. 7B is a cross-sectional view taken along the line Ib-Ib in FIG. It is.
- a laminated film 7 including the insulating film 4, the charge storage layer 5, and the insulating film 6 is formed on the semiconductor substrate 1 having the element isolation region 15.
- the insulating film 12 is formed so as to be in contact with one side of the laminated film 7, and the laminated film 11 is formed so as to be in contact with the side surface of the insulating film 12 on the side not in contact with the laminated film 7.
- a gate electrode 8 is formed on the laminated film 7, and a gate electrode 13 is formed on the insulating film 11 and the insulating film 12.
- An insulating film 10 is formed between the gate electrode 8 and the gate electrode 13, and the gate electrode 8 and the gate electrode 13 are electrically separated from each other.
- the source region 2 and the drain region 3 are formed in the semiconductor substrate 1 so as to partially overlap the gate electrode 13 and the gate electrode 8, respectively.
- the nonvolatile memory device according to the present invention is characterized in that the equivalent oxide thickness of the insulating film 12 under the gate electrode 13 is larger than the equivalent oxide thickness of the insulating film 11 that also exists under the gate electrode 13. is there.
- hot electrons are generated by applying a positive voltage to the gate electrodes 8 and 13 and the drain region 3 when data is written, and injected into the charge storage layer below the gate electrode 8. . Further, when reading data, a positive voltage is applied to the source region 2 and the gate electrodes 8 and 13 to monitor the source current value.
- the flat band of the charge storage layer is shifted in the positive direction, and current is less likely to flow than when electrons are not stored in the charge storage layer.
- Information can be stored by binarizing the state in which current does not easily flow and the state in which current easily flows.
- a negative voltage is applied to the gate electrode 8 to remove electrons from the charge storage layer using a Fowler-Nordheim (FN) tunnel current, or the gate electrode If a negative voltage is applied to 8, a positive voltage is applied to the drain region 3, holes generated by band-to-band tunneling in the substrate 1 are injected into the charge storage layer, and electrons existing in the charge storage layer are neutralized. good.
- FN Fowler-Nordheim
- the equivalent oxide thickness of the insulating film 12 under the gate electrode 13 is larger than the equivalent oxide thickness of the insulating film 11 that also exists under the gate electrode 13.
- the threshold value of the region ⁇ is larger than the threshold value of the region ⁇ under the insulating film 12. For this reason, even if the write current (channel current) is the same, the voltage drop from the source to the drain is lower than in the related structure II in which the equivalent oxide thickness of the insulating film under the gate electrode 13 is constant in the plane. It is less likely to occur in the ⁇ region with low channel resistance.
- the electrons concentrate in the high-resistance ⁇ region close to the charge storage layer 5, so that electrons in the channel are easily accelerated (hot), and the efficiency of electron injection into the charge storage layer is improved. That is, the writing efficiency (the value obtained by dividing the amount of channel hot electrons injected into the charge storage layer per unit time by the channel current flowing from the source to the drain) is improved.
- FIG. 8 is an explanatory diagram for explaining a nonvolatile memory device according to the present invention.
- the horizontal axis indicates the threshold voltage -Vinh
- the left and right vertical axes indicate the voltage change in each cell.
- the equivalent oxide thickness of the insulating film 11 in contact with the source region is small, the electric field applied to the substrate 1 from the gate electrode 13 in the vicinity of the source region is strengthened, and the depletion layer and the drain on the source side are in the vicinity of the source region.
- the punch-through current generated by the connection with the depletion layer on the side can be efficiently suppressed.
- the disturbance fluctuation amount between the cell arrangement B and the cell arrangement C is both The minimum value of the total disturbance fluctuation amount of the cell arrangement B and the cell arrangement C can be efficiently reduced (disturb tolerance can be improved).
- the stacked film having a function of storing charges may have at least two layers of a charge storage layer and a tunnel insulating film from the gate electrode side.
- the laminated film include a two-layer structure including a charge storage layer and a tunnel insulating film, and a three-layer structure including an insulating film B, a charge storage layer, and a tunnel insulating film.
- a silicon nitride film, a silicon oxynitride film, an alumina film, a hafnium silicate film, a hafnium oxide silicate film, or an aluminum silicate film is preferably used as the charge storage layer.
- the tunnel insulating film is preferably a silicon oxide film or a silicon oxynitride film. By using these charge storage layer and tunnel insulating film, high charge storage properties can be expressed. When the insulating film B is used, the same material as the tunnel insulating film can be used for the same reason as described above.
- the thickness of the tunnel insulating film is preferably 25 nm or more, more preferably 35 nm or more, and even more preferably 45 nm or more, in which the tunnel mechanism when electrons are transmitted does not become a direct tunnel mechanism. .
- the thickness of the insulating film B is preferably 25 nm or more, more preferably 35 nm or more, and even more preferably 45 nm or more, so that the tunnel mechanism when electrons are transmitted does not become a direct tunnel mechanism.
- the electrical conductivity at room temperature of the dielectric (insulator) used as the material for the charge storage layer is 10 ⁇ 6 ( S / m) or less, preferably 10 ⁇ 8 (S / m) or less, and more preferably 10 ⁇ 10 (S / m) or less.
- the equivalent oxide thickness of the insulating film under the word gate electrode 13 in contact with the stacked film having a function of storing charges.
- the ratio with the oxide film equivalent film thickness of the side which does not carry out the one where the former is larger is desirable, 6 to 4 is preferable, 7 to 3 is preferable, and 8 to 2 is still more preferable.
- the ratio of the length occupied in the channel direction between the large oxide film equivalent film thickness and the small oxide film thickness is such that the latter is concentrated in order to generate acceleration of channel hot electrons at the time of writing in the vicinity of the charge storage layer. Larger is better, 3 to 7 is preferable, 2 to 8 is preferable, and 1 to 9 is more preferable.
- the channel width (distance from the end of the accumulation layer to the boundary of the region with a small oxide film thickness) in the region with a large oxide film thickness is that the channel electrons at the time of writing are accelerated by the lateral electric field. It is desirable that the distance is longer than necessary for becoming hot, preferably 5 nm or more, more preferably 10 nm or more, and further preferably 15 nm or more.
- the source region and the drain region need not be at the same height with respect to the substrate, and the channel need not be formed on the same plane in the substrate. Therefore, the boundary surface between the insulating film 11 and the substrate 1 is lower than the boundary surface between the laminated film 7 and the substrate 1, and the insulating film 12 is L-shaped, and at each end, the insulating film 11 and the laminated film 7 It may be provided so that it may touch.
- the method for manufacturing a nonvolatile memory device includes the following steps. (1) preparing a semiconductor substrate; (2) depositing a tunnel insulating film material, a charge storage layer material and a gate electrode material in order on one main surface of the semiconductor substrate; (3) removing a part of the gate electrode material, the charge storage layer material, and the tunnel insulating film material to expose the semiconductor substrate; (4) depositing an insulating film material on one main surface side of the semiconductor substrate; (5) After depositing the gate electrode material on one main surface side of the semiconductor substrate, etching back is performed to leave the gate electrode material on the side surface of the previously formed gate electrode; (6) increasing the dielectric constant of the insulating film material formed on the semiconductor substrate without being etched back; (7) depositing a gate electrode material on one main surface side of the semiconductor substrate; (8) exposing the top of each gate electrode by etching; (9) removing a predetermined gate electrode material, insulating film material, charge storage layer material, and tunnel insulating film material to expose the semiconductor substrate; (
- 9A to 9H are process diagrams showing a method of manufacturing a trap type memory as a nonvolatile memory device.
- 9A to 9H show a trap type memory cut along a section corresponding to the line IIa-IIa shown in FIG.
- FIG. 9A First, an oxide film (tunnel insulating film material) 4 and a nitride film (charge storage layer material) 5 are sequentially deposited on the surface of the P-type semiconductor substrate 1 by using a CVD (Chemical Vapor Deposition) method. Further, the upper part of the nitride film 5 is oxidized by ISSG (In-site Steam Steam Generation) to form an oxide film (insulating film B material) 6, and a stacked layer composed of the oxide film 4, the nitride film 5, and the oxide film 6. A film 7 is formed.
- ISSG In-site Steam Steam Generation
- a phosphorus-added silicon film (gate electrode material) 8 is deposited on the oxide film 6 of the laminated film 7 by using the CVD method. Then, after depositing an antireflection film and a resist film and patterning by exposure and development, the gate electrode material 8 and the laminated film 7 are etched using a dry etcher to expose a predetermined portion of the semiconductor substrate 1. Then, the antireflection film and the resist film are removed by wet.
- FIG. 9B Next, an oxide film 12 and a phosphorus-added silicon film 13 are deposited on one main surface (upper surface in the drawing) of the wafer by using the CVD method.
- FIG. 9C Next, the gate electrode material 13 is etched back by dry etching so that the gate electrode material 13 remains only on both side walls of the gate electrode material 8.
- FIG. 9D Next, nitrogen is ion-implanted into the oxide film on the substrate 1 with low energy to improve the dielectric constant, and then annealing is performed to recover the damage caused by the implantation.
- FIG. 9E Next, phosphorus-added silicon is deposited on the entire surface of one main surface (upper surface in the figure) of the wafer.
- CMP Chemical Mechanical Polishing
- FIG. 9G Next, after depositing an antireflection film and a resist film, patterning by exposure and development, the gate electrode material 8 and the laminated film 7, the gate insulating film 13 and the oxide film using a dry etcher 11 is etched to expose a predetermined portion of the semiconductor substrate 1, and then the antireflection film and the resist film are wet-removed.
- the nonvolatile memory device according to the present invention can be formed.
- FIG. 10 shows an example of a cross-sectional view of a trap memory as a nonvolatile memory device according to the present invention cut along the channel direction.
- a laminated film 7 including an insulating film 4, a charge storage layer 5, and an insulating film 6 is formed on one main surface (upper surface in the drawing) of the semiconductor substrate 1.
- a gate electrode 8 is formed.
- a gate electrode 13 is formed so as to be in contact with both the gate electrode 8 and the semiconductor substrate 1 through the insulating film 11.
- a source region 2 and a drain region 3 are formed in the semiconductor substrate 1 so as to sandwich the two electrodes of the gate electrode 13 and the gate electrode 8.
- a part of the physical film thickness in contact with the laminated film 7 of the insulating film 11 existing between the gate electrode 13 and the semiconductor substrate 1 is thicker than the physical film thickness of the non-contact part.
- hot electrons are generated by applying a positive voltage to the gate electrodes 8 and 13 and the drain region 3 at the time of data writing, and injected into the charge storage layer 5 of the stacked film 7. Further, when reading data, a positive voltage is applied to the source region 2 and the gate electrodes 8 and 13 to monitor the source current value.
- the flat band of the charge storage layer 5 is shifted in the positive direction, and current is less likely to flow than when electrons are not stored in the charge storage layer 5.
- Information can be stored by binarizing the state in which current does not easily flow and the state in which current easily flows.
- a negative voltage is applied to the gate electrode 8 to remove electrons from the charge storage layer 5 using a Fowler-Nordheim (FN) type tunnel current
- a negative voltage is applied to the electrode 8 and a positive voltage is applied to the drain region 3 to inject holes generated by band-to-band tunneling in the semiconductor substrate 1 into the charge storage layer 5 to neutralize electrons present in the charge storage layer 5.
- FN Fowler-Nordheim
- the film thickness of the insulating film 11 in the region ⁇ in contact with the laminated film 7 under the gate electrode 13 is larger than the film thickness of the insulating film 11 in the region ⁇ not in contact with the laminated film 7 under the gate electrode 13. Is larger than the threshold value of the region ⁇ .
- the write current channel current
- the voltage drop from the source to the drain is lower than that in the related structure II in which the film thickness of the insulating film under the gate electrode 13 is constant in the plane.
- the electrons are concentrated in the high-resistance ⁇ region close to the charge storage layer 5, so that electrons in the channel are easily accelerated (hot) and the efficiency of electron injection into the charge storage layer 5 is improved. That is, the writing efficiency (the value obtained by dividing the amount of channel hot electrons injected into the charge storage layer per unit time by the channel current flowing from the source to the drain) is improved.
- the thickness of the insulating film 11 in contact with the source region is small, the electric field applied to the semiconductor substrate 1 from the gate electrode 13 in the vicinity of the source region is strengthened, and the depletion layer and the drain on the source side are in the vicinity of the source region.
- the punch-through current generated by the connection with the side depletion layer can be efficiently suppressed.
- the disturbance fluctuation amount of the cell arrangement B and the cell arrangement C is reduced as compared with the related structure II in which the equivalent oxide thickness of the insulating film under the gate electrode 13 is constant in the plane. Therefore, the minimum value of the total disturbance variation of the cell arrangement B and the cell arrangement C can be efficiently reduced (disturb tolerance can be improved).
- FIG. 11A are process diagrams showing an embodiment of a method for manufacturing a nonvolatile memory device according to the present invention.
- FIG. 11A First, an oxide film (tunnel insulating film material) 4 and a nitride film (charge storage layer material) 5 are sequentially deposited on the surface of the P-type semiconductor substrate 1 using a CVD method. 5 is oxidized by ISSG (In-situ Steam Generation) to form an oxide film (insulating film B material) 6, and a laminated film 7 including the oxide film 4, the nitride film 5, and the oxide film 6 is formed. .
- ISSG Insulating film B material
- a phosphorus-added silicon film (gate electrode material) 8 is deposited on the oxide film 6 of the laminated film 7 by using the CVD method. Then, after depositing an antireflection film and a resist film and patterning by exposure and development, the gate electrode material 8 and the laminated film 7 are etched using a dry etcher to expose a predetermined portion of the semiconductor substrate 1. Then, the antireflection film and the resist film are wet removed.
- FIG. 11B Next, an oxide film 11 and a phosphorus-added silicon film 13 are deposited on the entire surface of one main surface (upper surface in the drawing) of the wafer by using the CVD method.
- FIG. 11C Next, the gate electrode material 13 is etched back by dry etching so that the gate electrode material 13 remains only on both side walls of the gate electrode material 8.
- FIG. 11E Next, a phosphorus-added silicon film 13 is deposited on the entire surface of one main surface of the wafer.
- CMP Chemical Mechanical Polishing
- the nonvolatile memory device shown in FIG. 10 can be formed.
- FIGS. 12 (a) to 12 (e) are process diagrams showing another embodiment of the method for manufacturing the nonvolatile memory device according to the present invention.
- FIG. 12A First, an oxide film 11 is deposited on the surface of the P-type semiconductor substrate 1 using the CVD method. Further, a phosphorus-added silicon film (gate electrode material) 13 is formed on the oxide film 11 using the CVD method. To deposit.
- the gate electrode material 13 and the oxide film 11 are etched using a dry etcher to expose a predetermined portion of the semiconductor substrate 1. Then, the antireflection film and the resist film are wet removed.
- FIG. 12B Next, by performing oxidation treatment, a bird's beak is introduced into the boundary portion of the oxide film 11 sandwiched between the semiconductor substrate 1 and the gate electrode material 13 exposed after the etching, and the oxide film 11 In addition, the excess oxide film formed on the upper surface of the semiconductor substrate 1 and the upper surface of the gate electrode material 13 is removed by performing dry etching.
- an oxide film (tunnel insulating film material) 4 and a nitride film (charge storage layer material) 5 are formed on the entire surface of one main surface (the upper surface in the figure) of the wafer by CVD. Are sequentially deposited, and the upper portion of the nitride film 5 is oxidized by ISSG (In-situ Steam Generation) to form an oxide film (insulating film B material) 6. The oxide film 4, the nitride film 5, and the oxide film are then oxidized. A laminated film 7 made of the film 6 is formed.
- a phosphorus-added silicon film (gate electrode material) 8 is deposited on the oxide film 6 of the laminated film 7 by using the CVD method. Thereafter, a CMP (Chemical-Mechanical-Polishing) process is performed to remove a part of the gate electrode material 8 and the laminated film 7 and expose an upper end portion of the gate electrode material 13.
- CMP Chemical-Mechanical-Polishing
- FIG. 12D Next, after depositing an antireflection film and a resist film, patterning by exposure and development, a predetermined portion of the gate electrode material 8 and laminated film 7 and gate electrode material 13 using a dry etcher. After the oxide film 11 is etched to expose the semiconductor substrate 1, the antireflection film and the resist film are wet removed.
- the nonvolatile memory device shown in FIG. 10 can also be formed.
- the steps shown in FIGS. 12A to 12E can reduce the number of steps because the gate electrode material need not be deposited twice. Therefore, the process cost can be reduced.
- the source region and the drain region do not need to be at the same height with respect to the semiconductor substrate 1 and the channel does not need to be formed on the same plane in the semiconductor substrate 1, as shown in FIG.
- the boundary surface between the insulating film 11 and the semiconductor substrate 1 may be lower than the boundary surface between the stacked film 7 and the semiconductor substrate 1, and the stacked film of the insulating film 11 existing between the gate electrode 13 and the semiconductor substrate 1. If the equivalent oxide thickness of the portion in contact with 7 is larger than the portion not in contact, the same effect as in the case of a flat surface can be obtained.
- FIG. 13 is a cross-sectional view showing another embodiment of the nonvolatile memory device according to the present invention.
- 14A to 14E are process diagrams showing an embodiment of a method for manufacturing the nonvolatile memory device shown in FIG. FIG. 14A: First, an oxide film (tunnel insulating film material) 4 and a nitride film (charge storage layer material) 5 are sequentially deposited on the surface of the P-type semiconductor substrate 1 using a CVD method. Further, the upper portion of the nitride film 5 is oxidized by ISSG (In-situ Steam Generation) to form an oxide film (insulating film B material) 6, and a laminated film 7 composed of the oxide film 4, the nitride film 5, and the oxide film 6. Form.
- ISSG In-situ Steam Generation
- a phosphorus-added silicon film (gate electrode material) 8 is deposited on the oxide film 6 of the laminated film 7 by using the CVD method. Then, after depositing an antireflection film and a resist film and patterning by exposure and development, the gate electrode material 8, the laminated film 7 and a part of the upper portion of the semiconductor substrate 1 are etched using a dry etcher, and then the reflection is performed. The prevention film and the resist film are removed by wet.
- FIG. 14B Next, an oxide film 11 is deposited on the entire surface of one main surface (upper surface in the figure) of the wafer by using the CVD method, and then etched back to form the oxide film 11 as a gate electrode.
- the material 8 is formed so as to remain only on both side walls.
- FIG. 14C Next, the oxide film 11 and the gate insulating material 13 are sequentially deposited on the entire main surface of one of the wafers by using the CVD method, and then etched back to provide the gate insulating material 13 and the oxide film. 11 is left only on the convex side surface.
- FIG. 14D Next, after depositing an antireflection film and a resist film, patterning by exposure and development, the gate electrode material 8 and the laminated film 7 are etched using a dry etcher to form a predetermined portion. After the semiconductor substrate 1 is exposed, the antireflection film and the resist film are wet removed.
- the nonvolatile memory device of the present invention it is possible to simultaneously improve the write efficiency and the disturb resistance.
- Patent Document 3 considered the closest to the present invention and the present invention will be described.
- the floating gate 4 in the abstract of Patent Document 3 is similar in appearance to the first gate electrode of the present invention.
- the floating gate 4 of Patent Document 3 is clearly designated as a gate, it is isolated as shown in FIG. 16 of Patent Document 3 and is not electrically connected to other parts (that is That's why it is a “floating gate”.)
- the first gate electrode of the present invention is an electrode for applying a voltage, and is different from the floating gate described in Patent Document 3.
- the biggest difference between the present invention and the invention described in Patent Document 3 is that the present invention is a trap-type memory, whereas the invention described in Patent Document 3 is a floating-type memory. It is.
- the trap type memory requires a separate memory gate in order to erase electrons injected into the charge storage layer (trap film). It is structurally different from a floating memory in which the charge storage layer is a memory gate (floating gate) itself that is electrically disconnected from the outside.
- the split gate structure trap type memory has two gates that are electrically controlled by one element, whereas the floating type memory similar to the split gate structure is electrically controlled by one element. The difference is that the number of gates is one.
- (a)-(d) is explanatory drawing of the non-volatile memory device relevant to this invention.
- (a), (b) is operation
- (a)-(c) is explanatory drawing of the non-volatile memory device relevant to this invention.
- (a), (b) is characteristic explanatory drawing of the non-volatile memory device relevant to this invention. It is the figure which compared the disturbance tolerance of the related structure II 'which increased the channel dope density
- 1 is a top view of an embodiment of a nonvolatile memory device according to the present invention.
- FIG. 6 is a cross-sectional view taken along line Ia-Ia of the trap type memory according to the embodiment of the nonvolatile memory device according to the present invention shown in FIG. 6, and (b) is a cross-sectional view taken along line Ib-Ib in FIG. It is. It is explanatory drawing for demonstrating the non-volatile memory device based on this invention.
- (a) to (h) are process diagrams showing a method of manufacturing a trap type memory as a nonvolatile memory device. It is a figure which shows an example of sectional drawing which cut
- FIGS. 4A to 4H are process diagrams showing an embodiment of a method for manufacturing a nonvolatile memory device according to the present invention.
- FIGS. 4A to 4E are process diagrams showing another embodiment of a method for manufacturing a nonvolatile memory device according to the present invention. It is sectional drawing which shows the other Example of the non-volatile memory device based on this invention.
- FIGS. 14A to 14E are process diagrams showing an embodiment of a method of manufacturing the nonvolatile memory device shown in FIG.
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Abstract
Description
ここで、0.13 μm世代までのフラッシュ(Flash)メモリの微細化では、フローティングゲート(Floating Gate:FG)型を用いたセル面積縮小や絶縁膜の薄膜化が主流であった。
図1(a)~(d)は、本発明に関連する不揮発性記憶装置の説明図である。
図1(a)は最も単純なプレーナー型構造(本発明に関連する構造、以下、「関連構造I」と表記する。)のトラップメモリを示している。シリコン基板1上に、順に第一の絶縁膜4、電荷蓄積層5、および第二の絶縁膜6からなる積層膜7と、積層膜7上にさらにメモリゲート電極8とが設けられている。また、シリコン基板1内のメモリゲート電極8を挟んだ両側には、メモリゲート電極8と一部オーバーラップするようにしてソース領域2およびドレイン領域3が形成されている。
このため、書き込み効率(単位時間あたりに電荷蓄積層中にチャネルホットエレクトロンを注入される量を、ソースからドレインに流れるチャネル電流で割った値)は、ゲート電圧を強めても大きく増加しないばかりか、減少することさえある。
図1(c)に示すように、シリコン基板1上に、順に第一の絶縁膜4、電荷蓄積層5、第二の絶縁膜6からなる積層膜7、およびメモリゲート電極8が設けられ、メモリゲート電極8の片側とシリコン基板1の一方の主面(図では上面)との両方に接するようにワードゲート電極13が絶縁膜10、11を介して設けられている。また、ゲート電極8、13を挟んだ両側のシリコン基板1内には、ソース領域2およびドレイン領域3がそれぞれのゲート電極8、13に一部オーバーラップするように形成されている。
ただし、電荷蓄積層5上のメモリゲート8に対して強い垂直電界をかけて電子を注入しやすくする一方で、ワードゲート13に対して印加する電圧を低く抑えてワードゲート13下を高抵抗化させ、チャネル電流が流れすぎないようにする必要がある(図1(d))。
このため、書き込み効率に優れたスプリットゲート構造は、周辺回路の小面積化によるチップコストの低減効果の大きいメモリ内蔵のロジックLSIにおいて、特に重要な構造になっている。
図2(a)、(b)は、本発明に関連する不揮発性記憶装置の動作説明図である。
書き込みのチャネル電流を同じにしても、領域αが低抵抗化している分(図2(b))、ソースからドレインにかけての電圧降下が高チャネル抵抗領域βのメモリゲート8近傍に集中し、チャネルエレクトロンが加速されやすく(ホットになりやすく)なっている。
このため、関連構造II’は、関連構造IIよりもさらに書き込み効率が向上している。
メモリセルはチップ内に効率的に配置するためにアレイ状(例えば16×16セル)になっている。
図3(a)~(c)は、本発明に関連する不揮発性記憶装置の説明図である。
図4(a)、(b)は、本発明に関連する不揮発性記憶装置の特性説明図である。図4(a)は各セルの時間と電圧変化との関係を示し、(b)は、各セルの閾値と電圧変化との関係を示している。
このため、書き込みセル(図3(a))に電圧を印加する時に、図3(b) に示すように共通配線を通して隣接したセル(非選択セル)の各電極にも電圧が印加されてしまう。外部電圧によるストレスよって、非選択セルの電荷蓄積層中にも基板内の電子が注入されてしまうため、特に非選択セルが消去状態にある場合は消去レベル(閾値)が上昇して、メモリウェインドウが狭窄してしまう(これをディスターブ問題と呼ぶ)。
Bの電圧配置のセルの閾値を変動させる主要因は、基板内部を流れるパンチスルー電流にある。このため、図4(b)に示すようにワードゲートに印加するインヒビット負電圧を小さくすると、Aの電圧配置のセルの閾値変動量は増加する。
同図において、横軸は閾値-Vinhを示し、左右縦軸は各セルの電圧変化を示す。
関連構造II’のAのストレス電圧配置による閾値変動量はソース領域近傍や基板内の深い位置でのドープ量は変わらないためにパンチスルー電流の低減は限定的で、変化したとしても小さい。
図5に示すように、関連構造II’のセル配置Bとセル配置Cとのディスターブ変動量の合計の最小値は、関連構造IIよりも増加している(すなわち、ディスターブ耐性が劣化している)。
特許文献1の不揮発性半導体記憶装置は、一導電型のシリコン基板上に形成されたフローティングゲートと、このフローティングゲートを被覆する絶縁膜と、この絶縁膜を介してフローティングゲート上に重なる領域を持つように形成されるコントロールゲートと、フローティングゲートおよびコントロールゲートに隣接するシリコン基板の表面に形成される逆導電型の拡散領域と、層間絶縁膜を介して拡散領域に接続された金属配線とを備えた不揮発性半導体記憶装置において、一方の拡散領域表面にはシリサイド膜を介して金属配線が形成され、他方の拡散領域表面にはシリサイド膜を介することなしに金属配線が形成されているものである。
そこで、本発明は、以上のような従来構造における問題点を鑑みて考案されたものである。
すなわち、本発明の目的は、スプリットゲート構造のトラップメモリにおいて、書き込み効率を向上させるとともに、ディスターブ耐性も向上させることが出来る不揮発性記憶装置の構造とその製造方法を提供することにある。
ここで、酸化膜換算膜厚とは、ある絶縁膜がシリコン酸化膜と同等の静電容量を得るのに要する膜厚をいう。
(特徴)
本発明に係る不揮発性記憶装置は、半導体基板上に形成された電荷を蓄積する機能を有する積層膜と、積層膜上に形成された第一のゲート電極と、第一のゲート電極と半導体基板にそれぞれ第一、第二の絶縁膜を介して接するように形成された第二のゲート電極と、第一のゲート電極と第二のゲート電極を挟み込むように半導体基板内に形成された第一および第二の拡散層を少なくとも含み、第二の絶縁膜の積層膜と接する一部が、接しない部分よりも酸化膜換算膜厚が大きいことを特徴とする。
図6に、本発明に係る不揮発性記憶装置の一実施の形態の上面図を示す。
図6に示すように、本発明に係る不揮発性記憶装置としてのトラップ型メモリは、半導体基板1の複数の所定の領域にライン状の素子分離領域15が配置されて、活性領域(第1不純物拡散領域、第2不純物拡散領域、チャネル領域など)を絶縁分離している。なお、半導体基板としては、N型半導体(Nウェル)であっても、P型半導体(Pウェル)であっても良い。
なお、一本のライン状電極は、さらに絶縁膜10を介して互いに側面で接する電極8と電極13との二つの電極から構成されている。ライン上状電極8と半導体基板1との間には、半導体基板1側から絶縁膜(トンネル絶縁膜)4、電荷蓄積層5、および絶縁膜6から成る積層膜7が設けられている。また、ライン状電極13と半導体基板1との間には、絶縁膜11と絶縁膜12とが所定方向16に対してお互いに隣接するように設けられている。なお、積層膜7と接しているほうが、絶縁膜12である。
図7(a)、(b)に示されているように、素子分離領域15を備えた半導体基板1上には、絶縁膜4、電荷蓄積層5、および絶縁膜6からなる積層膜7と、積層膜7の片側に接するように絶縁膜12と、さらに積層膜7と接していない側の絶縁膜12の側面に接するように積層膜11とが形成されている。
積層膜7上にはゲート電極8が形成され、絶縁膜11および絶縁膜12の上にはゲート電極13が形成されている。ゲート電極8とゲート電極13との間には絶縁膜10が形成されており、ゲート電極8とゲート電極13とはお互いに電気的に分離されている。また、ソース領域2とドレイン領域3とは、ゲート電極13およびゲート電極8に対してそれぞれ、その一部がオーバーラップするように半導体基板1内に形成されている。
本発明に係る不揮発性記憶装置では、ゲート電極13下の絶縁膜12の酸化膜換算膜厚が、ゲート電極13下に同じく存在する絶縁膜11の酸化膜換算膜厚よりも大きいことに特徴がある。
本発明に係る不揮発性記憶装置では、データの書き込み時にゲート電極8、13およびドレイン領域3に正の電圧を印加することでホットエレクトロンを生成し、ゲート電極8下の電荷蓄積層内に注入する。また、データの読み出し時にはソース領域2とゲート電極8、13とに正の電圧を印加し、ソース電流値をモニターする。
電荷蓄積層内に電子が蓄積している場合、電荷蓄積層のフラットバンドが正方向にシフトして、電荷蓄積層内に電子が蓄積していない場合と比べて、電流が流れにくくなる。このように電流が流れにくい状態と、電流が流れやすい状態を2値化することによって、情報を記憶することが可能となる。
この不揮発性記憶装置は、ゲート電極13下の絶縁膜12の酸化膜換算膜厚が、ゲート電極13下に同じく存在する絶縁膜11の酸化膜換算膜厚よりも大きいために、絶縁膜12下の領域βの閾値が、絶縁膜12下の領域αの閾値よりも大きくなっている。このため、書き込み電流(チャネル電流)が同じであっても、ゲート電極13下の絶縁膜の酸化膜換算膜厚が面内で一定である関連構造IIよりも、ソースからドレインへの電圧降下が、低チャネル抵抗のα領域では起こりにくくなった。その分だけ、電荷蓄積層5に近い高抵抗なβ領域により集中するため、チャネル中の電子が加速されやすく(ホットになりやすく)、電荷蓄積層への電子注入効率が向上している。すなわち、書き込み効率(単位時間あたりに電荷蓄積層中にチャネルホットエレクトロンを注入される量を、ソースからドレインに流れるチャネル電流で割った値)が向上している。
このため、図8に示すように、図3(c)に示した書き込み動作の際の非選択セルCのディスターブ時間内の閾値変動量は、ゲート電極13下の絶縁膜の酸化膜換算膜厚が面内で一定(=絶縁膜11と絶縁膜12との平均値)である関連構造IIよりも、低減させることが出来る。
図8は、本発明に係る不揮発性記憶装置を説明するための説明図である。
同図において、横軸は閾値電圧-Vinhを示し、左右両縦軸は各セルにおける電圧変化を示す。
積層膜としては例えば、電荷蓄積層、およびトンネル絶縁膜の2層構成のもの、絶縁膜B、電荷蓄積層、およびトンネル絶縁膜の3層構成のものを挙げることができる。この場合、電荷蓄積層としては、窒化シリコン膜、酸窒化シリコン膜、アルミナ膜、ハフニウムシリケート膜、酸化ハフニウムシリケート膜又はアルミニウムシリケート膜を用いることが好ましい。
(1)半導体基板を準備する工程と、
(2)半導体基板の一方の主面に順にトンネル絶縁膜材料、電荷蓄積層材料およびゲート電極材料を堆積する工程と、
(3)ゲート電極材料、電荷蓄積層材料、トンネル絶縁膜材料の一部を除去して半導体基板を露出させる工程と、
(4)半導体基板の一方の主面側に絶縁膜材料を堆積する工程と、
(5)半導体基板の一方の主面側にゲート電極材料を堆積した後、エッチバックを施して先に形成したゲート電極の側面にゲート電極材料を残留させる工程と、
(6)エッチバックされずに半導体基板上に形成されている絶縁膜材料の誘電率を高める工程と、
(7)半導体基板の一方の主面側にゲート電極材料を堆積する工程と、
(8)エッチングによって各ゲート電極の上部を露出させる工程と、
(9)所定のゲート電極材料、絶縁膜材料、電荷蓄積層材料、およびトンネル絶縁膜材料を除去し、半導体基板を露出させる工程と、
(10)半導体基板内に拡散層を形成する工程。
図9(a)~(h)は、不揮発性記憶装置としてのトラップ型メモリの製造方法を示す工程図である。図9(a)~(h)には図10に示したIIa―IIa線に相当する断面で切断されたトラップ型メモリが示されている。
図10に、本発明に係る不揮発性記憶装置としてのトラップ型メモリをチャネル方向に沿って切断した断面図の一例を示す。
同図に示すように半導体基板1の一方の主面(図では上側の面)上に絶縁膜4、電荷蓄積層5、絶縁膜6からなる積層膜7が形成され、積層膜7上にはさらにゲート電極8が形成されている。また、絶縁膜11を介してゲート電極8と半導体基板1の両方に接するようにゲート電極13が形成されている。半導体基板1内には、ゲート電極13とゲート電極8との二つの電極を挟むようにソース領域2とドレイン領域3とが形成されている。ゲート電極13と半導体基板1との間に存在する絶縁膜11の積層膜7と接する一部の物理膜厚は、接しない部分の物理膜厚よりも厚い。
本実施例では、データの書き込み時にゲート電極8、13およびドレイン領域3に正の電圧を印加することでホットエレクトロンを生成し、積層膜7の電荷蓄積層5内に注入する。また、データの読み出し時にはソース領域2とゲート電極8、13とに正の電圧を印加し、ソース電流値をモニターする。電荷蓄積層5内に電子が蓄積している場合、電荷蓄積層5のフラットバンドが正方向にシフトして、電荷蓄積層5内に電子が蓄積していない場合と比べて、電流が流れにくくなる。このように電流が流れにくい状態と、流れやすい状態とを2値化することによって、情報を記憶することが可能となる。
なお、記憶させた情報を消去するには、ゲート電極8に負電圧を印加して、ファウラー・ノルドハイム(FN)型トンネル電流を利用して電荷蓄積層5から電子を除去するか、又は、ゲート電極8に負電圧、ドレイン領域3に正電圧を印加して、半導体基板1中のバンド間トンネルによる生成ホールを電荷蓄積層5に注入し、電荷蓄積層5中に存在する電子を中和させれば良い。
この不揮発性記憶装置によって、以下に示す効果を奏すことが出来る。
ゲート電極13下の積層膜7と接する領域βの絶縁膜11の膜厚は、ゲート電極13下の積層膜7と接しない領域α上の絶縁膜11の膜厚よりも大きいために、領域βの閾値が、領域αの閾値よりも大きくなっている。
すなわち、書き込み効率(単位時間あたりに電荷蓄積層中にチャネルホットエレクトロンを注入される量を、ソースからドレインに流れるチャネル電流で割った値)が向上している。
このため、図8に示すように、図3(c)に示した書き込み動作の際の非選択セルCのディスターブ時間内の閾値変動量は、ゲート電極13下の絶縁膜の膜厚が面内で一定(=絶縁膜11の面内平均値)である関連構造IIよりも、低減することが出来る。
このため、図8に示すように、図3(c)に示した書き込み動作の際の非選択セルBのディスターブ時間内の閾値変動量は、ゲート電極13下の絶縁膜の膜厚が面内で一定(=絶縁膜11の面内平均値)である関連構造IIよりも、低減させることが出来る。
図11(a)~(h)は、本発明に係る不揮発性記憶装置の製造方法の一実施例を示す工程図である。
図11(a):まず、P型半導体基板1の表面にCVD法を用いて酸化膜(トンネル絶縁膜材料)4および窒化膜(電荷蓄積層材料)5を順次、堆積させ、さらに、窒化膜5の上部をISSG(In-situ Steam Generation)で酸化することにより酸化膜(絶縁膜B材料)6を形成し、酸化膜4、窒化膜5、および酸化膜6からなる積層膜7を形成する。
図12(a)~(e)は、本発明に係る不揮発性記憶装置の製造方法の他の実施例を示す工程図である。
図12(a):まず、P型半導体基板1の表面にCVD法を用いて酸化膜11を堆積させ、さらに、酸化膜11上にCVD法を用いてリン添加シリコン膜(ゲート電極材料)13を堆積する。そして、反射防止膜およびレジスト膜を堆積し、露光・現像することによりパターニングした後、ドライエッチャーを用いてゲート電極材料13および酸化膜11をエッチングして所定部分の半導体基板1を露出させた後、反射防止膜とレジスト膜をウェット除去する。
図12(a)~(e)に示した工程は、図11(a)~(h)に示した工程に比べると、ゲート電極材料を2度堆積させる必要がない分、工程数を減らせることが出来るためプロセスコストを低減することが出来る。
図14(a):まず、P型半導体基板1の表面にCVD法を用いて酸化膜(トンネル絶縁膜材料)4および窒化膜(電荷蓄積層材料)5を順次、堆積させる。さらに、窒化膜5の上部をISSG(In-situ Steam Generation)で酸化することにより酸化膜(絶縁膜B材料)6を形成し、酸化膜4、窒化膜5、酸化膜6からなる積層膜7を形成する。
次に、積層膜7の酸化膜6上にCVD法を用いてリン添加シリコン膜(ゲート電極材料)8を堆積する。そして、反射防止膜およびレジスト膜を堆積し、露光・現像することによりパターニングした後、ドライエッチャーを用いてゲート電極材料8、積層膜7および半導体基板1の上部の一部をエッチングした後、反射防止膜とレジスト膜をウェット除去する。
以上の様にして、図13に示した不揮発性記憶装置を形成する事ができる。
特許文献3の要約書のフローティングゲート4は、本願発明の第1のゲート電極に一見類似している。
しかしながら、特許文献3のフローティングゲート4は、ゲートと明記されているものの、特許文献3の図16に示されているように孤立しており、電気的に他の部分に接続されていない(それゆえの「フローティングゲート」である。)。
これに対して本願発明の第一のゲート電極は、電圧を印加するための電極であり、特許文献3に記載のフローティングゲートとは異なる。
トラップ型メモリは、電荷蓄積層(トラップ膜)に注入された電子を消去するために、別途メモリゲートを必要とする。電荷蓄積層が外部と電気的に切断されたメモリゲート(フローティングゲート)そのものであるフローティング型メモリとは構造的に異なっている。
スプリットゲート構造に似たフローティング型メモリの書き込み動作時の非選択セルにおいては、フローティングゲートには電圧が印加されないため、フローティングゲート(トラップ型メモリに対応させた表現ではメモリゲートとなる。)とワードゲート(トラップ型メモリに対応させた表現ではコントロールゲートとなる。)との境界でのバンド間トンネル効果によるディスターブは発生しない。
従って、特許文献3に記載の技術は本願発明と構成及び作用効果が相違する。
2 第1不純物拡散領域(ソース)
3 第2不純物拡散領域(ドレイン)
4 絶縁膜(トンネル絶縁膜)
5 電荷蓄積層
6 絶縁膜
7 積層膜
8、13 ゲート電極
9 反転層
10~12 絶縁膜
13 第二のゲート電極
14 コンタクト
15 素子分離層
16 所定方向(その1)
17 所定方向(その2)
18 拡散層
Claims (13)
- 基板上に形成され、電荷を蓄積する積層膜と、前記積層膜上に形成された第一のゲート電極と、前記第一のゲート電極および前記基板にそれぞれ第一、第二の絶縁膜を介して接するように形成された第二のゲート電極と、前記第一のゲート電極と前記第二のゲート電極とを挟み込むように前記基板内に形成された第一および第二の不純物拡散層とを少なくとも含み、前記第二の絶縁膜の前記積層膜と接する部分の一部が、前記第二の絶縁膜の前記積層膜と接しない部分よりも酸化膜換算膜厚が大きいことを特徴とする不揮発性記憶装置。
- 前記第二の絶縁膜の前記積層膜と接する部分の一部が、前記第二の絶縁膜の前記積層膜と接しない部分よりも物理膜厚が大きいことを特徴とする請求項1に記載の不揮発性記憶装置。
- 前記第二の絶縁膜の前記積層膜と接する部分の一部の誘電率が、前記第二の絶縁膜の前記積層膜と接しない部分の誘電率よりも低いことを特徴とする請求項1または2に記載の不揮発性記憶装置。
- 前記第二の絶縁膜の前記積層膜と接しない部分の一部が、前記第二の絶縁膜の前記積層膜と接する部分よりも高い誘電率の材料からなることを特徴とする請求項3に記載の不揮発性記憶装置。
- 前記第二の絶縁膜の前記積層膜と接する部分の一部が酸化シリコンであり、前記第二の絶縁膜の前記積層膜と接しない部分が酸窒化シリコン、アルミナ、ハフニウムシリケート、酸化ハフニウムシリケート、アルミシリケート、酸化アルミシリケートのいずれかであることを特徴とする請求項4に記載の不揮発性記憶装置。
- 前記第二の絶縁膜の前記積層膜と接しない部分の一部が不純物の添加によって、前記第二の絶縁膜の前記積層膜と接する部分よりも誘電率が高いことを特徴とする請求項3に記載の不揮発性記憶装置。
- 前記第二の絶縁膜が酸化シリコンであり、前記積層膜と接しない部分に窒素が添加されていることを特徴とする請求項6に記載の不揮発性記憶装置。
- 前記電荷を蓄積する機能を有する積層膜が、基板側からトンネル絶縁膜と電荷蓄積層からなる二層構造であることを特徴とする請求項1に記載の不揮発性記憶装置。
- 前記電荷蓄積層は、窒化シリコン膜、酸窒化シリコン膜、アルミナ膜、ハフニウムシリケート膜、酸化ハフニウムシリケート膜またはアルミニウムシリケート膜であり、前記トンネル絶縁膜は、酸化シリコン膜または酸窒化シリコン膜であることを特徴とする請求項8に記載の不揮発性記憶装置。
- 前記電荷蓄積層は、更に前記トンネル絶縁膜上に設けられた電荷蓄積層上に絶縁膜を有し、前記絶縁膜は、酸化シリコン又は酸窒化シリコン膜であることを特徴とする請求項1に記載の不揮発性記憶装置。
- 半導体基板を準備する工程と、前記半導体基板の一方の主面に順にトンネル絶縁膜材料、電荷蓄積層材料およびゲート電極材料を堆積する工程と、前記ゲート電極材料、前記電荷蓄積層材料、前記トンネル絶縁膜材料の一部を除去して前記半導体基板を露出させる工程と、前記半導体基板の一方の主面側に絶縁膜材料を堆積する工程と、前記半導体基板の一方の主面側にゲート電極材料を堆積した後、エッチバックを施して先に形成したゲート電極の側面にゲート電極材料を残留させる工程と、エッチバックされずに基板上に形成されている絶縁膜材料の誘電率を高める工程と、前記半導体基板の一方の主面側にゲート電極材料を堆積する工程と、エッチングによって各ゲート電極の上部を露出させる工程と、所定のゲート電極材料、前記絶縁膜材料、前記電荷蓄積層材料、前記トンネル絶縁膜材料を除去し、前記半導体基板を露出させる工程と、前記半導体基板内に拡散層を形成する工程とを含むことを特徴とする不揮発性記憶装置の製造方法。
- 半導体基板を準備する工程と、前記半導体基板の一方の主面に絶縁膜材料とゲート電極材料とを堆積する工程と、前記絶縁膜材料と前記ゲート電極材料の一部を除去して前記半導体基板を露出させる工程と、酸化によって前記ゲート電極と前記半導体基板とに挟まれた絶縁膜の一部の領域にバーズビークを導入する工程と、前記半導体基板の一方の主面側に順にトンネル絶縁膜材料、電荷蓄積層材料、およびゲート電極材料を堆積させる工程と、エッチングによって各ゲート電極の上部を露出させる工程と、所定のゲート材料、前記絶縁膜材料、前記電荷蓄積層材料、および前記トンネル絶縁膜材料を除去し、前記半導体基板を露出させる工程と、前記半導体基板内に拡散層を形成する工程とを含むことを特徴とする不揮発性記憶装置の製造方法。
- 半導体基板を準備する工程と、前記半導体基板の一方の主面に順にトンネル絶縁膜材料、電荷蓄積層材料およびゲート電極材料を堆積する工程と、所定のゲート電極材料、前記電荷蓄積層材料、前記トンネル絶縁膜材料を除去する工程と、エッチングを連続して行い前記半導体基板材料の一方の主面側を一部除去して前記半導体基板を凸型にする工程と、前記半導体基板の一方の主面側に絶縁膜材料を堆積した後、エッチバックしてゲート電極と凸型の基板の側面に絶縁膜材料を残留させる工程と、前記半導体基板の一方の主面側に絶縁膜材料とゲート電極材料とを堆積した後、エッチングバックして先に形成したゲート電極の側面にゲート電極材料を残留させる工程と、所定のゲート電極材料、前記電荷蓄積層材料、および前記トンネル絶縁膜材料を除去し、前記半導体基板を露出させる工程と、前記半導体基板内に拡散層を形成する工程とを含むことを特徴とする不揮発性記憶装置の製造方法。
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US10971629B2 (en) * | 2018-06-28 | 2021-04-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned unsymmetrical gate (SAUG) FinFET and methods of forming the same |
JP7089967B2 (ja) * | 2018-07-17 | 2022-06-23 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
TWI725767B (zh) * | 2020-03-12 | 2021-04-21 | 力晶積成電子製造股份有限公司 | 記憶體結構及其製造方法 |
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