WO2009087855A1 - 半導体デバイスの製造方法 - Google Patents
半導体デバイスの製造方法 Download PDFInfo
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- WO2009087855A1 WO2009087855A1 PCT/JP2008/072647 JP2008072647W WO2009087855A1 WO 2009087855 A1 WO2009087855 A1 WO 2009087855A1 JP 2008072647 W JP2008072647 W JP 2008072647W WO 2009087855 A1 WO2009087855 A1 WO 2009087855A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 107
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 91
- 238000010030 laminating Methods 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 76
- 238000003776 cleavage reaction Methods 0.000 claims description 15
- 230000007017 scission Effects 0.000 claims description 15
- 238000000149 argon plasma sintering Methods 0.000 claims description 8
- 238000003325 tomography Methods 0.000 claims description 8
- 238000011156 evaluation Methods 0.000 claims description 6
- 238000005259 measurement Methods 0.000 claims description 5
- 238000005136 cathodoluminescence Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 19
- 238000000926 separation method Methods 0.000 abstract 1
- 229910002704 AlGaN Inorganic materials 0.000 description 18
- 230000007547 defect Effects 0.000 description 17
- 229910004298 SiO 2 Inorganic materials 0.000 description 16
- 239000013078 crystal Substances 0.000 description 14
- 238000005530 etching Methods 0.000 description 12
- 238000005253 cladding Methods 0.000 description 9
- 230000003287 optical effect Effects 0.000 description 8
- 238000005498 polishing Methods 0.000 description 6
- 239000006061 abrasive grain Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 239000002002 slurry Substances 0.000 description 5
- 239000002131 composite material Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 2
- 208000012868 Overgrowth Diseases 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 2
- 238000007716 flux method Methods 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 239000011734 sodium Substances 0.000 description 2
- 229910052708 sodium Inorganic materials 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- 238000012935 Averaging Methods 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910010093 LiAlO Inorganic materials 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc oxide Inorganic materials [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a method for manufacturing a semiconductor device.
- a semiconductor device using this GaN substrate is generally manufactured by forming an epitaxial layer on the GaN substrate, forming electrodes on the back side of the substrate and on the epitaxial layer, and then dividing into chips.
- Patent Document 1 there is a method in which a wafer in which a semiconductor element is formed on the main surface of a substrate is attached to a reinforcing plate, then divided into chips by scribing, and then divided into chips by peeling the chip from the reinforcing plate. It is disclosed.
- the defect density of the GaN substrate in particular, the threading dislocation density in the direction perpendicular to the main surface of the GaN substrate, that is, the growth direction of the GaN crystal, for the purpose of reducing the occurrence of defects.
- various contrivances have been made, for example, an ELO (Epitaxial Lateral Overgrowth) method using a SiO 2 mask, and growing a GaN crystal on a rough substrate.
- the present invention has been made in view of the above, and an object of the present invention is to provide a method for manufacturing a semiconductor device in which the defect occurrence rate during chip division is reduced and the yield is improved.
- a semiconductor device manufacturing method measures a dislocation density in a cross section intersecting with a main surface in a GaN substrate, and selects a GaN substrate having the dislocation density equal to or lower than a certain value.
- the method includes a dislocation density evaluation step, and a division step of dividing the functional element portion on the GaN substrate selected in the dislocation density evaluation step and then dividing the functional element portion into chips.
- the inventors have found that the formation of chips, burrs, and cracks after forming an epitaxial layer, electrodes, etc. on a GaN substrate is closely related to the defect density of the GaN substrate, particularly the lateral defect density. Found that there is. Therefore, when measuring the dislocation density in the cross section intersecting with the main surface corresponding to the defect density in the lateral direction, and selecting and using a GaN substrate having the dislocation density below a certain value, when dividing into chips Therefore, the yield of semiconductor devices is improved.
- the cross section is a surface along the cleavage plane of the GaN substrate.
- the dislocation density is preferably measured by the cathodoluminescence method or the light scattering tomography method in the dislocation density evaluation step.
- the yield when a semiconductor device is produced can be further improved as compared with a destructive inspection.
- the certain numerical value is preferably 3.0 ⁇ 10 6 / cm 2 .
- the yield of semiconductor devices is significantly improved. Therefore, it is preferable to select a GaN substrate using the above numerical values.
- the threading dislocation density of the main surface of the GaN substrate is preferably 4.2 ⁇ 10 6 / cm 2 or less.
- a method of manufacturing a semiconductor device in which the defect occurrence rate during chip division is reduced and the yield is improved.
- FIG. 1A is a cross-sectional view of a semiconductor device 110 according to the first embodiment of the present invention.
- FIG. 1B is a cross-sectional view of the semiconductor device 110 according to the first embodiment of the present invention.
- FIG. 2 is a view schematically showing the GaN substrate 1 used for manufacturing the semiconductor device 110 according to the first embodiment of the present invention.
- FIG. 3 is a cross-sectional view of a semiconductor device 120 according to the second embodiment of the present invention.
- FIG. 4 is a cross-sectional view of a semiconductor device 130 according to the third embodiment of the present invention.
- FIG. 5 is a cross-sectional view of a semiconductor device 140 according to the fourth embodiment of the present invention.
- FIG. 6 is a cross-sectional view of a semiconductor device 150 according to the fifth embodiment of the present invention.
- FIG. 7 is a diagram showing the relationship between the dislocation density in the horizontal direction and the chip yield.
- FIG. 8 is a diagram showing the relationship between the main surface threading dislocation density and the device yield.
- FIG. 1A is a cross-sectional view of a semiconductor device 110 according to the first embodiment of the present invention.
- a semiconductor device 110 according to this embodiment includes a base 1A made of a GaN substrate, and an n-type GaN buffer layer 201, an n-type AlGaN cladding layer 202, an n-type GaN optical waveguide on the main surface of the base 1A.
- the semiconductor device 110 functions as an LD (Laser Diode).
- the semiconductor device 110 of this embodiment is manufactured by the following method, for example.
- a layer 205, a p-type AlGaN cap layer 206, a p-type GaN optical waveguide layer 207, a p-type AlGaN cladding layer 208, and a p-type GaN contact layer 209 are sequentially formed.
- a pattern is formed by lithography.
- etching is performed to a predetermined depth in the thickness direction of the p-type AlGaN cladding layer 208 to form the ridge 210.
- an SiO 2 insulating film 211 is formed on the entire surface of the substrate.
- an opening 211a is formed in the SiO 2 insulating film by resist pattern formation and etching, and a p-side electrode 251 is formed only on the main surface of the p-type GaN contact layer 209 by a lift-off method.
- an n-side electrode 252 is formed on the back surface of the GaN substrate 1 and then separated into chips, whereby an LD that is the semiconductor device 110 is obtained.
- the SiO 2 film may be formed by using a vacuum deposition method, a sputtering method, or the like.
- the etching method of the SiO 2 film is RIE (Reactive Ion Etching: reactive ion etching) using an etching gas containing fluorine. ) Method.
- a GaN single crystal is grown on the base substrate.
- the base substrate sapphire, ZnO, SiC, AlN, GaAs, LiAlO, GaAlLiO or GaN is preferably used.
- the method for growing the GaN single crystal on the base substrate is not particularly limited, but a vapor phase such as MOCVD (Metal Organic Chemical Vapor Deposition) method, HVPE (Hydride Vapor Phase Epitaxy) method, etc.
- a growth method or a liquid phase growth method such as a sodium flux method or an ammonothermal method can be used.
- the GaN single crystal grown by these methods is taken out from the base substrate to obtain a GaN substrate made of the GaN single crystal.
- the dislocation density in the cross section intersecting with the main surface of the GaN substrate 1 is measured, A dislocation density evaluation step of selecting a GaN substrate having the dislocation density equal to or lower than a certain value is performed.
- FIG. 2 is a diagram schematically showing the GaN substrate 1 used for manufacturing the semiconductor device of this embodiment.
- FIG. 2 shows a state in which the functional element portion 30 is formed on the main surface of the GaN substrate 1 in accordance with the method for manufacturing the semiconductor device 110 according to the present embodiment.
- a semiconductor layer is formed as the functional element portion 30 on the main surface of the GaN substrate 1 and then divided into chips along the dotted line shown in FIG.
- the dividing direction C1 is a direction along the cleaved surface and the dividing direction C2 is a direction perpendicular to the cleaved surface.
- an OF (orientation flat) surface 10 is provided in a direction along the cleavage plane.
- the OF surface 10 indicates the crystal direction of the GaN crystal in the GaN substrate 1. Normally, if the dividing direction C1 is a direction along the cleavage plane, the division of the GaN substrate 1 in the C1 direction is performed by cleavage.
- the C2 direction which is a direction perpendicular to the cleavage plane, is divided by inserting a scribe line into the GaN substrate 1 and performing braking.
- a GaN substrate can be selected by measuring the dislocation density of the OF surface 10.
- the OF surface since the OF surface may be provided in a direction different from the cleavage surface, in that case, it is preferable to perform measurement after forming a surface along the cleavage surface.
- the dislocation density on the OF surface 10 can be measured by CL (Cathodoluminescence), TEM (Transmission Electron Microscope), light scattering tomography, and etching using a solvent. There is a method of generating and counting (Etch Pits Density: EPD).
- the CL method is a method of measuring the number of dark spots by setting the OF surface 10 perpendicular to the electron gun.
- the OF surface 10 to be observed is preferably formed by cleavage so that the dark spot can be clearly observed.
- the light scattering tomography method is a method in which laser light is made incident from the OF surface 10 and the number and length of dark lines are measured with an optical microscope from the surface on which the epitaxial layer is formed (that is, the main surface of the GaN substrate 1). is there.
- the OF surface 10 is preferably a mirror surface produced by cleavage or the like so that laser light can be easily incident.
- the GaN substrate 1 having a dislocation density of the OF surface 10 of the GaN substrate 1 of 3.0 ⁇ 10 6 / cm 2 or less for manufacturing the semiconductor device 110.
- the inventors have found that the formation of chips, burrs, and cracks after forming an epitaxial layer, electrodes, etc. on a GaN substrate is closely related to the defect density of the GaN substrate, particularly the lateral defect density. Found that there is. Conventionally, in order to reduce the defect density of the GaN substrate, particularly the threading dislocation density, the following method has been employed.
- ELO Epiaxial Lateral Overgrowth: selective lateral growth
- SiO 2 mask SiO 2 mask
- PENDEO method Protaxial Lateral Overgrowth: selective lateral growth
- a substrate is processed to be uneven and then grown so as to fill a concave portion
- dislocations are bent in the horizontal direction.
- the dislocation density penetrating the crystal surface perpendicular to the crystal growth direction has been reduced.
- the dislocations of the crystal grown by such a method are bent in the lateral direction, and observation of a cross section parallel to the crystal growth direction revealed that the dislocation density penetrating the cross section is high. Therefore, the presence of dislocations penetrating through the cross section parallel to the crystal growth direction causes lattice distortion.
- the dislocation density in the cross section intersecting with the main surface of the GaN substrate 1 is measured, and only the GaN substrate 1 having a certain numerical value (3.0 ⁇ 10 6 / cm 2 ) or less is used.
- the yield of the semiconductor device 110 can be further improved.
- a method for measuring the threading dislocation density of the GaN substrate 1 a CL method, a TEM method, a method of generating and counting pits by etching using a solvent (EPD), or the like can be used. Is preferably used.
- each semiconductor device includes a base 1A that is a part of the GaN substrate 1 in order to divide the GaN substrate 1 into a plurality of chips during the semiconductor device manufacturing process.
- FIG. 3 is a cross-sectional view of a semiconductor device 120 according to the second embodiment of the present invention.
- the semiconductor device 120 according to the present embodiment includes an n-type GaN layer 212, an n-type AlGaN layer 213, a light emitting layer 214, a p-type AlGaN layer 215, and a p-type GaN layer on the main surface of the base 1A.
- 216 is formed of a semiconductor layer, a p-side electrode 251 formed on the p-type GaN layer 216, and an n-side electrode 252 formed on the back surface of the base 1A.
- the semiconductor device 110 functions as an LED (Light Emitting Diode).
- the light emitting layer 214 may have, for example, an MQW (Multi-Quantum Well) structure in which GaN layers and In 0.2 Ga 0.8 N layers are alternately stacked.
- MQW Multi-Quantum Well
- the semiconductor device 120 of this embodiment is manufactured by the following method, for example.
- the main surface of the GaN substrate 1 selected by measuring the dislocation density of the OF surface 10 is formed by the MOCVD method on the main surface of the GaN substrate 1, the layer that becomes the n-type GaN layer 212, the layer that becomes the n-type AlGaN layer 213, A layer to be a 3 nm light emitting layer 214 (In 0.2 Ga 0.8 N layer), a layer to be a 60 nm thick p-type AlGaN layer 215 (Al 0.2 Ga 0.8 N layer), a 150 nm thick layer Layers to be the p-type GaN layer 216 are sequentially formed.
- a portion that becomes the p-side electrode 251 having a thickness of 100 nm is formed on the layer that becomes the p-type GaN layer 216.
- the surface of the layer that becomes the p-type GaN layer 205 is bonded to a polishing holder and then polished using a slurry containing SiC abrasive grains having an average particle diameter of 30 ⁇ m.
- An electrode to be an n-side electrode 252 is formed on the back surface of 1A and divided into chips. Thus, an LED that is the semiconductor device 120 is obtained.
- this cross section is obtained. Therefore, it is possible to reduce the occurrence of defects due to chipping or the like when divided into chips along the semiconductor device 120, so that the yield of the semiconductor device 120 (LED) can be improved.
- FIG. 4 is a cross-sectional view of a semiconductor device 130 according to the third embodiment of the present invention.
- the semiconductor device 130 according to this embodiment includes a base 1A and a group III nitride semiconductor layer 221 in which an i-type GaN layer 221a and an i-type AlGaN layer 221b are sequentially stacked on the main surface of the base 1A. And a source electrode 253, a gate electrode 254, and a drain electrode 255 formed on the i-type AlGaN layer 221b.
- the semiconductor device 130 functions as a HEMT (High Electron Mobility Transistor).
- HEMT High Electron Mobility Transistor
- the semiconductor device 130 of the present embodiment is manufactured by the following method, for example.
- a layer to be an i-type GaN layer 221a having a thickness of 3 ⁇ m and a layer to be an i-type AlGaN layer 221b having a thickness of 30 nm are formed by MOCVD. (I-type Al 0.15 Ga 0.85 N layer) is grown.
- a Ti layer (thickness 50 nm) / Al layer (thickness 100 nm) / Ti layer (thickness 20 nm) / Au layer (thickness) is formed on the layer to be the i-type AlGaN layer 221b by photolithography and lift-off methods.
- a gate electrode 254 made of an Au layer having a thickness of 300 nm is further formed. At this time, the gate length is 2 ⁇ m and the gate width is 150 ⁇ m.
- the surface of the p-type GaN layer is attached to a polishing holder, and then the GaN substrate is polished using a slurry containing SiC abrasive grains having an average particle diameter of 30 ⁇ m. . Then, the HEMT which is the semiconductor device 130 is obtained by dividing into chips.
- the dislocation density of the cross section intersecting with the main surface of the GaN substrate 1 is measured, and the semiconductor device 130 (HEMT) is manufactured using a GaN substrate having a dislocation density of a certain value or less. Since the occurrence of defects due to chipping or the like when divided along the chip can be reduced, the yield of the semiconductor device 130 (HEMT) can be improved.
- FIG. 5 is a cross-sectional view of a semiconductor device 140 according to the fourth embodiment of the present invention.
- the semiconductor device 140 according to this embodiment has an n ⁇ -type GaN layer 221 as one or more group III nitride semiconductor layers on the main surface of the base portion 1A, and on the back surface of the base portion 1A.
- An ohmic electrode 256 is provided.
- the semiconductor device 140 includes a Schottky electrode 257 on the main surface of the n ⁇ -type GaN layer 221.
- the semiconductor device 140 functions as a Schottky diode.
- the semiconductor device 140 of this embodiment is manufactured by the following method, for example.
- a layer (electron concentration is 1 ⁇ 10 16 cm ⁇ 3 ) to be the n ⁇ -type GaN layer 221 is grown by MOCVD.
- an ohmic electrode 256 made of a composite layer of Ti layer (thickness 50 nm) / Al layer (thickness 100 nm) / Ti layer (thickness 20 nm) / Au layer (thickness 200 nm) is formed on the back surface of the GaN substrate 1. To do.
- a Schottky electrode 257 made of an Au layer and having a diameter of 200 ⁇ m and a thickness of 300 nm is formed on the n ⁇ -type GaN layer 221 by photolithography and lift-off.
- the surface of the p-type GaN layer is attached to a polishing holder, and then the GaN substrate is polished using a slurry containing SiC abrasive grains having an average particle diameter of 30 ⁇ m. .
- a Schottky diode which is the semiconductor device 140 is obtained by dividing into chips.
- the semiconductor device 140 (Schottky diode) is produced. Since the occurrence of defects due to chipping or the like when divided into chips along the cross section can be reduced, the yield of the semiconductor device 140 (Schottky diode) can be improved.
- FIG. 6 is a cross-sectional view of a semiconductor device 150 according to the fifth embodiment of the present invention.
- the semiconductor device 150 according to this embodiment includes a base 1A, an n ⁇ -type GaN layer 221c formed on the main surface of the substrate 1A, and two left and right positions on the n ⁇ -type GaN layer 221c.
- a group III nitride semiconductor layer 221 including a p-type GaN layer 221d and an n + -type GaN layer 221e formed to be embedded.
- the semiconductor device 150 includes a drain electrode 255 formed on the back surface of the base 1A, a gate electrode 254 formed on the n ⁇ -type GaN layer 221c via an insulating film 258, and two n + -type GaN layers. And a source electrode 253 formed over 221e.
- the semiconductor device 150 functions as a MIS (Metal Insulator Semiconductor) type transistor.
- the semiconductor device 150 of this embodiment is manufactured by the following method, for example.
- a layer (electron concentration is 1 ⁇ 10 16 cm ⁇ 3 ) to be an n ⁇ -type GaN layer 221c having a thickness of 5 ⁇ m is formed by MOCVD.
- the p-type GaN layer 221d and the n + -type GaN layer 221e are sequentially formed in a partial region of the main surface of the layer to be the n ⁇ -type GaN layer by selective ion implantation.
- annealing is performed to activate the implanted ions.
- SiO 2 film by P-CVD (Plasma Enhanced Chemical Vapor Deposition) as an insulating film for MIS
- the above MIS film is formed by photolithography and selective etching using buffered hydrofluoric acid.
- a part of the insulating film is etched, and a Ti layer (thickness 50 nm) / Al layer (thickness 100 nm) / Ti layer (thickness 20 nm) / on top of the layer to be the n + -type GaN layer 221e by a lift-off method.
- a source electrode 253 made of a composite layer of an Au layer (thickness: 200 nm) is formed.
- a portion to be a gate electrode 254 made of an Al layer having a thickness of 300 nm is formed on the MIS insulating film 258 by photolithography and lift-off.
- the surface of the p-type GaN layer is attached to a polishing holder, and then the GaN substrate is polished using a slurry containing SiC abrasive grains having an average particle diameter of 30 ⁇ m. Divide into chips. Finally, a drain electrode 255 composed of a composite layer of Ti layer (thickness 50 nm) / Al layer (thickness 100 nm) / Ti layer (thickness 20 nm) / Au layer (thickness 200 nm) is formed on the entire back surface of the GaN substrate 1. By forming the MIS transistor, the semiconductor device 150 is obtained.
- the semiconductor device 150 (MIS type transistor) is manufactured. Since the occurrence of defects due to chipping or the like when divided into chips along the cross section can be reduced, the yield of the semiconductor device 150 (MIS type transistor) can be improved.
- Example 1 As the GaN substrate used in Example 1, a GaN substrate having a thickness of 450 ⁇ m and having an OF surface cleaved by the (1-100) plane having a (0001) plane as the main surface was prepared.
- the threading dislocation density (main surface threading dislocation density) on the (0001) plane of this GaN substrate was measured by a CL apparatus attached to a SEM (Scanning Electron Microscope), and was 4.2 ⁇ 10 6 / cm 2 . there were.
- the dislocation density (lateral dislocation density) on the OF plane was measured by the CL method and found to be 3.0 ⁇ 10 6 / cm 2 .
- the dislocation density was calculated by counting and averaging the number of dark spots in five regions having an arbitrarily selected size of 100 ⁇ m ⁇ 100 ⁇ m.
- an LD which is the semiconductor device 110 according to the first embodiment of the present invention, was produced as Example 1.
- the detailed manufacturing method is as follows.
- An n-type GaN buffer layer having a thickness of 0.05 ⁇ m, doped with Si as a group III nitride semiconductor layer by MOCVD on the main surface of the GaN substrate;
- An active layer having a multiple quantum well structure in which the N layer is repeated five times,
- a p-type Al 0.2 Ga 0.8 N cap layer having a thickness of 10 nm doped with magnesium (Mg);
- a ridge extending in the ⁇ 1-100> direction was formed by etching to a predetermined depth in the thickness direction of the p-type AlGaN cladding layer by the RIE method using this SiO 2 film as a mask.
- the width of this ridge is 2 ⁇ m. Chlorine-based gas was used as the etching gas for this RIE.
- a SiO 2 insulating film having a thickness of 0.3 ⁇ m was formed on the entire surface of the substrate by CVD. Subsequently, a resist pattern covering the main surface of the insulating film in a region excluding the p-side electrode formation region was formed by lithography. The opening was formed by etching the insulating film using this resist pattern as a mask.
- a p-side electrode is formed on the entire surface of the substrate by vacuum deposition with the resist pattern remaining, and then removed together with the p-side electrode formed on the resist pattern, and only on the p-type GaN contact layer. Side electrodes were formed.
- the surface of the p-type GaN layer is attached to a polishing holder, and then the GaN substrate has a thickness of 450 ⁇ m using a slurry containing SiC abrasive grains having an average particle diameter of 2.5 ⁇ m. Polishing was performed until 130 ⁇ m.
- n-side electrode was formed on the back surface of the GaN substrate. Thereafter, the GaN substrate on which the laser structure was formed as described above was scribed along the contour line of the element region, and the GaN substrate was cleaved and divided into bars. Next, a semiconductor device (LD) of Example 1 was obtained by putting a scribe line in a direction perpendicular to the cleavage direction, performing braking, and dividing the chip into chips.
- LD semiconductor device
- the semiconductor device obtained by the above method was evaluated by the following method. First, as the chip yield, the chip main surface was observed with a microscope to confirm whether there was any chipping or cracking. Furthermore, the cleaved end face was measured with an AFM (Atomic Force Microscope), and pass / fail was judged. As a result, the pass rate was 79%.
- an LD life test was conducted.
- the test conditions were an ambient temperature of 70 ° C., an optical output of 30 mW, and the test was accepted if the time until the current value at the time of driving constant light output increased to 1.2 times was 3000 hours or more. As a result, the pass rate was 64%.
- the product of the above chip yield and device yield was determined as the total yield. What is the total yield of the semiconductor device of Example 1? It was 50.6%.
- Examples 2 to 7 and Examples 8 to 10 are the same as Example 1 except that the GaN substrates are different. That is, nine GaN substrates having a thickness of 450 ⁇ m having an OF surface cleaved by the (0001) plane and the (1-100) plane were prepared, and the (0001) plane (main surface) of each GaN substrate was prepared. ) And the dislocation density in the OF plane (transverse dislocation density) were measured by the CL method. As a result, those having a threading dislocation density of 4.2 ⁇ 10 6 / cm 2 or less and a lateral dislocation density of 3.0 ⁇ 10 6 / cm 2 or less were designated as Examples 2 to 7, respectively. Examples with a value larger than 10 6 / cm 2 were designated as Examples 8 to 10, respectively. Using these GaN substrates, a semiconductor device (LD) was produced in the same manner as in Example 1.
- LD semiconductor device
- Table 1 shows the results of Examples 1 to 10. Compared to Examples 8 to 10, Examples 1 to 7 had higher chip yields, so the total yield was also higher.
- Examples 11 and 12 are the same as Example 1 except that the main surface direction of the GaN substrate is different and the dislocation density is different. That is, two GaN substrates having a thickness of 450 ⁇ m and having an OF surface cleaved by the (1-100) plane and 35 ° off from the (0001) plane in the ⁇ 11-20> direction are prepared. The threading dislocation density in the (0001) plane and the dislocation density (lateral dislocation density) in the OF plane of each GaN substrate were measured by the CL method.
- Example 11 a threading dislocation density greater than 4.2 ⁇ 10 6 / cm 2 and a lateral dislocation density greater than 3.0 ⁇ 10 6 / cm 2 was taken as Example 11, and the threading dislocation density was 4.2 ⁇ .
- a semiconductor device (LD) was produced in the same manner as in Example 1.
- Table 2 shows the results of Examples 11 and 12.
- Example 8 since the chip yield was high, the total yield was also high. Thus, it was confirmed that the same result can be obtained even when the principal planes have different plane orientations.
- FIG. 7 is a diagram showing the relationship between the dislocation density in the horizontal direction and the chip yield.
- the horizontal axis shows the dislocation density in the horizontal direction, and the vertical axis shows the chip yield.
- FIG. 8 is a diagram showing the relationship between the main surface threading dislocation density and the device yield.
- the horizontal axis shows the main surface threading dislocation density, and the vertical axis shows the device yield.
- the dislocation density of the GaN substrate affects the chip yield and the device yield of the semiconductor device.
- the chip yield and device yield of semiconductor devices depend on the lateral dislocation density and main surface threading dislocation density of the GaN substrate, and include vapor phase growth methods such as MOCVD method and HVPE method, sodium flux method or ammono method. It was found that it does not depend on the growth method such as the liquid phase growth method such as the thermal method. Therefore, by providing a certain threshold value in advance and manufacturing a semiconductor device using only a GaN substrate having a dislocation density smaller than the threshold value, the yield can be improved.
- the constant threshold value is “a threading dislocation density of 4.2 ⁇ 10 6 / cm 2 or less and a lateral dislocation, as in the standard (threshold value) that distinguishes Examples 1 to 7 and Examples 8 to 10. It has become clear from the above examples that the yield of the semiconductor device can be improved by setting the density to be 3.0 ⁇ 10 6 / cm 2 or less.
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Abstract
Description
1A…基部
10…OF面
30…機能素子部
110…半導体デバイス(LD)
120…半導体デバイス(LED)
130…半導体デバイス(HEMT)
140…半導体デバイス(ショットキーダイオード)
150…半導体デバイス(MIS型トランジスタ)
図1Aは、本発明の第1実施形態に係る半導体デバイス110の断面図である。図1Aに示すように、本実施形態に係る半導体デバイス110は、GaN基板からなる基部1Aと、基部1Aの主面に、n型GaNバッファ層201、n型AlGaNクラッド層202、n型GaN光導波層203、活性層204、アンドープInGaN劣化防止層205、p型AlGaNキャップ層206、p型GaN光導波層207、p型AlGaNクラッド層208、p型GaNコンタクト層209を順次形成した半導体層と、p型GaNコンタクト層209の上部に形成したp側電極251と、基部1Aの裏面に形成したn側電極252と、p型AlGaNクラッド層208を覆うSiO2絶縁膜211と、からなる。この半導体デバイス110は、LD(Laser Diode:レーザダイオード)として、機能する。
したがって、結晶成長方向と平行な断面を貫通する転位が存在することで格子歪が発生し、この断面(例えば、へき開面)に沿ってチップ状に分割したときに、割断面の乱れが発生し、欠け等が発生していることが判明した。また、この欠け等の発生が、半導体デバイスの歩留まりの低下を引き起こしていた。
図3は、本発明の第2実施形態に係る半導体デバイス120の断面図である。図3に示すように、本実施形態に係る半導体デバイス120は、基部1Aの主面に、n型GaN層212、n型AlGaN層213、発光層214、p型AlGaN層215、p型GaN層216を順次形成した半導体層と、p型GaN層216上に形成したp側電極251、基部1Aの裏面上に形成したn側電極252と、からなる。この半導体デバイス110は、LED(Light Emitting Diode:発光ダイオード)として機能する。なお、発光層214は、例えばGaN層とIn0.2Ga0.8N層とを交互に積層したMQW(Multi-QuantumWell:多重量子井戸)構造としてもよい。
図4は、本発明の第3実施形態に係る半導体デバイス130の断面図である。図4に示すように、本実施形態に係る半導体デバイス130は、基部1Aと、基部1Aの主面にi型GaN層221a、i型AlGaN層221bが順次積層されたIII族窒化物半導体層221と、i型AlGaN層221b上に形成されたソース電極253、ゲート電極254及びドレイン電極255と、からなる。この半導体デバイス130は、HEMT(HighElectron Mobility Transistor:高電子移動度トランジスタ)として機能する。
図5は、本発明の第4実施形態に係る半導体デバイス140の断面図である。図5に示すように、本実施形態に係る半導体デバイス140は、基部1Aの主面に、1層以上のIII族窒化物半導体層としてn-型GaN層221を有し、基部1Aの裏面にオーミック電極256を備える。また、半導体デバイス140は、n-型GaN層221の主面にショットキー電極257を備える。この半導体デバイス140は、ショットキーダイオードとして機能する。
図6は、本発明の第5実施形態に係る半導体デバイス150の断面図である。図6に示すように、本実施形態に係る半導体デバイス150は、基部1Aと、基板1Aの主面に形成されたn-型GaN層221c、n-型GaN層221c上の左右の二箇所に埋め込まれるように形成されたp型GaN層221d及びn+型GaN層221eからなるIII族窒化物半導体層221と、を有する。さらに、半導体デバイス150は、基部1Aの裏面に形成されたドレイン電極255と、n-型GaN層221c上に絶縁膜258を介して形成されたゲート電極254と、二箇所のn+型GaN層221e上に形成されたソース電極253と、を備える。この半導体デバイス150はMIS(MetalInsulator Semiconductor:金属-絶縁体-半導体)型トランジスタとして機能する。
実施例1に用いるGaN基板として、主面が(0001)面であり、(1-100)面でへき開したOF面を有する厚み450μmのGaN基板を準備した。このGaN基板の(0001)面における貫通転位密度(主面貫通転位密度)をSEM(Scanning ElectronMicroscope:走査型電子顕微鏡)に装着したCL装置により測定したところ、4.2×106/cm2であった。一方、OF面における転位密度(横方向転位密度)をCL法により測定したところ、3.0×106/cm2であった。転位密度は、任意に選択した大きさが100μm×100μmである5箇所の領域の暗点数をカウントし、平均することで算出した。
Siをドープした、厚さが0.05μmのn型GaNバッファ層、
Siをドープした、厚さが1.0μmのn型Al0.08Ga0.92Nクラッド層、
Siをドープした、厚さが0.1μmのn型GaN光導波層、アンドープの厚さ3nmのIn0.15Ga0.85N層と、厚さが6nmのIn0.03Ga0.97N層とを5回繰り返した多重量子井戸構造の活性層、
アンドープの、厚さが0.01μmのAl0.2Ga0.8N劣化防止層、
マグネシウム(Mg)をドープした、厚さが10nmのp型Al0.2Ga0.8Nキャップ層、
Mgをドープした、厚さが0.1μmのp型GaN光導波層、
Mgをドープした、厚さが0.3μmのp型Al0.08Ga0.92Nクラッド層、及び
Mgをドープした、p型GaNコンタクト層
を順次エピタキシャル成長させた後、GaN基板をMOCVD装置から取り出した。続いて、p型GaNコンタクト層の全面に厚さが0.1μmのSiO2膜をCVD法で形成した後、このSiO2膜上にリソグラフィによりリッジ部の形状に対応したパターンを形成した。
さらに、AFM(Atomic Force Microscope:原子間力顕微鏡)でへき開端面を測定し、合否を判定した。この結果、合格率は79%であった。
実施例2~7及び実施例8~10は、GaN基板がそれぞれ異なるほかは、実施例1と同様である。すなわち、主面が(0001)面であり、(1-100)面でへき開したOF面を有する厚さが450μmのGaN基板を9枚準備し、それぞれのGaN基板の(0001)面(主面)における貫通転位密度及びOF面における転位密度(横方向転位密度)をCL法により測定した。その結果、貫通転位密度が4.2×106/cm2以下であり、横方向転位密度が3.0×106/cm2以下のものをそれぞれ実施例2~7とし、3.0×106/cm2より大きいものをそれぞれ実施例8~10とした。これらのGaN基板を用いて実施例1と同様の方法で半導体デバイス(LD)を作製した。
実施例11、12は、GaN基板の主面方向がそれぞれ異なり、転位密度が異なる点を除いて、実施例1と同様である。すなわち、主面が(0001)面から<11-20>方向へ35°オフした面であり、(1-100)面でへき開したOF面を有する厚さが450μmのGaN基板を2枚準備し、それぞれのGaN基板の(0001)面における貫通転位密度及びOF面における転位密度(横方向転位密度)をCL法により測定した。その結果、貫通転位密度が4.2×106/cm2より大きく、横方向転位密度が3.0×106/cm2より大きいものを実施例11とし、貫通転位密度が4.2×106/cm2以下であり、横方向転位密度が3.0×106/cm2以下のものを実施例12とした。これらのGaN基板を用いて実施例1と同様の方法で半導体デバイス(LD)を作製した。
Claims (5)
- GaN基板中の主面と交差する断面の転位密度を測定し、当該転位密度が一定の数値以下であるGaN基板を選択する転位密度評価工程と、
前記転位密度評価工程で選択された前記GaN基板上に機能素子部を積層した後、チップ状に分割する分割工程と、
を有することを特徴とする半導体デバイスの製造方法。 - 前記断面は、前記GaN基板のへき開面に沿った面であることを特徴とする請求項1記載の半導体デバイスの製造方法。
- 前記転位密度評価工程の際に、
前記転位密度の測定をカソードルミネッセンス法又は光散乱トモグラフィ法によって行うことを特徴とする請求項1又は2記載の半導体デバイスの製造方法。 - 前記一定の数値は、3.0×106/cm2であることを特徴とする請求項1~3のいずれか一項に記載の半導体デバイスの製造方法。
- 前記GaN基板の主面の貫通転位密度は、4.2×106/cm2以下であることを特徴とする請求項1~4のいずれか一項に記載の半導体デバイスの製造方法。
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US10018579B1 (en) | 2015-02-18 | 2018-07-10 | Kla-Tencor Corporation | System and method for cathodoluminescence-based semiconductor wafer defect inspection |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001196700A (ja) * | 1999-10-29 | 2001-07-19 | Nichia Chem Ind Ltd | 窒化物半導体の成長方法及び窒化物半導体素子 |
JP2002029897A (ja) * | 2000-07-10 | 2002-01-29 | Sumitomo Electric Ind Ltd | 単結晶GaN基板の製造方法と単結晶GaN基板 |
JP2002329684A (ja) | 2001-04-27 | 2002-11-15 | Matsushita Electric Ind Co Ltd | 窒化物半導体チップ及びその製造方法 |
JP2003051636A (ja) * | 2001-08-06 | 2003-02-21 | Sony Corp | 半導体素子及びその製造方法 |
JP2006332240A (ja) * | 2005-05-25 | 2006-12-07 | Sanyo Electric Co Ltd | 窒化物半導体発光素子の製造方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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JP2002029897A (ja) * | 2000-07-10 | 2002-01-29 | Sumitomo Electric Ind Ltd | 単結晶GaN基板の製造方法と単結晶GaN基板 |
JP2002329684A (ja) | 2001-04-27 | 2002-11-15 | Matsushita Electric Ind Co Ltd | 窒化物半導体チップ及びその製造方法 |
JP2003051636A (ja) * | 2001-08-06 | 2003-02-21 | Sony Corp | 半導体素子及びその製造方法 |
JP2006332240A (ja) * | 2005-05-25 | 2006-12-07 | Sanyo Electric Co Ltd | 窒化物半導体発光素子の製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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