WO2009061642A1

WO2009061642A1 - Improvements in carbon nanotube growth

Info

Publication number: WO2009061642A1
Application number: PCT/US2008/081495
Authority: WO
Inventors: Ce Ma
Original assignee: Linde North America, Inc.
Priority date: 2007-11-07
Filing date: 2008-10-29
Publication date: 2009-05-14
Also published as: TW200936498A

Abstract

Improved techniques for the growth of carbon nanotubes are disclosed. These methods include controlling the size of semiconducting single-wall carbon nanotubes by controlling the size of the catalytic particles on which the carbon nanotubes are grown. Further, methods of growing multi-wall carbon nanotubes at low temperatures for use as interconnects are disclosed.

Description

IMPROVEMENTS IN CARBON NANOTUBE GROWTH

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority from U.S. Provisional Patent Application Serial No. 60/986,086 filed November 7, 2007.

FIELD OF THE INVENTION

[0002] The present invention relates to improvements in techniques for the growth of carbon nanotubes.

BACKGROUND OF THE INVENTION

[0003] Carbon nanotubes (CNT) have shown great potential in feature electronics since their discovery in 1991. CNT comprise nanometer diameter tubes that resemble rolled-up crystalline graphite sheets. CNT materials can either single-wall CNT (SWCNT) or multi-wall CNT (MWCNT) and composed of either metallic CNT or semiconducting CNT. CNT materials can have very high electrical and thermal conductivity and mechanical strength. The use of semiconducting CNT to replace silicon channels and metallic CNT to replace metal wiring in semiconductor chips is an important research area with many leading semiconductor companies identifying CNT as a top candidate to replace silicon in transistors as early as 2013.

[0004] CNT materials can be synthesized using electric discharge, laser ablation, flaming synthesis and chemical vapor deposition (CVD) techniques, using metal catalyst particles and carbon precursors as starting materials. Top growth from anchored surface catalytic particles using CVD methods provides the most promise as an approach for electronics device fabrication as it allows for both pattern and direction control. However, there are significant challenges in achieving CNT semiconductor devices. In particular, it is difficult to achieve controlled growth of target CNT to have unique electronics properties. This is especially true for the front- end-process steps. Further, it is difficult to carry out CNT growth at temperatures below the thermal budget of the deposition wafer, especially during the interconnect steps.

[0005] Therefore, there remains a need in the art for improvements to growth techniques for carbon nano tubes.

SUMMARY OF THE PRESENT INVENTION

[0006] The present invention provides improved techniques for the growth of CNT that address the challenges noted above.

[0007] A first embodiment of the present invention addresses problems associated with achieving growth of size selected semiconducting SWCNT for transistor channels. The ability to control the growth size of SWCNT is extremely important, because without accurate size control, the SWCNT can grow in various proportions, and therefore exhibit different properties, e.g. one third metallic and two thirds semi- conductive properties, as well as a variety of band-gaps. Because the growth depends on the roll-up vector of the graphite sheet making up the SWCNT, growth can result in a number of different diameters that exhibit different electronics properties.

[0008] The present invention provides a method to carefully control the size of the starting catalytic particles which leads to unique sized SWCNT being grown onto the controlled nano -template. According to the present invention, by fixing the size of the catalytic particles, it is possible to grow selected band-gap semiconducting CNT materials that are tailored and suitable for particular semiconducting needs. The method according to the present invention overcomes disadvantages associated with known growth methods that use catalytic particles with sizes that are either too large (>10nm) or that are poly-dispersed and therefore result in the growth of different sized CNT on a single catalytic particle.

[0009] The preferential growth on CNT is accomplished according to the present invention by using patterned hydrophobic/hydrophilic (e.g. Si/SiO₂) or non- metallic/metallic (e.g. Si or oxide or nitride/ Au) wafer chips as the starting material. A self-assembled-monolayer (SAM) is then selectively deposited onto either the hydrophilic (e.g. SiO₂) or metallic (e.g. Au) pads. Once the SAM is in place, a single monolayer of metal (e.g. Nickel) is then deposited onto the function heads of the SAM using a deposition method, such as atomic layer deposition (ALD), or by wet dip. The metal monolayer is then thermally treated in an oxidizing environment to remove carbon content and to form metal oxide particles on the hydrophilic or metallic pads. The density of the SAM layer can be controlled by controlling the concentration of the SAM in the deposition solution which allows the size of metal oxide particles to be controlled and reduced by 100' s to 1000's of times as compared with starting materials used in the prior art. These controlled size and uniform nano or sub-nano metal oxide particles can be then converted into active metallic catalysts by an H₂ annealing process.

[0010] In one alternative to the above, the SAM layer can also be used as a metal deposition mask rather than as a metal deposition template, so that unprotected surface areas may be deposited with metallic layers through the openings in the SAM layer mask. In addition, the present invention contemplates other nano-template methods can be used, such as micro-contact SAM patterning in combination with ALD and nano-porous materials, as well as ALD and self-assembled mono-spheres.

[0011] A second aspect of the present invention addresses the need for low temperature growth of metallic CNT for use as interconnects. Metallic SWCNT and MWCNT are advantageous candidates for use as interconnect wiring for silicon or non-silicon based transistor devices because these CNT materials allow electrons to flow without ballistic scattering. MWCNT have bee shown to be mostly metallic and therefore are particularly useful as interconnect materials. However, because typical CVD deposition temperatures for CNT are in the range of 700 -1000⁰C, with the lowest reported temperature being about 55O⁰C, this can cause problems for electronic device, particularly semiconductor device manufacturing. This is because processing at these temperatures can be detrimental to front-end processing steps carried out before the CNT growth, e.g. transistor doping and substrate material thermal budget limits. The preferred interconnect process temperature is 400⁰C or less.

[0012] To achieve CNT growth at temperatures of 400⁰C or less, the present invention utilizes low temperature performance catalysts or carbon precursors. When using carbon precursors, a gas phase catalytic dissociation of the carbon precursor lowers the energy barrier of CNT formation while preserving C₂ type building blocks and a catalytic screen made of transition metal wires resistively heats and activates the carbon precursor to enable the low substrate deposition temperature. Bimetal catalysts with low eutectic temperatures may also be used. The use of either gas phase or solid phase catalytic reactions is possible in the present invention to achieve low temperature growth of MWCNT using larger catalytic particles and higher carbon flux.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is graph showing the energy band gap of SWCNT plotted against tube diameter.

[0014] Figure 2 is a schematic drawing showing a processing step according to one embodiment of the present invention.

[0015] Figure 3 is a schematic drawing showing a processing step according to a further embodiment of the present invention. [0016] Figure 4 is a schematic drawing showing another processing step according to one embodiment of the present invention.

[0017] Figure 5 is a schematic drawing showing another processing step according to one further embodiment of the present invention.

[0018] Figure 6 is a schematic drawing showing further processing steps according to one embodiment of the present invention.

[0019] Figure 7 is a schematic drawing showing a general processing arrangement according to another aspect of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0020] As noted above, a first embodiment of the present invention relates to the growth of size selected semiconducting SWCNT for transistor channels. The chiral index of SWCNT determine its electrical properties, including electrical conductivity. In addition, the chiral index is related to the unique structured size of SWCNT. Figure 1 shows the energy band gap of SWCNT plotted against tube diameter. SWCNT made by prior art methods have mixed conductivity, however, as shown in Figure 1, there are certain windows of tube diameters where pure semiconducting SWCNT can be obtained having specific band gaps. In accordance with the present invention, by controlling SWCNT sizes through the control of the size of the catalytic surface area on which the SWCNT is grown, it is possible to grow SWCNT having specific diameters and thereby to utilize these pure semiconducting properties.

[0021] Figure 1 in particular shows the energy band-gap, Eg, for all diameters of SWCNT from 3 A to 12 A. Metallic SWCNT (represented by the closed circles) show zero Eg, while semiconductive SWCNT (represented by open squares) have non-zero Eg. Selected growth windows are labeled from A to G to identify pure semiconductive SWCNT growth, wherein each window has a unique band gap range. Windows C and F or of particular interest because they represent Si-like or Ge-like band gap SWCNT respectively.

[0022] The preferred growth windows of pure semiconducting SWCNT are further shown in Table 1 below. By controlling the diameter of SWCNT in accordance with the methods of the present invention, it is possible to obtain unique semiconducting SWCNT. The prior art methods of growing SWCNT results in diameters of more than 10 A because of the catalytic particle size used. However, as can be seen Figure 1 and Table 1, SWCNT having diameters as small as 3 A can theoretically be grown. When catalytic particles are small enough, e.g., less than 12 A, SWCNT may grow around the particle in either tip growth (floating particle) or bottom growth (fixed surface) configurations. Therefore in accordance with the present invention, specific sizes of SWCNT can be produced by using a mono- dispersed small catalytic surfaces or particles. For example, as shown in Table 1, SWCNT having a diameter in the window C of 6.4A to 6.8 A only chiral indexes of only (8,1) and (7,2) and therefore exhibit Si-like band gaps from 1.06 eV to 1.1 eV.

[0023] The method for growing size selected semiconducting SWCNT for transistor channels in accordance with the present invention will be described below with reference to Figures 2 through 6. For this discussion, specific materials will be referred to, but the present invention is no so limited as will be discussed in more detail below. Figure 2 shows a starting substrate for SWCNT growth comprising a silicon substrate 10, and a patterned SiO₂ layer formed into pads 20, as depicted. The patterned SiO₂ pads 20, are the sites for later CNT growth and have a size X and spacing L, where X can be 100 nm or less and L can be equal to or greater than X. Alternatively, as shown in Figure 3, the CNT growth sites can be SiO₂ wells formed from an SOI wafer, having an underlying silicon substrate 110, an SiO₂ layer 120 and a patterned silicon layer 130 exposing the SiO₂ growth sites. The wells can have a size X of 100 nm or less and spacing L equal to or greater than X. The well size is preferably smaller than the desired CNT diameter to account for growth of the CNT layers over the silicon pads.

[0024] Once the patterned growth areas, e.g. SiO₂ pads or wells, are formed, the wafer is cleaned under cleanroom conditions to remove surface contamination. Such cleaning can also be done by plasma treatment or vacuum annealing of the patterned surface. A SAM layer is then deposited onto the CNT growth sites. There are two types of SAM layers generally used for electronics applications. The first is an alkanethiol monolayer that is applied to gold substrates. The second is a SAM layer that attaches to SiO₂/Si surfaces and has a general chemical structure of R(CH₂)_πSiX₃, where R is a surface group, (CH₂)_n is an alkyl inter-chain, and SiX₃ is the head group that reacts with the SiO₂/Si substrate, with X being Cl, OCH₃, OC₂Hs, or other suitable compounds having hydrogen terminations that can react with surface hydroxide groups or oxygen sites on the SiO₂ surface. SAM layers are generally deposited using two different methods. Small SAM layers are deposited onto the surface via vapor exposure processes, while larger SAM layers may be deposited by solution dipping methods, wherein the standard solution is an alkane solvent (e.g. n- Hexane) of about 0.001 M concentration.

[0025] Figure 4 shows a SAM layer 30, comprised of SAM molecules having a function head of an alkyl chain and one or more surface groups in place on the SiO₂ pads 20, This SAM layer 30, can be formed by dip patterning in a SAM solution so that the function head reacts with the SiO₂ surface sites. For example, a SAM having -SiCl₃ end groups can be chemically absorbed onto the SiO₂ surface through reaction between SiCl₃ head group and surface OH sites or oxygen sites with H terminations. Figure 4 also shows surface groups linked by alkyl chains. Similarly, Figure 5 shows a SAM layer 140, deposited with the wells and onto the SiO₂ layer 120.

[0026] After the SAM has been deposited, catalytic metal molecules, e.g. transition metal or rare-earth metal, are deposited onto the surface group R of the SAM layer by ALD or solution dipping processes. The surface group R of the SAM layer can be any group, such as -OH, -COOH, C=C, etc., that allows bonding to the catalytic metal. The use of ALD methods to deposit the catalytic metal provides for precision digital control of the catalytic metal layer thickness. A catalytic bi-metallic layer is preferred, in particular a bi-metallic layer that contains mostly transition metals, such as Ni, Co, Fe, Rd, Rh or Ru, with small amounts of rare-earth or lanthanide metals, such as Y, Ti or La. For such deposits an ALD metal precursor with water as co-reactant may be selected. Alternatively, metal precursors can be dissolved in organic solvents, such as MCl_x or bi-metal mixtures and the catalytic metal can be deposited by a solution dip coating process.

[0027] Figure 6 shows a the process according to the present invention of forming the catalytic metal dots and the CNT growth thereon, hi particular, Step A of Figure 6 shows the deposition of the metal or metal oxide, preferably a bi-metallic layer 40, onto the SAM layer 30, and SiO₂ surface 20. Step B of Figure 6 comprises a thermal annealing to remove organic chains and form a nano or sub-nano metal oxide dot 42. Step C of Figure 6 comprises thermal reduction in a hydrogen environment to produce active catalytic dot 44. Step D of Figure 6 shows SWCNT 50, growth that is size controlled according to the size of the catalytic dot 44. By performing this method according to the present invention, it is possible to reduce the size of the catalytic metal dots by a hundred fold from the original pattern size and create growth sites much smaller than could be accomplished in prior art methods. This is in part because the size of sintered dots is proportional to the density of the SAM layer and to the deposited metal layer thickness which are both precisely controlled in the present invention. [0028] The discussion above used examples of forming catalytic metals for SWCNT on SiO₂ surfaces, e.g. pads or wells. However, the present invention is applicable to other substrates and surfaces as well, including hydrophobic/hydrophilic, metal/non-metal, or dielectric/metal layered starting substrates. The surface material can be SiO2, Si, Au, or other dielectric and metallic surfaces.

[0029] The SAM layers described above have end groups that are appropriate for bonding to SiO₂. When depositing SAM layers onto metal surfaces, the surface group R of the SAM is typically an -S end groups that can be chemically absorbed onto the metallic surface. Alternatively, the methodology described above can be applied to metal and non-metal surfaces using different head groups of SAM. Some examples of head groups appropriate for different surfaces are shown below in Table 2.

[0030] Further, in the above examples, the SAM layer was used as a deposition template, but can alternatively be used as a mask layer, wherein inert surface group, such as -CH3, are used to mask off patterned areas during metal layer deposition.

[0031] Moreover, the above examples focused on the use of a SAM layer for formation of precisely controlled catalytic dots. Other methods of forming nano or sub-nano catalytic surfaces can also be used, such as micro -contact printing SAM, copolymer templates, opal sphere templates, or nano-porous templates, hi micro-contact printing methods, the SAM layer can be deposited onto a blanket substrate surface without lithographic pattering A molded PDMS stamp may have resolution in the 100 nm range and after micro-contact printing, similar metal and CNT processes as discussed above can be carried out. For co-polymer and porous templates, additional size reduction from nano-sized pores to sub-nano sized pores by using ALD deposition layers can be achieved. An opal sphere template is self-assembled onto the substrate, although the size of the opal is typically in the range of 10-1000 nm. By using an ALD film, such as Al₂O₃ coated between and around the opal, polishing off the top half of the opal and etching off the bottom half, a bowl shaped reverse opal with exposed contact points to a metallic surface is produced, wherein the metallic surface can be a catalytic surface, such as Ni, Co or Fe.

[0032] The present invention provides methods for formation of SWCNT transistors having predetermined unique band gaps and properties for use in future electronics devices.

[0033] The present invention also provides methods for the low temperature growth of metallic CNT for use as interconnects. In order to grow metallic CNT for interconnects and replace the current copper wire used, the thermal budget of the substrate is a key parameter because of the temperature limitations on transistor and low-k dielectric materials, hi this aspect of the present invention, MWCNT that are mostly metallic are the focus with the outcome being growth of MWCNT at temperatures of 400⁰C or less, hi this aspect of the present invention, the control of catalytic particle sizes is not as critical and therefore, many standard methods of producing catalytic particles in the range of 1-10 nm size can be used. Rather, the critical portion of this aspect of the present invention is the gas phase chemistry, the gas phase activation and the metal catalytic particle performance at low surface temperatures.

[0034] The growth surface can be prepared in the same way noted above using patterned templates, but as noted, since catalyst particle size is not as critical, conventional methods for producing larger metallic particles without tight control over their size can also be used. For example, a thin layer of metallic or alloy film, such as Ni, can be deposited using ALD, sputtering or evaporating methods to produce either metal or metal oxide layers having a typical layer thickness of a few nm. Catalytic particles are formed after thermal processing of the deposited metal film. The size of the particle is determined by the metal film thickness and the materials of both metal and substrate layer. Metal particles can also be formed from solution-based processes wherein the substrate can be coated with either a metal precursor from solution or metallic particles with predetermined size distribution. Active catalytic particles are generated by thermal processing.

[0035] The low temperature growth of CNT according to the present invention is realized by using low temperature catalytic metal or metal alloys, hi particular, according to one embodiment of the present invention, a carbon precursor is dissolved onto a transition metal surface. The diffusion rate of carbon in melting metal is very high and there is no stable carbide phase but instead a metastable phase, e.g. Ni₃C, and therefore, the carbon advantageously saturates the melting metal surface. To reduce the surface energy, the use of a graphite sheet is preferable. Then by continuing to add carbon building blocks, CNT growth occurs on the catalytic surface. The addition of minor amounts of rare earths or Lanthanides can help to dissolve carbon by forming carbide phases. Further, the addition of some elements, such as sulfur, allows for the reduction of the eutectic temperature of the catalytic alloy to be reduced from that of a single metal-carbon mixture.

[0036] The present invention particularly relies on the thermodynamics of carbon- metal alloy systems to provide the low melting temperature compositions. Catalytic alloys that contain mainly transition metals, such as Ni, Co, Fe, Ru, Rh or Pd, with minor components of other metals and non-metals are preferred. Other metals can be chooses from Y, Ti or La, while the non-metals can be Si, P or S. All of these possible additions can help to form low temperature eutectic points. The use of supporting dielectric/conductive materials for metallic catalysts is also important for promoting CNT growth.

[0037] More particularly, the present invention, controls the gas phase chemistry and activation by using highly reactive carbon precursors, such as acetylene C₂H₂, ethylene C₂H₄ or unsaturated C_nH_1n (2<n<12; 2<m<12) compounds as CVD precursors for the process. In some cases, alcohol and CO based chemistries can also be applied. The C_nH_m precursors contain the C₂-type building blocks necessary for CNT growth. Hydrogen gas may be used as a dilution and cleaning gas to keep catalytic surfaces active. Trace of oxidants, such as H₂O, can held to suppress non- CNT carbon growth. The dissociation energies of several carbon precursors and reactions useful in the processes of the present invention are shown in Table 3.

[0038] Reduction of the substrate deposition temperature can also be aided by pre- activation of the carbon precursor. The substrate deposition temperature reduction is achieved in part because pre-activation of the carbon precursor allows sharing of the thermal burden from the substrate. However, traditional plasma enhanced CVD (PECVD) can dissociate the carbon precursor completely and generate surface bombardment by generated ions. Therefore, "soft" activation methods that preserve the radical C₂ building blocks after being partially stripped of hydrogen atoms are preferred. Acceptable methods of soft activation for use in the present invention include remote plasma, photo-assisted, and hot-wire. For example, growth of CNT using a single W filament as a hot wire has been reported. By passing 20-25 A of electric current at 20V, the W filament reached a temperature of about 2000⁰C. The deposition temperature of CNT can then proceed in the temperature range of 450- 600⁰C. The use of other single wires, e.g. Fe wire has also been reported. According to the present invention, an array of catalytic wires assembled either on the top space of the substrate or at the upper stream of the deposition surfaces is used. The metal wire array can be made from W, Pt, Ni, Co, Fe, alloys or combinations thereof. [0039] A schematic arrangement of the process according to the present invention is shown in Figure 7, wherein the chosen gas precursor 250, is passed through the hot wire screen 240, and thereby converted to active precursor 255. The active precursor then serves to deposit catalyst sites 220, onto substrate 210.

[0040] As discussed above the processes of the present invention provide a means to achieve size selected semiconducting SWCNT growth for transistor channels by accurately controlling the size of catalyst growth sites. This results in ability to selectively grow SWCNT channels that exhibit particular properties as desired for next generation electronics devices. The present invention also provides methods for achieving low temperature, e.g. less than 400⁰C, growth of MWCNT on substrates for use as interconnects through the use of selected low temperature carbon precursors. The methods according to the present invention overcome a number of disadvantages and problems in achieving these goals associated with prior art methods.

[0041] It is anticipated that other embodiments and variations of the present invention will become readily apparent to the skilled artisan in the light of the foregoing description, and it is intended that such embodiments and variations likewise be included within the scope of the invention as set out in the appended claims.

Claims

What is claimed:

1. A method of forming carbon nano tubes having a diameter less than 12 A comprising: forming a patterned surface of pads or wells having a size of 100 nm or less; depositing a catalytic layer onto the surface bonding layer; creating catalytic dots from the catalytic layer; and growing carbon nanotubes onto the catalytic dots.

2. A method according to claim 1 wherein the patterned surface is formed from an SiO2 layer, a Si layer, an Au layer or other dielectric or metal layers.

3. A method according to claim 1 wherein depositing a catalytic layer comprises forming surface bonding sites by a SAM method and depositing the catalytic layer onto the surface bonding sites.

4. A method according to claim 1 wherein depositing a catalytic layer comprises a micro-contact printing SAM process, a co-polymer template process, an opal sphere process or a nano-porous template process,

5. A method according to claim 1 wherein the catalytic layer is bi -metallic layer of a transition metal and a rare-earth or lanthanide metal.

6. A method according to claim 4, wherein the transition metal is Ni₅ Co, Fe, Rd, Rh or Ru and the rare- earth or lanthanide metal is Y, Ti or La.

7. A method according to claim 1 wherein creating catalytic dots comprises thermal annealing and thermal reduction of the catalytic layer,

8. A method according to claim 1 wherein in the carbon nanotubes are single- wall carbon nanotubes.

9. A method of forming carbon nanotubes having specific semiconductor properties comprising restricting growth of the carbon nanotubes to have a particular diameter.

10. A method according to claim 9 wherein the diameter is between 6.4 A and 6.8 A and the carbon nanotubes exhibit Si-like properties.

11. A method according to claim 9 wherein the diameter is between 10.0 A and 10.4 A and the carbon nanotubes exhibit Ge-like properties.

12. A method o f growing carbon nanotubes comprising providing a carbon precursor sites on a substrate; and growing carbon nanotubes on the carbon precursor sites at a temperature of 400⁰C or less; wherein the carbon precursor has a formula of C_nH_1n wherein 2<n<12 and 2<m<12.

13. A method according to claim 12 wherein the carbon precursor is C₂H₄, C₂H₂, or C₂H₆.

14. A method according to claim 12 wherein the carbon nanotubes are multi-wall carbon nanotubes.

15. A semiconductor device having transistor channels formed from carbon nanotubes with a diameter of 12 A or less.

16. A semiconductor device according to claim 15 wherein the carbon nanotubes are single- wall carbon nanotubes.

17. A semiconductor device having interconnects formed from carbon nano tubes grown at 400^cC or less.

18. A semiconductor device according to claim 17 wherein the carbon nanotubes are multi-wall carbon nanotubes.