WO2009016795A1 - 貼り合わせウエーハの製造方法 - Google Patents

貼り合わせウエーハの製造方法 Download PDF

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Publication number
WO2009016795A1
WO2009016795A1 PCT/JP2008/001754 JP2008001754W WO2009016795A1 WO 2009016795 A1 WO2009016795 A1 WO 2009016795A1 JP 2008001754 W JP2008001754 W JP 2008001754W WO 2009016795 A1 WO2009016795 A1 WO 2009016795A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
ion implantation
bonded wafer
bonded
bonding
Prior art date
Application number
PCT/JP2008/001754
Other languages
English (en)
French (fr)
Inventor
Norihiro Kobayashi
Hiroji Aga
Yasuo Nagaoka
Nobuhiko Noto
Original Assignee
Shin-Etsu Handotai Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin-Etsu Handotai Co., Ltd. filed Critical Shin-Etsu Handotai Co., Ltd.
Priority to EP08776766.1A priority Critical patent/EP2175477B1/en
Priority to KR1020107001557A priority patent/KR101462397B1/ko
Priority to CN2008801006440A priority patent/CN101765901B/zh
Priority to US12/452,085 priority patent/US8173521B2/en
Publication of WO2009016795A1 publication Critical patent/WO2009016795A1/ja

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

　本発明は、ガスイオンの注入により形成された微小気泡層を有するボンドウエーハと支持基板となるベースウエーハとを接合し、前記微小気泡層を境界としてボンドウエーハを剥離してベースウエーハ上に薄膜を形成するイオン注入剥離法によって貼り合わせウエーハを製造する方法において、ボンドウエーハを剥離後の貼り合わせウエーハを、オゾン水で洗浄した後、水素含有雰囲気下でＲＴＡ処理を行い、次に、酸化性ガス雰囲気下で熱処理を行って前記貼り合わせウエーハの表層に熱酸化膜を形成した後、該熱酸化膜の除去を行い、その後、非酸化性ガス雰囲気下で熱処理する。これによって、イオン注入剥離法を用いた貼り合わせウエーハの製造方法であり、イオン注入によるダメージを除去するとともに、剥離後の貼り合わせウエーハの表面の面粗さを損なうことなく凹状欠陥の発生が抑制された貼り合わせウエーハの製造方法が提供される。
PCT/JP2008/001754 2007-07-27 2008-07-03 貼り合わせウエーハの製造方法 WO2009016795A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP08776766.1A EP2175477B1 (en) 2007-07-27 2008-07-03 Bonded wafer manufacturing method
KR1020107001557A KR101462397B1 (ko) 2007-07-27 2008-07-03 접합 웨이퍼의 제조 방법
CN2008801006440A CN101765901B (zh) 2007-07-27 2008-07-03 贴合晶片的制造方法
US12/452,085 US8173521B2 (en) 2007-07-27 2008-07-03 Method for manufacturing bonded wafer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007196467A JP5135935B2 (ja) 2007-07-27 2007-07-27 貼り合わせウエーハの製造方法
JP2007-196467 2007-07-27

Publications (1)

Publication Number Publication Date
WO2009016795A1 true WO2009016795A1 (ja) 2009-02-05

Family

ID=40304039

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/001754 WO2009016795A1 (ja) 2007-07-27 2008-07-03 貼り合わせウエーハの製造方法

Country Status (6)

Country Link
US (1) US8173521B2 (ja)
EP (1) EP2175477B1 (ja)
JP (1) JP5135935B2 (ja)
KR (1) KR101462397B1 (ja)
CN (1) CN101765901B (ja)
WO (1) WO2009016795A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012520579A (ja) * 2009-03-18 2012-09-06 ソイテック 「シリコン−オン−インシュレーター」ｓｏｉ型の基板のための表面処理方法
WO2013111242A1 (ja) * 2012-01-24 2013-08-01 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8252700B2 (en) * 2009-01-30 2012-08-28 Covalent Materials Corporation Method of heat treating silicon wafer
JP5387450B2 (ja) * 2010-03-04 2014-01-15 信越半導体株式会社 Ｓｏｉウェーハの設計方法及び製造方法
JP5387451B2 (ja) * 2010-03-04 2014-01-15 信越半導体株式会社 Ｓｏｉウェーハの設計方法及び製造方法
JP5703920B2 (ja) * 2011-04-13 2015-04-22 信越半導体株式会社 貼り合わせウェーハの製造方法
CN102280387B (zh) * 2011-08-31 2016-05-04 上海华虹宏力半导体制造有限公司 Sonos结构和sonos存储器的形成方法
CN102280378B (zh) * 2011-08-31 2016-06-29 上海华虹宏力半导体制造有限公司 Sonos结构的形成方法
JP5704039B2 (ja) * 2011-10-06 2015-04-22 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP5927894B2 (ja) * 2011-12-15 2016-06-01 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP2013143407A (ja) 2012-01-06 2013-07-22 Shin Etsu Handotai Co Ltd 貼り合わせｓｏｉウェーハの製造方法
JP6086031B2 (ja) * 2013-05-29 2017-03-01 信越半導体株式会社 貼り合わせウェーハの製造方法
JP6200273B2 (ja) * 2013-10-17 2017-09-20 信越半導体株式会社 貼り合わせウェーハの製造方法
JP6107709B2 (ja) * 2014-03-10 2017-04-05 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP6036732B2 (ja) 2014-03-18 2016-11-30 信越半導体株式会社 貼り合わせウェーハの製造方法
JP6344271B2 (ja) * 2015-03-06 2018-06-20 信越半導体株式会社 貼り合わせ半導体ウェーハ及び貼り合わせ半導体ウェーハの製造方法
JP6380245B2 (ja) * 2015-06-15 2018-08-29 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP6473970B2 (ja) * 2015-10-28 2019-02-27 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211128A (ja) 1991-09-18 1993-08-20 Commiss Energ Atom 薄い半導体材料フィルムの製造方法
JP2000150905A (ja) * 1998-09-04 2000-05-30 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2000294754A (ja) * 1999-04-07 2000-10-20 Denso Corp 半導体基板及び半導体基板の製造方法並びに半導体基板製造装置
WO2006070220A1 (en) * 2004-12-28 2006-07-06 S.O.I.Tec Silicon On Insulator Technologies Method for obtaining a thin layer having a low density of holes
WO2006109614A1 (ja) * 2005-04-06 2006-10-19 Shin-Etsu Handotai Co., Ltd. Ｓｏｉウェーハの製造方法およびこの方法により製造されたｓｏｉウェーハ

Family Cites Families (9)

* Cited by examiner, † Cited by third party
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JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
FR2797713B1 (fr) 1999-08-20 2002-08-02 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
EP1408551B1 (en) * 2001-07-17 2014-07-02 Shin-Etsu Handotai Co., Ltd. Method for producing bonding wafer
JP4407127B2 (ja) 2003-01-10 2010-02-03 信越半導体株式会社 Ｓｏｉウエーハの製造方法
US7256104B2 (en) * 2003-05-21 2007-08-14 Canon Kabushiki Kaisha Substrate manufacturing method and substrate processing apparatus
KR101142138B1 (ko) * 2003-09-10 2012-05-10 신에쯔 한도타이 가부시키가이샤 적층기판의 세척방법, 기판의 접합방법 및 접합 웨이퍼의제조방법
JP4661784B2 (ja) * 2004-09-30 2011-03-30 信越半導体株式会社 Ｓｏｉウエーハの洗浄方法
JP2006216826A (ja) * 2005-02-04 2006-08-17 Sumco Corp Ｓｏｉウェーハの製造方法
JP4977999B2 (ja) * 2005-11-21 2012-07-18 株式会社Ｓｕｍｃｏ 貼合せ基板の製造方法及びその方法で製造された貼合せ基板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211128A (ja) 1991-09-18 1993-08-20 Commiss Energ Atom 薄い半導体材料フィルムの製造方法
JP2000150905A (ja) * 1998-09-04 2000-05-30 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2000294754A (ja) * 1999-04-07 2000-10-20 Denso Corp 半導体基板及び半導体基板の製造方法並びに半導体基板製造装置
WO2006070220A1 (en) * 2004-12-28 2006-07-06 S.O.I.Tec Silicon On Insulator Technologies Method for obtaining a thin layer having a low density of holes
WO2006109614A1 (ja) * 2005-04-06 2006-10-19 Shin-Etsu Handotai Co., Ltd. Ｓｏｉウェーハの製造方法およびこの方法により製造されたｓｏｉウェーハ

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2175477A4 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012520579A (ja) * 2009-03-18 2012-09-06 ソイテック 「シリコン−オン−インシュレーター」ｓｏｉ型の基板のための表面処理方法
WO2013111242A1 (ja) * 2012-01-24 2013-08-01 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
US9093497B2 (en) 2012-01-24 2015-07-28 Shin-Etsu Handotai Co., Ltd. Method for manufacturing bonded SOI wafer

Also Published As

Publication number Publication date
CN101765901B (zh) 2012-06-13
EP2175477B1 (en) 2017-01-04
KR101462397B1 (ko) 2014-11-17
EP2175477A1 (en) 2010-04-14
US20100120223A1 (en) 2010-05-13
JP5135935B2 (ja) 2013-02-06
EP2175477A4 (en) 2010-10-20
KR20100033414A (ko) 2010-03-29
US8173521B2 (en) 2012-05-08
CN101765901A (zh) 2010-06-30
JP2009032972A (ja) 2009-02-12

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