WO2006109614A1 - Soiウェーハの製造方法およびこの方法により製造されたsoiウェーハ - Google Patents
Soiウェーハの製造方法およびこの方法により製造されたsoiウェーハ Download PDFInfo
- Publication number
- WO2006109614A1 WO2006109614A1 PCT/JP2006/307078 JP2006307078W WO2006109614A1 WO 2006109614 A1 WO2006109614 A1 WO 2006109614A1 JP 2006307078 W JP2006307078 W JP 2006307078W WO 2006109614 A1 WO2006109614 A1 WO 2006109614A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- soi
- wafer
- layer
- oxide film
- soi layer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 34
- 238000010438 heat treatment Methods 0.000 claims abstract description 32
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims abstract description 28
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 18
- 150000002500 ions Chemical class 0.000 claims abstract description 10
- 239000012298 atmosphere Substances 0.000 claims abstract description 8
- 239000001257 hydrogen Substances 0.000 claims abstract description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 7
- -1 hydrogen ions Chemical class 0.000 claims abstract description 7
- 239000007789 gas Substances 0.000 claims abstract description 5
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 238000005498 polishing Methods 0.000 claims description 25
- 238000005468 ion implantation Methods 0.000 claims description 21
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 14
- 230000032798 delamination Effects 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 5
- 239000007864 aqueous solution Substances 0.000 claims description 4
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 4
- 238000004299 exfoliation Methods 0.000 claims 2
- 238000000926 separation method Methods 0.000 abstract description 10
- 230000003746 surface roughness Effects 0.000 abstract description 9
- 235000012431 wafers Nutrition 0.000 description 69
- 239000010408 film Substances 0.000 description 50
- 238000004140 cleaning Methods 0.000 description 20
- 238000009826 distribution Methods 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000010306 acid treatment Methods 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000003776 cleavage reaction Methods 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000010079 rubber tapping Methods 0.000 description 2
- 230000007017 scission Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- NIPNSKYNPDTRPC-UHFFFAOYSA-N N-[2-oxo-2-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)ethyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 NIPNSKYNPDTRPC-UHFFFAOYSA-N 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Definitions
- the present invention relates to an SOI (Silicon On Insulator) wafer manufacturing method using an ion implantation delamination method, in which a damaged layer remaining on an SOI layer after delamination is removed, and the flatness (maximum thickness after SOI layer polishing) is removed. And the difference between the minimum thickness and the in-plane film thickness distribution.
- SOI Silicon On Insulator
- a so-called ion implantation separation method (smart cut method) is disclosed in which an SOI wafer is manufactured by bonding ion-implanted wafers after bonding.
- an oxide film is formed on at least one of the two silicon wafers, and hydrogen ions or rare gas ions are implanted from the upper surface of one silicon wafer, and a microbubble layer is formed inside the wafer.
- the surface into which the ions are implanted is brought into close contact with the other silicon wafer through the oxide film, and then heat treatment (peeling heat treatment) is applied to form the microbubble layer.
- an SOI wafer having a good mirror surface as a cleavage plane (peeling surface) and high uniformity in the thickness of the SOI layer can be obtained relatively easily.
- the ion implantation delamination method there is a damage layer due to ion implantation on the surface of the SOI wafer after delamination, and the surface roughness is on the mirror surface of a normal silicon wafer. Compared to this, the film thickness distribution of the SOI layer varies. Therefore, in the ion implantation separation method, it is necessary to remove such a damaged layer and surface roughness.
- the SOI wafer after peeling is subjected to a heat treatment in an acidic atmosphere, and after forming an oxide film on the SOI layer, the oxide film is removed, so-called sacrificial oxidation is performed to perform a damage layer.
- a method was proposed to remove. With this method, the damage layer can be removed regardless of polishing which is machining.
- the present invention has been made in view of such problems, and in the ion implantation separation method, the damage layer remaining on the surface of the SOI layer after the separation and the surface roughness are made uniform in the thickness of the SOI layer. Even if the surface of the SOI layer is polished while maintaining its properties, a method for producing a high-quality SOI wafer without deteriorating the film thickness distribution and flatness is provided. The purpose is to improve productivity.
- the present invention provides a method for manufacturing an SOI wafer by an ion implantation delamination method, and includes at least one surface of a base wafer serving as a support substrate and a bond wafer serving as an SOI layer. After forming an oxide film on the surface and implanting at least one of hydrogen ions or rare gas ions from the surface of the bond wafer to form an ion implantation layer, the bond wafer and the base wafer are in close contact with each other through the oxide film.
- heat treatment is performed to peel off the ion-implanted layer to form an SOI layer, and then heat treatment is performed in an oxidizing atmosphere to form an oxide film on the surface of the SOI layer, and then the oxide film is formed.
- a method for manufacturing an SOI wafer characterized by etching and removing, then cleaning the surface of the SOI layer with ozone water, and then polishing the surface of the SOI layer.
- an SOI wafer is manufactured by an ion implantation delamination method, If the surface of the SOI layer is cleaned using ozone water before the polishing process of the surface of the layer, the film thickness distribution of the natural oxide film on the surface of the SOI layer before polishing will be the same as that of conventional acid cleaning (eg SC-2). This is rather worse than the case of (cleaning) .However, this causes the abrasive grains to spread over the entire polished surface, and the film thickness distribution and flatness after polishing are improved, resulting in efficient and high quality. You can get SOI wafers and improve productivity.
- conventional acid cleaning eg SC-2
- a heat treatment for increasing the bond strength may be performed at a higher temperature than during the peeling heat treatment.
- the bonding strength between the SOI layer (bonded wafer) and the support substrate (base wafer) can be increased if the bonded wafer is subjected to heat treatment at a temperature higher than that during the peeling heat treatment after the peeling heat treatment. is there.
- the peeling heat treatment temperature can be set to a high value, and it can also serve as a bonding heat treatment.
- the oxide film is etched away using an aqueous solution containing hydrogen fluoride, only the oxide film can be etched, and the damaged layer remaining on the surface of the SOI layer due to sacrificial oxidation can be removed. It can be easily removed.
- the ozone concentration in the ozone water is 3 ppm or more and 10 ppm or less.
- the conventional cleaning is performed with the ozone water.
- the film thickness distribution of the native oxide film on the surface of the SOI layer can be moderately deteriorated, and the SOI layer with a uniform film thickness distribution can be obtained by subsequent polishing. .
- polishing force is performed by a tapping borish.
- the polishing process is performed by touch polishing, mirror polishing with an extremely small polishing allowance can be applied to the wafer, and the high-quality SOI can be obtained by flattening without degrading the film thickness distribution as much as possible. You can get woofer.
- An SOI wafer manufactured by the method for manufacturing an SOI wafer as described above is of high quality with a high flatness and a uniform in-plane film thickness.
- a method of manufacturing an SOI wafer by an ion implantation separation method as in the present invention wherein the SOI wafer is bonded through an oxide film, separated at the ion implantation layer, and an oxide film is formed on the surface of the SOI layer. After forming and removing the oxide film by etching, the surface of the SOI layer is washed with ozone water and then polished, so that the damage layer remaining on the surface of the SOI layer after peeling, the surface roughness, It is possible to remove while maintaining the uniformity of the SOI layer thickness. In particular, it is possible to obtain a high-quality sow wafer without deteriorating the thickness uniformity despite polishing the surface of the SOI layer. Can do. As a result, the yield and productivity of wafer manufacturing can be improved.
- FIG. 1 is a schematic process diagram showing an example of a manufacturing process in a method for manufacturing an SOI wafer by an ion implantation delamination method according to the present invention.
- FIG. 1 is a schematic process diagram showing an example of a manufacturing process of a method for manufacturing an SOI wafer by the ion implantation delamination method of the present invention.
- step (a) two silicon mirror wafers are prepared in the ion implantation delamination method 1, and a base wafer 1 serving as a support substrate that meets the device specifications and a bond wafer 2 serving as an SOI layer are prepared. prepare.
- step (b) at least one of these units, in this case, the bond wafer 2 is subjected to, for example, thermal oxidation, and an oxide film 3 having a thickness of about 0.1 to 2.0 m is formed on the surface thereof. Form.
- step (c) at least one of hydrogen ions or rare gas ions, in this case hydrogen ions, is implanted into one side of Bondueha 2 having an oxide film formed on the surface, and the average penetration depth of the ions is adjusted. Then, the ion implantation layer 4 parallel to the surface is formed.
- hydrogen ions or rare gas ions in this case hydrogen ions
- the step (d) is a step in which the base wafer 1 is superposed and adhered to the hydrogen ion-implanted surface of the bond wafer 2 into which hydrogen ions have been implanted through an oxide film, and is clean at room temperature. By bringing the surfaces of two wafers into contact with each other under an atmosphere, the wafers are bonded together without using an adhesive.
- step (e) separation is performed to separate the separation wafer 5 and the SOI wafer 6 (SOI layer 7 + buried oxide film 3 + base wafer 1) by peeling off with the ion implantation layer 4 as a boundary.
- the heat treatment step for example, if heat treatment is performed at a temperature of about 500 ° C. or more in an inert gas atmosphere, the separation wafer 5 and the SOI wafer 6 are separated by crystal rearrangement and bubble aggregation. The damaged layer 8 remains in the SOI layer 7 on the surface of the SOI wafer as it is peeled off.
- a bonding heat treatment step is performed in step (f).
- the bonding strength between the wafers adhered in the adhesion process and the peeling heat treatment process in the steps (d) and (e) is weak to use in the device process as it is.
- This heat treatment is preferably carried out in an inert gas atmosphere at 1000 to 1300 ° C. for 30 minutes to 2 hours.
- the bonding heat treatment may be performed, and the bonding heat treatment performed alone may be omitted.
- step (g) first, heat treatment is performed in an oxidizing atmosphere to form the oxide film 9 on the SOI layer 7 so that the damaged layer 8 is taken into the oxide film 9.
- step (h) the oxide film 9 formed on the SOI layer 7 is removed.
- the removal of the oxide film 9 may be performed by etching with an aqueous solution containing hydrogen fluoride.
- an aqueous solution containing hydrogen fluoride By performing the hydrofluoric acid treatment in this way, only the oxide film 9 is removed by etching, and the SOI wafer 6 with the damaged layer removed by sacrificial oxidation can be obtained.
- this wafer has the advantage that the hydrofluoric acid treatment is simple and low-cost.
- step (i) cleaning with ozone water is performed. If ozone water cleaning is added after hydrofluoric acid treatment, the removal of metal impurities is further accelerated by the strong acidity of ozone, and the metal impurities are prevented from reattaching to the outer surface of the wafer. That is, since ozone water shows a higher acid-reduction potential than hydrogen peroxide and hydrogen peroxide, it is considered that impurities with a higher oxidizing power, particularly metal elements, are strongly ionized to prevent adhesion to the substrate surface. In addition, cleaning with ozone water is generally smoother than that of SC-2 cleaning.
- polishing agent spreads throughout the wafer during the next polishing process, for example, touch polish, and the flatness and film thickness distribution of the SOI layer after the touch bolish is improved.
- touch polish it has been common knowledge to clean the SOI layer so as not to deteriorate the flatness as much as possible.
- the surface roughness of the surface of the natural oxide film is rather moderate. It was found that the polishing agent spreads more, and as a result, the flatness and film thickness uniformity of the surface of the SOI layer after polishing can be secured.
- the ozone water concentration at this time is preferably, for example, 3 ppm or more and lOppm or less.
- the ozone water concentration is preferably, for example, 3 ppm or more and lOppm or less.
- the ozone concentration in ozone water was set to 15 ppm (Example 2) and 2 Oppm (Example 3). Otherwise, the same processes as in Example 1 were performed on 10 wafers. It was. At this time, the P-V values of the natural oxide film thickness on the SOI layer surface of each wafer after ozone cleaning are 0.1693 nm and 0.1855 nm, respectively, and the standard deviations are 0.0627 and 0.0734. Example The value was larger than the value after ozone cleaning in Comparative Example 1. And after touch polishing the surface of the SOI layer, the P ⁇ V value of the SOI layer thickness is 6.21 ⁇ respectively. m, 6.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007512915A JP4421652B2 (ja) | 2005-04-06 | 2006-04-04 | Soiウェーハの製造方法 |
EP06731026.8A EP1868230B1 (en) | 2005-04-06 | 2006-04-04 | Manufacting method of soi wafer and soi wafer manufactured by this method |
KR1020077022582A KR101229760B1 (ko) | 2005-04-06 | 2006-04-04 | Soi 웨이퍼의 제조방법 및 이 방법에 의해 제조된soi 웨이퍼 |
US11/887,574 US20090117706A1 (en) | 2005-04-06 | 2006-04-04 | Manufacturing Method of SOI Wafer and SOI Wafer Manufactured by This Method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005110019 | 2005-04-06 | ||
JP2005-110019 | 2005-04-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006109614A1 true WO2006109614A1 (ja) | 2006-10-19 |
Family
ID=37086892
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2006/307078 WO2006109614A1 (ja) | 2005-04-06 | 2006-04-04 | Soiウェーハの製造方法およびこの方法により製造されたsoiウェーハ |
Country Status (6)
Country | Link |
---|---|
US (1) | US20090117706A1 (ja) |
EP (1) | EP1868230B1 (ja) |
JP (1) | JP4421652B2 (ja) |
KR (1) | KR101229760B1 (ja) |
CN (1) | CN101151708A (ja) |
WO (1) | WO2006109614A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009016795A1 (ja) * | 2007-07-27 | 2009-02-05 | Shin-Etsu Handotai Co., Ltd. | 貼り合わせウエーハの製造方法 |
JP2011071493A (ja) * | 2009-08-25 | 2011-04-07 | Semiconductor Energy Lab Co Ltd | 半導体基板の再生方法、再生半導体基板の作製方法、および、soi基板の作製方法 |
JP2016082093A (ja) * | 2014-10-17 | 2016-05-16 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8698106B2 (en) * | 2008-04-28 | 2014-04-15 | Varian Semiconductor Equipment Associates, Inc. | Apparatus for detecting film delamination and a method thereof |
JP5544986B2 (ja) * | 2010-04-01 | 2014-07-09 | 信越半導体株式会社 | 貼り合わせsoiウェーハの製造方法、及び貼り合わせsoiウェーハ |
JP5533624B2 (ja) * | 2010-12-16 | 2014-06-25 | 信越半導体株式会社 | 半導体ウェーハの洗浄方法 |
CN102544360B (zh) * | 2010-12-30 | 2014-03-12 | 中芯国际集成电路制造(上海)有限公司 | 相变存储器形成方法 |
JP2012156495A (ja) * | 2011-01-07 | 2012-08-16 | Semiconductor Energy Lab Co Ltd | Soi基板の作製方法 |
JP5862521B2 (ja) * | 2012-09-03 | 2016-02-16 | 信越半導体株式会社 | Soiウェーハの製造方法 |
JP6200273B2 (ja) * | 2013-10-17 | 2017-09-20 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
US10283384B2 (en) * | 2015-04-27 | 2019-05-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for etching etch layer and wafer etching apparatus |
Citations (2)
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JP2000091279A (ja) * | 1998-09-09 | 2000-03-31 | Shin Etsu Handotai Co Ltd | 被鏡面研磨用半導体基板及び半導体基板の製造方法 |
JP2004259970A (ja) * | 2003-02-26 | 2004-09-16 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法及びsoiウエーハ |
Family Cites Families (4)
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JP3385972B2 (ja) * | 1998-07-10 | 2003-03-10 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法および貼り合わせウェーハ |
JP2000124092A (ja) * | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
US7256104B2 (en) * | 2003-05-21 | 2007-08-14 | Canon Kabushiki Kaisha | Substrate manufacturing method and substrate processing apparatus |
US6911375B2 (en) * | 2003-06-02 | 2005-06-28 | International Business Machines Corporation | Method of fabricating silicon devices on sapphire with wafer bonding at low temperature |
-
2006
- 2006-04-04 WO PCT/JP2006/307078 patent/WO2006109614A1/ja active Application Filing
- 2006-04-04 JP JP2007512915A patent/JP4421652B2/ja active Active
- 2006-04-04 US US11/887,574 patent/US20090117706A1/en not_active Abandoned
- 2006-04-04 KR KR1020077022582A patent/KR101229760B1/ko active IP Right Grant
- 2006-04-04 CN CNA2006800107854A patent/CN101151708A/zh active Pending
- 2006-04-04 EP EP06731026.8A patent/EP1868230B1/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000091279A (ja) * | 1998-09-09 | 2000-03-31 | Shin Etsu Handotai Co Ltd | 被鏡面研磨用半導体基板及び半導体基板の製造方法 |
JP2004259970A (ja) * | 2003-02-26 | 2004-09-16 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法及びsoiウエーハ |
Non-Patent Citations (1)
Title |
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See also references of EP1868230A4 * |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009016795A1 (ja) * | 2007-07-27 | 2009-02-05 | Shin-Etsu Handotai Co., Ltd. | 貼り合わせウエーハの製造方法 |
JP2009032972A (ja) * | 2007-07-27 | 2009-02-12 | Shin Etsu Handotai Co Ltd | 貼り合わせウエーハの製造方法 |
EP2175477A1 (en) * | 2007-07-27 | 2010-04-14 | Shin-Etsu Handotai Co., Ltd. | Bonded wafer manufacturing method |
EP2175477A4 (en) * | 2007-07-27 | 2010-10-20 | Shinetsu Handotai Kk | METHOD FOR MANUFACTURING LINED WAFER |
US8173521B2 (en) | 2007-07-27 | 2012-05-08 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing bonded wafer |
CN101765901B (zh) * | 2007-07-27 | 2012-06-13 | 信越半导体股份有限公司 | 贴合晶片的制造方法 |
JP2011071493A (ja) * | 2009-08-25 | 2011-04-07 | Semiconductor Energy Lab Co Ltd | 半導体基板の再生方法、再生半導体基板の作製方法、および、soi基板の作製方法 |
JP2016082093A (ja) * | 2014-10-17 | 2016-05-16 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP4421652B2 (ja) | 2010-02-24 |
KR20080003328A (ko) | 2008-01-07 |
EP1868230A4 (en) | 2012-03-07 |
KR101229760B1 (ko) | 2013-02-06 |
EP1868230A1 (en) | 2007-12-19 |
CN101151708A (zh) | 2008-03-26 |
JPWO2006109614A1 (ja) | 2008-11-06 |
US20090117706A1 (en) | 2009-05-07 |
EP1868230B1 (en) | 2013-10-23 |
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