WO2008114564A1 - 薄膜トランジスタ及び薄膜トランジスタの製造方法 - Google Patents
薄膜トランジスタ及び薄膜トランジスタの製造方法 Download PDFInfo
- Publication number
- WO2008114564A1 WO2008114564A1 PCT/JP2008/052833 JP2008052833W WO2008114564A1 WO 2008114564 A1 WO2008114564 A1 WO 2008114564A1 JP 2008052833 W JP2008052833 W JP 2008052833W WO 2008114564 A1 WO2008114564 A1 WO 2008114564A1
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- WO
- WIPO (PCT)
- Prior art keywords
- thin film
- film transistor
- semiconductor layer
- electrode
- gate
- Prior art date
Links
- 239000010409 thin film Substances 0.000 title 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 abstract 4
- 239000007864 aqueous solution Substances 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 239000002109 single walled nanotube Substances 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000000576 coating method Methods 0.000 abstract 1
- 239000004094 surface-active agent Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/6715—Apparatus for applying a liquid, a resin, an ink or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
- H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
- H10K71/135—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing using ink-jet printing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
- H10K71/15—Deposition of organic active material using liquid deposition, e.g. spin coating characterised by the solvent used
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
- H10K85/221—Carbon nanotubes
Abstract
ボトムゲート型の薄膜トランジスタを製造する場合、基板上にゲート電極を形成した後(S11)、当該ゲート電極を覆うように基板上にゲート絶縁層を形成する(S12)。続いて、ゲート絶縁層上に、ソース電極及びドレイン電極を形成し(S13)、当該ソース電極とドレイン電極との間に、シングルウォールカーボンナノチューブを含む半導体層を形成する(S14)。半導体層の形成は、半導体層形成用の水溶液を、インクジェット法等の塗布法により塗布することにより行う。半導体層形成用の水溶液中では、界面活性剤により被覆されたシングルウォールカーボンナノチューブが、均一に分散している。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/383,523 US8030139B2 (en) | 2007-02-21 | 2009-03-25 | Thin film transistor and method of producing thin film transistor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007040679 | 2007-02-21 | ||
JP2007-040679 | 2007-02-21 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/383,523 Continuation-In-Part US8030139B2 (en) | 2007-02-21 | 2009-03-25 | Thin film transistor and method of producing thin film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2008114564A1 true WO2008114564A1 (ja) | 2008-09-25 |
Family
ID=39765677
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2008/052833 WO2008114564A1 (ja) | 2007-02-21 | 2008-02-20 | 薄膜トランジスタ及び薄膜トランジスタの製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8030139B2 (ja) |
JP (1) | JP2008235880A (ja) |
WO (1) | WO2008114564A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010056568A1 (en) * | 2008-11-14 | 2010-05-20 | 3M Innovative Properties Company | Off-center deposition of organic semiconductor in an organic semiconductor device |
US7948016B1 (en) | 2009-11-03 | 2011-05-24 | 3M Innovative Properties Company | Off-center deposition of organic semiconductor in an organic semiconductor device |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101582382B (zh) * | 2008-05-14 | 2011-03-23 | 鸿富锦精密工业(深圳)有限公司 | 薄膜晶体管的制备方法 |
CN101593699B (zh) * | 2008-05-30 | 2010-11-10 | 清华大学 | 薄膜晶体管的制备方法 |
CN101582448B (zh) * | 2008-05-14 | 2012-09-19 | 清华大学 | 薄膜晶体管 |
CN101582449B (zh) * | 2008-05-14 | 2011-12-14 | 清华大学 | 薄膜晶体管 |
CN101582451A (zh) * | 2008-05-16 | 2009-11-18 | 清华大学 | 薄膜晶体管 |
CN101582444A (zh) | 2008-05-14 | 2009-11-18 | 清华大学 | 薄膜晶体管 |
CN101599495B (zh) * | 2008-06-04 | 2013-01-09 | 清华大学 | 薄膜晶体管面板 |
CN101582445B (zh) * | 2008-05-14 | 2012-05-16 | 清华大学 | 薄膜晶体管 |
CN101582446B (zh) * | 2008-05-14 | 2011-02-02 | 鸿富锦精密工业(深圳)有限公司 | 薄膜晶体管 |
CN101582447B (zh) | 2008-05-14 | 2010-09-29 | 清华大学 | 薄膜晶体管 |
CN101587839B (zh) | 2008-05-23 | 2011-12-21 | 清华大学 | 薄膜晶体管的制备方法 |
CN101582450B (zh) * | 2008-05-16 | 2012-03-28 | 清华大学 | 薄膜晶体管 |
WO2011111736A1 (ja) | 2010-03-10 | 2011-09-15 | 日本電気株式会社 | 電界効果型トランジスタ及びその製造方法 |
TWI445180B (zh) * | 2011-09-28 | 2014-07-11 | E Ink Holdings Inc | 陣列基板及使用其之顯示裝置 |
CN104112777B (zh) * | 2013-04-16 | 2017-12-19 | 清华大学 | 薄膜晶体管及其制备方法 |
CN108365095A (zh) * | 2017-09-30 | 2018-08-03 | 广东聚华印刷显示技术有限公司 | 薄膜晶体管及其制备方法 |
Citations (3)
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JP2004071654A (ja) * | 2002-08-01 | 2004-03-04 | Semiconductor Energy Lab Co Ltd | カーボンナノチューブ半導体素子の作製方法 |
JP2005101424A (ja) * | 2003-09-26 | 2005-04-14 | Sony Corp | 電界効果半導体装置の製造方法 |
JP2007031238A (ja) * | 2005-07-29 | 2007-02-08 | Sony Corp | 金属的カーボンナノチューブの分離方法ならびに半導体的カーボンナノチューブ薄膜の製造方法ならびに薄膜トランジスタおよびその製造方法ならびに電子素子およびその製造方法 |
Family Cites Families (8)
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JP4140180B2 (ja) * | 2000-08-31 | 2008-08-27 | 富士ゼロックス株式会社 | トランジスタ |
JP4834950B2 (ja) | 2003-09-12 | 2011-12-14 | ソニー株式会社 | 電界効果半導体装置の製造方法 |
CN101840997A (zh) * | 2003-09-12 | 2010-09-22 | 索尼株式会社 | 用于制造场效应半导体器件的方法 |
JP4443944B2 (ja) | 2004-01-20 | 2010-03-31 | 独立行政法人科学技術振興機構 | トランジスタとその製造方法 |
JP2006298715A (ja) * | 2005-04-22 | 2006-11-02 | Sony Corp | カーボンナノチューブ薄膜の製造方法、電子素子の製造方法、薄膜の製造方法、構造体の製造方法および気泡の形成方法 |
US7667230B2 (en) * | 2006-03-31 | 2010-02-23 | 3M Innovative Properties Company | Electronic devices containing acene-thiophene copolymers |
US7744717B2 (en) * | 2006-07-17 | 2010-06-29 | E. I. Du Pont De Nemours And Company | Process for enhancing the resolution of a thermally transferred pattern |
US7528448B2 (en) * | 2006-07-17 | 2009-05-05 | E.I. Du Pont De Nemours And Company | Thin film transistor comprising novel conductor and dielectric compositions |
-
2008
- 2008-02-20 WO PCT/JP2008/052833 patent/WO2008114564A1/ja active Application Filing
- 2008-02-20 JP JP2008038628A patent/JP2008235880A/ja active Pending
-
2009
- 2009-03-25 US US12/383,523 patent/US8030139B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2004071654A (ja) * | 2002-08-01 | 2004-03-04 | Semiconductor Energy Lab Co Ltd | カーボンナノチューブ半導体素子の作製方法 |
JP2005101424A (ja) * | 2003-09-26 | 2005-04-14 | Sony Corp | 電界効果半導体装置の製造方法 |
JP2007031238A (ja) * | 2005-07-29 | 2007-02-08 | Sony Corp | 金属的カーボンナノチューブの分離方法ならびに半導体的カーボンナノチューブ薄膜の製造方法ならびに薄膜トランジスタおよびその製造方法ならびに電子素子およびその製造方法 |
Non-Patent Citations (1)
Title |
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TANAKA S. ET AL.: "10p-R-14 Choenshin Bunriho o Mochiita Kobunsansei Carbon Nanotube/Polymer-maku ni yoru FET Device", 2005 NEN SHUKI DAI 66 KAI EXTENDED ABSTRACTS, THE JAPAN SOCIETY OF APPLIED PHYSICS, vol. 3, 7 September 2005 (2005-09-07), pages 1174 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010056568A1 (en) * | 2008-11-14 | 2010-05-20 | 3M Innovative Properties Company | Off-center deposition of organic semiconductor in an organic semiconductor device |
US7948016B1 (en) | 2009-11-03 | 2011-05-24 | 3M Innovative Properties Company | Off-center deposition of organic semiconductor in an organic semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US8030139B2 (en) | 2011-10-04 |
US20090224292A1 (en) | 2009-09-10 |
JP2008235880A (ja) | 2008-10-02 |
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