WO2008097219A2 - Système et procédé pour une élimination automatique de violations d'électromigration et de chauffage automatique pendant la construction d'un bloc de disposition de masque, en maintenant l'exactitude des règles de conception de processus (drc propre) et de la connectivité de disposition (l - Google Patents

Système et procédé pour une élimination automatique de violations d'électromigration et de chauffage automatique pendant la construction d'un bloc de disposition de masque, en maintenant l'exactitude des règles de conception de processus (drc propre) et de la connectivité de disposition (l Download PDF

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Publication number
WO2008097219A2
WO2008097219A2 PCT/US2007/003253 US2007003253W WO2008097219A2 WO 2008097219 A2 WO2008097219 A2 WO 2008097219A2 US 2007003253 W US2007003253 W US 2007003253W WO 2008097219 A2 WO2008097219 A2 WO 2008097219A2
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WIPO (PCT)
Prior art keywords
electromigration
self heat
polygon
clean
violation
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Application number
PCT/US2007/003253
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English (en)
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WO2008097219A3 (fr
Inventor
Dan Rittman
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Dan Rittman
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Priority to PCT/US2007/003253 priority Critical patent/WO2008097219A2/fr
Publication of WO2008097219A2 publication Critical patent/WO2008097219A2/fr
Publication of WO2008097219A3 publication Critical patent/WO2008097219A3/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Definitions

  • the present invention is generally related to the field of integrated circuits, and more particularly to a system and method for eliminating electromigration and self heating violations during construction of a mask layout block, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness, in the metallic, polysilicon, contacts and VIA's interconnects of an integrated circuit device.
  • DRC Clean process design rules
  • LVS Clean layout connectivity
  • Nanometer designs contain millions of devices and operate at very high frequencies.
  • the current densities (current per cross-sectional area) in the signal lines and power are consequently high and can result in either signal or power electromigration problems.
  • the electron movement induced by the current in the metal power lines causes metal ions to migrate. That phenomenon of transport of mass in the path of a DC flow, as in the metal power lines in the design, is termed power electromigration.
  • Electromigration is harmful from the point of view of design reliability, since the transport of mass can cause open circuits, or shorts, to neighboring wires. Electromigration is actually not a function of current, but a function of current density. It is also accelerated by elevated temperature. Thus, electromigration is easily observed in Al metal lines that are subjected to high current densities at high temperature over time. The higher current density around the void results in localized heating that further accelerates the growth of the void, which again increases the current density. The cycle continues until the void becomes large enough to cause the metal line to fuse open. Typically the most susceptible to electromigration phenomenon are metallic interconnections of integrated circuit. (IC) EM effects become more prominent as IC feature sizes decrease and as IC frequencies and current densities increase.
  • EM in IC devices occurs due to direct current flow.
  • High direct current density in an IC device causes atoms and ions in the conductors of the device to move in the opposite direction of the direct current flow.
  • metal ions accumulate in some regions and voids form in other regions of the conductors. The accumulation of metal ions may result in a short circuit to adjacent conductors and the voids may result in an open-circuit condition.
  • the current density can be kept below a predetermined EM threshold, EM can be rendered negligible for the life of any particular IC device. Therefore, EM due to direct current flow in IC devices is a major concern with respect to the potential for device failures and the overall reliability of the device.
  • IC devices may also have alternating current flow.
  • the alternating current density in an IC device that results from alternating current flow causes atoms and ions in the conductors of the device to first move in one direction and then move in the opposite direction, back to their original positions.
  • a plurality of conductors with alternating current flow is defined as a signal net.
  • conductors with alternating current flow do not directly cause EM problems.
  • conductors with alternating current flow do use power and generate heat. Since EM is very sensitive to the temperature of the conductors, it is often necessary to limit the temperature increase of the conductors in IC devices that results from the heating due to alternating current flow. Therefore, the alternating current flow in a conductor does have an impact on EM because the heating due conductors with alternating current may increase the overall temperature of the IC device by heating up neighboring conductors with direct current flow.
  • the maximum current limit is set by: (1) considering the minimum distance between conductors with alternating current flow and conductors with direct current flow; and (2) the maximum temperature difference .DELTA.T.sub.MAX that maintains the reliability of the IC device.
  • using this type of worst-case "minimum distance- between-conductors" approach to determine space between conductors also wastes valuable space on the IC device.
  • Electromigration failures take time to develop, and are therefore very difficult to detect until it happens. Thus, the best solution to electromigration problems is to prevent them from taking place. Therefore, it is imperative to eliminate electromigration and self heating issues in order to maintain a reliable integrated circuit operation for many years.
  • the system and method described in this invention eliminates electromigration and self heating issues early in the IC layout design phase. In this way a significant amount of time is saved during the final reliability verification of the integrated circuit, achieving on-time tape outs and avoiding re-spins.
  • a method for eliminating electromigration and self heat violations during construction of a mask layout block includes automatically preventing a polygon from being placed, created or edited in a selected position in a mask layout block if an electromigration and self heat rule violation is identified.
  • an automated method for eliminating electromigration and self heat violations during construction of a mask layout block includes analyzing a selected polygon(s) in a mask layout block and obtaining one or more electromigration and self heat rules associated with the polygon from a technology or external constraints file.
  • the method provides a violation marker associated with the selected position for the polygon that graphically represents a space, width or length in the mask layout block where the selected polygon's position complies with the electromigration and self heat rules.
  • an automated method for eliminating electromigration and self heat violations during construction of a mask layout block includes analyzing a selected polygon in a mask layout block and identifying a electromigration and self heat violation in the mask layout block if the selected position, with or length of the polygon is less than electromigration and self heat value permitted from a technology or external constraints file. If the electromigration and self heat violation is identified, the placement, creation or edition of the polygon at the selected position is automatically prevented, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness.
  • DRC Clean process design rules
  • LVS Clean layout connectivity
  • a computer system for eliminating electromigration and self heat violations during construction of a mask layout block, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness includes a processing resource coupled to a computer readable memory. Processing instructions are encoded in the computer readable memory. When the processing instructions are executed by the processing resource, the instructions analyze a selected polygon in a mask layout block and identify an electromigration and self heat violation in the mask layout block if the selected position is less than an electromigration and self heat rule from a technology or external constraints file. If the electromigration and self heat violation is identified, the instructions prevent the polygon from being placed, created or edited at the selected position in the mask layout block, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness.
  • DRC Clean process design rules
  • LVS Clean layout connectivity
  • an electromigration-self heat aware (EMSH Aware) tool that prevents electromigration and self heat violations from being created during the construction of a mask layout block.
  • a layout designer may move a cursor or click on a polygon in order to select it.
  • the EMSH Aware tool highlights a violation marker that may represent a width, space or length in the layout block to eliminate electromigration and self heat violation according to technology or external constraints file.
  • the EMSH Aware tool provides an information window with the current and required electromigration and self heat conditions related to the selected polygon.
  • the information window includes an option to perform an automatic correction of the selected polygon, also can be done by Right-Click of the mouse.
  • the system will change the selected polygon width, length or space according to electromigration and self heat rules taken from technology or external constraints file, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness.
  • DRC Clean process design rules
  • LVS Clean layout connectivity
  • the system will automatically adjust the amount of contacts or vias according to electromigration and self heat rules taken from technology or external constraints file, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness.
  • the mask layout block therefore, may be created free of electromigration and self heat violations.
  • an electromigration and self heat check (EMSH Check) tool analyzes a mask layout file for electromigration and self heat violations and identifies any violations in an output file.
  • a layout designer may use the output file to manually eliminate the identified electromigration and self heat violations.
  • DRC Design Rule Check
  • LVS Layerout vs. Schematics
  • the present invention may eliminate electromigration and self heat violations from a mask layout block before the mask layout block is converted into a mask layout file.
  • the time needed to complete the design process for the integrated circuit therefore, may be substantially reduced since the steps of checking the layout with an EMSH tool and correcting the identified electromigration and self heat violations may be eliminated.
  • FIG. 1 illustrates four Metals wires. These are given without electromigration or self heat analysis
  • FIG. 2 illustrates four Metals, each selected and analyzed for electromigration and/or self heat violation.
  • Metal 1 wire has LENGTH violation shown as a dashed line violation marker.
  • Metal 2 wire has WIDTH violation shown as a dashed line violation marker.
  • Metal 3 wire has PARTIAL WIDTH violation shown as a dashed line violation marker.
  • Metal 4 wire has WIDTH and LENGTH violation shown as a dashed line violation marker.
  • the boundaries of the violation marker have to be met in order to eliminate the electromigration and/or self heat violation
  • FIG. 3 illustrates the information window.
  • an information window is opened.
  • User has the option to FIX the selected polygon by clicking on the: FIX button or close it by clicking on the Close button;
  • FIG. 4 illustrates a layout view of the example Metals connections.
  • two (2) Metals [Metal 1 and Metal 2] are connected through two (2) VIA's.
  • FIG. 5 illustrates a layout view of the example Metals connections.
  • two (2) Metals [Metal 1 and Metal 2] are connected through two (2) VIA's.
  • the information window shows the system's recommendation to place four (4) VIA's in order to connect the two (2) metals.
  • the user has the option to automatically correct the situation by clicking on the: FIX button, located within the Information Window.
  • the system Upon clicking on the FIX button in the Information Window, the system will create a new layout within the connection area (Surrounded by GREEN rectangle) and place four (4) VIA's.
  • the system maintains all design rules dimensions according to technology file.
  • FIG. 6 illustrates the tool's basic interface with layout editor.
  • the system offers Advise mode and Correct mode.
  • Advise Mode - User receives graphical feedback during IC layout construction. No automatic correction is performed.
  • Correct Mode - User actions are automatically corrected by the system to eliminate electromigration and/or self heat violations, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness. User may check both options to activate the two modes at the same time. If none of these modes are checked, the system is disconnected from the layout editor.
  • DRC Clean process design rules
  • LVS Clean layout connectivity
  • FIG. 7 illustrates the tool's option to check the entire cell. With the selection of this option the entire cell that is loaded within the layout editor window is checked for electromigration and self heat. Violation(s) will be shown as violation markers. In addition a log file is generated with a complete coordinates and description of each violation.
  • FIG. 8 illustrates a flow chart for one example of a method for eliminating electromigration and/or self heat violations during construction of a mask layout block in accordance with teachings of the present invention.
  • the processing instructions may include a commercially available layout editor interfaced with an electromigration-self-heat Aware (EMSH Aware) tool.
  • EMSH Aware electromigration-self-heat Aware
  • the EMSH Aware tool may provide the ability to analyze the width, length and placement of polygons in a mask layout block and determine if an electromigration and/or self heat violation is created.
  • the EMSH Aware tool may provide the ability to analyze the number of contacts and VIA's, determine the amount needed in order to comply with electromigration and self heat rules.
  • the EMSH Aware tool may be operated in two different modes: an Advise mode and a Correct mode.
  • the EMSH Aware tool may graphically display a violation marker which shows the required width, length or space of the selected polygon without violating any electromigration and/or self heat or design rules included in a technology and/or external constraints file.
  • the EMSH Aware tool may prevent or adjust the creation, placement or edition of polygons in order to eliminate electromigration and/or self heat and design rule violation, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness.
  • DRC Clean process design rules
  • LVS Clean layout connectivity
  • the EMSH Aware tool reads a technology and/or external constraints file corresponding to a desired manufacturing process.
  • the technology file may contain design rules for the desired manufacturing process that ensures an integrated circuit fabricated on a semiconductor wafer functions correctly.
  • the technology file may contain electromigration and self heat rules to ensure reliable integrated circuit operation for desired time period.
  • the tool has an option to read another constraints file which contains layout extraction information (resistance and capacitance values) per circuit net.
  • the electromigration and self heat rules may define the minimum or maximum allowable feature dimensions (e.g., metal and polysilicons wires width, spaces and length) for the desired manufacturing process.
  • the EMSH Aware tool uses the electromigration and self heat rules to prevent the layout designer from creating electromigration and self heat violations during the construction of the mask layout block, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness.
  • DRC Clean process design rules
  • LVS Clean layout connectivity
  • the layout designer may select a polygon by moving a cursor over the desired polygon or selecting it.
  • the EMSH Aware tool uses the electromigration and self heat rules to graphically display the required length, width or space through a violation marker, within the mask layout block where the layout designer may move, place, create or edit a polygon. If the layout designers selects, create or move contacts or VIA's the EMSH Aware tool may graphically guide for the amount, location and space of the contacts or VIA's, maintaining the process design rules (DRC Clean) and layout connectivity (LVS Clean) correctness.
  • DRC Clean process design rules
  • LVS Clean layout connectivity
  • the EMSH Aware tool may graphically represent the violation marker in the mask layout block by highlighting the required width, length or space with an appropriate color and/or pattern.
  • the violation marker color and/or pattern can be set in an initial tool setup.
  • the EMSH Aware tool may show an Information Window with the current and required conditions. The Information Window also provides with the option to correct the violation.
  • the EMSH Aware tool may prevent the layout designer from creating, placing or editing a polygon in a position within the mask layout block that will cause an electromigration and/or self heat violation. If the layout designer attempts to create a polygon in a certain width or length that does not comply with the electromigration and/or self heat requirements, the EMSH Aware tool automatically adjusts the polygon to the correct width or length size. Another example, if the layout designer is stretching a metal polygon's edge, the EMSH Aware tool automatically stretches the edge to the required length to comply with electromigration and/or self heat rule.
  • the EMSH Aware tool will automatically adjust the amount and location of the VIA's to meet electromigration and/or self heat rules.
  • the VIA's that will be placed maintaining design rule correctness regarding distance, width, length and metal coverage.
  • the EMSH Aware tool is included an entire layout block Check mode. This mode is aimed to be activation with the completion of the entire layout block. Using this feature the entire block will be analyzed for electromigration and self heat violations. When analysis is complete all violations will be shown using violation marker. This mode operates in flat or fully hierarchical mode.
  • the processing instructions for correcting electromigration and/or self heat violations in a mask layout file may be encoded in computer- usable media.
  • Such computer-usable media may include, without limitation, storage media such as floppy disks, hard disks, CD-ROMS, DVDs, read-only memory, and random access memory; as well as communications media such wires, optical fibers, microwaves, radio waves, and other electromagnetic or optical carriers.

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  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention concerne un système et un procédé pour une élimination automatique de violations d'électromigration (EM) et de chauffage automatique (SH) pendant la construction d'un bloc de disposition de masque, en maintenant l'exactitude des règles de conception de processus (DRC propre) et de la connectivité de disposition (LVS propre). Le procédé comprend l'analyse d'un polygone sélectionné pour l'espace, la largeur et la longueur, dans un bloc de disposition de masque, et l'obtention d'une ou de plusieurs règles d'électromigration et/ou de chauffage automatique associées au polygone à partir d'une technologie et d'un fichier externe de contraintes. Le procédé comprend également l'analyse de contacts et de VIA concernant la quantité et l'emplacement, pour une conformité à des règles d'électromigration et de chauffage automatique. Le procédé propose un marqueur de violation associé à la position sélectionnée du polygone, représentant graphiquement une largeur, un espace, une longueur et d'autres caractéristiques physiques du polygone dans le bloc de disposition de masque, le polygone sélectionné répondant à la violation d'électromigration et/ou de chauffage automatique. Le procédé et le système proposent également une option pour corriger automatiquement la violation d'électromigration (EM) et de chauffage automatique du bloc de disposition de masque, en maintenant l'exactitude des règles de conception de processus (DRC propre) et de la connectivité de disposition (LVS propre).
PCT/US2007/003253 2007-02-06 2007-02-06 Système et procédé pour une élimination automatique de violations d'électromigration et de chauffage automatique pendant la construction d'un bloc de disposition de masque, en maintenant l'exactitude des règles de conception de processus (drc propre) et de la connectivité de disposition (l WO2008097219A2 (fr)

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PCT/US2007/003253 WO2008097219A2 (fr) 2007-02-06 2007-02-06 Système et procédé pour une élimination automatique de violations d'électromigration et de chauffage automatique pendant la construction d'un bloc de disposition de masque, en maintenant l'exactitude des règles de conception de processus (drc propre) et de la connectivité de disposition (l

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PCT/US2007/003253 WO2008097219A2 (fr) 2007-02-06 2007-02-06 Système et procédé pour une élimination automatique de violations d'électromigration et de chauffage automatique pendant la construction d'un bloc de disposition de masque, en maintenant l'exactitude des règles de conception de processus (drc propre) et de la connectivité de disposition (l

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8082525B2 (en) * 2008-04-15 2011-12-20 Luminescent Technologies, Inc. Technique for correcting hotspots in mask patterns and write patterns

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5581475A (en) * 1993-08-13 1996-12-03 Harris Corporation Method for interactively tailoring topography of integrated circuit layout in accordance with electromigration model-based minimum width metal and contact/via rules
US20060101367A1 (en) * 2004-11-08 2006-05-11 Matsushita Electric Industrial Co., Ltd. Design method of semiconductor device and semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5581475A (en) * 1993-08-13 1996-12-03 Harris Corporation Method for interactively tailoring topography of integrated circuit layout in accordance with electromigration model-based minimum width metal and contact/via rules
US20060101367A1 (en) * 2004-11-08 2006-05-11 Matsushita Electric Industrial Co., Ltd. Design method of semiconductor device and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8082525B2 (en) * 2008-04-15 2011-12-20 Luminescent Technologies, Inc. Technique for correcting hotspots in mask patterns and write patterns

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