WO2008081806A1 - 配線膜の形成方法、トランジスタ、及び電子装置 - Google Patents

配線膜の形成方法、トランジスタ、及び電子装置 Download PDF

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Publication number
WO2008081806A1
WO2008081806A1 PCT/JP2007/074931 JP2007074931W WO2008081806A1 WO 2008081806 A1 WO2008081806 A1 WO 2008081806A1 JP 2007074931 W JP2007074931 W JP 2007074931W WO 2008081806 A1 WO2008081806 A1 WO 2008081806A1
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WIPO (PCT)
Prior art keywords
film
wiring film
transistor
electronic device
metallic
Prior art date
Application number
PCT/JP2007/074931
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English (en)
French (fr)
Inventor
Satoru Takasawa
Masaki Takei
Hirohisa Takahashi
Hiroaki Katagiri
Sadayuki Ukishima
Noriaki Tani
Satoru Ishibashi
Tadashi Masuda
Original Assignee
Ulvac, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ulvac, Inc. filed Critical Ulvac, Inc.
Priority to KR1020097008421A priority Critical patent/KR101135418B1/ko
Priority to EP07860160.6A priority patent/EP2096666A4/en
Priority to JP2008552119A priority patent/JP5017282B2/ja
Priority to KR1020117011099A priority patent/KR101073421B1/ko
Priority to CN2007800404022A priority patent/CN101529566B/zh
Publication of WO2008081806A1 publication Critical patent/WO2008081806A1/ja
Priority to US12/475,907 priority patent/US8218122B2/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02631Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233Copper alloys
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/16Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation by cathodic sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Physical Vapour Deposition (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Liquid Crystal (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

 密着性とバリア性に優れ、抵抗値が低い配線膜を形成する。成膜対象物21が配置された真空槽2に酸素ガスを導入し、酸素を含む真空雰囲気中で、銅を主成分とし、Mgと、Alと、Siと、Beと、Caと、Srと、Baと、Raと、Scと、Yと、Laと、Ceと、Prと、Ndと、Pmと、Smと、Euと、Gdと、Tbと、Dyとからなる添加元素群より選択される少なくとも1種類の添加元素が含有されたスパッタリングターゲット11をスパッタリングし、成膜対象物21の表面に第一の金属膜23を成膜した後、酸素ガスの導入を停止した状態でスパッタリングターゲット11をスパッタリングし、第一の金属膜23の表面に第二の金属膜24を形成した後、第一、第二の金属膜23、24をエッチングして配線膜を形成する。
PCT/JP2007/074931 2006-12-28 2007-12-26 配線膜の形成方法、トランジスタ、及び電子装置 WO2008081806A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1020097008421A KR101135418B1 (ko) 2006-12-28 2007-12-26 배선막의 형성 방법, 트랜지스터, 및 전자 장치
EP07860160.6A EP2096666A4 (en) 2006-12-28 2007-12-26 METHOD FOR PRODUCING A WIRING FOIL, TRANSISTOR AND ELECTRONIC DEVICE
JP2008552119A JP5017282B2 (ja) 2006-12-28 2007-12-26 配線膜の形成方法
KR1020117011099A KR101073421B1 (ko) 2006-12-28 2007-12-26 배선막의 형성 방법, 트랜지스터, 및 전자 장치
CN2007800404022A CN101529566B (zh) 2006-12-28 2007-12-26 布线膜的形成方法、晶体管及电子装置
US12/475,907 US8218122B2 (en) 2006-12-28 2009-06-01 Method for forming wiring film, transistor and electronic device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2006-354860 2006-12-28
JP2006-354859 2006-12-28
JP2006354860 2006-12-28
JP2006354859 2006-12-28

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/475,907 Continuation US8218122B2 (en) 2006-12-28 2009-06-01 Method for forming wiring film, transistor and electronic device

Publications (1)

Publication Number Publication Date
WO2008081806A1 true WO2008081806A1 (ja) 2008-07-10

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PCT/JP2007/074931 WO2008081806A1 (ja) 2006-12-28 2007-12-26 配線膜の形成方法、トランジスタ、及び電子装置

Country Status (7)

Country Link
US (1) US8218122B2 (ja)
EP (1) EP2096666A4 (ja)
JP (1) JP5017282B2 (ja)
KR (2) KR101135418B1 (ja)
CN (1) CN101529566B (ja)
TW (1) TWI430396B (ja)
WO (1) WO2008081806A1 (ja)

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008311283A (ja) * 2007-06-12 2008-12-25 Mitsubishi Materials Corp 密着性に優れた配線下地膜およびこの配線下地膜を形成するためのスパッタリングターゲット
JP2009043797A (ja) * 2007-08-07 2009-02-26 Mitsubishi Materials Corp 薄膜トランジスター
JP2009170769A (ja) * 2008-01-18 2009-07-30 Mitsubishi Materials Corp 薄膜トランジスター
JP2010040535A (ja) * 2008-07-31 2010-02-18 Mitsubishi Materials Corp 薄膜トランジスター
JP2010040536A (ja) * 2008-07-31 2010-02-18 Mitsubishi Materials Corp 薄膜トランジスター
JP2010045322A (ja) * 2008-02-19 2010-02-25 Mitsubishi Materials Corp 薄膜トランジスター
JP2010066529A (ja) * 2008-09-11 2010-03-25 Hitachi Displays Ltd 液晶表示装置、及びその製造方法
JP2010080681A (ja) * 2008-09-26 2010-04-08 Mitsubishi Materials Corp 薄膜トランジスター
JP2010103324A (ja) * 2008-10-24 2010-05-06 Mitsubishi Materials Corp バリア膜とドレイン電極膜およびソース電極膜が高い密着強度を有する薄膜トランジスター
WO2010082638A1 (ja) * 2009-01-16 2010-07-22 株式会社神戸製鋼所 Cu合金膜および表示デバイス
WO2010082637A1 (ja) * 2009-01-16 2010-07-22 株式会社神戸製鋼所 表示装置
JP2010165955A (ja) * 2009-01-16 2010-07-29 Kobe Steel Ltd Cu合金膜および表示デバイス
JP2010212465A (ja) * 2009-03-11 2010-09-24 Mitsubishi Materials Corp バリア層を構成層とする薄膜トランジスターおよび前記バリア層のスパッタ成膜に用いられるCu合金スパッタリングターゲット
WO2010143609A1 (ja) * 2009-06-12 2010-12-16 株式会社アルバック 電子装置の形成方法、電子装置、半導体装置及びトランジスタ
WO2011024770A1 (ja) * 2009-08-26 2011-03-03 株式会社アルバック 半導体装置、半導体装置を有する液晶表示装置、半導体装置の製造方法
WO2011024704A1 (ja) * 2009-08-28 2011-03-03 株式会社アルバック 配線層、半導体装置、液晶表示装置
JP2011049505A (ja) * 2009-08-28 2011-03-10 Mitsubishi Materials Corp 半導体装置、その製造方法及びその製造方法に用いるスパッタリングターゲット
WO2011052471A1 (ja) * 2009-10-27 2011-05-05 株式会社アルバック 配線層、半導体装置、半導体装置を有する液晶表示装置
KR101184240B1 (ko) 2008-10-24 2012-09-21 가부시키가이샤 알박 박막 트랜지스터의 제조 방법, 박막 트랜지스터
JP2013503459A (ja) * 2009-08-26 2013-01-31 ヘレーウス マテリアルズ テクノロジー ゲゼルシャフト ミット ベシュレンクテル ハフツング ウント コンパニー コマンディートゲゼルシャフト 銅電極を有する薄膜トランジスタ(tft)
JP2013179265A (ja) * 2012-01-31 2013-09-09 Hitachi Metals Ltd 電子部品用積層配線膜
JP2013541192A (ja) * 2010-09-03 2013-11-07 アプライド マテリアルズ インコーポレイテッド スタガー薄膜トランジスタおよびその形成方法
US8624397B2 (en) 2009-06-12 2014-01-07 Mitsubishi Materials Corporation Electrode layer structure for a thin-film transistor and process for manufacture thereof
JP2015065471A (ja) * 2009-10-09 2015-04-09 株式会社半導体エネルギー研究所 半導体装置
JP2019114799A (ja) * 2008-11-07 2019-07-11 株式会社半導体エネルギー研究所 半導体装置

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CN104064454A (zh) 2014-06-11 2014-09-24 京东方科技集团股份有限公司 薄膜及阵列基板的制备方法、阵列基板
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Cited By (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008311283A (ja) * 2007-06-12 2008-12-25 Mitsubishi Materials Corp 密着性に優れた配線下地膜およびこの配線下地膜を形成するためのスパッタリングターゲット
JP2009043797A (ja) * 2007-08-07 2009-02-26 Mitsubishi Materials Corp 薄膜トランジスター
JP2009170769A (ja) * 2008-01-18 2009-07-30 Mitsubishi Materials Corp 薄膜トランジスター
JP2010045322A (ja) * 2008-02-19 2010-02-25 Mitsubishi Materials Corp 薄膜トランジスター
JP2010040536A (ja) * 2008-07-31 2010-02-18 Mitsubishi Materials Corp 薄膜トランジスター
JP2010040535A (ja) * 2008-07-31 2010-02-18 Mitsubishi Materials Corp 薄膜トランジスター
JP2010066529A (ja) * 2008-09-11 2010-03-25 Hitachi Displays Ltd 液晶表示装置、及びその製造方法
KR101527626B1 (ko) * 2008-09-26 2015-06-09 미쓰비시 마테리알 가부시키가이샤 박막 트랜지스터 및 박막 트랜지스터 중간체
JP2010080681A (ja) * 2008-09-26 2010-04-08 Mitsubishi Materials Corp 薄膜トランジスター
US20110133190A1 (en) * 2008-09-26 2011-06-09 Mitsubishi Materials Corporation Thin-film transistor and intermediate of thin-film transistor
CN102165596B (zh) * 2008-09-26 2014-07-09 三菱综合材料株式会社 薄膜晶体管及薄膜晶体管中间体
TWI476930B (zh) * 2008-09-26 2015-03-11 Mitsubishi Materials Corp 薄膜電晶體及薄膜電晶體中間體
US8502285B2 (en) * 2008-09-26 2013-08-06 Mitsubishi Materials Corporation Thin-film transistor and intermediate of thin-film transistor
CN102165596A (zh) * 2008-09-26 2011-08-24 三菱综合材料株式会社 薄膜晶体管及薄膜晶体管中间体
JP2010103324A (ja) * 2008-10-24 2010-05-06 Mitsubishi Materials Corp バリア膜とドレイン電極膜およびソース電極膜が高い密着強度を有する薄膜トランジスター
US8384083B2 (en) 2008-10-24 2013-02-26 Mitsubishi Materials Corporation Thin-film transistor having high adhesive strength between barrier film and drain electrode and source electrode films
JP5285710B2 (ja) * 2008-10-24 2013-09-11 三菱マテリアル株式会社 薄膜トランジスタの製造方法
US8470651B2 (en) 2008-10-24 2013-06-25 Mitsubishi Materials Corporation Method for producing a thin film transistor, and a thin film transistor
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JP2019114799A (ja) * 2008-11-07 2019-07-11 株式会社半導体エネルギー研究所 半導体装置
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US20090303406A1 (en) 2009-12-10
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TW200839946A (en) 2008-10-01
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EP2096666A1 (en) 2009-09-02

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