WO2008035432A1 - Dispositif de stockage à semi-conducteur, procédé pour fabriquer un dispositif de stockage à semi-conducteur, procédé d'écriture de dispositif de stockage à semi-conducteur et procédé de lecture de dispositif de stockage à semi-conducteur - Google Patents

Dispositif de stockage à semi-conducteur, procédé pour fabriquer un dispositif de stockage à semi-conducteur, procédé d'écriture de dispositif de stockage à semi-conducteur et procédé de lecture de dispositif de stockage à semi-conducteur Download PDF

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Publication number
WO2008035432A1
WO2008035432A1 PCT/JP2006/318832 JP2006318832W WO2008035432A1 WO 2008035432 A1 WO2008035432 A1 WO 2008035432A1 JP 2006318832 W JP2006318832 W JP 2006318832W WO 2008035432 A1 WO2008035432 A1 WO 2008035432A1
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WIPO (PCT)
Prior art keywords
resistance
memory
selection transistor
electrode
resistance memory
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PCT/JP2006/318832
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English (en)
Japanese (ja)
Inventor
Kentaro Kinoshita
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Fujitsu Limited
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Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2008535249A priority Critical patent/JP5062176B2/ja
Priority to PCT/JP2006/318832 priority patent/WO2008035432A1/fr
Publication of WO2008035432A1 publication Critical patent/WO2008035432A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/32—Material having simple binary metal oxide structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/34—Material includes an oxide or a nitride
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • Semiconductor memory device semiconductor memory device manufacturing method, semiconductor memory device writing method, and semiconductor memory device reading method
  • the present invention relates to a semiconductor memory device including memory cells including a resistance memory that stores information by changing electrical resistance.
  • a RRAM Resistance Random Access Memory
  • a RRAM has a cell array in which a large number of memory cells capable of storing “0” and “1” are arranged in a lattice like a flash memory, etc.
  • increasing the density of memory cells is an important issue.
  • each memory cell is provided with a resistance memory and a selection transistor that applies a voltage to the resistance memory.
  • Each memory cell is connected to the bit line BL and the word line WL and also to the source line SL for applying a reference potential (FIG. 3 of Patent Document 1).
  • a selection transistor is formed on a silicon substrate, and its source region is connected to a source line SL via a contact plug.
  • the drain region of the selected transistor is connected to the resistance memory (one electrode) via a contact plug, and the other electrode of the resistance memory is connected to the bit line BL via a contact plug.
  • Patent Document 1 JP 2005-25914 A
  • Non-Patent Document 1 1. G. Baek et al, Tech. DigestlEDM 2004, p.587
  • the conventional RRAM has a structure in which a large number of layers are formed on a silicon substrate having a memory cell strength, and thus there is a problem that many manufacturing processes are required.
  • the volume occupied by the memory cell is increased, and the memory in the RRAM is increased.
  • the mounting density of the Mori cell was lowered.
  • the drain force of the selection transistor resistance memory (two layers disposed on both ends of the resistance memory material layer and the resistance memory material layer) As a result, the number of layers formed on the substrate is increased, preventing high density.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide an RRAM having a simple configuration of a memory cell and realizing high density of the memory cell.
  • the above problems can be solved by adopting a circuit configuration that does not use the source line SL connected to the memory cell, and a simple configuration for each memory cell.
  • a semiconductor memory device of the present invention includes a plurality of word lines, a plurality of bit lines arranged in a direction intersecting the word lines, and the word lines and the bit lines.
  • the memory cells are respectively arranged at positions intersecting with the gate lines.
  • each of the plurality of memory cells includes a force resistance memory, a selection transistor that controls application of a voltage to the resistance memory, and each of the memory cells includes a selection transistor.
  • the drain is connected to one electrode of the resistance memory
  • the word line is connected to the gates of the plurality of selection transistors included in a memory cell group arranged along the word line, and the memory cell Connected to the other electrode of the plurality of resistance memory bodies included in the group, and the bit line is connected to sources of the plurality of selection transistors included in the memory cell group arranged along the bit line. It is characterized by.
  • a method for manufacturing a semiconductor memory device of the present invention includes a plurality of word lines, a plurality of bit lines arranged in a direction intersecting the word lines, and a resistance.
  • a method of manufacturing a semiconductor memory device wherein a memory cell having a memory and disposed at a position where the word line and the bit line intersect is formed on a substrate. Further, a first step of forming a selection transistor on the substrate, the gate electrode of which is electrically connected to the word line and controlling the application of voltage to the resistance memory, and the selection. A portion of the gate electrode is exposed on the substrate on which the select transistor is formed.
  • a second step of forming a first film having an insulating material force; and the gate electrode on the gate electrode Forming a resistance memory layer of the resistance memory so as to be in contact with the exposed portion of the gate electrode, and forming a second film having an insulating material force so that a part of the resistance memory layer is exposed. And forming a first contact plug connected to the drain region of the selection transistor by filling the hole with a conductive material after drilling the first film and the second film. Forming a wiring for electrically connecting the exposed portion of the resistance memory layer and the first contact plug, and covering the entire wiring with a third film made of an insulating material. And a sixth step of forming the bit line electrically connected to the source region of the selection transistor.
  • the bias voltage applied to the memory cell is applied from the bit line BL and the word line WL. Therefore, according to the present invention, the source line SL is not required, and the memory cell can have a simple structure. It becomes possible. As a result, it is possible to provide a semiconductor memory device in which memory cells are arranged at high density.
  • FIG. 1 is a graph showing current-voltage characteristics of a resistive memory according to Example 1 of the present invention.
  • FIG. 2A and FIG. 2B are diagrams showing a basic configuration of a memory cell in the semiconductor memory device according to Embodiment 1 of the present invention.
  • FIG. 3 is a circuit diagram of a memory cell array according to Embodiment 1 of the present invention.
  • FIGS. 4A and 4B are time charts of write control in the memory cell array according to Embodiment 1 of the present invention.
  • FIG. 5 is a view showing a time chart of read control in the memory cell array according to Embodiment 1 of the present invention.
  • 6A and 6B are diagrams (a plan view and a cross-sectional view) showing an arrangement of the memory cell array according to Embodiment 1 of the present invention.
  • FIG. 7A to FIG. 7C are diagrams showing a manufacturing process (part 1) of a memory cell array according to Embodiment 1 of the present invention.
  • FIGS. 8D to 8F show the manufacturing process of the memory cell array according to Embodiment 1 of the present invention (part 2).
  • FIG. 8 shows the manufacturing process of the memory cell array according to Embodiment 1 of the present invention (part 2).
  • FIG. 9G to FIG. 91 are views showing a manufacturing process (part 3) of the memory cell array according to Embodiment 1 of the present invention.
  • FIG. 10J to FIG. 10L are views showing a manufacturing process (No. 4) of the memory cell array according to Embodiment 1 of the present invention.
  • FIG. 11A and FIG. 11B are diagrams showing a basic configuration of a memory cell in a semiconductor memory device according to Embodiment 2 of the present invention.
  • FIG. 12 is a circuit diagram of a memory cell array according to Embodiment 2 of the present invention.
  • FIGS. 13A and 13B are diagrams (a plan view and a cross-sectional view) showing an arrangement of a memory cell array according to Embodiment 2 of the present invention. It is sectional drawing.
  • FIG. 14A and FIG. 14B are diagrams showing a basic configuration of a memory cell in a semiconductor memory device according to Embodiment 3 of the present invention.
  • FIG. 1 is a graph when titanium oxide (TiO 2) is used as the resistance memory material.
  • the initial state (high resistance state) of the resistance memory be a point.
  • the current gradually increases along curve A.
  • the applied voltage increases further and exceeds approximately 1.5V (point b in the figure)
  • the resistance memory switches (sets) from the high resistance state to the low resistance state.
  • the current value is approximately 2 mA and constant (straight line B) from the point b to the point c. This is because the current is limited. That is, the resistance memory has already transitioned to the low resistance state at the point b. Therefore, if the current limit is removed, a large current will flow through the resistance memory, and the resistance memory may be damaged.
  • the resistance memory is switched (reset) from the low resistance state to the high resistance state.
  • the absolute value of the current sharply decreases, and the current-voltage characteristics transition from point d to point e.
  • the applied voltage is If the voltage is lower than the voltage at point b (about 1.5V), the current-voltage characteristics change linearly along curve A and the high resistance state is maintained. Similarly, in the low resistance state, if the applied voltage is lower than the voltage at point d (approximately 0.7V), the current-voltage characteristics change along curve C and the low resistance state is maintained. That is, no matter what the resistance state of the resistance memory is, it is stable if the voltage applied to the resistance memory is lower than a predetermined voltage (in this case, for example, 0.7 V). The resistance state at the time is maintained.
  • a predetermined voltage in this case, for example, 0.7 V
  • the characteristics shown in FIG. 1 are not necessarily obtained in the initial state immediately after the element formation.
  • a process called forming may be required. In forming, a voltage higher than the set voltage is applied to the resistance memory material. Once the forming is performed, the resistance memory does not return to the initial state.
  • FIG. 2A is a circuit diagram illustrating a memory cell in the semiconductor memory device according to the first embodiment
  • FIG. 2B is a schematic cross-sectional view illustrating a structure of the memory cell in the semiconductor memory device according to the first embodiment.
  • the memory cell 10 of the semiconductor memory device includes a resistance memory body 12 and a selection transistor 14.
  • the source S of the selection transistor 14 is connected to the bit line BL, and the gate G is connected to the word line WL.
  • the resistance memory 12 has one end connected to the drain D of the selection transistor 14 and the other end connected to the word line WL.
  • the resistance memory 12 is a force in which a resistance memory layer 12b that also has a resistance memory material force is sandwiched between a pair of electrodes (lower electrode 12a, upper electrode 12c).
  • a unipolar resistive memory material such as TiO is used.
  • the selection transistor 14 is formed on the silicon substrate 11.
  • the drain region 18 of the selection transistor 14 is connected to one electrode 12c of the resistance memory 12 via a contact plug 25.
  • Resistance The resistance memory layer 12 b of the anti-memory body 12 is connected to the gate electrode G of the selection transistor 14.
  • the source region 16 of the selection transistor 14 is connected to the bit line 17 via the contact plug 24.
  • FIG. 2B shows an example in which the lower electrode 12a of the resistance memory 12 is not provided between the resistance memory layer 12b and the gate electrode G, and the lower electrode 12a is substituted for the gate electrode G.
  • the lower electrode 12a may be arranged between the gate electrode G and the gate electrode G.
  • the gate G of the selection transistor 14 extends from the front side to the back side of the paper surface (ie, in a direction perpendicular to the paper surface). (Hereinafter, the direction in which the gate G extends is referred to as the “row direction.”)
  • the gate G also has a function as a word line WL that connects the gates G of the select transistors 14 arranged in the row direction. .
  • the lead wire WL also serves as the electrode 12a of the resistance memory 12.
  • the selection transistor 14 is, for example, an N-channel MOS transistor, and the selection transistor 14 having a threshold voltage Vth of 0.4 V is used.
  • FIG. 3 is a diagram showing a circuit of the memory cell array 20 in which the memory cells 10 of FIG. 2 are arranged in a matrix.
  • Figure 6 shows an example in which the memory cell array shown in Fig. 3 is actually placed on a silicon substrate. As shown in FIG. 6, the memory cells 10 are arranged side by side in the row direction and the column direction.
  • each word line is connected to the gate G of the selection transistor 14 of each memory cell 10 and also connected to one end of the resistance memory 12 (connected to the selection transistor 14).
  • bit lines BL1, BL2, BL3, B L4-... are arranged in parallel extending in the column direction, and these bit lines are arranged in the column direction.
  • a plurality of memory cells 10 are connected to each other. Specifically, each bit line BL is connected to the source S of the selected transistor 14 of each memory cell 10.
  • each bit line BL has a function as a variable resistance element.
  • the bit line selection transistor 17—1, 17-2, 17-3, 17—4 reads the data stored in each memory sensor 10 (not shown) before the sense amplifier. Each is provided.
  • FIG. 4 is a time chart of write control in the memory cell array 20 shown in FIG.
  • Step 1 The bit line BL1 is set to a reference potential (eg, ground potential OV).
  • the state before the bit line BL1 is set to the reference potential is, for example, a flow state that is not connected to a predetermined voltage.
  • the word line WL1 is set to, for example, the ground potential OV.
  • Step 2 A bias voltage is applied to the word line WL1.
  • the value of the bias voltage is 2. OV.
  • the initial state of the word line WL1 is, for example, the ground potential OV.
  • Step 3 A voltage based on the bias voltage is also applied between the gate G and source S of the selection transistor 14 together with the application of the bias voltage.
  • Vth threshold voltage
  • the selection transistor 14 is turned on, and the bias voltage is selected from the resistance memory 12.
  • OV is distributed according to the resistance value Rh of the resistance memory 12 in the high resistance state and the channel resistance Rch of the selection transistor 14.
  • the selection transistor 14 is turned off, the voltage at the drain D of the selection transistor 14 is equal to the voltage at WL.
  • the voltage is substantially the same as the voltage, and almost no voltage is applied to the resistance memory 12.
  • the resistance value Rh force (for example, high resistance state) of the resistance memory 12 is about 750 kQ, for example, and the channel resistance Rch force of the selection transistor 34 is 1. Ok ⁇ . Then, a voltage corresponding to such a divided resistance value is applied, 1.997 V is applied to the resistance memory 32, and the resistance memory 12 changes from the high resistance state to the low resistance state (set operation). To do.
  • Step 4 Next, the voltage of the word line WL1 is returned to OV. After that, disconnect from the ground potential of bit line BL1. Return to a flow state that is not connected to the specified voltage to complete the set operation.
  • a plurality of bit lines BL for example, BL1 to BL3
  • a plurality of memory cells 30 connected to the selected word line for example, WL1 are collectively collected. It is also possible to perform a set operation.
  • Step 1 The bit line BL1 is set to 0.8 V, for example. Specifically, before setting step 1, for example, the bit line BL1 is in a flow state that is not connected to a predetermined voltage, and when setting step 1, the bit line BL1 is set to 0.8V. .
  • Step 2 A bias voltage is applied to the word line WL1.
  • the value of the bias voltage is 2.0V, for example.
  • Vreset 0.7 V in this embodiment
  • the initial state of the word line WL1 is, for example, 0 V which is the ground potential.
  • Step 3 A voltage based on the bias voltage is applied between the gate G and source S of the selection transistor 14 together with the application of the bias voltage.
  • Vth threshold voltage
  • the selection transistor 14 is turned on, and the bias voltage is selected from the resistance memory 12.
  • 1.2V is the resistance of the resistance memory 12 in the high resistance state Distribution is performed according to the value Rh and the channel resistance Rch of the selection transistor 14.
  • the resistance value R1 (in the low resistance state) of the resistance memory 12 is about 10 kQ, for example, and the channel resistance Rch force of the selection transistor 34 is, for example, 1. OkQ. Then, a voltage corresponding to such a divided resistance value is applied, 10.9 V is applied to the resistance memory 12, and the resistance memory 12 changes from the low resistance state to the high resistance state (reset operation). To do.
  • Step 4 Next, the voltage of the word line WL1 is returned to 0V. After that, the connection with the ground potential of the bit line BL1 is released, the flow state is not connected to the predetermined voltage, and the reset operation is completed.
  • the resistance memory 12 In the reset operation, almost all of the bias voltage (1.2 V in this embodiment) is applied to the resistance memory 12 at the moment when the resistance memory 12 is switched from the low resistance state to the high resistance state. It is a little different from being applied. However, the voltage applied to the resistance memory 12 does not exceed 1.5 V, which is the reset voltage of the resistance memory 12. Therefore, the resistance memory 12 must be reset after the reset operation. There is nothing.
  • FIG. 5 shows a time chart of read control in the memory cell array 20 shown in FIG. The description will be made with respect to the memory sensor 10 surrounded by a dotted line in FIG.
  • Resistive memory 12 does not cause a set or reset operation. Therefore, the bias voltage to the memory cell 10 (the resistance memory 12 and the selection transistor 14) in the read control is set to 0.5 V, for example.
  • This set value is a value that secures a margin of 0.2V with respect to the above 0.7V.
  • the word line WL1 is set to 2.0 V, for example (step 1). That After that, for example, 1.5 V is applied to the bit line BL1 (step 2). In this way, 0.5V is applied as the read bias voltage.
  • the selection transistor 14 is turned on, and a 0.5V noise voltage is applied to the selection transistor 14 and the resistance memory 12 of the memory cell 10 (step 3).
  • the data write / read control described above shows a control method when an N-channel MOS type transistor is used as the selection transistor 14.
  • the force selection transistor 14 has a P-channel MOS type. Transistors can also be used. However, when a P-channel MOS transistor is used as the selection transistor 14, the control is performed so that the voltage value of the word line WL1 is lower than the voltage value of the bit line BL1 (as opposed to the control described above). However, it is necessary to store such a bias voltage in the memory cell.
  • FIG. 6A is a schematic cross-sectional view showing the structure of the memory cell array according to this embodiment
  • FIG. 6B is a view of the memory cell array of FIG. 6A as viewed from above.
  • FIG. 6A is a view showing a cut surface of line AA ′ in FIG. 6B.
  • an element isolation film 19 that defines an element region is formed on the silicon substrate 11.
  • a selection transistor 14 having a gate electrode 12a and source Z drain regions 16, 18 is formed.
  • the gate G of the selection transistor extends in the direction extending from the front to the back of the page, that is, in the row direction.
  • the gate G also has a function as a word line WL that connects the gates G of select transistors arranged side by side in the row direction. Note that the word line WL also serves as the electrode 12c of the resistance memory 12.
  • a contact plug 24 that is electrically connected to the source region 16 and an electric current to the drain region 18 are provided. Connected contact plugs 25 are formed. Further, an interlayer insulating film 13a is formed on the silicon substrate 11 so as to fill the periphery of the gate G and the contact plugs 24, 25.
  • a resistance memory layer 12b is formed on the gate G that also serves as the word line WL so as to be in contact with the gate G.
  • An interlayer insulating film 13b is formed on the interlayer insulating film 13a so as to cover and embed the periphery of the resistance memory layer 12b and the contact plugs 24, 25.
  • an upper electrode 12c (of the resistance memory 12) is formed on the resistance memory layer 12b so as to be in contact with the resistance memory layer 12b.
  • the upper electrode 12c extends to a position reaching the contact plug 25 connected to the drain region 18, and is connected to the contact plug 25.
  • an interlayer insulating film 13c is formed which covers the periphery of the upper electrode 12c and the contact plug 24 and embeds them.
  • the insulating film 13c is formed so as to cover the upper surface of the upper electrode 12c not only on the side surface of the upper electrode 12c.
  • a bit line BL 2 is formed on the contact plug 24 so as to be in contact with the contact plug 24.
  • the bit line BL2 extends in parallel along the paper surface.
  • the bit line BL is covered with an interlayer insulating film (not shown) formed on the interlayer insulating film 13c.
  • the bias voltage applied to the memory cell is configured to apply the bit line and word line force
  • the source line SL becomes unnecessary, and the process for forming the source line SL is reduced. Can do.
  • the overall mounting density can be increased.
  • the word line WL is one electrode (silicon) of the resistance memory 12. It can also serve as the electrode 12a) on the substrate side. As a result, the number of stacked layers constituting the memory cell 10 is reduced.
  • the other electrode (electrode 12c opposite to the silicon substrate) of the resistance memory 12 extends to a position reaching the contact plug 25 connected to the force source region 18, and the contact plug 25 Connected with.
  • the electrode 12c of the resistance memory 12 also serves as a wiring for connecting the resistance memory 12 and the contact plug 25, so that the wiring becomes unnecessary.
  • Step 1 As shown in FIG. 7A, a selection transistor having a gate electrode and source Z drain regions 16 and 18 is formed. Specifically, an element isolation film 19 that defines an element region is formed in the silicon substrate 11 by, for example, STI (Shallow Trench Isolation). Next, the selection transistor 14 having the gate electrode G (12a) and the source Z drain regions 16 and 18 is formed on the silicon substrate 11 by using an ordinary MOS transistor manufacturing method.
  • STI Shallow Trench Isolation
  • the gate electrode G for example, a polysilicon (polySi) material is used.
  • silicide (not shown) is formed on the upper surface of the polySi.
  • the silicide used here include NiSi, CoSi, TiSi, WSi, and MoSi.
  • silicide is formed by the following method. First, a cobalt (Co) film (not shown) is formed so as to cover the poly-Si gate electrode G by, for example, sputtering or CVD (Chemical Vapor Deposition). Subsequently, annealing is performed at several hundred degrees for several tens of seconds, and a part of PolySi is silicided. Thereafter, Co is removed by wet etching, and then annealing is performed at several hundred degrees for several tens of seconds to complete the formation of silicide. Such silicide may be formed on the surfaces of the source Z drain regions 16 and 18 that are formed only on the surface of the gate electrode G.
  • Step 2 As shown in FIG. 7B, a film 13a ′ for forming an interlayer insulating film is formed. Specifically, a silicon oxide film (SiO 2) is deposited on the silicon substrate 11 on which the selection transistor 14 is formed by, for example, a CVD (Chemical Vapor Deposition) method.
  • SiO 2 silicon oxide film
  • a film 13a ′ is formed.
  • Step 3 As shown in FIG. 7C, the deposited interlayer insulating film 13a ′ is polished to a thickness at which the tip of the gate G is exposed by, for example, CMP (Chemical Mechanical Polish), and the interlayer insulating film 13a is polished. Form. When performing the polishing process, the surface of the interlayer insulating film 13a is also planarized.
  • Step 4 As shown in FIG. 8D, a layer 12b ′ for forming the resistance memory layer 12b is formed.
  • a titanium oxide (TiO 2) film is deposited by, for example, a PLD (Pulsed Laser Deposition) method, a sol-gel method, a sputtering method, a MOCVD (Metal-Organic Chemical Vapor Deposition) method, and the resistance memory layer 12b is formed.
  • a layer 12b ′ for forming is formed.
  • the film thickness of TiO is, for example, 60 nm.
  • Step 5 As shown in FIG. 8E, the resistance memory layer 12b is formed. Specifically, the resistance memory layer 12b is formed by selectively patterning the layer 12b ′ formed in step 4 by, for example, photolithography and dry etching. The resistance memory layer 12b is formed at a position directly above the gate G so as to be in contact with the gate G (12a) of the selection transistor.
  • the material of the layer 12b ′ for forming the resistance memory layer 12b for example, TiO, NiO, YO, CeO, MgO, ZnO, Zr
  • Examples include oxides such as O, WO, NbO, TaO, CrO, MnO, AIO, VO, and SiO.
  • the material of the layer 12b '(resistance storage layer 12b) includes, for example, Ti, Ni, Y, Ce, Mg, Zn, Zr, W, Nb, Ta, Cr, Mn, Al, V And metals such as Si. Further, the material of the layer 12b ′ (resistance memory layer 12b) may be a mixture of these oxides and metals. Furthermore, the resistance memory layer 12b may have a structure in which the oxide layer and the metal layer are laminated.
  • layer 12b ′ resistance storage layer 12
  • the material of b) may be a mixture of these oxides and metals. Still further, the resistance memory layer 12b may have a structure in which the oxide layer and the metal layer are stacked.
  • Step 5 before forming the resistance memory element 12b, Pt, Ir, W, Ni ⁇ Au, Cu, Ag, Pd, Zn, Cr, Al are formed on the gate electrode G (12a). , Mn, Ta, Si ⁇ TaN, TiN, Si
  • Step 6 As shown in FIG. 8F, an interlayer insulating film 13b covering the periphery of the resistance memory layer 12b is formed. Specifically, a silicon oxide film (not shown) is deposited so as to cover the resistance memory layer 12b by, for example, the CVD method. Thereafter, the deposited silicon oxide film is polished by, eg, CMP to a thickness at which a part (tip surface) of the resistance memory layer 12b is exposed to form an interlayer insulating film 13b. When performing the polishing process, the surface of the interlayer insulating film 13b is also planarized.
  • Step 7 As shown in FIG. 9G, a contact hole 23 is formed. Specifically, for example, by photolithography and dry etching, a hole (through the interlayer insulating film 13a and the interlayer insulating film 13b) is made in the interlayer insulating film 13a and the interlayer insulating film 13b, and a contact hole reaching the drain region is formed. Form 23.
  • Step 8 As shown in FIG. 9H, a contact plug 25 is formed. Specifically, a tungsten (Ta) film is deposited on the contact hole 23 by, for example, the CVD method so that the contact hole 23 is completely filled. Thereafter, these deposits (barrier metal and tungsten film) are etched back to form contact plugs 25 electrically connected to the drain region. In this etch knocking process, etching is performed on the entire surface of the deposited Ta film so that the Ta film remains only in the contact hole 23, and the other (deposited outside the contact hole 23). Remove all Ta film.
  • a tungsten (Ta) film is deposited on the contact hole 23 by, for example, the CVD method so that the contact hole 23 is completely filled. Thereafter, these deposits (barrier metal and tungsten film) are etched back to form contact plugs 25 electrically connected to the drain region. In this etch knocking process, etching is performed on the entire surface of the deposited Ta film so that the Ta film remains only in the contact hole 23, and the other (deposited
  • Step 9 As shown in FIG. 91, the upper electrode 12c (of the resistance memory 12) is formed. Specifically, first, the upper electrode 12c is formed on the layer (the resistance memory layer 12, the contact plug 25, and the interlayer insulating film 13b covering the periphery thereof) flattened by the etch back process. A layer (not shown) is formed. Thereafter, the upper electrode 12c is formed by selectively patterning the layer for forming the upper electrode by, for example, photolithography and dry etching. At this time, the upper electrode 12c is patterned into a shape extending to a position reaching the contact plug 25 as shown in the figure.
  • the material of the upper electrode 12c is, for example, Pt, Ir, W, Ni, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN, TiN, Si N , Ru, ITO, NiO, IrO, SrRuO, CoSi
  • Step 10 As shown in FIG. 10J, an interlayer insulating film 13c covering the periphery and upper surface of the upper electrode 12c is formed. Specifically, a silicon oxide film (not shown) is deposited so as to cover the upper electrode 12c by, eg, CVD. Thereafter, the deposited silicon oxide film is polished to a predetermined thickness by, eg, CMP, to form an interlayer insulating film 13c. When performing the polishing process, the surface of the interlayer insulating film 13c is also planarized.
  • Step 11 As shown in FIG. 10K, a contact plug 24 is formed. Specifically, contact holes (not shown) are formed in the silicon oxide films 13a, 13b, 13c deposited up to the previous step by, for example, photolithography and dry etching. Next, a Ta film is deposited by CVD, for example, so that the contact hole is completely filled, and then this deposit (Ta film) is etched back. The contact plug 24 is formed by such processing.
  • Step 12 As shown in FIG. 10L, the bit line 17 and an interlayer insulating film (covering the periphery of the bit line 17, not shown) are formed. Specifically, first, a tungsten (Ta) film (not shown) is deposited by a PLD (Pulsed Laser Deposition) method, a sol-gel method, a sputtering method, a MOCVD (Metal Organic Chemical Vapor Deposition) method, or the like. Let At this time, the thickness of Ta is set to 60 nm, for example. Next, the bit line 17 is formed by selectively patterning the deposited Ta film by, for example, photolithography and dry etching.
  • PLD Pulsed Laser Deposition
  • sol-gel method sol-gel method
  • MOCVD Metal Organic Chemical Vapor Deposition
  • a silicon oxide film (not shown) is deposited so as to cover the bit line 17 by, eg, CVD. Thereafter, the deposited silicon oxide film is polished by, eg, CMP, to form a silicon oxide film (not shown). When the polishing process is performed, the surface of the deposited silicon oxide film is also planarized.
  • the bit line 17 and the interlayer insulating film may be formed by the following method. For example, after a silicon oxide film is first deposited by the CVD method on the layer formed by the step 11 (the layer consisting of the contact plug 24 and the interlayer insulating film 13c covering the periphery thereof), the CMP method, etc. The surface of the silicon oxide film deposited by is flattened. Next, a trench for forming the bit line 17 is formed on the deposited silicon oxide film by, for example, photolithography and dry etching (not shown).
  • bit line 17 is formed, and an interlayer insulating film covering the periphery of the bit line 17 (not shown) is formed.
  • the process of forming the source line SL becomes unnecessary, and the manufacturing process can be simplified. Become.
  • FIG. 11A is a circuit diagram illustrating a memory cell in the semiconductor memory device according to the second embodiment.
  • FIG. 11B is a schematic cross-sectional view illustrating the structure of the memory cell in the semiconductor memory device according to the second embodiment.
  • the memory cell 30 and the memory cell 50 are arranged adjacent to each other.
  • the memory cell 30 has a resistance memory 32 and a selection transistor 34
  • the memory cell 50 has a resistance memory 52 and a selection transistor 54.
  • the source S of the selection transistor 34 is connected to the bit line BL1, and the gate G is connected to the word line WL1.
  • One end of the resistance memory 32 is connected to the drain D of the selection transistor 34, and the other end is connected to the word line WL1.
  • the source S of the selection transistor 54 is connected to the bit line BL1, and the gate G is connected to the node line WL2.
  • One end of the resistance memory 52 is connected to the drain D of the selection transistor 54, and the other end is connected to the word line WL2.
  • the memory cell 30 and the memory cell 50 are connected by the drain D of the selection transistor provided in each memory cell (the drain D of the selection transistor 34 and the drain D of the selection transistor 54).
  • FIG. 11B shows a structure of memory cells 30 and 50 shown in FIG. 11A. As shown in FIG. 11B, the memory cell 30 and the memory cell 50 are arranged adjacent to each other on the silicon substrate 31. Specifically, the selection transistor 34 of the memory cell 30 and the selection transistor 54 of the memory cell 50 share one drain region 38.
  • the selection transistors 34 and 54 share one drain region 38. In addition to the selection transistors 34 and 54, one contact plug 45 is shared. Furthermore, the resistance memory 32 (52 of the memory cell 30 and the memory cell 50) 52, 52 force shares one electrode 32c.
  • the selection transistor 34 has a drain region 38, and the drain region 38 is connected to the upper electrode 32c of the resistance memory 32 via the contact plug 45.
  • the selection transistor 54 has a drain region 38 (same as the transistor 34), and the drain region 38 is connected to the upper electrode 32c via the contact plug 45.
  • the drain region 38, the contact plug 45, and the upper electrode 32c are shared by two adjacent memory cells 30, 50.
  • FIG. 12 is a diagram showing a circuit of memory cell array 40 in which memory cells 30 and 50 shown in FIG. 11 are arranged in a matrix.
  • FIG. 13 shows an example in which the memory cell array shown in FIG. 12 is actually arranged on a silicon substrate. As shown in FIG. 13, the memory cells 10 are arranged side by side in the row direction and the column direction.
  • FIG. 13A is a diagram showing a cut surface of line BB ′ in FIG. 13B.
  • a plurality of word lines WL1, WL2, WL3 ′ are arranged extending in the row direction. These word lines are respectively connected to a plurality of memory cells arranged in the row direction.
  • the word line WL1 is connected to the gate G of the selection transistor 34 of the memory cell 30 and to one end of the resistance memory 32 (connected to the selection transistor 34).
  • the word line WL2 is connected to the gate G of the selection transistor 54 of the memory cell 50 and to one end of the resistance memory 52 (connected to the selection transistor 54).
  • the selection transistor 34 of the memory cell 30 and the selection transistor 54 of the memory cell 50 have a common drain D. That is, the selection transistors 34 and 54 are coupled to each other at the drain D.
  • the resistance memory 32 of the memory cell 30 and the select transistor 52 of the memory cell 50 are connected to the ends not connected to the word lines (WL1, WL2). The rest of the configuration is the same as that of the first embodiment, and a description thereof will be omitted.
  • the memory cells arranged along the bit line are adjacent to each other.
  • the two memory cells are paired.
  • one drain region is shared by each selection transistor force included in the paired two memory cells.
  • two memory cells in a pair share one contact plug (connected to the drain region) and one upper electrode (of the resistance memory). Therefore, the mounting area occupied by one memory cell is reduced, and the mounting density of the memory cells in the semiconductor memory device is improved.
  • FIG. 14A is a circuit diagram illustrating a memory cell in the semiconductor memory device according to the third embodiment.
  • FIG. 14B is a schematic cross-sectional view illustrating the structure of the memory cell in the semiconductor memory device according to the third embodiment.
  • the memory cell 70 of the semiconductor memory device includes a resistance memory 72 and a selection transistor 74.
  • the source S of the selection transistor 74 is connected to the bit line BL, and the gate G is connected to the word line WL.
  • One end of the resistance memory 72 is connected to the drain D of the selection transistor 74 and the other end is connected to the word line WL.
  • FIG. 14B shows a structure of memory cell 70 shown in FIG. 14A.
  • a selection transistor 74 is formed on a silicon substrate 71.
  • the drain region 78 of the selection transistor 74 is connected to the resistance memory layer 72b via one electrode 72c of the resistance memory 72 that also serves as a contact plug.
  • the gate G of the selection transistor 74 is disposed on the opposite side of the electrode 72c across the resistance memory layer 72b.
  • the gate G of the selection transistor 74 also functions as the electrode 72c (of the resistance memory 72) and also functions as the word line WL.
  • a select transistor having a gate electrode 72a and source Z drain regions 16 and 18 is formed by the same method as in the first embodiment.
  • one side wall of the gate electrode 72a is removed and a part (on the side where the side wall is removed) of the gate electrode 72a is removed by, for example, photolithography and dry etching.
  • the removed portion is obtained.
  • a resistance memory layer 72b is formed, and an electrode 72c (of a resistance memory body) is formed on the side surface of the resistance memory layer 72b.
  • the rest of the configuration is the same as that of the first embodiment, and a description thereof will be omitted.
  • the two electrodes 72a and 72c constituting the resistance memory 72 and the resistance memory layer 72b sandwiched between them are arranged along the surface of the semiconductor substrate 71. Arranged. With this arrangement, the number of stacked layers when forming the memory cell 70 is reduced. In other words, by arranging the three components (two electrodes 72a and 72c and the resistance memory layer 72b) constituting the resistance memory 72 side by side along the surface of the semiconductor substrate 71, the electrode 72c is placed in the resistance memory layer 72b. Since there is no need to place it on top, the number of stacked layers is reduced accordingly. In addition, with the configuration in which the electrode 72c is not disposed on the resistance memory layer 72b, the surface force of the semiconductor substrate 71 can also be lowered to the bit line BL.
  • the semiconductor memory device and the manufacturing method thereof according to the present invention have a simple circuit configuration of the memory cell, and realize improvement in mounting efficiency of the memory cell. Therefore, the semiconductor memory device and the manufacturing method thereof according to the present invention are extremely useful for highly integrating the semiconductor memory device.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'objet de l'invention est un dispositif de stockage à semi-conducteur dans lequel des cellules de mémoire peuvent être formées aussi bien dans une structure simple que dans une densité plus élevée. Le drain (18) du transistor de sélection (14) de chacune des cellules de mémoire (10) est relié à une électrode (12c) d'un élément d'enregistrement à résistance (12). Une ligne de mots (WL) est reliée à la grille (G) de chacun des transistors de sélection (14) dans un premier groupe de cellules de mémoire disposées le long de la ligne de mots (WL), ainsi qu'à l'autre électrode (12a) de chacun des éléments d'enregistrement à résistance dans le premier groupe de cellules de mémoire. Une ligne de bits (BL) est reliée à la source (16) de chacun des transistors de sélection (14) dans un second groupe de cellules de mémoire disposées le long de la ligne de bits (BL).
PCT/JP2006/318832 2006-09-22 2006-09-22 Dispositif de stockage à semi-conducteur, procédé pour fabriquer un dispositif de stockage à semi-conducteur, procédé d'écriture de dispositif de stockage à semi-conducteur et procédé de lecture de dispositif de stockage à semi-conducteur WO2008035432A1 (fr)

Priority Applications (2)

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JP2008535249A JP5062176B2 (ja) 2006-09-22 2006-09-22 半導体記憶装置、半導体記憶装置の製造方法、半導体記憶装置の書き込み方法及び半導体記憶装置の読み出し方法
PCT/JP2006/318832 WO2008035432A1 (fr) 2006-09-22 2006-09-22 Dispositif de stockage à semi-conducteur, procédé pour fabriquer un dispositif de stockage à semi-conducteur, procédé d'écriture de dispositif de stockage à semi-conducteur et procédé de lecture de dispositif de stockage à semi-conducteur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/318832 WO2008035432A1 (fr) 2006-09-22 2006-09-22 Dispositif de stockage à semi-conducteur, procédé pour fabriquer un dispositif de stockage à semi-conducteur, procédé d'écriture de dispositif de stockage à semi-conducteur et procédé de lecture de dispositif de stockage à semi-conducteur

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010199104A (ja) * 2009-02-23 2010-09-09 National Institute For Materials Science ノンポーラ型不揮発性メモリー素子
JP2012523061A (ja) * 2009-04-03 2012-09-27 サンディスク スリーディー，エルエルシー ダイオードを有するクロスポイント不揮発性メモリセルの書き込み方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005203463A (ja) * 2004-01-14 2005-07-28 Sharp Corp 不揮発性半導体記憶装置
JP2005217408A (ja) * 2004-01-26 2005-08-11 Macronix Internatl Co Ltd 薄膜相変化メモリ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005203463A (ja) * 2004-01-14 2005-07-28 Sharp Corp 不揮発性半導体記憶装置
JP2005217408A (ja) * 2004-01-26 2005-08-11 Macronix Internatl Co Ltd 薄膜相変化メモリ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010199104A (ja) * 2009-02-23 2010-09-09 National Institute For Materials Science ノンポーラ型不揮発性メモリー素子
JP2012523061A (ja) * 2009-04-03 2012-09-27 サンディスク スリーディー，エルエルシー ダイオードを有するクロスポイント不揮発性メモリセルの書き込み方法

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