WO2008029535A1 - Dispositif d'affichage et son procédé de commande - Google Patents

Dispositif d'affichage et son procédé de commande Download PDF

Info

Publication number
WO2008029535A1
WO2008029535A1 PCT/JP2007/058053 JP2007058053W WO2008029535A1 WO 2008029535 A1 WO2008029535 A1 WO 2008029535A1 JP 2007058053 W JP2007058053 W JP 2007058053W WO 2008029535 A1 WO2008029535 A1 WO 2008029535A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
voltage
subframe
gradation
period
Prior art date
Application number
PCT/JP2007/058053
Other languages
English (en)
Japanese (ja)
Inventor
Hidekazu Miyata
Original Assignee
Sharp Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kabushiki Kaisha filed Critical Sharp Kabushiki Kaisha
Publication of WO2008029535A1 publication Critical patent/WO2008029535A1/fr

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0285—Improving the quality of display appearance using tables for spatial correction of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/16—Determination of a pixel data signal depending on the signal applied in the previous frame

Definitions

  • the present invention relates to a hold-type display device, and more particularly to a hold-type display device that displays an image by dividing one frame period into a plurality of subframe periods and a driving method thereof.
  • an impulse-type display device and a hold-type display device are known as display devices.
  • an impulse-type display device for example, a CRT (Cathode Ray Tube) is known.
  • a hold-type display device for example, a TFT liquid crystal panel is known.
  • an impulse-type display device when attention is paid to individual pixels, a lighting period in which an image is displayed and a light-out period in which no image is displayed are alternately repeated. For example, even when a moving image is displayed, since an extinguishing period is inserted when an image for one screen is rewritten, an afterimage of an object moving in human vision does not occur. For this reason, the background and the object can be clearly distinguished, and the moving image can be visually recognized without a sense of incongruity.
  • the hold-type display device when a voltage is applied to each pixel, the luminance obtained by the voltage application is held until the next voltage application.
  • a moving image is displayed on the hold-type display device, an afterimage of a moving object is generated in human vision. Specifically, the outline of the moving object is visually recognized in a blurred state. Such a phenomenon is called “motion blur” and is thought to be caused by the tracking ability of human eyes.
  • motion blur occurs when displaying a moving image. Therefore, an inols-type display device has generally been used for a display such as a television that mainly displays a moving image. Met.
  • TFT liquid crystal panels have been rapidly adopted in displays such as televisions because of their thinness and light weight. For this reason, the TFT LCD panel It has been an issue to improve the display quality by improving the responsiveness at the time of display.
  • a technique for improving the display quality when displaying a moving image a method of performing pseudo innocent driving by inserting a black display period within one frame period has been proposed.
  • the TFT liquid crystal panel is inferior in display quality when viewing an oblique force image as compared with a CRT.
  • one frame period is divided into two or more subframe periods, and the luminance of each subframe period is integrated by one frame period.
  • a method of gradation display is proposed so that the brightness of a frame is 1 frame period!
  • a one-frame period is used in order to make the target luminance visible to the human eye. 2 or more brightness is displayed.
  • time-division driving a method of driving a display device by dividing one frame period into a plurality of periods (subframe periods) is referred to as “time-division driving”.
  • first subframe period when one frame period is divided into two subframe periods
  • second subframe period the next subframe period
  • TFT LCD panels generally employ an 8-bit output source driver (hereinafter referred to as an “8-bit output source driver”) having a ⁇ characteristic with a ⁇ (gamma) value of 2.2.
  • FIG. 14 is a block diagram showing the configuration of the 8-bit output source driver.
  • This source line is a sampling 'latch circuit that outputs ⁇ -stage shift register 331 equal to the number of source bus lines SLl to SLn and 8-bit digital image signals dl to dn corresponding to the source bus lines SLl to SLn.
  • a selection circuit 333 for selecting a voltage to be applied to each source bus line SLl to SLn, and a voltage selected by the selection circuit 333 to apply to the source bus lines SLl to SLn as a drive video signal Output circuit 334, and a gradation voltage generation circuit 335 that outputs voltages (gradation voltage group) corresponding to 256 gradation levels in the brass polarity and the negative polarity, respectively.
  • the RGB 8-bit digital video signal DV given to the source driver is sampled by the sampling pulse output from the shift register 331 to the 'latch circuit 332
  • the signals are held and simultaneously output to the selection circuit 333 by the pulse of the latch strobe signal LS.
  • a voltage (gradation voltage group) corresponding to each gradation level is generated by resistance-dividing a plurality of reference voltages.
  • the selection circuit 333 selects one of the voltages output from the gradation voltage generation circuit 335, and the selected voltage force S impedance is converted and output from the output circuit 334.
  • the polarity of the voltage is determined based on the polarity inversion signal POL supplied to the selection circuit 333.
  • Vn (VHn-VLn) / 2 (1)
  • VHn is a voltage applied to the liquid crystal layer when the polarity is positive
  • VLn is a voltage applied to the liquid crystal layer when the polarity is negative.
  • the magnitude of the voltage for writing data to the TFT liquid crystal panel is determined according to the VT characteristic of the panel (liquid crystal applied voltage panel transmittance characteristic).
  • the gradation voltage generation circuit 335 has a configuration as shown in FIG. 8, and the resistance values RH1 to RH255 and 13 ⁇ 4 ⁇ 1 to 13 ⁇ 4 ⁇ 255 of each resistor are determined in consideration of the panel ⁇ 0 characteristics. ing. Since this VT characteristic varies depending on the panel model (type), it is necessary to create a source driver for each panel model. For this reason, a general-purpose source driver that can be used for any panel has not been provided.
  • a general-purpose source driver that performs desired gradation display by inputting / outputting data having a larger number of bits than the number of bits of externally applied data.
  • a source driver that inputs and outputs 10-bit data compared to 8-bit externally applied data.
  • the grayscale voltage is generated by dividing the reference voltage into 1024 equal parts for each of the positive polarity and the negative polarity.
  • the gray scale voltage at which the luminance is displayed based on each of the 8-bit data given from the outside is measured in advance, and the source driver can select the desired gray scale voltage so that the desired gray scale voltage can be selected.
  • Data is input to the source driver Before the measurement, the data is converted from 8 bits to 10 bits in the display control circuit based on the measurement results. With such a configuration, even if the panel model is changed, it is only necessary to change the configuration of the data conversion part included in the display control circuit etc., and it is not necessary to create a new source driver. Disappear. Note that such a source driver has a reference voltage divided equally and inputs / outputs a bit number larger than the number of data bits to which an external force is applied. Noku ”(or“ Linear 10-bit output source driver ”when 10-bit data is input / output).
  • FIG. 15 is a cross-sectional view of a general TFT liquid crystal panel.
  • the TFT liquid crystal panel includes two insulating substrates (TFT glass substrate 51 and counter glass substrate 52) facing each other.
  • a pixel electrode 14 is provided on the TFT glass substrate 51, and an electrode for applying a voltage between the counter glass substrate 52 and the pixel electrode 14 via the liquid crystal layer 53 (hereinafter referred to as “counter electrode”). 16 is provided.
  • FIG. 3 is an equivalent circuit diagram near the TFT.
  • gate bus lines scanning signal lines
  • source bus lines video signal lines
  • TFTs 10 are provided in the vicinity of intersections between the gate bus lines and the source bus lines.
  • the TFT 10 has a gate electrode 11 that also branches the gate bus line coupler, a source electrode 12 that also branches the source bus line coupler! /, A drain electrode 13, and a drain electrode 13.
  • the drain electrode 13 is connected to the pixel electrode 14.
  • a counter electrode (common electrode) 16 is provided to face the pixel electrode 14, and a liquid crystal capacitor 15 is formed by the pixel electrode 14 and the counter electrode 16.
  • auxiliary capacitance electrode 18 is also provided on the TFT glass substrate 51, and the auxiliary capacitance 17 is formed by the pixel electrode 14 and the auxiliary capacitance electrode 18.
  • the gate electrode 11 of each TFT 10 receives an active scanning signal (gate signal)
  • the video signal (data signal) that the source electrode 12 of the TFT 10 receives also the source bus line ) Is applied to the pixel electrode 14.
  • Clc is the capacity of the liquid crystal capacitor
  • Ccs is the capacity of the auxiliary capacitor 17
  • Vgh is the difference between the voltage when the gate is on and the voltage when the gate is off.
  • FIG. 17 is a diagram showing the relationship between the liquid crystal applied voltage and the liquid crystal dielectric constant and the relationship between the liquid crystal applied voltage and the pull-in voltage. As shown in Fig. 17, the liquid crystal dielectric constant increases and the pull-in voltage ⁇ increases as the liquid crystal applied voltage increases. Therefore, voltage is applied to the source bus line in consideration of the magnitude of the pull-in voltage ⁇ according to the gradation.
  • Patent Document 1 Japanese Unexamined Patent Publication No. 2003-22061
  • Patent Document 2 Japanese Unexamined Patent Publication No. 2005-173573
  • the second subframe period is black.
  • the magnitude of the pull-in voltage ⁇ generated when a voltage is applied to the source bus line in the second subframe period differs depending on the luminance in the first subframe period. For this reason, even if the luminance in the second subframe period is a specific luminance, the voltage applied to the source bus line must be a different voltage depending on the luminance in the first subframe period.
  • the voltage applied to the source bus line is adjusted according to the gradation for each frame period to eliminate the influence of the pull-in voltage ⁇ .
  • the magnitude of the pull-in voltage ⁇ in the first subframe period is the second subframe in the previous frame period (the frame period to which the first subframe period belongs).
  • the magnitude of the pull-in voltage ⁇ in the second subframe period depends on the display gradation in the first subframe period (in the frame period to which the second subframe period belongs). For this reason, the influence of the pull-in voltage cannot be removed by a conventional source driver.
  • the gradation voltage is generated by equally dividing the reference voltage. Therefore, strictly speaking, a desired voltage can be obtained. Also, depending on the characteristics of the panel, smooth gradation display may not be performed.
  • a first aspect of the present invention divides one frame period into a plurality of subframe periods, and displays based on an image signal sent from an external device indicating the gradation of an image to be displayed in each frame period.
  • a display device that displays an image by applying a voltage to the video signal line provided in the unit for each subframe period,
  • a subframe data generation unit that generates subframe data that is data for each of the plurality of subframe periods based on the image signal transmitted from the external force;
  • Current subframe gradation data which is subframe data in the current subframe period as a subframe period to be displayed, and previous subframe data, which is subframe data in the previous subframe period that is one subframe period before the current subframe period
  • a data conversion unit for generating voltage determination gradation data for determining a voltage to be applied to the video signal line in the current subframe period based on frame gradation data
  • a video signal line driving circuit for applying a voltage having a magnitude based on the voltage determining gradation data to the video signal line
  • the data conversion unit generates a look-up table indicating a correspondence relationship between a combination of the current subframe grayscale data and the previous subframe grayscale data and the voltage determination grayscale data for each of the plurality of subframe periods and According to another aspect of the present invention, the polarity of the voltage to be applied to the video signal line is provided for the current subframe period.
  • a second aspect of the present invention is the first aspect of the present invention.
  • the number of bits of the current subframe gradation data and the number of bits of the previous subframe gradation data are larger than the number of bits of the previous subframe gradation data, and the number represented by J bits (J is a natural number) is equal to a predetermined reference voltage.
  • a gradation voltage generating circuit for generating a plurality of divided gradation voltages
  • the data conversion unit generates the ej bit voltage determination gradation data
  • the video signal line driving circuit generates the ej bit voltage from the plurality of gradation voltages generated by the gradation voltage generation circuit.
  • a gradation voltage selected based on the gradation data for determination is applied to the video signal line.
  • a third aspect of the present invention is the first aspect of the present invention.
  • the data conversion unit further includes the lookup table for each RGB color.
  • a fourth aspect of the present invention is the first aspect of the present invention.
  • a temperature detection unit for detecting the temperature
  • the data conversion unit may further include the lookup table for each temperature range obtained by classifying the temperatures detected by the temperature detection unit with a predetermined threshold.
  • One frame period is divided into K (K is a natural number of 2 or more) subframe periods, and the subframe data generation unit
  • An output frequency converter for receiving an image signal sent from the outside and outputting a K-times speed image signal obtained by multiplying the frequency of the received image signal by K;
  • a data delay unit that receives the K double speed image signal and outputs a delayed image signal obtained by delaying the received K double speed image signal by one subframe period;
  • the data converter is configured to output the K-times speed image signal as the current subframe gradation data.
  • the voltage determining gradation data is generated on the basis of the signal and the delayed image signal as the previous subframe gradation data.
  • one frame period is divided into a plurality of subframe periods, and display is performed based on an image signal sent from an external source indicating the gradation of an image to be displayed in each frame period.
  • a sub-frame data generation step for generating sub-frame data, which is data for each of the plurality of sub-frame periods, based on the externally transmitted image signal; and a sub-frame period of the current sub-frame period as a display target sub-frame period.
  • a look-up table showing a correspondence relationship with voltage determination gradation data for determining a voltage to be applied to the video signal line, the video being previously divided into the plurality of subframe periods and in the current subframe period. Refer to the lookup table provided for the polarity of the voltage to be applied to the signal line.
  • a seventh aspect of the present invention is the sixth aspect of the present invention.
  • the number of bits of the current subframe gradation data and the number of bits of the previous subframe gradation data are larger than the number of bits of the previous subframe gradation data, and the number represented by J bits (J is a natural number) is equal to a predetermined reference voltage.
  • the 6J-bit gradation data for voltage determination is generated, and in the video signal line driving step, the J-bit voltage is determined from the plurality of gradation voltages generated in the gradation voltage generation step. Selected based on gradation data A pressure is applied to the video signal line.
  • An eighth aspect of the present invention is the sixth aspect of the present invention.
  • One frame period is divided into K (K is a natural number of 2 or more) subframe periods, and the subframe data generation step includes:
  • the current subframe gradation data The voltage determination gradation data is generated on the basis of the K double speed image signal as and the delayed image signal as the previous subframe gradation data.
  • the data conversion unit that generates the voltage determination gradation data includes the voltage determination floor based on the gradation in the current subframe period and the gradation in the previous subframe period.
  • Look-up table force for determining key data is provided for each subframe period and for each polarity of applied voltage in the current subframe period.
  • the magnitude of the bow-in voltage varies depending on the subframe period and the polarity of the applied voltage.
  • a voltage that takes into account the magnitude of the voltage is applied to the video signal line.
  • the number of bits of input / output data of the video signal line drive circuit is larger than the number of bits of the image signal sent from the outside. Are divided equally to generate a gradation voltage.
  • time-division driving is employed. For this reason, although the reference voltage is divided equally, the number of display gradations is increased as compared with the case where time-division driving is not employed, so that a transmittance close to the desired panel transmittance can be obtained.
  • the bit of the image signal sent from the outside Since the number conversion is performed by the data converter, it is not necessary to create a video signal line driver circuit for each panel model. As a result, a general-purpose video signal line driving circuit capable of obtaining a transmittance close to a desired panel transmittance is realized.
  • a lookup table for generating voltage determining gradation data is provided for each RGB color. For this reason, the gradation data for voltage determination is generated in consideration of the characteristics of the panel for each RGB color. As a result, higher-quality gradation display is realized in a color display device.
  • a lookup table for generating voltage determining gradation data is provided for each temperature range. Therefore, gradation data for voltage determination is generated in consideration of the temperature in the panel. As a result, higher-quality gradation display is realized even at high or low temperatures.
  • the current subframe grayscale data and the previous subframe grayscale data necessary for specifying the voltage determination grayscale data from the lookup table can be easily configured. To be acquired.
  • FIG. 1 is a block diagram showing a configuration of a display control circuit of an active matrix liquid crystal display device according to an embodiment of the present invention.
  • FIG. 2 is a block diagram showing the overall configuration of the active matrix liquid crystal display device according to the embodiment.
  • FIG. 3 is an equivalent circuit diagram of a pixel formation portion.
  • FIG. 4 is a block diagram showing a configuration of a source driver in the embodiment.
  • FIG. 5 is a diagram showing input / output characteristics of a linear 10-bit output source driver in the embodiment.
  • FIG. 6 AC are diagrams showing changes in pixel voltage in various driving methods.
  • FIG. 7 A and B are signal waveform diagrams for explaining a driving method in the embodiment.
  • FIG. 8 is a diagram showing a configuration of a gradation voltage generation circuit of an 8-bit output source driver.
  • FIG. 9 is a diagram showing a VT characteristic (liquid crystal applied voltage—panel transmittance characteristic) of a liquid crystal panel.
  • FIG. 10 is a diagram showing input / output characteristics of an 8-bit output source driver.
  • FIG. 11 is a diagram for explaining data conversion in the data conversion unit in the embodiment.
  • FIG. 12 is a block diagram showing a configuration of a display control circuit in the first modification of the embodiment.
  • FIG. 13 is a block diagram showing a configuration of a display control circuit in a second modification of the embodiment.
  • FIG. 14 is a block diagram showing a configuration of an 8-bit output source driver in a conventional example.
  • FIG. 15 is a cross-sectional view of a TFT liquid crystal panel.
  • FIG. 16 A and B are diagrams for explaining the pull-in voltage.
  • FIG. 17 is a diagram showing the relationship between the liquid crystal applied voltage and the liquid crystal dielectric constant and the relationship between the liquid crystal applied voltage and the pull-in voltage.
  • FIG. 18 is a diagram for explaining a change in luminance in a display device employing time-division driving.
  • FIG. 2 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to an embodiment of the present invention.
  • the liquid crystal display device includes a display control circuit 200, a source driver (video signal line driving circuit) 300, a gate driver (scanning signal line driving circuit) 400, and a display unit 500.
  • the display unit 500 includes a plurality (n) of source bus lines SL1 to SLn, a plurality (m) of gate bus lines GLl to GLm, and a plurality of these source bus lines SL1 to SLn.
  • a plurality of (n ⁇ m) pixel forming portions provided corresponding to the intersections with the gate bus lines GL 1 to GLm are included.
  • each pixel forming portion has a switching element in which a gate electrode 11 is connected to a gate bus line passing through a corresponding intersection and a source electrode 12 is connected to a source bus line passing through the intersection.
  • TFT 10 as a pixel
  • a pixel electrode 14 connected to the drain electrode 13 of the TFT 10
  • a common electrode 16 and auxiliary capacitance electrode 18 commonly provided in the plurality of pixel forming portions
  • a liquid crystal capacitor 15 formed by 16 and an auxiliary capacitor 17 formed by the pixel electrode 14 and the auxiliary capacitor electrode 18 are included.
  • the liquid crystal capacitor 15 and the auxiliary capacitor 17 form a pixel capacitor.
  • the display control circuit 200 includes a data signal DAT and a timing control signal TS sent from the outside.
  • Digital video signal DV as gradation data for voltage determination, source start pulse signal SSP, source clock signal SCK, latch strobe signal LS, polarity inversion for controlling the timing of displaying an image on display unit 500 Outputs signal POL, gate start pulse signal GSP, and gate clock signal GCK.
  • the detailed configuration of the display control circuit 200 will be described later.
  • the source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, the latch strobe signal LS, and the polarity inversion signal POL output from the display control circuit 200, and displays the display unit.
  • a drive video signal is applied to each source bus line SLl to SLn in order to charge the pixel capacity of each pixel formation section in 500.
  • the detailed configuration of the source driver 300 will be described later.
  • the gate dry 00 applies an active scan signal to the gate bus lines GLl to GLm based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200! To do.
  • one frame period is divided into two subframe periods, and the gate bus lines GL1 to GLm are driven for each subframe period. That is, each gate bus line GLl to GLm is driven twice in one frame period.
  • the drive video signal is applied to each of the source nose lines SLl to SLn, and the scanning signal is applied to each of the gate bus lines GLl to GLm, whereby an image is displayed on the display unit 500.
  • the liquid crystal display device according to the present embodiment will be described as being of a normally black type.
  • FIG. 1 is a block diagram showing the configuration of the display control circuit 200 in the present embodiment.
  • the display control circuit 200 includes a double speed controller 21, an output frequency conversion unit (frame memory) 22, a data delay unit (subframe memory) 23, and a data conversion unit 24.
  • the data conversion unit 24 has four lookup tables (hereinafter referred to as “conversion LUTs”) for converting the number of bits of input data!
  • conversion LUT the first subframe plus polarity conversion LUT251, the first subframe minus polarity conversion LUT252, the second subframe plus polarity conversion LUT253, and the second subframe marker are used.
  • a negative polarity conversion LUT254 is provided. A detailed description of these conversion LUTs 251 to 254 will be described later.
  • a subframe data generation unit is realized by the output frequency conversion unit 22 and the data delay unit 23.
  • Double speed controller 21 receives timing control signal TS to which an external force is also sent, and doubles the operation of first control signal CTL1 for doubling the operation of output frequency converter 22 and the operation of data delay unit 23 Second control signal CTL2 for switching the data converter 24, third control signal CTL3 for doubling the operation of the data converter 24, and a source start pulse for controlling the timing of displaying an image on the display 500 Outputs signal SSP, source clock signal SCK, latch strobe signal LS, polarity inversion signal POL, gate start pulse signal GSP, and gate clock signal GCK.
  • the output frequency converter 22 receives an 8-bit data signal DAT sent from the outside, and holds data for one frame. Further, the output frequency conversion unit 22 is a data signal (hereinafter referred to as “double speed data”) that has doubled the frequency of the data signal DAT sent from the outside based on the first control signal CTL1 output from the double speed controller 21. “Signal”)) Da is output. In the present embodiment, the current subframe gradation data is realized by the double speed data signal Da.
  • the data delay unit 23 receives the double speed data signal Da output from the output frequency converter 22 and the second control signal CTL2 output from the double speed controller 21, and receives the double speed data signal Da as one subframe.
  • Signal delayed by period hereinafter referred to as “delayed data signal”
  • Db is output.
  • the previous subframe gradation data is realized by the delayed data signal Db.
  • the data converter 24 outputs the 8-bit double speed data signal Da output from the output frequency converter 22 and the 8-bit delayed data signal Db output from the data delay section 23 and the double speed controller 23.
  • the third control signal CTL3 is received and a 10-bit digital video signal DV is output.
  • FIG. 4 is a block diagram showing the configuration of the source driver 300 in the present embodiment.
  • This source driver 300 is equivalent to the number of source bus lines SLl to SLn! /, N-stage shift registers.
  • a gradation voltage generation circuit 35 that outputs a corresponding voltage (gradation voltage group).
  • a source start pulse signal SSP and a source clock signal SCK are input to the shift register 31. Based on these signals SSP and SCK, the shift register 31 sequentially transfers the noise included in the source start pulse signal SSP from the input end to the output end. In response to the pulse transfer, sampling pulses corresponding to the source bus lines SL1 to SLn are sequentially output from the shift register 31, and the sampling pulses are sequentially input to the sampling latch circuit 32.
  • the sampling 'latch circuit 32 samples and holds the 10-bit digital video signal DV output from the display control circuit 200 at the timing of the sampling pulse output from the shift register 31. Further, the sampling and latch circuit 32 simultaneously outputs the digital video signal DV held at the timing of the pulse of the latch strobe signal LS as the 10-bit internal image signals dl to dn.
  • the gradation voltage generation circuit 35 is based on a plurality of reference voltages to which a predetermined power supply circuit (not shown) force is also applied, and voltages VH0 to VH1023 corresponding to 1024 gradation levels with respect to plus and minus polarities. VL0 to VL1023 are generated and output as gradation voltage groups.
  • the gradation voltage generation circuit 35 generates a voltage obtained by dividing the reference voltage into 1024 equal parts. Therefore, the input / output characteristics of the source driver (linear 10-bit output source line) having the gradation voltage generation circuit 35 are as shown in FIG. As shown in FIG. 5, the relationship between the signal value of the digital video signal DV sent from the display control circuit 200 and the voltage output from the source driver 300 (voltage value of the driving video signal) is a linear relationship.
  • the selection circuit 33 uses the gradation voltage groups VHO to VH1023 and VH output from the gradation voltage generation circuit 35 based on the digital image signals dl to dn output from the sampling 'latch circuit 32. Any voltage from L0 to VL1023 is selected and output. At this time, the polarity of the voltage is determined based on the polarity inversion signal POL output from the display control circuit 200. The voltage output from the selection circuit 33 is input to the output circuit 34.
  • the output circuit 34 performs impedance conversion of the voltage output from the selection circuit 33 by, for example, a voltage follower, and outputs the converted voltage to the source bus lines SL1 to SLn as drive video signals.
  • one frame period is divided into two subframe periods.
  • the first subframe period is driven to display a relatively higher luminance than the second subframe period. That is, the pixel voltage in the first subframe period is relatively higher than the pixel voltage in the second subframe period (the voltage applied to the liquid crystal layer in each pixel formation portion).
  • the polarity of the pixel voltage is driven so as to be inverted every frame period. That is, within one frame period, the polarity of the pixel voltage in the first subframe period and the polarity of the pixel voltage in the second subframe period are the same.
  • the magnitude of the voltage of the driving video signal is determined in consideration of the magnitude of the pull-in voltage described above. These are described below.
  • FIGS. 6A to 6C are diagrams showing changes in pixel voltage in various driving methods.
  • the pixel voltage changes as shown in FIG. That is, positive polarity and negative polarity appear alternately every frame period.
  • the DC component of the voltage is removed in two frame periods.
  • time-division driving driving in such a way that positive and negative polarities appear alternately every subframe period, the pixel voltage changes as shown in FIG. 6 (B).
  • the polarity of the pixel voltage is positive and the absolute value thereof is relatively large.
  • the pixel voltage has a negative polarity, and its absolute value is relatively small. For this reason, the DC component of the voltage remains in the entire frame period as shown in Fig. 6 (B). So thus, in this embodiment that employs time-division driving, driving is performed so that positive polarity and negative polarity appear alternately every frame period. Then, the pixel voltage changes as shown in Fig. 6 (C), and it can be thought that "the DC component of the voltage is removed during the entire frame period".
  • the magnitude of the pull-in voltage generated in a certain subframe period depends on the state of the liquid crystal one period before the subframe period. For this reason, even when a constant luminance display is continuously performed, as shown in FIG. 6 (C), the subframe period before the subframe period and for each polarity (applied voltage) as shown in FIG. Since the pixel voltage is different, the magnitude of the pull-in voltage is different for each subframe period and for each polarity. Therefore, in this embodiment, in order to determine the voltage of the video signal for driving in consideration of the pull-in voltage, four conversion LUTs 251 to 254 for each polarity for each subframe period as shown in FIG. It is provided in the data converter 24 in the 200.
  • the conversion LUTs 251 to 254 include 8-bit data indicating gradation in a subframe period to which a voltage is applied (hereinafter referred to as a "current subframe period") and a subframe to which the voltage is applied. Select the grayscale voltage for displaying the desired brightness and the combination of 8-bit data indicating the grayscale in the subframe period (hereinafter referred to as the “previous subframe period”) one subframe period before the period. Stores the correspondence with 10-bit data. [0057] When data conversion is performed in the data conversion unit 24, one of the four conversion LUTs 251 to 254 is referred to according to the current subframe period and the polarity of the applied voltage in the current subframe period.
  • the first subframe positive polarity conversion LUT 251 when data conversion is performed in order to determine the voltage of the driving video signal in the first subframe period in the case of positive polarity, the first subframe positive polarity conversion LUT 251 is referred to and the level indicated by the double-speed data signal Da.
  • the signal value of the digital video signal DV for selecting the gradation voltage is determined based on the gradation and the gradation indicated by the delayed data signal Db.
  • the second subframe negative polarity conversion LUT 254 when data conversion is performed to determine the voltage of the driving video signal in the second subframe period when the polarity is negative, the second subframe negative polarity conversion LUT 254 is referred to and the digital video The signal value of signal DV is determined.
  • the data conversion unit 24 includes the conversion LUTs 251 to 254 for each subframe period and for each polarity, and based on the conversion LUT according to the current subframe period and the polarity of the applied voltage in the current subframe period.
  • the voltage value of the driving video signal is determined in consideration of the pull-in voltage regardless of which subframe period changes from which subframe period.
  • the data conversion unit 24 in the display control circuit 200 includes data indicating the gray scale in the current subframe period (double speed data signal Da) and the previous subframe period. Data indicating the gray level (delayed data signal Db) is input. Further, the data converter 24 is provided with conversion LUTs 251 to 254 in which the gradation voltage is set in advance for each polarity according to the subframe period so that the voltage considering the pull-in voltage is applied to the source bus lines SL1 to SLn. .
  • the data converter 24 refers to the conversion LUT according to the current subframe period (force that is either the first subframe period or the second subframe period) and the polarity of the applied voltage in the current subframe period. Then, the gradation voltage is determined based on the gradation in the current subframe period and the gradation in the previous subframe period. For this reason, regardless of which subframe period is changed from which subframe period to which subframe period, a voltage considering the pull-in voltage corresponding to the change is applied to the source nose lines SLl to SLn. In this embodiment, time-division driving is performed using a linear 10-bit output source driver.
  • the configuration of the gradation voltage generating circuit 35 is, for example, as shown in FIG.
  • the gradation voltages VHO to VH255 and VL0 to VL255 are generated by resistance division or capacitance division.
  • the VT characteristics (liquid crystal applied voltage panel transmittance characteristics) of a liquid crystal panel are generally represented by a curve as shown in Fig. 9 for a normally black type. Therefore, in order to obtain a desired panel transmittance, the resistance value 13 ⁇ 411 of each resistor in the gradation voltage generating circuit 35 is set so that the input / output characteristics of the source driver are as shown in FIG. ⁇ 13 ⁇ 41255 and 13 ⁇ 4 ⁇ 1 ⁇ 1 ⁇ 255 are determined.
  • the grayscale voltage generation circuit 35 generates a voltage obtained by dividing the reference voltage by 1024 regardless of whether the polarity is positive or negative. . Therefore, as for the input / output characteristics of the source driver 300, as shown in FIG. 5, the relationship between the signal value of the digital video signal DV and the output voltage is a linear relationship.
  • the VT characteristic of a liquid crystal panel is represented by a curve as shown in Fig. 9. Therefore, in order to obtain a desired panel transmittance, the data converter 24 in the display control circuit 200 has an 8-bit data (data signal DAT transmitted externally) 10-bit as shown in FIG. Data (digital video signal DV).
  • the gradation voltage generation circuit 35 of the linear 10-bit output source driver generates the gradation voltage by dividing the reference voltage into 1024 equal parts, so the desired panel transmittance cannot be obtained strictly.
  • smooth gradation display may not be obtained.
  • one frame period is divided into two subframe periods. For this reason, the number of display gradations is doubled compared to the case where time-division driving is not adopted. Thereby, a panel transmittance close to a desired panel transmittance can be obtained, and a smooth gradation display is realized.
  • the influence of the pull-in voltage when the time-division drive is adopted.
  • a display device that can be removed and can perform smooth gradation display using a general-purpose source driver is realized.
  • FIG. 12 is a block diagram showing a configuration of the display control circuit 200 in the first modification of the embodiment.
  • this modified example for each color of RGB, conversion LUTs 251R to 254R, 251G to 254G, and 251B to 254B for each polarity according to subframe period are provided.
  • the VT characteristics of each RGB are different. Therefore, by adopting the configuration according to this modification, it is possible to generate the digital video signal DV for determining the gradation voltage in consideration of each VT characteristic of RGB. As a result, higher-quality gradation display is realized in a color liquid crystal display device.
  • FIG. 13 is a block diagram showing a configuration of the display control circuit 200 in the second modification example of the embodiment.
  • a temperature sensor 60 is provided as a temperature detection unit, and the temperature T detected by the temperature sensor 60 is given to the display control circuit 200.
  • the display control circuit 200 is provided with power conversion LUTs 251a to 254a, 251b to 254b, 251c to 254c, and so on for each range of temperature T classified by a predetermined threshold. . Since the VT characteristics of the liquid crystal panel differ depending on the temperature, the digital video signal DV for determining the gradation voltage is generated by considering the temperature in the liquid crystal panel by adopting the configuration according to this modification. be able to.
  • modification 1 and modification 2 are combined to provide a configuration including a conversion LUT for each polarity of each subframe period for each RGB and each temperature range.
  • the power described with an example in which one frame period is divided into two subframe periods is not limited to this.
  • a display device in which one frame period is divided into K subframe periods K is a natural number greater than or equal to 2
  • the present invention can also be applied to.
  • the double-speed controller 21 shown in FIG. 1 starts with the first control signal CTL1 and the second control signal CTL1 and the second control signal for increasing the operation of the output frequency conversion unit 22, the data delay unit 23, and the data conversion unit 24, respectively.
  • the control signal CTL2 and the third control signal CTL3 are output.
  • the data conversion unit 24 includes a conversion LUT for each of the first to Kth subframe periods.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Cette invention concerne un appareil d'affichage par maintien et a pour but de mettre à disposition un appareil d'affichage dans lequel en cas d'emploi d'une commande de répartition dans le temps, l'effet d'une tension de traction peut être supprimé. L'appareil d'affichage décrit, qui effectue un affichage d'image sur la base d'un signal de données à 8 bits appliqué de manière externe (DAT), inclut une commande de source de sortie à 10 bits linéaire. Un circuit de commande d'affichage (200) comprend un contrôleur de doublement de débit (21) ; une partie de conversion de fréquence de sortie (22) qui transmet un signal de données à débit doublé (Da) obtenu en doublant la fréquence d'un signal de données ; une partie de retardement de données (23) qui transmet un signal de données retardé (Db) obtenu en retardant le signal de données à débit doublé par un intervalle de sous-trame ; et une partie de conversion de données (24) qui convertit les données de huit bits en dix bits. La partie de conversion de données inclut des tables de conversion (251-254), qui stockent des correspondances entre des tensions d'échelle des gris et des combinaisons des échelles des gris d'un intervalle de sous-trame actuel et les échelles des gris de l'intervalle de sous-trame précédent, pour les intervalles de sous-trame respectifs et pour les polarités respectives des tensions appliquées.
PCT/JP2007/058053 2006-09-07 2007-04-12 Dispositif d'affichage et son procédé de commande WO2008029535A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006-242641 2006-09-07
JP2006242641 2006-09-07

Publications (1)

Publication Number Publication Date
WO2008029535A1 true WO2008029535A1 (fr) 2008-03-13

Family

ID=39156980

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/058053 WO2008029535A1 (fr) 2006-09-07 2007-04-12 Dispositif d'affichage et son procédé de commande

Country Status (1)

Country Link
WO (1) WO2008029535A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011065063A1 (fr) * 2009-11-27 2011-06-03 シャープ株式会社 Dispositif d'affichage à cristaux liquides et procédé de commande de dispositif d'affichage à cristaux liquides

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02271390A (ja) * 1989-04-12 1990-11-06 Japan Aviation Electron Ind Ltd 液晶表示装置
JPH08227283A (ja) * 1995-02-21 1996-09-03 Seiko Epson Corp 液晶表示装置、その駆動方法及び表示システム
JPH09269511A (ja) * 1996-03-29 1997-10-14 Seiko Epson Corp 液晶装置、その駆動方法及び表示システム
JP2001201732A (ja) * 2000-01-21 2001-07-27 Victor Co Of Japan Ltd 液晶表示装置
JP2002182622A (ja) * 2000-10-04 2002-06-26 Seiko Epson Corp 画像信号補正回路、その補正方法、液晶表示装置及び電子機器
JP2005234552A (ja) * 2004-01-21 2005-09-02 Sharp Corp 表示装置，液晶モニター，液晶テレビジョン受像機および表示方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02271390A (ja) * 1989-04-12 1990-11-06 Japan Aviation Electron Ind Ltd 液晶表示装置
JPH08227283A (ja) * 1995-02-21 1996-09-03 Seiko Epson Corp 液晶表示装置、その駆動方法及び表示システム
JPH09269511A (ja) * 1996-03-29 1997-10-14 Seiko Epson Corp 液晶装置、その駆動方法及び表示システム
JP2001201732A (ja) * 2000-01-21 2001-07-27 Victor Co Of Japan Ltd 液晶表示装置
JP2002182622A (ja) * 2000-10-04 2002-06-26 Seiko Epson Corp 画像信号補正回路、その補正方法、液晶表示装置及び電子機器
JP2005234552A (ja) * 2004-01-21 2005-09-02 Sharp Corp 表示装置，液晶モニター，液晶テレビジョン受像機および表示方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011065063A1 (fr) * 2009-11-27 2011-06-03 シャープ株式会社 Dispositif d'affichage à cristaux liquides et procédé de commande de dispositif d'affichage à cristaux liquides
JP5405593B2 (ja) * 2009-11-27 2014-02-05 シャープ株式会社 液晶表示装置
US8994760B2 (en) 2009-11-27 2015-03-31 Sharp Kabushiki Kaisha Liquid crystal display device and method for driving a liquid crystal display device
US9218791B2 (en) 2009-11-27 2015-12-22 Sharp Kabushiki Kaisha Liquid crystal display device and method for driving a liquid crystal display device

Similar Documents

Publication Publication Date Title
JP5357932B2 (ja) 液晶表示装置
KR101303424B1 (ko) 액정표시장치와 그 구동방법
KR101186024B1 (ko) 액정 표시 장치의 데이터 처리 방법 및 장치
KR100870500B1 (ko) 액정표시장치와 그 구동 방법
US10417980B2 (en) Liquid crystal display device and driving method thereof
JP2007538268A (ja) 液晶表示装置及びその駆動方法、並びに液晶表示装置を備えた液晶テレビ及び液晶モニタ
KR20140126148A (ko) 표시 장치 및 그 구동 방법
JPWO2004070697A1 (ja) 液晶表示装置
JP2007148369A (ja) 表示制御回路、表示制御方法及び表示回路
JPWO2013118323A1 (ja) 表示装置および表示方法
KR101255705B1 (ko) 게이트 구동 회로, 그를 이용한 액정 표시 장치 및 그의구동 방법
KR20080067091A (ko) 액정표시장치와 그 구동 방법
US8872809B2 (en) Liquid crystal display apparatus, drive circuit therefor, and drive method therefor
KR100870510B1 (ko) 액정표시장치와 그 구동방법
KR20150011173A (ko) 표시 장치 및 그 구동 방법
KR101386569B1 (ko) 액정표시장치의 응답속도 개선 장치 및 방법
WO2008029535A1 (fr) Dispositif d'affichage et son procédé de commande
US20080062210A1 (en) Driving device, display apparatus having the same and method of driving the display apparatus
JP2004061782A (ja) 液晶表示装置
KR100870491B1 (ko) 액정표시장치와 그 구동방법
KR101213924B1 (ko) 액정표시장치 및 그의 구동방법
KR101341784B1 (ko) 액정표시장치와 그 구동방법
KR100874640B1 (ko) 액정표시장치와 그 구동 방법
KR101237157B1 (ko) 표시장치의 다운 샘플링 방법 및 장치
KR20080067093A (ko) 액정표시장치와 그 구동 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07741489

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07741489

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP