WO2007088804A1 - Procédé d'excitation d'affichage plasma, circuit de sortie, et affichage plasma - Google Patents

Procédé d'excitation d'affichage plasma, circuit de sortie, et affichage plasma Download PDF

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Publication number
WO2007088804A1
WO2007088804A1 PCT/JP2007/051368 JP2007051368W WO2007088804A1 WO 2007088804 A1 WO2007088804 A1 WO 2007088804A1 JP 2007051368 W JP2007051368 W JP 2007051368W WO 2007088804 A1 WO2007088804 A1 WO 2007088804A1
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WIPO (PCT)
Prior art keywords
voltage
switch element
plasma display
display panel
sustain
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Application number
PCT/JP2007/051368
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English (en)
Japanese (ja)
Inventor
Manabu Inoue
Toshikazu Nagaki
Yasuhiro Arai
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Matsushita Electric Industrial Co., Ltd.
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Priority to JP2007556844A priority Critical patent/JPWO2007088804A1/ja
Publication of WO2007088804A1 publication Critical patent/WO2007088804A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G09G3/2965—Driving circuits for producing the waveforms applied to the driving electrodes using inductors for energy recovery

Definitions

  • the present invention relates to a plasma display panel driving method, a driving apparatus, and a plasma display.
  • a plasma display is a display device that utilizes a light emission phenomenon associated with gas discharge.
  • the display portion of a plasma display that is, a plasma display panel (hereinafter referred to as “PDP”) is more advantageous than other display devices in terms of large screen, thinning, and wide viewing angle.
  • P DP is roughly divided into DC type that operates with DC pulse and AC type that operates with AC pulse.
  • AC type PDP is particularly bright and simple in structure. Therefore, AC PDP is suitable for mass production and pixel definition and is widely used.
  • AC PDPs have, for example, a three-electrode surface discharge structure (see, for example, Patent Documents 1 and 2).
  • address electrodes are arranged in the vertical direction of the panel on the back substrate of the PDP, and sustain electrodes and scan electrodes (also referred to as X electrode and Y electrode, respectively) are alternately placed on the front substrate of the PDP. And it arrange
  • the address electrode and the scan electrode can be individually changed in potential.
  • Discharge cells are installed at intersections between the pair of sustain electrodes and scan electrodes adjacent to each other and the address electrodes.
  • a layer made of a dielectric dielectric layer
  • a layer for protecting the electrode and the dielectric layer protective layer
  • a layer containing a phosphor phosphor layer
  • Gas is sealed inside the discharge cell.
  • the PDP drive device controls the potentials of the sustain electrode, the scan electrode, and the address electrode of the PDP according to an ADS (Address Display-period Separation) method.
  • the ADS method is a kind of sub-field method.
  • one field of an image has multiple Divided into subfields.
  • the subfield includes an initialization period, an address period, and a discharge maintaining period.
  • the above three periods are set in common for all discharge cells of the PDP (see, for example, Patent Documents 1 and 2).
  • an initialization pulse voltage is applied between the sustain electrode and the scan electrode.
  • a scan pulse voltage is sequentially applied to the scan electrodes, and an address pulse voltage is applied to some of the address electrodes.
  • an address electrode to which an address pulse voltage is to be applied is selected based on a video signal input from the outside.
  • a discharge sustain pulse voltage is applied simultaneously and periodically to all pairs of sustain electrodes and scan electrodes.
  • the sustaining pulse voltage is lower than the discharge start voltage.
  • the wall charge voltage that is, the wall voltage is added to the sustaining pulse voltage. Therefore, the voltage between the sustain electrode and the scan electrode exceeds the discharge start voltage. As a result, gas discharge continues and light is emitted.
  • Patent Document 1 Japanese Patent Laid-Open No. 2005-266776
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2004-287003
  • the start voltage of the up-ramp waveform is too low, it takes time for the voltage applied to the scan electrode to reach a predetermined upper limit potential, and the initialization period becomes longer. As the initialization period becomes longer, the number of subfields that can be set decreases and the number of display gradations decreases.
  • the initialization period is preferably short.
  • the start voltage of the up-ramp waveform is increased (for example, higher than the discharge start voltage), strong light emission occurs and the contrast is adversely affected.
  • the PDP drive device includes a separation switch element, and the potential fluctuation is realized by electrically disconnecting the sustain voltage source of each electrode drive circuit as necessary via the separation switch element.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a PDP drive device and drive that realize good contrast and gradation without causing an increase in the initialization period. It is to provide a moving method.
  • a method for driving a plasma display panel which includes a scan electrode, a sustain electrode, and an address electrode, and includes a plurality of discharge cells.
  • the start voltage of the monotonically increasing waveform is applied during the address period in the initialization period in which the voltage is applied prior to the address period in which the discharge cells to be discharged are selected.
  • the maximum value force of the voltage applied to the scan electrode is set to be larger than the i-th voltage, which is a voltage difference obtained by subtracting the minimum value, and less than the discharge start voltage.
  • a method for driving a plasma display panel including a scan electrode, a sustain electrode and an address electrode, and including a plurality of discharge cells.
  • the start voltage of the monotonically increasing waveform is set to the minimum value of the voltage applied to the scanning electrode in the discharge sustain period. Is set to a predetermined voltage lower than the sustain voltage, which is a maximum value of the voltage applied to the scanning electrode during the discharge sustain period, and a monotonically increasing waveform is applied using the predetermined voltage as a start voltage.
  • a driving device for a plasma display panel which includes a sustain electrode, a scan electrode, and an address electrode, and includes a plurality of discharge cells.
  • the drive device rises sharply at the start of the initialization period, and then generates a monotonically increasing waveform, a sustaining power supply that provides a voltage to be applied to the scan electrode during the discharge sustain period, A discharge sustain pulse generation circuit including a high side sustain switch element and a low side sustain switch element electrically connected in series, and a voltage applied to the scan electrode during an address period for selecting a discharge cell to be discharged are applied.
  • a scanning voltage source, and a scanning circuit including a non-side scanning switch element and a low-side scanning switch element electrically connected in series.
  • a driving device for a plasma display panel which includes a sustain electrode, a scan electrode, and an address electrode, and includes a plurality of discharge cells.
  • the drive device includes a high-side ramp waveform generator for generating a monotonically increasing waveform, a sustain power supply for applying a voltage to be applied to the scan electrode during the discharge sustain period, and a no-side sustain switch electrically connected in series.
  • a discharge sustain pulse generating circuit including a device and a low-side sustain switch device, and a scan voltage source for applying a voltage to be applied to the previous scan electrode during an address period for selecting a discharge cell to be discharged. Inserted in the path between the scanning circuit that includes the high-side scanning switch element and the low-side scanning switch element, and the positive terminal of the sustain voltage source and the high-side ramp waveform generator, preventing the current from flowing into the positive terminal of the sustain power source First separation switch element.
  • a plasma comprising a plasma display panel capable of displaying an image by light emission by discharge between electrodes, and a driving device for driving the plasma display panel of any one of the above aspects.
  • a display is provided.
  • the start voltage of the up-ramp waveform applied in the initialization period is set to a value in a predetermined range, so that the initialization period is not lengthened and good contrast and level are obtained.
  • a PDP drive unit that achieves tonal display can be realized.
  • the breakdown voltage of the isolation switch element can be reduced.
  • the isolation switch elements become low resistance as the withstand voltage is reduced, so the number of isolation switch elements connected in parallel can be reduced, the mounting area can be reduced, the wiring impedance is reduced, the ringing is reduced, and the operating margin of the PDP An effect such as enlargement of the image can be obtained. Furthermore, since the conduction loss due to the separation switch element during the discharge sustain period is reduced, the power consumption can also be reduced.
  • FIG. 1 is a block diagram showing a configuration of a plasma display according to an embodiment of the present invention.
  • FIG. 2 is a detailed configuration diagram of a scanning electrode driving unit in the plasma display driving device in the first exemplary embodiment.
  • FIG. 3A shows the voltage waveform applied to the scan electrode of the PDP and the on period of each switch element included in the scan electrode driver in the initialization period, the address period, and the discharge sustain period in the first embodiment.
  • FIG. 3B In another example of the PDP driving method of the first embodiment, the voltage waveform applied to the scan electrode of the PDP in the initialization period, the address period, and the discharge sustain period, and each of the voltage included in the scan electrode drive unit The figure which shows the ON period of the switch element
  • FIG. 3C In another example of the PDP driving method of the first embodiment, the voltage waveform applied to the scan electrode of the PDP in the initialization period, the address period, and the discharge sustain period, and each of the voltage included in the scan electrode drive unit The figure which shows the ON period of the switch element
  • FIG. 4 is a diagram showing another circuit configuration example of the scan electrode driving unit.
  • FIG. 5 is a diagram showing another circuit configuration example of the scan electrode driving unit.
  • FIG. 6A is a diagram showing another circuit configuration example of the scan electrode driver
  • FIG. 6B is a diagram showing another circuit configuration example of the scan electrode driving unit.
  • FIG. 7A is a diagram showing another circuit configuration example of the scan electrode driver
  • FIG. 7B is a diagram showing another circuit configuration example of the scan electrode driver
  • FIG. 8 is a detailed configuration diagram of a scan electrode driving unit in the plasma display driving apparatus in the second embodiment.
  • ⁇ 10 A diagram showing a voltage waveform applied to the scan electrode of the PDP and an on period of each switch element included in the scan electrode driving unit in the initialization period, the address period, and the discharge sustain period in the second embodiment.
  • ⁇ 11 A diagram showing a voltage waveform applied to the scan electrode of the PDP and an on period of each switch element included in the scan electrode driving unit in the initialization period, the address period, and the discharge sustain period in the third embodiment
  • FIG. 12 is a detailed configuration diagram of a scan electrode driving unit in the plasma display driving apparatus in the fourth embodiment.
  • FIG. 16 is a detailed configuration diagram of a scan electrode driving unit in the plasma display driving apparatus in the sixth embodiment.
  • FIG. 1 is a block diagram showing a configuration of a plasma display according to an embodiment of the present invention.
  • the plasma display has a PDP drive 10, plasma display panel (PDP ) 20 and a control unit 30.
  • the PDP 20 is, for example, an AC type, and has a three-electrode surface discharge type structure.
  • Address electrodes Al, A2, A3,... Are arranged on the rear substrate of the PDP 20 along the width direction of the panel.
  • sustain electrodes XI, X2, X3,... And scan electrodes Yl,... 2, ⁇ 3,... Are alternately arranged along the longitudinal direction of the panel.
  • the sustain electrodes XI, ⁇ 2, ⁇ 3, ... are connected to each other and have substantially the same potential.
  • a discharge cell is installed at the intersection of a pair of sustain electrode and scan electrode adjacent to each other (for example, a pair of sustain electrode ⁇ 2 and scan electrode ⁇ 2) and an address electrode (for example, address electrode ⁇ 2) (for example, FIG. (See the shaded area (1) shown in 1).
  • a layer made of a dielectric (dielectric layer), a layer for protecting the electrode and the dielectric layer (protective layer), and a layer containing a fluorescent substance (fluorescent layer) are provided on the surface of the discharge cell.
  • a layer made of a dielectric (dielectric layer), a layer for protecting the electrode and the dielectric layer (protective layer), and a layer containing a fluorescent substance (fluorescent layer) are provided on the surface of the discharge cell.
  • a predetermined pulse voltage is applied between the sustain electrode, the scan electrode, and the address electrode, discharge occurs in the discharge cell.
  • the gas in the discharge cell is excited and emits ultraviolet rays.
  • the ultraviolet rays excite the fluorescent material on the
  • the PDP driver 10 includes a scan electrode driver 11, a sustain electrode driver 12, and an address electrode driver 13.
  • Input terminals 1 of scan electrode drive unit 11 and sustain electrode drive unit 12 are connected to a power supply unit (not shown).
  • the power supply unit first converts an AC voltage from an external commercial AC power source into a constant DC voltage (for example, 400 V). Furthermore, the DC voltage is converted to the sustain voltage Vs by a DC-DC converter.
  • the sustain voltage Vs is applied to the PDP driving device 10. As a result, the potential of the input terminal 1 is maintained higher than the ground potential (0) by the sustain voltage Vs.
  • the output terminals of the scan electrode driver 11 are individually connected to the scan electrodes Yl, ⁇ 2, ⁇ 3, ... of the PDP 20, respectively.
  • the scan electrode driver 11 changes the potential of each of the scan electrodes Yl, ⁇ 2, ⁇ 3,.
  • the output terminal of sustain electrode drive unit 12 is connected to sustain electrodes XI, X2, X3,.
  • the sustain electrode driver 12 changes the potentials of the sustain electrodes XI, X2, X3,.
  • the address electrode drive unit 13 is individually connected to each of the address electrodes Al, A2, A3,.
  • the address electrode driver 13 generates a signal pulse voltage based on the video signal from the external force and applies it to the electrode selected from the address electrodes Al, A2, A3,.
  • the PDP driving device 10 follows the ADS (Address Display-period Separation) method and controls the potential of each electrode of the PDP20.
  • each field is divided into a plurality of subfields.
  • three periods initialization period, address period, and discharge sustain period
  • the length of the sustain period varies from subfield to subfield. In each of the initialization period, the address period, and the discharge sustain period, different pulse voltages are applied to the discharge cells as follows.
  • an initialization pulse voltage is applied between the sustain electrodes XI, X2, X3,... And the scan electrodes Yl, ⁇ 2, ⁇ 3,.
  • the wall charge is made uniform in all discharge cells.
  • the scan electrode driver 11 sequentially applies the scan pulse voltage to the scan electrodes Yl, ⁇ 2, ⁇ 3,.
  • the address electrode driver 13 applies the signal pulse voltage to the address electrodes Al, ⁇ 2, A3,.
  • the address electrode to which the signal pulse voltage is to be applied is selected based on the video signal input from the outside.
  • the scan electrode drive unit 11 and the sustain electrode drive unit 12 alternately change the discharge sustain pulse voltage to the scan electrodes Yl, ⁇ 2, ⁇ 3, ... and the sustain electrodes XI, ⁇ 2, ⁇ 3, ... and Apply to.
  • discharge is maintained in the discharge cell in which wall charges are accumulated during the address period, and light emission occurs. Since the length of the discharge sustain period varies from subfield to subfield, the light emission time per field of the discharge cell, that is, the luminance of the discharge cell is adjusted by selecting the subfield to emit light.
  • Scan electrode driver 11, sustain electrode driver 12, and address electrode driver 13 each include a switching inverter.
  • the control unit 30 performs switching control for these drive units. As a result, an initialization pulse voltage, a scan pulse voltage, a signal pulse voltage, and a discharge sustaining pulse voltage are generated with a predetermined waveform and timing, respectively.
  • the control unit 30 selects an address electrode to which a signal pulse voltage is applied based on a video signal having an external force.
  • the controller 30 further determines the length of the discharge sustain period after the application of the signal pulse voltage, that is, the subfield to which the signal pulse voltage is to be applied. As a result, each discharge cell emits light with appropriate brightness. In this way, the image corresponding to the video signal is reproduced by PDP20.
  • FIG. 2 shows a detailed configuration of the scan electrode driving unit 11.
  • Figure 2 also shows the equivalent circuit of PDP20.
  • Scan electrode driver 11 includes a scan pulse generator 1Y, an initialization pulse generator 2 ⁇ ⁇ , a discharge sustain pulse generator 3 ⁇ , and a recovery circuit 4 ⁇ .
  • PDP20 is equivalently represented by the stray capacitance Cp (hereinafter referred to as “PDP panel capacitance”) between sustain electrode X and scan electrode ⁇ , and the path of current flowing through PDP20 during discharge in the discharge cell is omitted. Is done.
  • the scanning noise generator 1Y includes a first constant voltage source VI and a series circuit (hereinafter referred to as “scanning circuit”) 10Y of a high side scanning switch element Q1Y and a low side scanning switch element Q2Y.
  • the first constant voltage source VI is based on the sustain voltage Vs applied from the power supply unit by, for example, a DC-DC converter (not shown). Maintain a certain voltage VI above the potential.
  • the two scanning switch elements Q1Y and Q2Y are, for example, MOSFETs. In addition, an IGBT or a bipolar transistor may be used.
  • the positive electrode of the first constant voltage source VI is connected to the drain of the high-side scanning switch element Q1Y.
  • the source of high side scan switch element Q1Y is connected to the drain of low side scan switch element Q2Y.
  • the connection point J1Y between them is connected to one scan electrode Y of the PDP20.
  • the source of the low-side scanning switch element Q2Y is connected to the negative electrode of the first constant voltage source VI.
  • the scanning circuit 10Y actually includes a series circuit of a no-side scanning switch element and a low-side scanning switch element, which is provided in the same number as the scanning electrodes Yl, ⁇ 2,. Each series circuit is connected to each of the scan electrodes Yl, ⁇ 2,.
  • the initial pulse generator 2 is the second constant voltage source V2, high side ramp waveform generator QR1
  • Low-side ramp waveform generator QR2 Low-side ramp waveform generator QR2, third constant voltage source V3, first isolation switch element Q
  • the second constant voltage source V2 maintains the potential of the positive electrode by a predetermined voltage V2 higher than the potential of the negative electrode based on the sustain voltage Vs applied from the power supply unit by, for example, a DC-DC converter.
  • the third constant voltage source V3 maintains the potential of the positive electrode by a predetermined voltage V3 higher than the potential of the negative electrode based on the sustain voltage Vs applied from the power supply unit by, for example, a DC-DC converter.
  • the high side ramp waveform generators QR1 and QR2 include, for example, an N-channel MOSFET (NMOS) and a capacitor that connects the gate and drain of the NMOS.
  • NMOS N-channel MOSFET
  • the ramp waveform generators QR1 and QR2 When the ramp waveform generators QR1 and QR2 are turned on, the NMOS drain-source voltage changes to zero at a substantially constant speed. That is, the ramp waveform generators QR1 and QR2 generate a ramp waveform that monotonously increases or monotonously decreases.
  • the ramp waveform is not limited to a waveform that increases or decreases linearly, but also includes a waveform that increases or decreases in a curvilinear manner and a waveform that increases or decreases in a stepwise manner due to the CR time constant.
  • the positive electrode of the second constant voltage source V2 is connected to the drain of the high side ramp waveform generator QR1.
  • the source of QR1 is connected to the negative terminal of the first constant voltage source VI. .
  • the negative electrode of the second constant voltage source V2 is grounded.
  • the drain of the low side ramp waveform generator QR2 is connected to the negative electrode of the first constant voltage source VI, and the source of the low side ramp waveform generator QR2 is connected to the negative electrode of the third constant voltage source V3.
  • the positive electrode of the third constant voltage source V3 is grounded.
  • the source of the second separation switch element QS2 is connected to the negative electrode of the first constant voltage source VI.
  • the drain of the second isolation switch element QS2 is connected to the drain of the first isolation switch element QS1, and the source of the first isolation switch element QS1 is connected to the connection point J2 Y of the discharge sustain pulse generator 3Y.
  • the case where the voltage V2 of the second constant voltage source is larger than the sustain voltage Vs is described.
  • the voltage V2 of the second constant voltage source is equal to or lower than the sustain voltage Vs, If the high-side sustaining switch element Q7Y is off, it will not be clamped to the sustaining voltage Vs in mode V! /, So the first isolation switch element QS1 is not required.
  • Discharge sustaining pulse generating unit 3Y includes a series circuit of high side sustaining switch element Q7Y and low side sustaining switch element Q8Y.
  • the sustain voltage source Vs maintains the positive electrode potential higher than the negative electrode potential by a constant voltage Vs.
  • the positive electrode of sustain voltage source Vs is connected to the drain of high side sustain switch element Q7Y, and the source of high side sustain switch element Q7Y is connected to the drain of low side sustain switch element Q8Y.
  • the source of the low-side sustain switch element Q8Y is connected to the negative electrode of the sustain voltage source Vs.
  • the negative electrode of the sustain voltage source Vs is, for example, 0V (ground state).
  • the connection point J2Y between the high-side sustain switch element Q7Y and the low-side sustain switch element Q8Y is connected to the source of the first separation switch element QS1 as the output terminal of the discharge sustain pulse generator 3Y.
  • the voltage Vs is the maximum voltage value applied to the scan electrode during the sustain discharge operation. In the following explanation, the ground potential is also high by the voltage V, and the potential is expressed as the potential V.
  • the recovery circuit 4Y includes a first recovery inductor LY1, a second recovery inductor LY2, a recovery capacitor CY, a first recovery diode D1, a second recovery diode D2, a noisy side recovery switch element Q9Y, and a low side recovery switch. Includes element Q10Y.
  • Two recovery switch elements The children Q9Y and Q10Y are, for example, MOSFETs. In addition, an IGBT or a bipolar transistor may be used.
  • the source of the high-side recovery switch element Q9Y is connected to the anode of the first recovery diode D1, and the force sword of the first recovery diode D1 is connected to one end of the first recovery inductor LY1.
  • One end of the second recovery inductor LY2 is connected to the anode of the second recovery diode D2, and the force sword of the second recovery diode D2 is connected to the drain of the low-side recovery switch element Q10Y.
  • the other end of the first recovery inductor LY1 is connected to the connection point J2Y.
  • the other end of the second recovery inductor LY2 is connected to the connection point J2Y.
  • One end of the recovery capacitor CY is connected to the negative electrode of the DC voltage Vs, and the other end is connected to the drain of the high side recovery switch element Q9Y and the source of the low side recovery switch element Q10Y.
  • the capacity of the recovery capacitor CY is sufficiently larger than the panel capacity Cp of the PDP20.
  • the voltage across the recovery capacitor CY is maintained substantially equal to the half value VsZ2 of the sustain voltage Vs applied from the power supply.
  • the recovery circuit 4Y performs LC resonance between the first and second recovery inductors LY1 and LY2, the recovery capacitor CY, and the panel capacitance of PDP20, via the diode D2 and the low-side recovery switch element Q10Y. Collect power from PDP20 to recovery capacitor CY. Further, the recovered power is supplied from the recovery capacitor CY to the PDP 20 via the high-side recovery switch element Q9Y and the diode D1. Note that the output end of the recovery circuit 4Y (the other end of the first recovery inductor LY1) is the “power supply end”, and the input end of the recovery circuit 4Y (the other end of the second recovery inductor LY2) is the “power recovery end”. " The recovery circuit 4Y reduces power consumption.
  • FIG. 3A is a diagram showing a voltage waveform applied to the scan electrode Y of the PDP 20 and an on period of each switch element included in the scan electrode driving unit 11 in each of the initialization period, the address period, and the discharge sustain period.
  • the ON period of each switch element is indicated by hatching.
  • the initialization period is divided into the following nine modes I to IX according to changes in the initialization pulse voltage. As shown in Fig. 3A, a voltage waveform (ramp waveform) that rises or falls in mode II, mode V, and mode IX is applied to the scan electrodes. The operation in each mode will be described below. Note that the period of the mode I and II in the initialization period is referred to as “erasing period”.
  • the erasing period is a period for erasing the wall charges of the discharge cells that have been discharged during the discharge maintaining period.
  • the strong discharge cell not discharged during the discharge sustain period in modes I and II is a strong discharge, Weak discharge does not occur.
  • the wall charges accumulated in the discharge cells are almost uniform. Therefore, all the discharge cells have an up-ramp waveform and a down-ramp waveform. A weak discharge occurs.
  • low-side scan switch element Q2Y, first separation switch element QS1, second separation switch element QS2, and high-side sustain switch element Q7Y are maintained in the ON state.
  • the remaining switch elements are kept off.
  • the scan electrode Y is maintained at the potential Vs which is higher by the sustain voltage Vs than the ground potential ( ⁇ 0) force.
  • the high side sustain switch element Q7Y and the second separation switch element QS2 are turned off while the low side scan switch element Q2Y and the first separation switch element QS1 are kept on, and the low side ramp waveform Generator QR2 turns on.
  • the remaining switch elements are kept off.
  • the potential of the scan electrode ⁇ falls at a constant speed to the potential V3, which is lower than the ground potential (0) by the voltage V3 of the third constant voltage source. In this way, the applied voltage uniformly drops to the potential of V3 uniformly in all the discharge cells of DP20. As a result, the wall charge is removed (erased) in the discharge cell having the wall charge of PDP20 and is made uniform.
  • the sustain voltage Vs is applied to the sustain electrode X immediately before the low-side ramp waveform generator QR2 is turned on.
  • the voltage applied to the sustain electrode X may be lower than the sustain voltage Vs.
  • the sustain voltage Vs may be applied during Mode I.
  • the low-side ramp waveform generator QR2 is turned off while the low-side scan switch element Q2Y and the first separation switch element QS1 are kept on, and the second separation switch element QS2 and the low-side maintenance switch are turned on.
  • the device Q8Y is turned on, and the remaining switch devices are kept off. As a result, the scan electrode Y rises to the ground potential (O).
  • the first separation switch element QS1, the second separation switch element Q S2 and the low side sustaining switch element Q8Y are maintained in the ON state, and the low side running switch element Q2Y is turned off and the high side switching element Q2Y is turned off.
  • the scanning switch element Q1Y is turned on, and the remaining switch elements are kept off.
  • the potential of the scan electrode Y rises from the ground potential (0) to the potential VI that is higher by the voltage VI of the first voltage source VI.
  • Voltage VI is smaller than the discharge start voltage applied to the scan electrode during sustain discharge operation.
  • the starting voltage when raising the applied voltage to the scan electrode Y in the initialization period is set to a value lower than the discharge starting voltage. This prevents light emission in the discharge cell. The reason will be described below.
  • a discharge sustaining period (Note: Mode I is a part of the discharge sustaining period)
  • the power that the discharge cell emits (discharges), that is, the wall of the discharge cell Whether or not charges are accumulated depends on the state of the image.
  • the discharge start voltage is lower than normal, so the position of the light emitting (discharged) discharge cell is It depends on the state of the image.
  • the discharge cells of the PDP 20 are subject to changes over time due to variations in the discharge starting voltage in each discharge cell and differences in light emission (discharge) time in the discharge cells.
  • the wall charge may not be sufficiently removed in the discharge cell with the wall charge of PDP20 in mode II.
  • the voltage applied to the scan electrode Y is lower than the discharge start voltage and can only be increased to the voltage, light emission does not occur in all the discharge cells of the PDP 20 even in such a case.
  • the discharge start voltage includes variations in the discharge start voltage within the surface of the panel, changes over time, and low discharge start voltage due to discharge cells between adjacent ones. In consideration of the following effects, the lowest discharge start voltage is adopted. This discharge start voltage is generally slightly higher than the sustain voltage Vs.
  • the first separation switch element QS1 and the low-side maintenance switch element Q8Y are turned off while the high-side scan switch element Q1Y and the second separation switch element QS2 are maintained in the on state.
  • Side ramp waveform generator QR1 turns on.
  • the remaining switch elements are kept off.
  • the sum voltage Vr is referred to as “the upper limit of the initialization pulse voltage”.
  • the drain potential of the first isolation switch element QS1 also rises via the second isolation switch element QS2.
  • the applied voltage uniformly increases in all the discharge cells of the PDP 20 toward the upper limit Vr of the initialization pulse voltage relatively slowly.
  • uniform wall charges are accumulated in all discharge cells of the PDP20.
  • the rate of increase of the applied voltage is small, so that the light emission of the discharge cell can be suppressed to be weak.
  • the high / side sustain switch element Q7Y is turned on while the high side scan switch element Q1Y, the second separation switch element QS2 and the high side ramp waveform generator QR1 are maintained in the on state. The remaining switch elements are kept off. In mode VI, the potential of scan electrode Y has already reached potential Vr.
  • the drain potential of the first isolation switch element QS1 rises.
  • the high-side switch element Q7Y may be turned on when the drain potential of the first isolation switch element QS1 becomes the potential V2 by the second constant voltage source V2.
  • the high-side sustain switch element Q7Y in mode VI, the high-side sustain switch element Q7Y is turned on. However, the drain potential of the first isolation switch element QS1 does not rise above the voltage V2 of the second constant voltage source, so the high-side sustain switch element Q7Y may remain off.
  • the applied voltage uniformly increases in all the discharge cells of the PDP 20 to the upper limit Vr of the initialization pulse voltage relatively slowly.
  • uniform wall charges are accumulated in all the discharge cells of the PDP20.
  • the rate of increase of the applied voltage is small, the light emission of the discharge cell is suppressed to be weak.
  • the high-side ramp waveform generator QR1 is turned off while the high-side scan switch element Q1Y, the second separation switch element QS2 and the high-side sustain switch element Q7Y are maintained in the ON state.
  • the isolation switch element QS1 turns on. The remaining switch elements are kept off. As a result, the potential of the scan electrode Y falls to the potential (Vs + Vl).
  • the high-side sustain switch element Q7Y is turned on. However, since the body diode of the high-side sustaining switch element Q7Y conducts, the non-side sustaining switch element Q7Y can remain off.
  • the first and second separation switch elements QS1, QS2 and the high-side sustain switch element Q7Y are maintained in the ON state, and the non-side shift switch element Q1Y is turned off.
  • the low-side scanning switch element Q2Y is turned on.
  • the remaining switch elements are kept off. As a result, the potential of the scan electrode Y falls to the potential Vs.
  • the low-side scan switch element Q2Y and the first separation switch element QS1 are maintained in the ON state, while the high-side sustain switch element Q7Y and the second switch element Q7Y Separation switch element QS2 turns off and low side ramp waveform generator QR2 turns on. The remaining switch elements are kept off.
  • the potential of the scan electrode Y drops to the potential –V3 at a constant rate.
  • the sustain voltage Vs is applied to the sustain electrode X immediately before the low-side ramp waveform generator QR2 is turned on.
  • the voltage applied to the sustain electrode X may be lower than the sustain voltage Vs. Further, the sustain voltage V s may be applied to the sustain electrode X during the modes VII and VIII.
  • mode IX modes IV to VIII
  • a relatively gentle voltage having a polarity opposite to that applied in modes IV to VIII is applied, so that unlike mode II, wall charges are uniformly removed in all discharge cells. , Uniform.
  • the rate of decrease of the applied voltage force S is small, so that the light emission of the discharge cell is suppressed weakly.
  • all address electrodes A are applied to the address electrode A during the mode IV period and the initial period of the mode V.
  • the upper limit Va of the signal pulse voltage may be applied (the signal pulse applied to the address electrode A may be turned on.) 0 Specifically, when the signal pulse voltage is applied during the mode IV period In the mode IV period, the potential of all address electrodes A may reach the upper limit Va of the signal pulse voltage.
  • the potential of the scan electrode Y rises due to capacitive coupling between the address electrode A and the scan electrode Y by applying the signal pulse voltage. Therefore, the potentials of all the address electrodes A only need to reach the upper limit Va of the signal pulse voltage by the initial period of mode V in which the potential of the scan electrode Y reaches the discharge start voltage due to the application of the signal pulse voltage.
  • the signal pulse voltage applied to all the address electrodes A may be set to the upper limit Va and the ground potential (the signal pulse applied to the address electrode A is turned off).
  • the potential of the sustain electrode X reaches the sustain voltage Vs during the period of modes IV to IX (mode IX in the figure).
  • the signal pulse voltage is set to the ground potential prior to the voltage application of the sustain electrode driver.
  • FIG. 3B shows another example of the driving method in the initialization period.
  • the operation in modes VII to VIII in which the voltage applied to the scan electrode is lowered from the upper limit Vr of the initialization pulse voltage to the sustain voltage Vs is different from that shown in FIG. 3A.
  • the high-side ramp waveform generator QR1 in mode VII, the high-side ramp waveform generator QR1 is turned off, the first separation switch element QS1 is turned on, and in mode VIII, the no-side running switch Element Q1Y was turned off, and low-side scan switch element Q2Y was turned on!
  • the high-side scanning switch element Q1Y in mode VII, the high-side scanning switch element Q1Y is turned off, the low-side scanning switch element Q2Y is turned on, and in mode VIII, the high-side ramp waveform generator QR1 is turned off.
  • the first separation switch element QS1 is turned on.
  • the operation of mode VII and the operation of mode VIII are reversed from those shown in FIG. 3A. Note that the concept of the driving method shown in FIG. 3B can be applied to other embodiments described later.
  • FIG. 3C shows another example of the driving method in the initialization period.
  • the operation in modes IV to V in which the voltage applied to the scan electrode is increased from the ground potential to the upper limit Vr of the initialization pulse voltage is different from that shown in FIG. 3A.
  • the operation of modes IV to V will be described.
  • the high side ramp waveform generator QR1 and the second separation switch element QS2 are maintained in the on state, the low side scan switch element Q2Y is turned off, and the no side scan switch element Q1Y is turned on. The remaining switch elements are kept off.
  • the potential of the scan electrode Y is increased by the voltage Vk increased by the negative ramp waveform generator QR1 during the mode IV period with respect to the ground potential (0) and the voltage VI of the first voltage source VI. ! Increases from the sum of the potential VI (Vk + Vl) to the initialization pulse voltage upper limit Vr.
  • the voltage (Vk + Vl) is smaller than the discharge start voltage.
  • the starting voltage when raising the voltage applied to the scan electrode Y in this initializing period is set to a value lower than the discharge starting voltage. This prevents light emission in the discharge cell.
  • the signal pulses are applied to all the address electrodes A in the initial period of mode V.
  • the upper limit Va of the source voltage may be applied! (The signal pulse applied to the address electrode A may be turned on.).
  • the potential of the scan electrode Y rises due to the capacitive coupling between the address electrode A and the scan electrode Y due to the application of the signal pulse voltage. Therefore, the potentials of all the address electrodes A only need to reach the upper limit Va of the signal pulse voltage by the initial period of mode V when the potential of the scanning electrode Y reaches the discharge start voltage due to the influence of the signal pulse voltage application.
  • the sustain voltage Vs is maintained at the sustain electrode.
  • the high side scan switch element Q1Y is maintained in the on state and the low side scan switch element Q2Y is maintained in the off state for all the scan electrodes Y !. Therefore, the potentials of all the scan electrodes Y are uniformly maintained at the upper limit Vp of the scan pulse voltage.
  • scan electrode driving unit 11 changes the potential of scan electrode Y as follows (see scan pulse voltage SP shown in FIG. 3A).
  • scan pulse voltage SP shown in FIG. 3A.
  • the high side scan switch element Q1Y connected to the scan electrode Y is turned off and the low side scan switch element Q2Y is turned on.
  • the potential of the scan electrode Y drops to ⁇ V3.
  • the low-side scanning switch element Q2Y connected to the scanning electrode Y is turned off and the high-side scanning switch element Q1Y is turned on.
  • the potential of the scan electrode Y rises to the upper limit Vp of the scan pulse voltage.
  • the scan electrode drive unit 11 sequentially performs the same switching operation as described above for the scan switch element pairs Q1Y and Q2Y connected to the scan electrodes.
  • the scan pulse voltage SP is sequentially applied to each of the scanning electrodes.
  • the scan pulse voltage SP is applied to one scan electrode Y and the signal pulse voltage is applied to one address electrode A
  • the voltage between the scan electrode Y and the address electrode A is different. Higher than the voltage between the electrodes. Therefore, a discharge occurs at the discharge cell located at the intersection between the scan electrode Y and the address electrode A. The discharge accumulates new wall charges on the surface of the discharge cell.
  • scan electrode drive unit 11 and sustain electrode drive unit 12 alternately apply a sustain discharge pulse voltage to scan electrode Y and sustain electrode X, respectively (see FIG. 3A).
  • discharge occurs in the discharge cells in which wall charges are accumulated during the address period. Since it is maintained, light emission occurs.
  • the non-side recovery switch element Q9Y is turned on, the low-side sustain switch element Q8Y is on, and the voltage across the panel capacitance Cp is maintained at 0V.
  • the high-side recovery switch element Q9Y is turned on, the recovery capacitor CY, the high-side recovery switch element Q9Y, the first recovery diode D1, the first recovery inductor LY1, and the panel capacitance Cp make the LC resonant circuit It is formed. This increases the voltage across the panel capacitance Cp to Vs. The remaining switch elements are kept off.
  • the high side recovery switch element Q9Y is turned off and the high side sustain switch element Q7 Y is turned on, the voltage across the panel capacitance Cp is maintained at Vs. At this time, since the drain-source voltage of the high-side sustain switch element Q7Y is zero, it can be turned on with almost no loss (the remaining switch elements are maintained in the off state).
  • the low side recovery switch element Q10Y is turned off and the low side sustain switch element Q8Y is turned on, the voltage across the panel capacitance Cp is maintained at zero. At this time, since the drain-source voltage of the low-side sustain switch element Q8Y is zero, it can be turned on with almost no loss (the remaining switch elements are maintained in the off state).
  • the technical idea of this embodiment can be applied to the circuit configuration of FIG. In Fig. 5, the connection position of the high-side ramp waveform generator QR1 of the initialization pulse generator 6Y is different from that in Fig. 2, and the source of the high-side waveform generator QR1 is connected to the drain of the high-side scan switch element Q1Y.
  • the second constant voltage source V2 of the initialization pulse generator 6Y is replaced with a fourth constant voltage source Vr.
  • the fourth constant voltage source Vr is based on the sustain voltage Vs applied from the power supply unit by, for example, a DC-DC converter (not shown), and the fourth constant voltage source Vr has a positive potential from a negative potential. Maintain a constant voltage Vr high.
  • the voltage Vr is the same voltage as the upper limit Vr of the initialization pulse voltage.
  • the technical idea of this embodiment can be applied to the circuit configuration of FIG. 6A.
  • the connection position of the first separation switch element QS1 in the initialization pulse generator 7Y is different from that in FIG. 2, and the source of the first separation switch element QS1 is connected to the source of the high-side sustain switch element Q7Y.
  • the drain of the first isolation switch element QS1 is connected to the drain of the low-side sustain switch element Q8Y. As a result, the amount of current flowing through the first separation switch element QS1 during the sustain period can be reduced.
  • FIG. 6B differs from that in FIG. 6A in the connection position of the source of the high-side ramp waveform generator QR1. That is, in the configuration shown in FIG. 6B, the source of the high-side ramp waveform generator QR1 is connected to the drain of the second separation switch QS2. With this configuration, the drain and source voltage of the absolute maximum rating of the no-side ramp waveform generator QR1 can be lowered.
  • FIG. 7B differs from that of FIG. 7A in the connection position of the source of the high-side ramp waveform generator QR1. That is, in the configuration shown in FIG. 7B, the source of the high-side ramp waveform generator QR1 is connected to the drain of the second separation switch QS2. With this configuration, the drain / source voltage of the absolute ramp waveform generator QR1 with the absolute maximum rating can be reduced. [0105] 1. 4 Summary
  • the PDP driving device of the present embodiment reduces the start voltage of the rising ramp waveform in the initialization period (that is, the start voltage when increasing the voltage applied to the scan electrode Y) to a voltage lower than the discharge start voltage. Set. Therefore, when a voltage exceeding the discharge start voltage is applied to the scan electrode Y, it is a period during which the voltage gradually rises to the scan electrode Y (up-ramp waveform period), and thus weak light emission occurs. This suppresses light emission when the applied voltage rises, and provides good contrast when displaying images on a PDP.
  • FIG. 8 shows a detailed configuration of the scan electrode driving unit according to the second embodiment of the present invention.
  • the scan electrode driving unit 11 according to the present embodiment is different from that of the first embodiment shown in FIG. 2 in the configuration of the initialization pulse generating unit. More specifically, the configuration of the high-side ramp waveform generator QR1 in the initialization pulse generator is different. Other components are the same as those in the first embodiment.
  • the configuration of the initialization pulse generator 9Y of the present embodiment is different from that of the initialization pulse generator 2 ⁇ of the first embodiment in the side ramp waveform generator QR1.
  • FIG. 9 ⁇ shows the detailed configuration of the high-side ramp waveform generator QR3.
  • the negative side ramp waveform generator QR3 includes a high side NMOS (Q30Y), a ramp waveform capacitor Cl, a ramp waveform Zener diode ZD1, and a gate circuit 33.
  • the drain of the high-side NMOS (Q30Y) is connected to the positive electrode of the second constant voltage source V2, and the source is connected to the negative electrode of the first constant voltage source VI.
  • One end of the ramp waveform capacitor C1 is connected to the drain of the high-side NMOS (Q30Y), and the other end is connected to the anode of the ramp waveform Zener diode ZD1.
  • Ramp waveform Zener diode ZD1's force sword is connected to the gate of the high-side NMOS (Q30Y).
  • the gate circuit 33 is connected to the gate of the high side NMOS (Q30Y), receives a control signal from the control unit 30, and outputs a predetermined current based on the control signal.
  • the gate circuit 33 when the gate circuit 33 receives a signal from the control unit 30, it outputs a constant current. As a result, a current flows through the zener diode ZD 1 for the ramp waveform, and a zener voltage Ve is generated. At this time, the charge accumulated in the ramp waveform capacitor C1 is a force that begins to discharge.
  • the drain-gate voltage of the high-side NMOS (Q30Y) is drastically reduced by the Zener voltage. For this reason, the source potential of the high-side NMOS (Q30Y) rises sharply even immediately after the control unit 30 receives the signal. This steep rise voltage depends on the Zener voltage of the ramp waveform Zener diode Z D1.
  • the electric current from the gate circuit 33 discharges the charge of the ramp waveform capacitor C1 at a constant rate, so that the source potential of the high side NMOS (Q30Y) also rises at a constant rate. After that, when the drain-gate voltage of the high-side NMOS (Q30Y) becomes zero and the gate-source voltage of the high-side NMOS (Q30Y) rises, the potential of the source and drain of the high-side NMOS (Q30Y) is almost Will be equal.
  • the start voltage (mode V start voltage) of the up-ramp waveform in the initialization period can be arbitrarily set by setting the Zener voltage of the Zener diode for the ramp waveform.
  • a shunt regulator, a diode, and a resistor may be used instead of the Zener diode. It can be set to any voltage depending on the relationship between the internal reference voltage and resistance.
  • Fig. 9B shows an example of the configuration of QR3, a high-side ramp waveform generator that includes a chantregulator.
  • 9A differs from the circuit configuration shown in FIG. 9A in that a diode D11, a series circuit of resistors Rll and R12, and a shunt regulator 35 are provided instead of the Zener diode ZD1 in the configuration of FIG. 9A. It is a point.
  • the electric current from the gate circuit 33 discharges the charge of the ramp waveform capacitor C1 at a constant rate, so that the source potential of the high side NMOS (Q30Y) also rises at a constant rate. After that, when the drain-gate voltage of the high-side NMOS (Q30Y) becomes zero and the gate-source voltage of the high-side NMOS (Q30Y) rises, the potential of the source and drain of the high-side NMOS (Q30Y) is almost Will be equal.
  • the start voltage (mode V start voltage) of the up-ramp waveform during the initialization period can be arbitrarily set by setting the predetermined voltage of the shunt regulator 35.
  • a constant voltage circuit can be used.
  • the ramp waveform in the initialization period in order to accumulate and remove wall charges uniformly and uniformly and to prevent strong light emission, the ramp waveform The slope cannot be steep.
  • the time of the initialization period depends on the potential difference between the ramp waveform slope, the ramp waveform start voltage, and the ramp waveform end voltage, if the ramp waveform slope is moderated, the initialization period becomes longer. Subfi The number of half periods is suppressed, and the number of gradations in image display is suppressed.
  • the start voltage of the rising ramp waveform in the initialization period is set so that the potential of the scan electrode Y is greater than VI and less than the discharge start voltage. Strong light emission can be suppressed by making the potential of the scan electrode Y smaller than the discharge start voltage.
  • the lowest discharge start voltage is adopted as the discharge start voltage in consideration of variations in the discharge start voltage within the surface of the panel, changes with time, and the effects of a decrease in the discharge start voltage due to discharge cells between adjacent ones.
  • This discharge start voltage is generally slightly higher than the sustain voltage Vs.
  • the ramp waveform start voltage in mode V can be increased by increasing the potential of scan electrode Y by V, so that the initialization period can be shortened. In this way, it is possible to achieve both shortening of the initialization period and suppression of light emission in mode IV. In other words, the contrast can be increased and the gradation can be increased in the image display.
  • FIG. 10 is a diagram illustrating a voltage waveform applied to the scan electrode Y of the PDP 20 and an on period of each switch element included in the scan electrode driving unit 11 in each of the initialization period, the address period, and the discharge sustain period.
  • the ON period of each switch element is indicated by hatching.
  • the operation in each period will be described. Note that only the voltage waveforms applied to the sustain electrode X and the address electrode A of the PDP 20 in the initialization period, the address period, and the discharge sustain period are shown, and the on period of each switch element is not shown.
  • the initialization period is divided into the following nine modes I to IX according to changes in the initialization pulse voltage.
  • low-side scan switch element Q2Y, first separation switch element QS1, second separation switch element QS2, and high-side sustain switch element Q7Y are maintained in the ON state.
  • the remaining switch elements are kept off. Accordingly, the scan electrode Y is maintained at a potential that is higher than the ground potential (0) by the voltage Vs of the sustain voltage Vs.
  • the sustain voltage Vs is applied to the sustain electrode X immediately before the low-side ramp waveform generator QR2 is turned on.
  • the voltage applied to the sustain electrode X may be a value lower than the sustain voltage Vs. Further, the sustain voltage Vs may be applied during the mode I period.
  • the low-side ramp waveform generator QR2 is turned off while the low-side scan switch element Q2Y and the first separation switch element QS1 are kept on, and the second separation switch element QS2 and the low-side maintenance switch are turned on. Turn on element Q8Y. The remaining switch elements are kept off. As a result, the scan electrode Y rises to the ground potential (0).
  • the first separation switch element QS1, the second separation switch element Q S2 and the low side sustain switch element Q8Y are maintained in the on state, and the low side running switch element Q2Y is turned off and the high side switch element Q2Y is turned off. Turn on the scanning switch element Q1Y. The remaining switch elements are kept off. As a result, the potential of the scan electrode Y rises to the potential that the ground potential (0) force is higher by the voltage VI of the first voltage source VI.
  • the voltage of scan electrode Y in mode IV is lower than voltage VI, that is, the discharge start voltage, and is increased only to the voltage. No light emission occurs in all the discharge cells of the PDP20 regardless of the image state during the period, for example, the discharge sustain period (Note: Mode I is part of the discharge sustain period)!
  • the value of the predetermined potential (that is, the start voltage of the up-ramp waveform) is Vs as an example of a value that is larger than V and less than the discharge start voltage.
  • the value of the predetermined potential can be appropriately changed by adjusting the Zener voltage Ve of the Zener diode ZD 1 for the ramp waveform.
  • the value of the predetermined potential (that is, the start voltage of the up-ramp waveform) may be set to a value that is larger than the V-beam and smaller than the discharge start voltage.
  • the applied voltage uniformly increases for all the discharge cells of the PDP 20, and rises relatively slowly as it tends to the upper limit Vr of the initialization pulse voltage.
  • uniform wall charges are accumulated in all discharge cells of the PDP20.
  • the rate of increase of the applied voltage is small, so that the light emission of the discharge cell can be suppressed to a weak level.
  • the drain potential of the first isolation switch element QS1 rises.
  • the high-side switch element Q7Y may be turned on when the drain potential of the first isolation switch element QS1 becomes the voltage V2 of the second constant voltage source.
  • first isolation switch element QS1 Force that one diode remains off Voltage fluctuation ⁇ is transmitted to the drain of first isolation switch element QS1 via the parasitic capacitance of first isolation switch element QS1.
  • the source potential of the second isolation switch element QS2 is clamped when the body diode of the high-side NMOS (Q30Y) in the negative side ramp waveform generator QR3 is turned on, so the voltage fluctuations in the potential of the scan electrode ⁇ ⁇ does not occur.
  • the high-side sustain switch element Q7Y in mode VI, the high-side sustain switch element Q7Y is turned on. However, since the drain potential of the first isolation switch element QS1 does not rise above the voltage V2 of the second constant voltage source, the high-side sustain switch element Q7Y may remain off.
  • the applied voltage rises relatively slowly to the upper limit Vr of the initialization pulse voltage uniformly in all the discharge cells of the PDP 20.
  • uniform wall charges are accumulated in all the discharge cells of the PDP20.
  • the rate of increase of the applied voltage is small, so that the light emission of the discharge cell can be suppressed to a weak level.
  • the high-side ramp waveform generator QR3 is turned off while the high-side scan switch element Q1Y, the second separation switch element QS2 and the high-side sustain switch element Q7Y are maintained in the ON state.
  • the isolation switch element QS1 turns on.
  • the remaining switch elements are kept off.
  • the potential of the scan electrode Y drops from Vr to (Vs + Vl).
  • the high side sustaining switch element Q7Y is turned on. However, since the body diode of the high side switching element Q7Y conducts, it may remain off.
  • the first and second separation switch elements QS1, QS2 and the high-side sustain switch element Q7Y are maintained in the ON state, and the non-side shift switch element Q1Y is turned off.
  • the low-side scanning switch element Q2Y is turned on.
  • the remaining switch elements are kept off. As a result, the scan electrode Y falls to the potential Vs.
  • ⁇ Mode IX> In the scan electrode driver 11, the high side sustain switch element Q7Y and the second separation switch element QS2 are turned off while the low side scan switch element Q2Y and the first separation switch element QS1 are kept on, and the low side ramp waveform Generator QR2 turns on. The remaining switch elements are kept off.
  • the potential of the scan electrode Y is lowered to the potential ⁇ V3 by the third constant voltage source at a constant speed.
  • the sustain voltage Vs is applied to the sustain electrode X immediately before the low-side ramp waveform generator QR2 is turned on.
  • the voltage applied to the sustain electrode X may be lower than the sustain voltage Vs. Further, the sustain voltage Vs may be applied to the sustain electrode X during modes VII and VIII.
  • mode IX modes IV to VIII
  • a relatively gentle voltage having a polarity opposite to that applied in modes IV to VIII is applied, so that unlike mode II, wall charges are uniformly removed in all discharge cells. , Uniform.
  • the rate of decrease of the applied voltage force S is small, so that the light emission of the discharge cell is suppressed weakly.
  • signal pulses are applied to all address electrodes A during mode IV and at the beginning of mode V.
  • An upper limit Va of the voltage may be applied. For example, if a signal pulse voltage is applied during the mode IV period, the potential of all address electrodes A may reach the upper limit Va of the signal pulse voltage during the mode IV period!
  • the Zener voltage Ve may be set in mode V in consideration of the voltage increase of the scanning electrode Y due to the Zener voltage and the voltage increase of the scan electrode Y due to the application of the signal pulse voltage.
  • the signal pulse voltage is applied to the address electrode during the period of mode IV. It is sufficient if the potential reaches the upper limit Va of the signal pulse voltage. In this case, the signal path Since the potential of scan electrode Y rises due to capacitive coupling between address electrode A and scan electrode Y, the potential of scan electrode Y rises to the discharge start voltage due to the influence of signal pulse voltage application. It is only necessary that the potentials of all address electrodes A reach the upper limit Va of the signal pulse voltage by the initial stage of V.
  • the Zener voltage Ve may be set in mode V in consideration of the voltage increase of the scan electrode Y due to the Zener voltage and the voltage increase of the scan electrode Y due to the application of the signal pulse voltage.
  • the signal pulse voltage applied to all address electrodes A can be set to the ground potential with an upper limit Va (the signal pulse applied to address electrode A is turned off).
  • the potential of the sustain electrode X reaches the sustain voltage Vs (mode IX in the figure).
  • the signal pulse voltage is set to the ground potential prior to the voltage application of the sustain electrode driver.
  • each switch element of the scan electrode unit 11 in the address period and the discharge sustain period is the same as that described in the first embodiment.
  • the high side ramp waveform generator QR3 can be provided instead of the high side ramp waveform generator QR1.
  • the driving method of FIGS. 3B and 3C shown in the first embodiment can be applied to the circuit configuration of the present embodiment.
  • the starting voltage when increasing the voltage applied to scan electrode Y in mode V during the initialization period is the voltage V k + Vl + Ve.
  • the voltage Vk + Vl + Ve at this time is set to a value lower than the discharge start voltage. This prevents light emission in the discharge cell.
  • the signal pulse voltage is applied to all the address electrodes A during the initial period of mode V. Even if the upper limit Va is applied, the signal pulse applied to the address electrode A may be turned on. At this time, the potential of the scan electrode Y rises due to capacitive coupling between the address electrode A and the scan electrode Y due to the application of the signal pulse voltage. Therefore, the potential of the scan electrode Y rises to the discharge start voltage due to the influence of the signal pulse voltage application. It is only necessary that the potentials of all address electrodes A reach the upper limit Va of the signal pulse voltage by the beginning of mode V.
  • the Zener voltage Ve should be set in mode V taking into account the voltage increase of scan electrode Y due to the Zener voltage and the voltage increase of scan electrode Y due to the application of the signal pulse voltage!
  • the start voltage of the rising ramp waveform in the initialization period is set so that the potential force of the scan electrode Y is larger and smaller than the discharge start voltage. Therefore, when a voltage exceeding the discharge start voltage is applied to the scan electrode Y, it is a period during which the voltage gradually rises to the scan electrode Y (up-ramp waveform period), and thus weak light emission occurs. This suppresses strong light emission by making the potential of the scan electrode Y smaller than the discharge start voltage, and increases the ramp waveform start voltage in mode V by setting the potential of the scan electrode Y to a larger value. Therefore, the initialization period will be shortened. Therefore, both the shortening of the initialization period and the suppression of light emission in mode IV can be achieved at the same time, that is, the contrast can be increased in the image display and the gradation can be increased.
  • the scan electrode driving unit 11 according to the present embodiment has the same circuit configuration as that of the first embodiment shown in FIG. 2, but the driving method is different.
  • the driving method of the present embodiment makes it possible to reduce the voltage applied between the drain and source of the first isolation switch element QS1.
  • the highest voltage applied between the drain and source of the first isolation switch element QS1 during the mode V period is the high-side ramp waveform generator immediately before the high-side sustain switch element Q7Y is turned on.
  • the drain-source voltage of the absolute maximum rating of the first isolation switch element QS1 according to the present embodiment is equal to or greater than the larger value of the voltage Vd and the voltage V2-Vs.
  • FIG. 11 shows the voltage waveform applied to the scan electrode Y of the PDP 20 and the ON period of each switch element included in the scan electrode drive unit 11 in each of the initialization period, address period, and discharge sustain period in this embodiment.
  • FIG. 11 the ON period of each switch element is indicated by hatching.
  • the operation in each period will be described.
  • the initialization period is divided into the following nine modes I to IX according to changes in the initialization pulse voltage.
  • the first separation switch element QS1, the second separation switch element QS2, and the low side maintenance switch element Q8Y are turned off while the high side scanning switch element Q1Y is maintained in the ON state.
  • Side ramp waveform generator QR1 turns on.
  • the remaining switch elements are kept off.
  • the potential of the scan electrode Y rises from the potential VI toward the upper limit Vr of the initialization pulse voltage at a constant speed.
  • the drain potential of the first isolation switch element QS1 also rises via the body diode of the second isolation switch element QS2. Therefore, in the mode V of FIG. 8, the second separation switch element QS2 is in the off state, but may be turned on.
  • the applied voltage force initialization pulse voltage rises relatively slowly toward the upper limit Vr of the applied voltage force initialization pulse voltage uniformly for all the discharge cells of the PDP 20.
  • uniform wall charges are accumulated in all discharge cells of the PDP20.
  • the rate of increase of the applied voltage is small, so that the light emission of the discharge cell can be suppressed to a weak level.
  • the mode VI when the potential of the scan electrode Y reaches the voltage Vr in the mode V, the mode VI is switched to.
  • the mode VI is switched to the mode VI before the potential of the scan electrode Y reaches the voltage Vr. This switching timing will be described later.
  • the high-side scan switch element Q1Y and the high-side ramp wave The high-side sustain switch element Q7Y is turned on while the shape generator QR1 is maintained in the on state and the second separation switch element QS2 is maintained in the off state. The remaining switch elements are kept off. Subsequent to mode V, the potential of the scan electrode Y rises at a constant speed to a potential higher by the upper limit Vr of the initialization pulse voltage from the ground potential (0).
  • the non-side maintaining switch element Q7Y needs to be turned on before the drain potential of the first isolation switch element QS1 becomes V2. Therefore, the high-side switch element Q7Y is turned on when the drain potential of the first isolation switch element QS1 is a predetermined potential lower than the voltage V2 of the second constant voltage source. This also switches the mode V force to mode VI.
  • sustain voltage Vs raises the source potential of first isolation switch element QS1 via high-side sustain switch element Q7Y.
  • the drain potential of the first isolation switch element QS1 becomes the sustain voltage Vs.
  • the drain potential of the first isolation switch element QS1 rises via the parasitic capacitance of the first isolation switch element QS1. In either case, the drain potential of the first isolation switch element QS1 rises.
  • the source potential of the first isolation switch element QS1 is turned on by turning on the first sustain switch element Q7Y before the potential of the drain of the first isolation switch element QS1 becomes the voltage V2. Since the voltage between the drain and source of the first isolation switch element QS1 can be suppressed, the voltage between the drain source and the absolute maximum rating of the first isolation switch element QS1 can be reduced. At this time, if the second separation switch element QS2 is turned on, the voltage due to the voltage Vs may be superimposed on the applied voltage of the rising scan electrode Y via the second separation switch element QS2. This hinders the formation of a smooth ramp waveform. Therefore, in the present embodiment, the second separation switch element QS2 is turned off before turning on the high-side sustain switch element Q7Y.
  • the drain potential of the second isolation switch element QS2 immediately before the high-side sustain switch element Q7Y is turned on and the drain potential of the second isolation switch element QS2 immediately after the high-side sustain switch element Q7Y is turned on The difference from the potential is referred to as “second voltage fluctuation ⁇ UJ.
  • the second separation switch element QS2 is turned off, so that the second voltage fluctuation ⁇ does not appear on the scan electrode Y as it is, and is largely suppressed.
  • the second voltage fluctuation ⁇ ⁇ is capacitively divided by the parasitic capacitance C2 and the panel capacitance Cp of the second separation switch element QS2.
  • the voltage variation of C2 / (C2 + Cp) X ⁇ occurs at the scan electrode Y according to the ratio of the parasitic capacitance C2 of the second isolation switch element QS2 and the panel capacitance Cp.
  • the voltage fluctuation generated at the scan electrode ⁇ ⁇ ⁇ is quite small, the light emission of the discharge cell can be suppressed to a weak level.
  • the parasitic capacitance C2 of the second isolation switch element QS2 it is possible to further suppress voltage fluctuations that occur at the scan electrode.
  • the voltage rises relatively slowly to the upper limit Vr of the applied voltage force initialization pulse voltage uniformly for all the discharge cells of the PDP 20.
  • uniform wall charges are accumulated in all the discharge cells of the PDP20.
  • the rate of increase of the applied voltage is small, so that the light emission of the discharge cell can be suppressed to a weak level.
  • the high-side ramp waveform generator QR1 is turned off while the high-side scan switch element Q1Y and the high-side sustain switch element Q7Y are maintained in the on state, and the first separation switch element QS1 and the second The isolation switch element QS2 is turned on. The remaining switch elements are kept off. As a result, the potential of the scan electrode Y drops to (Vs + Vl).
  • each switch element of the scan electrode unit 11 in the address period and the discharge sustain period is the same as that described in the first embodiment.
  • the driving method described in this embodiment can be applied to the circuit configurations of FIGS. 4 to 7B in addition to the circuit configuration of FIG. [0173] 3.4 Summary
  • the present embodiment it is possible to reduce the drain-source voltage of the absolute maximum rating of the first isolation switch element QS1.
  • the first isolation switch element can be reduced in withstand voltage, the switch element has a low resistance. Therefore, the number of first isolation switch elements connected in parallel can be reduced, and the circuit scale can be reduced. Can be reduced. Also, as the number of first separation switch elements decreases, the mounting area force S decreases, so that the wiring impedance due to the board can be reduced.
  • Ringing which is a high-frequency component generated when a voltage is applied to the DP, can be reduced, and the operating margin of the PDP is expanded. Furthermore, since the conduction loss due to the separation switch element during the discharge sustain period is greatly reduced, the power consumption can be reduced.
  • the first isolation switch element Q S1 can be further reduced in breakdown voltage in the configuration of the first embodiment.
  • FIG. 12 shows a detailed configuration of the scan electrode driving unit according to the fourth embodiment of the present invention.
  • the scan electrode drive unit 11 according to the present embodiment is different from that of the first embodiment shown in FIG. 2 in the configuration of the initialization pulse generator 2Y. More specifically, the initialization pulse generator 2Y is provided with a protection circuit 50 that limits the drain-source voltage of the first isolation switch element QS1 in parallel with the first isolation switch element QS1. Is different.
  • the protection circuit 50 limits the drain-source voltage of the first isolation switch element QS1 within a certain range by increasing the source potential of the first isolation switch element QS1. Other configurations are the same as those of the first embodiment.
  • specific configuration examples 50a to 50d of the protection circuit 50 will be described.
  • Fig. 13 (a) shows an example of the configuration of the protection circuit.
  • the protection circuit 50a includes a protection switch element Sl, a first limiting resistor Rl, a gate Zener diode ZD2, a first detection resistor R2, and a second detection resistor R3.
  • the collector is connected to one end of the first limiting resistor R1, the base is connected to the anode of the gate Zener diode ZD2, and the emitter is the first isolation switch element QS1. Connect with the source.
  • the other end of the first limiting resistor R1 is connected to the drain of the first isolation switch element QS1.
  • the first detection resistor R2 and the second detection resistor R3 are connected in series, and the connection point is connected to the force sword of the gate Zener diode ZD2, and the first detection resistor R2 is connected to the first isolation switch element QS1.
  • the second detection resistor R3 is connected to the source of the first isolation switch element QS1.
  • the protection circuit 50a operates when the first isolation switch element QS1 is off. As the drain-source voltage of the first isolation switch element QS1 rises, the voltage across the second detection resistor R3 rises. When the voltage between the drain and source of the first isolation switch element QS1 reaches the predetermined voltage Vc, the voltage across the second detection resistor R3 is also a voltage value (the first detection resistor R2 and the second detection resistor R3 The value determined by the ratio of the resistance values). At this time, the zener voltage of the gate zener diode ZD2 and the base-emitter voltage of the protective switch element S1 become equal, and the protective switch element S1 starts to operate.
  • the protective switch element S1 controls the drain-source voltage of the first isolation switch element QS1 to be constant.
  • the protection circuit 50a continues to operate, so the source potential of the first separation switch element QS1 also continues to rise.
  • the source potential of the high-side ramp waveform generator QR1 rises for a while, the source potential of the first separation switch element QS1 reaches the sustain voltage Vs.
  • no side maintenance When the body diode of the switch element Q7Y is turned on, the source potential of the first isolation switch element QS1 is clamped to the sustain voltage Vs.
  • the protective switch element S1 operates to pass a current in order to control the constant voltage, but the operation is limited by the first limiting resistor R1 and cannot be controlled to a constant voltage.
  • the drain-source voltage of the first isolation switch element QS1 increases, but the drain-source voltage of the first isolation switch element QS1 increases.
  • the maximum applied voltage is up to (V2-Vs), and the drain-source voltage of the first isolation switch element QS1 is greatly reduced.
  • the high-side sustain switch element Q7Y is turned on while the body diode of the high-side sustain switch element Q7Y is in the conductive state, the source potential of the first isolation switch element QS1 does not vary, so the potential difference ⁇ varies with the potential of the scan electrode Y. Does not occur.
  • the source potential of the negative ramp waveform generator QR1 increases, the source potential of the first isolation switch element QS1 also increases, and the drain potential of the first isolation switch element QS1 increases.
  • the source potential of the first isolation switch element QS1 becomes the sustain voltage Vs, so the drain of the absolute maximum rating of the first isolation switch element QS1 'The source-to-source voltage is reduced. Can be made.
  • the high-side sustain switch element Q7Y is turned on after the source potential of the first separation switch element QS1 becomes the sustain voltage Vs, the voltage fluctuation ⁇ does not occur in the potential of the scan electrode Y.
  • Fig. 13 (b) shows another configuration of the protection circuit 50b.
  • the protection circuit 50b shown in FIG. 13 (b) includes a protective Zener diode ZD3 and a second limiting resistor.
  • the anode of the protective Zener diode is connected to one end of the second limiting resistor R4, the cathode of the protective Zener diode ZD3 is connected to the drain of the first isolation switch element QS1, and the other of the second limiting resistor R4 The end is connected to the source of the first isolation switch element QS1.
  • the protection circuit 50b operates when the first separation switch element QS1 is off.
  • the protective Zener diode ZD3 starts operating. .
  • This protective Zener diode ZD3 The isolation switch element QSl drain is controlled so that the source-to-source voltage is constant.
  • the voltage value Vz controlled at a constant voltage may be set to a value equal to or lower than the drain-source voltage of the absolute maximum rating of the first separation switch element QS1.
  • the protection circuit starts operating. Furthermore, as the source potential of the high-side ramp waveform generator QR1 rises, the protection circuit 50b continues to operate, so the source potential of the first separation switch element QS1 also continues to rise.
  • the drain to source voltage of the first isolation switch element QS1 increases, but the drain of the first isolation switch element QS1 to source voltage
  • the maximum applied voltage is up to (V2-Vs), and the drain-source voltage of the first isolation switch element QS1 is greatly reduced.
  • the high-side sustain switch element Q7Y is turned on while the body diode of the high-side sustain switch element Q7Y is in a conductive state, the source potential of the first separation switch element does not vary, so the potential difference ⁇ varies with the potential of the scan electrode Y. Does not occur.
  • the source potential of the negative ramp waveform generator QR1 increases, the source potential of the first isolation switch element QS1 also increases, and the drain potential of the first isolation switch element QS1 increases.
  • the source potential of the first isolation switch element QS1 is limited to the sustain voltage Vs by the protection circuit 50b, so the drain of the first isolation switch element QS1 'source The inter-voltage can reduce the drain-source voltage of its absolute maximum rating.
  • the source potential of the first isolation switch element QS1 is the sustain voltage V Since the high-side sustain switch element Q7Y is turned on after s, voltage fluctuation ⁇ V does not occur at the potential of the scan electrode Y.
  • Figure 13 (c) shows another configuration of the protection circuit.
  • the protection circuit 50c shown in FIG. 13 (c) includes a fourth limiting resistor R4.
  • One end of the third limiting resistor R5 is connected to the drain of the first isolation switch element Q S1 and the other end is connected to the source of the first isolation switch element QS1.
  • the protection circuit 50c operates when the first separation switch element QS1 is OFF.
  • High-side ramp waveform generator When the source potential of QR1 rises and the drain-source voltage of the first isolation switch element QS1 rises, the first isolation switch is connected via the third limiting resistor R5. A current flows toward the source of the element QS1, and the source potential of the first isolation switch element QS1 rises.
  • the source potential of the high side ramp waveform generator QR1 further increases, the source potential of the first isolation switch element QS1 reaches the sustain voltage Vs. Then, when the body diode of the high-side sustain switch element Q7Y becomes conductive, the source potential of the first isolation switch element QS1 is clamped to the sustain voltage Vs.
  • the drain of the first isolation switch element QS1 'the source-to-source voltage increases, but the drain of the first isolation switch element QS1' source
  • the maximum applied voltage is between (V2 and Vs), and the drain-source voltage of the first isolation switch element QS1 is greatly reduced.
  • the no-side sustain switch element Q7Y is turned on while the body diode of the no-side sustain switch element Q7Y is in the conductive state, the source potential of the first separation switch element does not change, so the potential difference ⁇ No fluctuations occur.
  • the source potential of the negative ramp waveform generator QR1 increases, the source potential of the first isolation switch element QS1 also increases, and the drain potential of the first isolation switch element QS1 increases.
  • the source potential of the first isolation switch element QS1 is limited to the sustain voltage Vs by the protection circuit 50c, so the drain of the first isolation switch element QS1 'source The voltage between can reduce the drain-source voltage of its absolute maximum rating. Since the high-side sustain switch element Q7Y is turned on after the source potential of the first separation switch element QS1 becomes the sustain voltage Vs, the scan electrode Y Voltage fluctuation ⁇ V does not occur in the potential.
  • Figure 13 (d) shows another configuration of the protection circuit.
  • the protection circuit 50d shown in Fig. 13 (d) includes a protection capacitor C2.
  • One end of the protective capacitor C2 is connected to the drain of the first isolation switch element QS1, and the other end is connected to the source of the first isolation switch element QS1.
  • the protection circuit 50d operates when the first separation switch element QS1 is OFF.
  • the source potential of QR1 rises, the source according to the capacitance division between the capacitance of the protective capacitor C2 and the parasitic capacitance that exists between the source of the first isolation switch element QS1 and ground The potential increases.
  • the source potential of the high-side ramp waveform generator QR1 further rises, the source potential of the first isolation switch element QS1 reaches the sustain voltage Vs. Then, the body diode of the high-side sustain switch element Q7Y becomes conductive, so that the source potential of the first isolation switch element QS1 is clamped at the sustain voltage Vs.
  • the drain-source voltage of the first isolation switch element QS1 increases, but the drain of the first isolation switch element Q S1 'source
  • the maximum applied voltage is between (V2 and Vs), and the drain-source voltage of the first isolation switch element QS1 is greatly reduced.
  • the source potential of the first separation switch element does not vary, so the potential difference ⁇ varies with the potential of the scan electrode Y. Does not occur.
  • the source potential of the non-side ramp waveform generator QR1 increases, the source potential of the first isolation switch element QS1 also increases, and the drain potential of the first isolation switch element QS1 increases.
  • the source potential of the first isolation switch element QS1 is limited to the sustain voltage Vs by the protection circuit 50d, so that the drain of the absolute maximum rating of the first isolation switch element QS1 'Can reduce the source-to-source voltage.
  • the high-side sustain switch element Q7Y is turned on after the source potential of the first separation switch element QS1 becomes the sustain voltage Vs, the voltage fluctuation ⁇ does not occur in the potential of the scan electrode Y.
  • FIG. 14 shows the initialization period, address period and discharge sustain period in this embodiment.
  • FIG. 6 is a diagram showing a voltage waveform applied to the scan electrode Y of the PDP 20 and an on period of each switch element included in the scan electrode driving unit 11 in each.
  • the ON period of each switch element is indicated by hatching.
  • the operation in each period will be described.
  • the initialization period is divided into the following nine modes ⁇ to ⁇ depending on the change of the initialization pulse voltage.
  • the first separation switch element QS1 and the low-side maintenance switch element Q8Y are turned off while the high-side scan switch element Q1Y and the second separation switch element QS2 are maintained in the on state.
  • Side ramp waveform generator QR1 turns on. The remaining switch elements are kept off. As a result, the potential of the scan electrode Y rises toward the potential Vr at a constant speed. At this time, the drain potential of the first isolation switch element QS1 also rises via the second isolation switch element QS2.
  • the source potential of the first isolation switch element QS1 rises, and when the source potential of the first isolation switch element QS1 reaches the sustain voltage Vs, the no-side sustain switch element
  • the source potential S of the first isolation switch element QS1 is clamped by the body diode of Q7Y.
  • the source potential of the first isolation switch element QS1 is maintained before reaching the upper limit Vr of the initialization pulse voltage (that is, before the drain potential of the first isolation switch element QS1 reaches the potential V2). Reach voltage VS. For this reason, the drain-source voltage of the first isolation switch element QS1 can reduce the drain-source voltage of its absolute maximum rating.
  • the applied voltage force initialization pulse voltage rises relatively slowly toward the upper limit Vr of the applied voltage force initialization pulse voltage uniformly for all the discharge cells of the PDP 20.
  • uniform wall charges are accumulated in all discharge cells of the PDP20.
  • the rate of increase of the applied voltage is small, so that the light emission of the discharge cell can be suppressed to a weak level.
  • the ON / OFF switch Q7Y is turned on during mode V. If the second separation switch element QS2 is turned off before the high side sustain switch element Q7Y is turned on as in the third embodiment, the voltage fluctuation ⁇ ⁇ is suppressed.
  • the high / side sustain switch element Q7Y is turned on while the high side scan switch element Q1Y, the second separation switch element QS2 and the high side ramp waveform generator QR1 are maintained in the on state.
  • the remaining switch elements are kept off.
  • the potential of the scanning electrode Y is maintained at a potential higher than the ground potential (0) by the upper limit Vr of the initialization pulse voltage.
  • the source potential of the first separation switch element QS 1 is already clamped to the sustain voltage Vs by the action of the protection circuit 50! /.
  • the voltage rises relatively slowly to the upper limit Vr of the applied voltage force initialization pulse voltage uniformly for all the discharge cells of the PDP 20.
  • uniform wall charges are accumulated in all the discharge cells of the PDP20.
  • the rate of increase of the applied voltage is small, so that the light emission of the discharge cell can be suppressed to a weak level.
  • each switch element of the scan electrode unit 11 in the address period and the discharge sustain period is the same as that described in the first embodiment.
  • the drain of the absolute maximum rating of the first separation switch element QS1 is prevented while preventing the occurrence of voltage fluctuation on the applied voltage of the scan electrode Y in the mode V of the initialization period. 'Reduce the source-to-source voltage.
  • the absolute maximum rated drain of the first isolation switch element 'Reduced source voltage reduces the resistance of the switch element, so the number of first isolation switch elements connected in parallel can be reduced and the circuit scale can be reduced. it can.
  • the mounting area is reduced as the number of first separation switch elements is reduced, so that the wiring impedance due to the substrate can be reduced, and ringing, which is a high-frequency component generated when a voltage is applied to the PDP, can be reduced.
  • the operating margin is expanded. Furthermore, since the conduction loss due to the separation switch element during the discharge sustain period is greatly reduced, the power consumption can be reduced.
  • the first isolation switch element Q S1 can be further reduced in breakdown voltage in the configuration of the first embodiment.
  • the scan electrode driving unit 11 according to the present embodiment has the same circuit configuration as that of the first embodiment shown in FIG. 2, but the driving method is different.
  • the driving method of the present embodiment makes it possible to reduce the drain-source voltage of the absolute maximum rating of the first separation switch element QS1.
  • FIG. 15 shows the voltage waveform applied to the scan electrode Y of the PDP 20 and the ON period of each switch element included in the scan electrode drive unit 11 in each of the initialization period, address period, and discharge sustain period in this embodiment.
  • FIG. 15 the ON period of each switch element is indicated by hatching. Hereinafter, the operation in each period will be described.
  • the initialization period is divided into the following nine modes I to IX according to changes in the initialization pulse voltage.
  • the high-side scan switch element Q1Y, the first separation switch element QS1 and the second separation switch element QS2 are maintained in the on state, and the low-side sustain switch element Q8Y is turned off.
  • the side ramp waveform generator QR1 is turned on.
  • the first separation switch element QS1 is turned on until the voltage applied to the scan electrode is rising, and turned off at a predetermined timing.
  • the remaining switch elements are kept off.
  • the potential of the scan electrode Y rises at a constant speed from the potential VI toward the upper limit Vr of the initialization pulse voltage.
  • the predetermined timing for turning off the first separation switch element QS1 means that the source potential of the first separation switch element QS1 reaches the potential Vs (that is, the voltage applied to the scan electrode). Is (Vs + Vl)).
  • the first separation switch element QS1 is turned on and off at an appropriate timing.
  • the rise of the drain-source voltage of the first isolation switch element QS1 is suppressed, and the breakdown voltage of the first isolation switch element QS1 is reduced.
  • the applied voltage force initialization pulse voltage rises relatively slowly toward the upper limit Vr of the applied voltage force initialization pulse voltage uniformly for all the discharge cells of the PDP 20.
  • uniform wall charges are accumulated in all discharge cells of the PDP20.
  • the rate of increase of the applied voltage is small, so that the light emission of the discharge cell can be suppressed to a weak level.
  • the high / side sustain switch element Q7Y is turned on while the high side scan switch element Q1Y, the second separation switch element QS2 and the high side ramp waveform generator QR1 are maintained in the on state.
  • the remaining switch elements are kept off.
  • the scanning electrode Y is maintained at a potential higher by the upper limit Vr of the initialization pulse voltage, in addition to the ground potential ( ⁇ 0).
  • the source potential of the first separation switch element QS1 is clamped at the sustain voltage Vs.
  • the non-side sustaining switch element Q7Y is turned on while the body diode of the high-side sustaining switch element Q7Y is in the conductive state, the source potential of the first separation switch element does not fluctuate. There will be no fluctuations.
  • the voltage rises relatively slowly to the upper limit Vr of the applied voltage force initialization pulse voltage uniformly for all the discharge cells of the PDP 20.
  • uniform wall charges are accumulated in all the discharge cells of the PDP20.
  • the rate of increase of the applied voltage is small, so that the light emission of the discharge cell can be suppressed to a weak level.
  • each switch element of the scan electrode unit 11 in the address period and the discharge sustain period is the same as that described in the first embodiment.
  • the driving method described in this embodiment can be applied to the circuit configurations of FIGS. 4 to 7B in addition to the circuit configuration of FIG.
  • the drain-source voltage of the absolute maximum rating of the first isolation switch element QS1 can be reduced.
  • the resistance of the switch element becomes low, so the number of first isolation switch elements connected in parallel can be reduced and the circuit scale can be reduced.
  • the mounting area is reduced, so that the wiring impedance due to the substrate can be reduced, and ringing, which is a high-frequency component generated when a voltage is applied to the PDP, can be reduced.
  • the operating margin increases. Furthermore, since the conduction loss due to the separation switch element during the discharge sustain period is greatly reduced, the power consumption can be reduced.
  • FIG. 3 shows another configuration of the scan electrode driving unit.
  • Fig. 16 shows the configuration of the scan electrode driver of this embodiment.
  • the scan electrode drive unit 11 of the present embodiment is different from that of the first embodiment shown in FIG. 2 in that the second high side ramp waveform generation unit QR4 is provided.
  • the detailed configuration of the second high-side lamp waveform generator QR4 is the same as that of the node-side ramp waveform generator QR3 shown in FIG. 9A or 9B in the second embodiment.
  • the drain of the high-side NMOS included inside is connected to the positive electrode of the second constant voltage source V2, and its source is connected to the negative electrode of the first constant voltage source VI. .
  • the discharge sustain period is maintained while the potential of the scan electrode Y is at the sustain voltage Vs. Was completed and transitioned to initialization mode I (see, for example, Figure 3A).
  • the sustain electrode X is at the ground potential and the scan electrode Y is at the ground potential, the discharge sustain period ends, and the mode transitions to the initialization period mode I. (See Figure 17).
  • the potential of the scan electrode Y is suddenly raised to a voltage lower than the sustain voltage Vs, and then the voltage of the scan electrode Y is gradually increased to a voltage higher than the sustain voltage Vs. Launch.
  • the discharge of the discharge cell having wall charges is applied with the sustain voltage Vs, and thus a strong discharge has occurred.
  • the potential of the scan electrode Y exceeds the discharge start voltage (a voltage slightly lower than the sustain voltage Vs)
  • the rate of increase of the potential is small. In this case, the light emission of the discharge cell is suppressed to be weak.
  • FIG. 17 is a diagram showing a voltage waveform applied to the scan electrode Y of the PDP 20 and an on period of each switch element included in the scan electrode driving unit 11 in each of the initialization period, the address period, and the discharge sustain period in the present embodiment. It is. In FIG. 17, the ON period of each switch element is indicated by hatching. Only the operation in modes I and II during the initialization period will be described below.
  • low-side scan switch element Q2Y, second separation switch element QS2, and second high-side ramp waveform generator QR4 are maintained in the on state. The remaining switch elements are kept off.
  • the second non-side ramp waveform generator QR4 is turned on, the potential of the scan electrode Y rises sharply from the ground potential by the Zener voltage (Vm) due to the action of the ramp waveform diode, and then the voltage becomes constant. Starts climbing at a speed of.
  • low-side scan switch element Q2Y is maintained in the ON state.
  • the second separation switch element QS2 and the second no-side ramp waveform generator QR4 are turned off, and the low-side ramp waveform generator QR2 and the first separation switch element QS1 are turned on.
  • the remaining switch elements are kept off.
  • the potential of the scan electrode can be set to an arbitrary voltage lower than V2 by adjusting the ON period of the second high-side ramp waveform generator QR4.
  • the number of parts can be reduced by sharing the constant voltage source for mode V in the initialization period and the constant voltage source for mode I in the initialization period. After that, the potential of the scan electrode Y starts to decrease toward -V3 at a constant speed by the low side ramp waveform generator QR2.
  • the ramp-up waveform has started the ground potential force (see, for example, JP-A-2005-250505).
  • the start voltage of the rising ramp waveform in the initialization period (mode I) is raised by the ground potential force to a predetermined potential, and the potential of the scan electrode Y is set to a value greater than the ground potential. .
  • the time required to subsequently increase the ramp waveform to the desired voltage can be shortened compared to the conventional method, and the initialization period can be shortened.
  • the start voltage of the up-ramp waveform in the initialization period (mode I) is set so that the potential of the scan electrode Y is larger than the ground potential and smaller than the discharge start voltage. Therefore, when a voltage exceeding the discharge start voltage is applied to the scan electrode Y, it is a period during which the voltage gradually rises to the scan electrode Y (up-ramp waveform period), and therefore weak light emission occurs. In this way, strong light emission is suppressed by making the potential of the scan electrode Y at the start of the initialization period smaller than the discharge start voltage.
  • the discharge start voltage in mode I during the initialization period is smaller than the sustain voltage Vs. It becomes.
  • the discharge start voltage also includes the influence of variations in the discharge start voltage within the surface of the panel, changes over time, and a decrease in the discharge start voltage due to the discharge cells between adjacent discharge cells that were discharged during the discharge sustain period. Consider the lowest discharge start voltage.
  • the transition is made to the initialization period mode III.
  • the transition may be made to the address period immediately after the initialization period mode II.
  • the initialization period modes ⁇ to ⁇ may be executed only once per TV field, and for each subfield, transition to the address period may occur after the initialization period modes ⁇ to ⁇ are executed. This can greatly reduce the initialization time. Further, even if V is V in the initialization period modes ⁇ to ⁇ , weak light emission is generated. Therefore, since such weak light emission is suppressed by such a method, luminance during black display is suppressed. The That is, the contrast can be improved.
  • the driving method of the present embodiment can be applied to the configuration shown in the second embodiment. Furthermore, when the slopes of the ramp waveforms in the high-side ramp waveform generator QR3 used in the second embodiment and the high-side ramp waveform generator QR4 used in the present embodiment are the same, they may be shared.
  • the driving method of the present embodiment can also be applied to the circuit configurations shown in Figs. Needless to say, the driving method of this embodiment can also be applied to the driving methods and driving circuits of Embodiments 3 to 5.
  • the start voltage of the rising ramp waveform in the initialization period (mode I) is also raised by the predetermined potential as the ground potential.
  • the time required to subsequently increase the ramp waveform to the desired voltage can be shortened, and the initialization period can be shortened.
  • the start voltage of the up-ramp waveform in the initialization period (mode I) is set so that the potential of the scan electrode is larger than the ground potential and smaller than the discharge start voltage. Thereby, the light emission in the initialization period can be weakened. In this way, it is possible to reduce both the time for the initialization period and the suppression of light emission in mode I, improve the contrast in image display, and increase the gradation.
  • the present invention is useful for a plasma display driving apparatus that requires good contrast, various gradation displays, low power consumption, and the like.

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Abstract

La présente invention concerne un dispositif d'excitation de PDP et un procédé permettant de réaliser un contraste et une gradation favorables sans inviter la prolongation de la période d'initialisation. La tension de démarrage d'une forme d'onde croissant monolithiquement (mode V) appliquée pendant la période d'initialisation pendant laquelle la charge de paroi de chaque cellule de décharge est initialisée est supérieure à une première tension (V1) qui est la différence entre les valeurs maximale et minimale de la tension appliquée à l'électrode de balayage pendant une période d'adressage pendant laquelle une cellule de décharge dans laquelle la décharge doit être provoquée est sélectionnée et inférieure à la tension de démarrage de décharge.
PCT/JP2007/051368 2006-02-03 2007-01-29 Procédé d'excitation d'affichage plasma, circuit de sortie, et affichage plasma WO2007088804A1 (fr)

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JP2013098987A (ja) * 2011-11-01 2013-05-20 Neo Energy Co Ltd スイッチングシステムおよびスイッチングシステムの制御方法

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