WO2007058231A1 - Semiconductor thin film, method for producing same, thin film transistor and active-matrix-driven display panel - Google Patents

Semiconductor thin film, method for producing same, thin film transistor and active-matrix-driven display panel Download PDF

Info

Publication number
WO2007058231A1
WO2007058231A1 PCT/JP2006/322808 JP2006322808W WO2007058231A1 WO 2007058231 A1 WO2007058231 A1 WO 2007058231A1 JP 2006322808 W JP2006322808 W JP 2006322808W WO 2007058231 A1 WO2007058231 A1 WO 2007058231A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
semiconductor thin
indium
film
amorphous
Prior art date
Application number
PCT/JP2006/322808
Other languages
French (fr)
Japanese (ja)
Inventor
Koki Yano
Kazuyoshi Inoue
Nobuo Tanaka
Original Assignee
Idemitsu Kosan Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Idemitsu Kosan Co., Ltd. filed Critical Idemitsu Kosan Co., Ltd.
Priority to US12/094,228 priority Critical patent/US7998372B2/en
Priority to CN2006800429985A priority patent/CN101309863B/en
Priority to KR1020087011741A priority patent/KR101291977B1/en
Publication of WO2007058231A1 publication Critical patent/WO2007058231A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01G—COMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
    • C01G15/00—Compounds of gallium, indium or thallium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01P—INDEXING SCHEME RELATING TO STRUCTURAL AND PHYSICAL ASPECTS OF SOLID INORGANIC COMPOUNDS
    • C01P2006/00—Physical properties of inorganic compounds
    • C01P2006/40—Electric properties
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133305—Flexible substrates, e.g. plastics, organic film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present invention relates to a semiconductor thin film having an amorphous film strength containing zinc oxide and indium oxide, a manufacturing method thereof, a thin film transistor using such a semiconductor thin film, and an active to which such a thin film transistor is applied.
  • the present invention relates to a matrix drive display panel.
  • Field effect transistors are widely used as unit electronic elements, high-frequency signal amplifier elements, liquid crystal driving elements, etc. in semiconductor memory integrated circuits, and are currently the most widely used electronic devices. is there.
  • silicon semiconductor compounds are the most widely used as the material.
  • silicon single crystals are used for high-frequency amplifier elements and integrated circuit elements that require high-speed operation, and are used for liquid crystal drive elements.
  • Amorphous silicon is used because of the demand for large area.
  • a crystalline silicon-based thin film requires a high temperature of, for example, 800 ° C. or higher when crystallization is performed, and is difficult to construct on a glass substrate or an organic substrate. For this reason, there is a problem that it can be formed only on an expensive substrate having high heat resistance such as a silicon wafer or quartz, and a lot of energy and the number of processes are required for production.
  • an amorphous silicon semiconductor (amorphous silicon) that can be formed at a relatively low temperature has a lower switching speed than a crystalline one, so when used as a switching element for driving a display device, It may not be possible to follow the display of high-speed movies. Furthermore, when the semiconductor active layer is irradiated with visible light, the semiconductor device exhibits electrical conductivity, and there is a problem that the characteristics as a switching element deteriorate, such as the possibility of malfunction due to leakage current. Therefore, a method of providing a light shielding layer that blocks visible light is known. For example, a metal thin film is used as the light shielding layer.
  • the transmittance of visible light is low, if the semiconductor layer protrudes from the electrode section, the transmittance of the display section may decrease, the illumination efficiency by the backlight may decrease, and the screen may become dark. It contributed to a small cost increase.
  • a conventional thin film transistor has a gate electrode, a gate insulating layer, a semiconductor layer such as hydrogenated amorphous silicon (a-Si: H), a source and a drain electrode stacked on a substrate such as glass.
  • a-Si: H hydrogenated amorphous silicon
  • Inverted staggered structures are used in the field of large area devices, including image sensors, and are used as driving elements for flat panel displays such as active matrix liquid crystal displays. In these applications, even those using conventional amorphous silicon have been required to operate faster with higher functionality.
  • a transparent semiconductor thin film made of a metal oxide such as zinc oxide, in particular, an oxide is superior in stability to a silicon-based semiconductor thin film (amorphous silicon).
  • a transparent semiconductor thin film made of zinc crystals has attracted attention.
  • Patent Document 1 and Patent Document 2 describe a method for forming a thin film transistor by crystallizing zinc oxide at a high temperature.
  • Patent Document 1 Japanese Patent Laid-Open No. 2003-86808
  • Patent Document 2 JP-A-2004-273614 Disclosure of the invention
  • the semiconductor thin film using zinc oxide has a problem that the hole mobility is lowered unless precise crystallization control is performed, so that the field effect mobility is lowered and the switching speed is lowered. was there.
  • the present invention has been made in view of the above circumstances, and is a semiconductor thin film that can be produced at a relatively low temperature and can be formed on a flexible resin substrate, and is stable to visible light.
  • the device characteristics such as transistor characteristics are high.
  • a semiconductor thin film that does not decrease the luminance of the display panel even if it overlaps with the pixel portion, and such a thin film.
  • the semiconductor thin film manufacturing method, and the field effect mobility and on-off ratio using such a semiconductor thin film are high, and the influence of irradiation light such as the generation of leakage current is reduced to improve the device characteristics. It is an object of the present invention to provide a thin film transistor and an active matrix drive display panel to which such a thin film transistor is applied.
  • a semiconductor thin film according to the present invention that solves the above problems is a semiconductor thin film made of an amorphous film containing zinc oxide and indium oxide, and has a carrier density of 10 + 17 cm- 3 or less and a hole.
  • the mobility is 2 cm 2 ZV 'sec or more and the energy band gap is 2.4 eV or more.
  • the semiconductor thin film according to the present invention makes it easy to produce a semiconductor thin film over a wide temperature range, and easily develops uniform physical properties over a large area. It is suitable for such applications.
  • the leakage current is generated, it has become a no Marion, If the on-off ratio is too small, good transistor performance may not be achieved. If the hole mobility is less than 2 cm 2 ZVs, the field-effect mobility of thin film transistor 1 will be small, and when used as a switching element to drive a display element, the switching speed is low, similar to amorphous silicon. May not be able to follow the display of moving images.
  • the energy band gap is less than 2.4 eV, when visible light is irradiated, electrons in the valence band are excited and become conductive, which may cause leakage current.
  • the semiconductor thin film according to the present invention enables the formation of a uniform amorphous film over a large area and avoids non-uniform film quality in order to form a non-uniform film.
  • the semiconductor thin film according to the present invention preferably has a transmittance of 75% or more at a wavelength of 550 nm, so that even when the semiconductor thin film protrudes from the pixel electrode portion. It is possible to effectively avoid problems such as a decrease in transmittance and brightness, or a change in color tone.
  • the semiconductor thin film according to the present invention is preferably a non-degenerate semiconductor thin film having a work function of 3.5 to 6.5 eV.
  • a degenerate semiconductor may not be able to stably control the carrier concentration at a low concentration, but by making the semiconductor thin film according to the present invention a non-degenerate semiconductor thin film, it is possible to effectively avoid such problems. it can.
  • the non-degenerate semiconductor thin film refers to a semiconductor thin film in which the carrier concentration varies depending on the temperature, and the temperature dependence of the carrier concentration can be obtained from hole measurement.
  • nanocrystals are dispersed in an amorphous film.
  • the hole mobility is improved.
  • the semiconductor thin film according to the present invention is an oxide oxide as long as the effects of the present invention are not impaired.
  • the atomic ratio of the third metal element [M] to indium [In] [M / (M + In)] is preferably 0 to 0.5.
  • the atomic ratio [MZ (M + In)] of the third metal element [M] to indium [In] is preferably 0 to 0.3. It is more preferable that
  • the semiconductor thin film according to the present invention has a maximum RDF value between the atomic distances of 0.3 to 0.36 nm in the radial distribution function (RDF) obtained by X-ray scattering measurement.
  • This ratio (A / B) that satisfies the relationship of A / B> 0.8, where B is the maximum value of RDF between atomic distances of 0.36 and 0.42 nm, is Indium Oxygen Indium bond form Strength It is estimated that it represents the ratio of the ridge sharing and apex sharing, or the maintenance ratio of short-range order.
  • this ratio is less than 0.8, the hole mobility and field effect mobility may be reduced.
  • the method for producing a semiconductor thin film according to the present invention provides a zinc oxide under the condition that the partial pressure of water HO in the atmospheric gas is 10 _3 Pa or less in producing the semiconductor thin film as described above.
  • the method for producing a semiconductor thin film according to the present invention preferably includes a step of oxidizing the amorphous film physically formed at a substrate temperature of 200 ° C or less, wherein the substrate temperature is preferably If the temperature is higher than 200 ° C, the carrier concentration may not decrease even after oxidation treatment, or deformation or dimensional change may occur if a resin substrate is used.
  • the semiconductor thin film formed in the above range it is preferable to subject the semiconductor thin film formed in the above range to heat treatment in the presence of oxygen or oxidation treatment such as ozone treatment in order to stabilize the carrier density.
  • the temperature of the film surface during the heat treatment is 100 to 270 ° C. higher than the substrate temperature during the film formation. If the temperature difference is less than 100 ° C, the heat treatment effect is not obtained. If the temperature difference is higher than 270 ° C, the substrate may be deformed, or the semiconductor thin film interface may be altered to deteriorate the semiconductor characteristics. In order to avoid such problems more effectively, it is more preferable that the temperature of the film surface during heat treatment is 130-240 ° C higher than the substrate temperature during film formation, which is 160-210 ° C higher. Is particularly preferred.
  • the thin film transistor according to the present invention can be configured to have the semiconductor thin film as described above, and the semiconductor thin film can be configured to be provided on a resin substrate.
  • the active matrix drive display panel according to the present invention may be configured to include the thin film transistor as described above.
  • a glass substrate or a resin substrate can be formed in a wide temperature range, is stable with respect to visible light, hardly causes a malfunction, and has a small leakage current.
  • a semiconductor thin film constituting an excellent field effect transistor can be provided. Further, since the semiconductor thin film of the present invention can be formed at a relatively low temperature, it can be formed on a resin substrate to provide a flexible thin film transistor or the like.
  • FIG. 1 is an explanatory diagram showing an outline of an embodiment of a thin film transistor according to the present invention.
  • FIG. 1 is an explanatory diagram showing an outline of an embodiment of a thin film transistor according to the present invention.
  • a thin film transistor 1 as a field effect transistor includes a drain electrode 10 and a source electrode 20 formed on a substrate 60 so as to be separated from each other, and at least each of the drain electrode 10 and the source electrode 20.
  • a transparent semiconductor thin film 40 is formed so as to be in contact with a part of the thin film transistor, and a gate insulating film 50 and a gate electrode 30 are formed on the transparent semiconductor thin film 40 in this order. Yes.
  • a glass substrate polyethylene terephthalate (1)
  • a resin substrate made of, for example, HPET) or polycarbonate (PC) can also be used.
  • each of the gate electrode 30, the source electrode 20, and the drain electrode 10 is not particularly limited. Any material that is generally used as long as the effect of the present embodiment is not lost can be arbitrarily selected. can do. For example, use transparent electrodes such as ITO, IZ ⁇ , ZnO, and Sn2, metal electrodes such as Al, Ag, Cr, Ni, Mo, Au, Ti, Ta, or metal electrodes of alloys containing these. Can do.
  • Each of the gate electrode 30, the source electrode 20, and the drain electrode 10 may have a multilayer structure in which two or more different conductive layers are stacked.
  • each of the electrodes 30, 20, and 10 The first conductive layers 31, 21 and 11 and the second conductive layers 32, 22, and 12 are included.
  • the material for forming the gate insulating film 50 is not particularly limited. Any one generally used can be selected as long as the effects of the invention of the present embodiment are not lost.
  • Oxides such as CaHfO can be used. Among these
  • Such a gate insulating film 50 may have a structure in which two or more different insulating films are stacked.
  • the gate insulating film 50 may be crystalline or amorphous.
  • the gate insulating film 50 is easily manufactured industrially, and is preferably amorphous.
  • the transparent semiconductor thin film 40 is made of an amorphous material containing zinc oxide and indium oxide, has a carrier density of 10 + 17 cm ⁇ 3 or less determined by hole measurement, and a hole mobility of 2 cm. 2 ZVS above, the energy band gap between the conduction band and the valence band 2. is formed so as to be on 4eV or more.
  • Such an amorphous film containing zinc oxide and indium oxide is manufactured in a wide temperature range, and it is easy to express uniform physical properties in a large area by using an amorphous film.
  • it can be suitably used for an active matrix drive display panel.
  • it can be confirmed that it is an amorphous film by a clear peak not appearing by X-ray diffraction.
  • the carrier density is 10 + 16 CM_ 3 or less and preferably 10 + 15 CM_ 3 than is preferred instrument to below the 10 + 14 c m_ 3 below Especially preferred to do.
  • the hole mobility is smaller than 2 cm 2 / Vs, the field effect mobility of the thin film transistor 1 is reduced, and when used as a switching element for driving a display element, the switching speed is similar to that for amorphous silicon. It may not be possible to follow the display of high-speed movies that are slow.
  • the hole mobility is preferably 5 cm 2 / Vs or more, more preferably 8 cm 2 / Vs or more, and even more preferably 1 lcm 2 / Vs or more. It is particularly preferably 14 cm 2 / Vs or more.
  • the transparent semiconductor thin film 40 the carrier density 10 + 17 cm- 3 or less, that the hole mobility be formed in more than 2 cm 2 / Vs, the field effect mobility, Onn- off ratio is also high
  • the energy band gap is less than 2.4 eV, when irradiated with visible light, electrons in the valence band are excited to show conductivity, and leakage current is likely to occur.
  • the energy band gap is preferably 2.6 eV or more, more preferably 2.8 eV or more, further preferably 3. Oev or more, and 3.2 eV or more. Particularly preferred.
  • the specific resistance of the transparent semiconductor thin film 40 is generally 10- 1 ⁇ 10 +8 Q cm and a force 10- 1 ⁇ 1 0 +8 ⁇ it is cm is preferred instrument 10 ° to 10 +6 Q cm is more preferred, and 10 + 1 to 10 + 4 ⁇ cm is even more preferred. 10 +2 to 10 +3 Q cm is particularly preferred.
  • high hole movement is achieved by adding indium oxide to the transparent semiconductor thin film 40.
  • the hole mobility is controlled by controlling the oxygen partial pressure in the atmospheric gas during film formation and the water H 0 or hydrogen H content in the atmospheric gas during film formation.
  • the carrier concentration is reduced and, as will be described later, by performing an oxidation treatment after film formation, the hole mobility is increased. It is also possible to control the carrier concentration without decreasing it.
  • the atomic ratio [Zn / (Zn + In)] of indium [In] and zinc [Zn] contained in the semiconductor thin film 50 can be set to 0 ⁇ 10 to 0 ⁇ 82. .
  • the atomic ratio [X / (X + In)] 3 ⁇ 40.5.51 to 0.80 is preferable, and more preferably ⁇ . 0.5 to 0.80, 0.6 to 0.75, especially preferred, 0
  • the transparent semiconductor thin film 40 preferably has a transmittance of 75% or more at a wavelength of 550 nm. If the transmittance at a wavelength of 550 nm is less than 75%, when the semiconductor thin film protrudes from the pixel electrode portion, the transmittance may be lowered, and the luminance may be lowered or the color tone may be changed. In order to avoid such problems more effectively, the transmittance at a wavelength of 550 nm is preferably 80% or more, more preferably 85% or more.
  • the transparent semiconductor thin film 40 preferably has a work function of 3.5 to 6.5 eV. If the work function is less than 3.5 eV, leakage will occur due to charge injection at the interface with the gate insulating film. There is a possibility that transistor characteristics may be deteriorated, such as generation of current. On the other hand, if the voltage is higher than 6.5 eV, an energy barrier may be generated at the interface with the gate insulating film, and the pinch_off characteristics may be deteriorated, which may deteriorate the transistor characteristics. In order to avoid such defects more effectively, the work function is preferably 3.8 to 6.2 eV, 4.0 to 6. OeV is more preferable, and 4.3 to 5.7 eV is more preferable. 4. 5 ⁇ 5.5eV especially preferred.
  • the transparent semiconductor thin film 40 is preferably a non-degenerate semiconductor thin film. If it is a degenerate semiconductor, the carrier concentration may not be controlled stably at a low concentration.
  • the non-degenerate semiconductor thin film is a semiconductor thin film in which the carrier concentration changes depending on the temperature
  • the degenerate semiconductor thin film is a constant value in which the carrier concentration does not depend on the temperature. It refers to a semiconductor thin film showing.
  • the temperature dependence of this carrier concentration can be obtained from Hall measurements.
  • the transparent semiconductor thin film 40 preferably has nanocrystals dispersed in an amorphous film. It is preferable that nanocrystals are dispersed in an amorphous film because hole mobility is improved, field effect mobility is increased, and transistor characteristics are improved. The presence of nanocrystals can be confirmed by observing with TEM.
  • the transparent semiconductor thin film 40 may contain a third metal element other than indium oxide and zinc oxide, or a compound thereof as long as the effects of the present embodiment are not impaired.
  • the atomic ratio [M / (M + In)] between indium [In] and the third metal element [M] is set to 0 to 0.5. If the atomic ratio [M / (M + In)] exceeds 0.5, the hole mobility may decrease. This is presumed to be because the number of bonds between the main elements decreases and the bar-colation conduction becomes difficult.
  • the atomic ratio [M / (M + In)] is preferably 0 to 0.3.
  • the transparent semiconductor thin film 40 has a maximum RDF value between A and A of 0.3 to 0.36 nm in the radial distribution function (RDF) obtained from X-ray scattering measurement. It is preferable that the relationship of A / B> 0.8 is satisfied, where B is the maximum value of RDF between the distances of 0.36 and 0.42 nm.
  • RDF radial distribution function
  • This ratio (A / B) indicates that the bonding form of indium, oxygen, and indium is It is presumed that it represents the ratio of those that share, or the maintenance ratio of short-range order, and if this ratio (A / B) is 0.8 or less, the hole mobility and field-effect mobility may decrease. is there.
  • the ratio (A / B) satisfies AZB> 0.9, more preferably AZB> 1.0, and A / It is presumed that the short-range indium-indium short-range order is maintained because the ratio (A / B) that satisfies B> 1.1 is most favorable. Therefore, it is expected that the electron movement route will be secured and the hole mobility and field effect mobility will be improved.
  • a film forming method for forming the transparent semiconductor thin film 40 in addition to a chemical film forming method such as a spray method, a dip method, and a CVD method, a physical film forming method is also used. It can. From the viewpoint of easy control of carrier density and improvement of film quality, the physical film formation method is preferred.
  • Examples of physical film formation methods include sputtering, vacuum deposition, ion plating, and pulsed laser deposition. Industrially, mass production is high, and sputtering is used. I like it.
  • the sputtering method examples include a DC sputtering method, an RF sputtering method, an AC sputtering method, an ECR sputtering method, and a counter target sputtering method.
  • the DC sputtering method and the AC sputtering method are preferable because they are industrially high in mass productivity and can easily lower the carrier concentration than the RF sputtering method.
  • the ECR sputtering method in order to suppress deterioration of the interface due to film formation, to suppress leakage current, and to improve the characteristics of the transparent semiconductor thin film 40 such as ⁇ -off ratio, the control of the film quality is effective, the ECR sputtering method, The opposed target sputtering method is preferred.
  • co-sputtering is performed using a sintered target containing indium oxide and a sintered target containing zinc oxide.
  • reactive sputtering may be performed while introducing a gas such as oxygen using a metal target made of indium or zinc, or an alloy target.
  • the partial pressure of HO is preferably 8 X 10 _4 Pa or higher.
  • the hydrogen H partial pressure in the atmospheric gas is usually preferably 10 _2 Pa or less and 5 X 10 _3 Pa or less.
  • Sig 10 _3 Pa or less, more preferably tool 5 X 10 _4 Pa or less and more preferably tool 2 X 10 _4 Pa hereinafter are particularly preferred. If H is present in the atmosphere gas, the carrier concentration will increase with force.
  • the partial pressure of oxygen O in the atmospheric gas is usually 40 X 10 _3 Pa or less. Atmospheric gas
  • the hole mobility may decrease, or the hole mobility and carrier concentration may become unstable. This is presumably because too much oxygen in the atmosphere gas during film formation causes more oxygen to be taken in between the crystal lattices, causing scattering, and easily leaving the film and destabilizing it.
  • the oxygen partial pressure in the atmospheric gas is preferably 15 X 10_ 3 Pa or less, more preferably 7 X 10_ 3 Pa or less, and 1 X 10_ 3 Particularly preferred is Pa or lower.
  • the ultimate vacuum is less usual 10- 5 Pa. Ultimate vacuum, and greater than 10- 5 Pa, the partial pressure of water HO increases, not the partial pressure of water HO be a 10_ 3 Pa or less
  • the ultimate pressure is preferably rather is below 5 X 10- 6 Pa, particularly preferably not more than 10- 6 Pa.
  • a film formation step usually, physical film formation is performed at a substrate temperature of 200 ° C or lower, and after the film formation step is completed, an oxidation treatment is performed on the thin film containing indium oxide and zinc oxide.
  • the carrier concentration in the transparent semiconductor thin film 40 can be controlled.
  • the substrate temperature is higher than 200 ° C. during film formation, there is a possibility that the carrier concentration does not decrease even when the oxidation treatment is performed, and deformation or dimensional change may occur when a resin substrate is used.
  • the substrate temperature is preferably 180 ° C or lower, more preferably 150 ° C or lower, further preferably 120 ° C or lower, and 90 ° C or lower. Is particularly preferred.
  • the carrier concentration in the transparent semiconductor thin film 40 is controlled by subjecting the thin film containing indium oxide and zinc oxide to an oxidation treatment. can do.
  • heat treatment is usually performed in the presence of oxygen under the conditions of 80 to 650 ° C, 0.5 to 12000 minutes.
  • the processing temperature is preferably 120 to 500 ° C, more preferably 150 to 450. C, more preferably 180-350 ° C, 200-300. C power is particularly preferred.
  • the processing time is preferably :! to 600 minutes, more preferably 5 to 360 minutes, still more preferably 15 to 240 minutes, and especially 30 to 120 minutes. I like it.
  • heat treatment can be performed with a lamp annealing device (LA), a rapid thermal annealing device (RTA), or a laser annealing device in the presence of oxygen.
  • LA lamp annealing device
  • RTA rapid thermal annealing device
  • laser annealing device in the presence of oxygen.
  • Ozone treatment can be applied as an oxidation treatment. wear.
  • indium oxide having an average particle size of 3.4 ⁇ and acid / zinc having an average particle size of 0.6 / im has an atomic ratio [In / (In + Zn)] of 0.28, The mixture was mixed so that the atomic ratio [ ⁇ / ( ⁇ + ⁇ )] was 0.72, then supplied to a wet ball mill, and mixed and ground for 72 hours to obtain a raw material fine powder.
  • the obtained raw material fine powder After granulating the obtained raw material fine powder, it is press-molded to a size of 10cm in diameter and 5mm in thickness, and this is put into a firing furnace, under the conditions of 1, 400 ° C and 48 hours under pressure of oxygen gas. Firing was performed to obtain a sintered body (target). At this time, the heating rate was 3 ° CZ.
  • the density and Balta resistance value were measured on the obtained target. As a result, the theoretical relative density was 99%, and the Balta resistance value measured by the four-point probe method was 0.8 m ⁇ .
  • the sputtering target obtained in the above (1) was mounted on a DC magnetron sputtering film forming apparatus, which is one of the DC sputtering methods, and a transparent conductive film was formed on a glass substrate (Couting 1737).
  • Sputtering conditions here are as follows: substrate temperature: 25 ° C, ultimate pressure: 1 X 10 _3 Pa, atmosphere gas: Arl00%, sputtering pressure (total pressure): 4 X 10 _1 Pa, input power 100 W, film formation The time was 20 minutes.
  • the carrier concentration and hole mobility of the transparent semiconductor thin film obtained in (3) above were measured with a hole measuring device.
  • the carrier concentration was 2 ⁇ 10 15 cm _3 and the hole mobility was 16 cm 2 / Vs.
  • the specific resistance value measured by the four probe method was 200 ⁇ cm.
  • the light transmittance for a light beam having a wavelength of 550 ⁇ m was 85% by a spectrophotometer, and the transparency was also excellent.
  • the energy band gap was 3.3 eV, which was sufficiently large.
  • Example 1 The production was evaluated in the same manner as in Example 1 except that the composition ratio of the raw materials, the film forming conditions, and the oxidation treatment conditions were adjusted as shown in Table 1.
  • yttrium oxide having a high dielectric constant was used as a gate insulating film with a thickness of 170 nm.
  • IZO with a thickness of 150 nm was used as the gate electrode, the source electrode, and the drain electrode.
  • the obtained thin film transistor was evaluated according to the following criteria. The results are shown in Table 1 together with the on-off ratio.
  • the semiconductor thin film in the present invention can be widely used as a semiconductor thin film used for a field effect transistor such as a thin film transistor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Dram (AREA)

Abstract

Disclosed is a semiconductor thin film which can be formed at a relatively low temperature even on a flexible resin substrate. Since the semiconductor thin film is stable to visible light and has high device characteristics such as transistor characteristics, it does not decrease the luminance of a display when overlapped with the pixel portion in case where the semiconductor thin film is used as a switching device for driving the display. Specifically disclosed is a transparent semiconductor thin film (40) produced by forming an amorphous film containing zinc oxide and indium oxide and then oxidizing the film so that the resulting film has a carrier density of 10+17 cm-3 or less, a hole mobility of 2 cm2/V·sec or more, and an energy band gap of 2.4 EV or more.

Description

明 細 書  Specification
半導体薄膜、及びその製造方法、並びに薄膜トランジスタ、アクティブマト リックス駆動表示パネル  Semiconductor thin film, manufacturing method thereof, thin film transistor, active matrix drive display panel
技術分野  Technical field
[0001] 本発明は、酸化亜鉛と酸化インジウムとを含有する非晶質膜力らなる半導体薄膜、 及びその製造方法、並びにそのような半導体薄膜を用いた薄膜トランジスタ、そのよ うな薄膜トランジスタを適用したアクティブマトリックス駆動表示パネルに関する。  [0001] The present invention relates to a semiconductor thin film having an amorphous film strength containing zinc oxide and indium oxide, a manufacturing method thereof, a thin film transistor using such a semiconductor thin film, and an active to which such a thin film transistor is applied. The present invention relates to a matrix drive display panel.
背景技術  Background art
[0002] 電界効果型トランジスタは、半導体メモリ集積回路の単位電子素子、高周波信号増 幅素子、液晶駆動用素子などとして広く用いられており、現在、最も多く実用化され てレ、る電子デバイスである。  Field effect transistors are widely used as unit electronic elements, high-frequency signal amplifier elements, liquid crystal driving elements, etc. in semiconductor memory integrated circuits, and are currently the most widely used electronic devices. is there.
そのなかでも、近年における表示装置のめざましい発展に伴い、液晶表示装置 (L CD)のみならず、エレクト口ルミネッセンス表示装置（EL)や、フィールドェミッション ディスプレイ（FED)などの各種の表示装置において、表示素子に駆動電圧を印加し て表示装置を駆動させるスイッチング素子として、薄膜トランジスタ (TFT)が多用され ている。  Among them, with the remarkable development of display devices in recent years, not only in liquid crystal display devices (L CD), but also in various display devices such as electoric luminescence display devices (EL) and field emission displays (FED), Thin film transistors (TFTs) are frequently used as switching elements for driving display devices by applying a driving voltage to the display elements.
また、その材料としては、シリコン半導体化合物が最も広く用いられており、一般に 、高速動作が必要な高周波増幅素子、集積回路用素子などには、シリコン単結晶が 用いられ、液晶駆動用素子などには、大面積化の要求からアモルファスシリコンが用 いられている。  In addition, silicon semiconductor compounds are the most widely used as the material. Generally, silicon single crystals are used for high-frequency amplifier elements and integrated circuit elements that require high-speed operation, and are used for liquid crystal drive elements. Amorphous silicon is used because of the demand for large area.
[0003] し力 ながら、結晶性のシリコン系薄膜は、結晶化を図る際に、例えば、 800°C以上 の高温が必要となり、ガラス基板上や有機物基板上への構成が困難である。このた め、シリコンウェハーや石英などの耐熱性の高い高価な基板上にしか形成できない ばかりか、製造に際して多大なエネルギーと工程数を要するなどの問題があった。  However, a crystalline silicon-based thin film requires a high temperature of, for example, 800 ° C. or higher when crystallization is performed, and is difficult to construct on a glass substrate or an organic substrate. For this reason, there is a problem that it can be formed only on an expensive substrate having high heat resistance such as a silicon wafer or quartz, and a lot of energy and the number of processes are required for production.
[0004] 一方、比較的低温で形成できる非晶性のシリコン半導体 (アモルファスシリコン）は、 結晶性のものに比べてスィッチング速度が遅いため、表示装置を駆動するスィッチン グ素子として使用したときに、高速な動画の表示に追従できない場合がある。 さらに、半導体活性層に可視光が照射されると導電性を示し、漏れ電流が発生して 誤動作のおそれがあるなど、スイッチング素子としての特性が劣化するという問題もあ る。そのため、可視光を遮断する遮光層を設ける方法が知られており、例えば、遮光 層としては金属薄膜が用いられてレ、る。 On the other hand, an amorphous silicon semiconductor (amorphous silicon) that can be formed at a relatively low temperature has a lower switching speed than a crystalline one, so when used as a switching element for driving a display device, It may not be possible to follow the display of high-speed movies. Furthermore, when the semiconductor active layer is irradiated with visible light, the semiconductor device exhibits electrical conductivity, and there is a problem that the characteristics as a switching element deteriorate, such as the possibility of malfunction due to leakage current. Therefore, a method of providing a light shielding layer that blocks visible light is known. For example, a metal thin film is used as the light shielding layer.
し力 ながら、金属薄膜からなる遮光層を設けると工程が増えるだけでなぐ浮遊電 位を持つこととなるので、遮光層をグランドレベルにする必要があり、その場合にも寄 生容量が発生するという問題がある。  However, if a light-shielding layer made of a metal thin film is provided, it will have a floating potential that only increases the number of processes, so the light-shielding layer must be at the ground level, and in this case, parasitic capacitance is generated. There is a problem.
また、可視光の透過率が低いため、半導体層が電極部にはみ出ると表示部の透過 率が下がり、バックライトによる照明効率が低下して画面が暗くなるおそれがあり、カロ ェ精度の公差が小さくコストアップの一因となっていた。  In addition, since the transmittance of visible light is low, if the semiconductor layer protrudes from the electrode section, the transmittance of the display section may decrease, the illumination efficiency by the backlight may decrease, and the screen may become dark. It contributed to a small cost increase.
[0005] なお、現在、表示装置を駆動させるスイッチング素子としては、シリコン系の半導体 膜を用いた素子が主流を占めているが、それは、シリコン薄膜の安定性、加工性の 良さの他、スイッチング速度が速いなど、種々の性能が良好なためである。そして、こ のようなシリコン系薄膜は、一般に化学蒸気析出法 (CVD)法により製造されている。 また、従来の薄膜トランジスタ (TFT)は、ガラスなどの基板上にゲ―ト電極、ゲ―ト 絶縁層、水素化アモルファスシリコン（a— Si : H)などの半導体層、ソース及びドレイ ン電極を積層した逆スタガ構造のものがあり、イメージセンサを始め、大面積デバイス の分野にぉレ、て、アクティブマトリスク型の液晶ディスプレイに代表されるフラットパネ ルディスプレイなどの駆動素子として用いられている。これらの用途では、従来ァモル ファスシリコンを用いたものでも高機能化に伴い作動の高速化が求められてきている  [0005] Currently, as a switching element for driving a display device, an element using a silicon-based semiconductor film occupies the mainstream, which is not only the stability and workability of a silicon thin film but also switching. This is because various performances such as high speed are good. Such silicon-based thin films are generally manufactured by chemical vapor deposition (CVD). A conventional thin film transistor (TFT) has a gate electrode, a gate insulating layer, a semiconductor layer such as hydrogenated amorphous silicon (a-Si: H), a source and a drain electrode stacked on a substrate such as glass. Inverted staggered structures are used in the field of large area devices, including image sensors, and are used as driving elements for flat panel displays such as active matrix liquid crystal displays. In these applications, even those using conventional amorphous silicon have been required to operate faster with higher functionality.
[0006] このような状況下、近年にあっては、シリコン系半導体薄膜 (アモルファスシリコン)よ りも安定性が優れるものとして、酸化亜鉛などの金属酸化物からなる透明半導体薄 膜、特に、酸化亜鉛結晶からなる透明半導体薄膜が注目されている。 [0006] Under these circumstances, in recent years, a transparent semiconductor thin film made of a metal oxide such as zinc oxide, in particular, an oxide, is superior in stability to a silicon-based semiconductor thin film (amorphous silicon). A transparent semiconductor thin film made of zinc crystals has attracted attention.
例えば、特許文献 1や、特許文献 2などには、酸化亜鉛を高温で結晶化し薄膜トラ ンジスタを構成する方法が記載されてレ、る。  For example, Patent Document 1 and Patent Document 2 describe a method for forming a thin film transistor by crystallizing zinc oxide at a high temperature.
特許文献 1 :特開 2003— 86808号公報  Patent Document 1: Japanese Patent Laid-Open No. 2003-86808
特許文献 2 :特開 2004— 273614号公報 発明の開示 Patent Document 2: JP-A-2004-273614 Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0007] し力しながら、酸化亜鉛を用いた半導体薄膜は、精緻な結晶化制御を行なわないと ホール移動度が低くなるため、電界効果移動度が低下してスイッチング速度が低くな るという問題があった。そして、結晶性を上げるためには、シリコン系薄膜と同様に結 晶性の高い特殊な基板上に成膜したり、 500°C以上の高温の処理を行なったりする 必要があった。そのため、大面積で均一に行なうこと、特に、ガラス基板上で行なうこ とは困難であり、液晶パネルでは実用化が難しかった。  [0007] However, the semiconductor thin film using zinc oxide has a problem that the hole mobility is lowered unless precise crystallization control is performed, so that the field effect mobility is lowered and the switching speed is lowered. was there. In order to improve the crystallinity, it was necessary to form a film on a special substrate having high crystallinity as in the case of the silicon-based thin film, or to perform a high temperature treatment of 500 ° C or higher. Therefore, it is difficult to carry out uniformly over a large area, particularly on a glass substrate, and it has been difficult to put it into practical use in a liquid crystal panel.
[0008] 本発明は、上記の事情に鑑みなされたものであり、比較的低温で作製でき、屈曲性 のある樹脂基板上にも形成可能な半導体薄膜であって、可視光に対して安定で、か つ、トランジスタ特性などの素子特性が高ぐまた、表示装置を駆動するスイッチング 素子として用いた際に、画素部と重なっても表示パネルの輝度を低下させない半導 体薄膜、及びそのような半導体薄膜の製造方法、並びにそのような半導体薄膜を用 いた、電界効果移動度と on— off比が高いとともに、漏れ電流の発生などの照射光 による影響を小さくして、素子特性を向上させた薄膜トランジスタ、そのような薄膜トラ ンジスタを適用したアクティブマトリックス駆動表示パネルの提供を目的とする。  The present invention has been made in view of the above circumstances, and is a semiconductor thin film that can be produced at a relatively low temperature and can be formed on a flexible resin substrate, and is stable to visible light. In addition, the device characteristics such as transistor characteristics are high. Also, when used as a switching element for driving a display device, a semiconductor thin film that does not decrease the luminance of the display panel even if it overlaps with the pixel portion, and such a thin film. The semiconductor thin film manufacturing method, and the field effect mobility and on-off ratio using such a semiconductor thin film are high, and the influence of irradiation light such as the generation of leakage current is reduced to improve the device characteristics. It is an object of the present invention to provide a thin film transistor and an active matrix drive display panel to which such a thin film transistor is applied.
課題を解決するための手段  Means for solving the problem
[0009] 上記課題を解決する本発明に係る半導体薄膜は、酸化亜鉛と酸化インジウムを含 有する非晶質膜からなる半導体薄膜であって、キャリア密度が 10+ 17cm— 3以下、ホ ール移動度が 2cm2ZV' sec以上、エネルギーバンドギャップが 2. 4eV以上である 構成としてある。 [0009] A semiconductor thin film according to the present invention that solves the above problems is a semiconductor thin film made of an amorphous film containing zinc oxide and indium oxide, and has a carrier density of 10 + 17 cm- 3 or less and a hole. The mobility is 2 cm 2 ZV 'sec or more and the energy band gap is 2.4 eV or more.
[0010] このような構成とすることにより、本発明に係る半導体薄膜は、広い温度範囲で半導 体薄膜を作製しやすくなるとともに、大面積で均一な物性を発現しやすくなるため、 表示パネルなどの用途に好適となる。  With such a configuration, the semiconductor thin film according to the present invention makes it easy to produce a semiconductor thin film over a wide temperature range, and easily develops uniform physical properties over a large area. It is suitable for such applications.
本発明に係る半導体薄膜において、キャリア密度が 10+ 17cm_3より大きくなると、薄 膜トランジスタ 1などの素子を構成した際に、漏れ電流が発生してしまうとともに、ノー マリーオンになってしまったり、 on— off比が小さくなつてしまったりすることにより、良 好なトランジスタ性能が発揮できないおそれがある。 また、ホール移動度が 2cm2ZVsより小さいと、薄膜トランジスタ 1の電界効果移動 度が小さくなつてしまい、表示素子を駆動するスイッチング素子として用いる場合に、 アモルファスシリコンと同様に、スイチング速度が遅ぐ高速な動画の表示に追従でき ないおそれがある。 In the semiconductor thin film according to the present invention, or when the carrier density is greater than 10 + 17 cm_ 3, at the time of constructing a device such as a thin-film transistor 1, the leakage current is generated, it has become a no Marion, If the on-off ratio is too small, good transistor performance may not be achieved. If the hole mobility is less than 2 cm 2 ZVs, the field-effect mobility of thin film transistor 1 will be small, and when used as a switching element to drive a display element, the switching speed is low, similar to amorphous silicon. May not be able to follow the display of moving images.
また、エネルギーバンドギャップが 2. 4eVより小さいと、可視光が照射された際に、 価電子帯の電子が励起されて導電性を示し、漏れ電流が生じやすくなるおそれがあ る。  On the other hand, if the energy band gap is less than 2.4 eV, when visible light is irradiated, electrons in the valence band are excited and become conductive, which may cause leakage current.
[0011] また、本発明に係る半導体薄膜は、大面積上に均一な非晶質の膜を形成できるよ うにするとともに、膜質が不均一となるのを回避するために、前記非晶質膜中の亜鉛 [Zn]とインジウム [In]の原子比力 Zn/ (Zn + In) =0. 10〜0. 82とするのが好ま しぐ前記非晶質膜中の亜鉛 Znとインジウム Inの原子比力 S、 Zn/ (Zn+In) =0. 51 〜0· 80とするのがより好ましい。  In addition, the semiconductor thin film according to the present invention enables the formation of a uniform amorphous film over a large area and avoids non-uniform film quality in order to form a non-uniform film. Zinc [Zn] and Indium [In] in the atomic specific force Zn / (Zn + In) = 0.1 to 0.82 It is more preferable that the atomic specific force S, Zn / (Zn + In) = 0.51 to 0 · 80.
[0012] また、本発明に係る半導体薄膜は、波長 550nmの透過率が 75%以上であるのが 好ましぐこのようにすることで、半導体薄膜が画素電極部にはみ出た場合であっても 、透過率や輝度を低下させたり、色調が変化したりするような不具合を有効に回避す ること力 Sできる。  In addition, the semiconductor thin film according to the present invention preferably has a transmittance of 75% or more at a wavelength of 550 nm, so that even when the semiconductor thin film protrudes from the pixel electrode portion. It is possible to effectively avoid problems such as a decrease in transmittance and brightness, or a change in color tone.
[0013] また、本発明に係る半導体薄膜は、仕事関数が 3. 5〜6. 5eVの非縮退半導体薄 膜であるのが好ましい。仕事関数を上記範囲とすることで、漏れ電流が発生したり、 エネルギー障壁などが発生したりすることによるトランジスタの特性低下を有効に回 避することができる。さらに、縮退半導体であるとキャリア濃度を低濃度で安定定期に 制御できないおそれがあるが、本発明に係る半導体薄膜を非縮退半導体薄膜とする ことで、このような不具合を有効に回避することもできる。ここで、非縮退半導体薄膜 はキャリア濃度が温度に依存して変化する半導体薄膜をいい、キャリア濃度の温度 依存性は、ホール測定から求めることができる。  [0013] The semiconductor thin film according to the present invention is preferably a non-degenerate semiconductor thin film having a work function of 3.5 to 6.5 eV. By setting the work function within the above range, it is possible to effectively avoid deterioration of transistor characteristics due to leakage current and energy barriers. Furthermore, a degenerate semiconductor may not be able to stably control the carrier concentration at a low concentration, but by making the semiconductor thin film according to the present invention a non-degenerate semiconductor thin film, it is possible to effectively avoid such problems. it can. Here, the non-degenerate semiconductor thin film refers to a semiconductor thin film in which the carrier concentration varies depending on the temperature, and the temperature dependence of the carrier concentration can be obtained from hole measurement.
[0014] また、本発明に係る半導体薄膜は、非晶質膜にナノクリスタルが分散しているのが 好ましぐ非晶質膜中にナノクリスタルが分散していると、ホール移動度が向上し、電 界効果移動度が高くなりトランジスタ特性が向上する場合があり好ましい。  [0014] Further, in the semiconductor thin film according to the present invention, it is preferable that nanocrystals are dispersed in an amorphous film. When nanocrystals are dispersed in an amorphous film, the hole mobility is improved. However, it is preferable because the field effect mobility is increased and the transistor characteristics are improved.
[0015] また、本発明に係る半導体薄膜は、本発明の効果を損なわない範囲で酸化インジ ゥム、酸化亜鉛以外の第三の金属元素 [M]や、その化合物を含有していてもよぐこ の場合、前記第三の金属元素 [M]とインジウム [In]の原子比 [M/ (M + In) ]は 0〜 0. 5であるのが好ましぐ前記第三の金属元素 [M]とインジウム [In]の原子比 [MZ (M + In) ]は 0〜0. 3であるのがより好ましい。 [0015] Further, the semiconductor thin film according to the present invention is an oxide oxide as long as the effects of the present invention are not impaired. In the case where it is possible to contain a third metal element [M] other than hum, zinc oxide, or a compound thereof, the atomic ratio of the third metal element [M] to indium [In] [M / (M + In)] is preferably 0 to 0.5. The atomic ratio [MZ (M + In)] of the third metal element [M] to indium [In] is preferably 0 to 0.3. It is more preferable that
[0016] また、本発明に係る半導体薄膜は、 X線散乱測定より求められる動径分布関数 (R DF)における、原子間距離が 0. 3〜0. 36nmの間の RDFの最大値を A、原子間距 離が 0. 36〜0. 42nmの間の RDFの最大値を Bとしたときに、 A/B > 0. 8の関係を 満たすのが好ましぐこの比率 (A/B)はインジウム 酸素 インジウムの結合形態 力 陵共有と頂点共有をなすものの比率、あるいは短距離秩序の維持比率を表して いるものと推定される。 [0016] In addition, the semiconductor thin film according to the present invention has a maximum RDF value between the atomic distances of 0.3 to 0.36 nm in the radial distribution function (RDF) obtained by X-ray scattering measurement. This ratio (A / B) that satisfies the relationship of A / B> 0.8, where B is the maximum value of RDF between atomic distances of 0.36 and 0.42 nm, is Indium Oxygen Indium bond form Strength It is estimated that it represents the ratio of the ridge sharing and apex sharing, or the maintenance ratio of short-range order.
そして、この比率が 0. 8以下だと、ホール移動度や電界効果移動度が低下するお それがある。  If this ratio is less than 0.8, the hole mobility and field effect mobility may be reduced.
[0017] また、本発明に係る半導体薄膜の製造方法は、前述したような半導体薄膜を製造 するにあたり、雰囲気ガス中の水 H Oの分圧が 10_3Pa以下となる条件で、酸化亜鉛 [0017] Also, the method for producing a semiconductor thin film according to the present invention provides a zinc oxide under the condition that the partial pressure of water HO in the atmospheric gas is 10 _3 Pa or less in producing the semiconductor thin film as described above.
2  2
と酸化インジウムを含有する非晶質膜を成膜する方法とすることができる。  And an amorphous film containing indium oxide can be formed.
このような方法とすることにより、ホール移動度が低下するおそれがあるという不具 合を有効に回避することができる。  By adopting such a method, it is possible to effectively avoid the problem that the hole mobility may be lowered.
[0018] また、本発明に係る半導体薄膜の製造方法は、基板温度 200°C以下で物理成膜 した前記非晶質膜を酸化処理する工程を含む方法とするのが好ましぐ基板温度が 200°Cより高いと、酸化処理してもキャリア濃度が下がらなかったり、樹脂製基板を用 レ、た場合に変形や寸法変化を起こすおそれがある。 [0018] Further, the method for producing a semiconductor thin film according to the present invention preferably includes a step of oxidizing the amorphous film physically formed at a substrate temperature of 200 ° C or less, wherein the substrate temperature is preferably If the temperature is higher than 200 ° C, the carrier concentration may not decrease even after oxidation treatment, or deformation or dimensional change may occur if a resin substrate is used.
また、上記範囲で成膜した半導体薄膜を酸素存在下の熱処理やオゾン処理などの 酸化処理をすることがキャリア密度を安定化させるために好ましレ、。  In addition, it is preferable to subject the semiconductor thin film formed in the above range to heat treatment in the presence of oxygen or oxidation treatment such as ozone treatment in order to stabilize the carrier density.
熱処理をする場合は、熱処理時の膜面の温度が、成膜時の基板温度より 100〜27 0°C高い方が好ましい。この温度差が 100°Cより小さいと熱処理効果が無ぐ 270°C より高いと基板が変形したり、半導体薄膜界面が変質し半導体特性が低下したりする おそれがある。このような不具合をより有効に回避するには、成膜時の基板温度より 熱処理時の膜面の温度が 130〜240°C高いものがより好ましぐ 160〜210°C高レ、も のが特に好ましい。 In the case of performing heat treatment, it is preferable that the temperature of the film surface during the heat treatment is 100 to 270 ° C. higher than the substrate temperature during the film formation. If the temperature difference is less than 100 ° C, the heat treatment effect is not obtained. If the temperature difference is higher than 270 ° C, the substrate may be deformed, or the semiconductor thin film interface may be altered to deteriorate the semiconductor characteristics. In order to avoid such problems more effectively, it is more preferable that the temperature of the film surface during heat treatment is 130-240 ° C higher than the substrate temperature during film formation, which is 160-210 ° C higher. Is particularly preferred.
[0019] また、本発明に係る薄膜トランジスタは、前述したような半導体薄膜を有する構成と することができ、前記半導体薄膜が、樹脂基板上に設けられている構成とすることが できる。  In addition, the thin film transistor according to the present invention can be configured to have the semiconductor thin film as described above, and the semiconductor thin film can be configured to be provided on a resin substrate.
[0020] また、本発明に係るアクティブマトリックス駆動表示パネルは、前述したような薄膜ト ランジスタを有する構成とすることができる。  [0020] Further, the active matrix drive display panel according to the present invention may be configured to include the thin film transistor as described above.
発明の効果  The invention's effect
[0021] 以上のように、本発明によれば、ガラス基板や樹脂基板などに広い温度範囲で形 成することができるとともに、可視光に対して安定で誤作動を起こし難い、漏れ電流 の小さい優れた電界効果型トランジスタを構成する半導体薄膜を提供することができ る。また、本発明の半導体薄膜は、比較的低温で形成することができるため、樹脂基 板上に形成して、屈曲性のある薄膜トランジスタなどを提供することもできる。  [0021] As described above, according to the present invention, a glass substrate or a resin substrate can be formed in a wide temperature range, is stable with respect to visible light, hardly causes a malfunction, and has a small leakage current. A semiconductor thin film constituting an excellent field effect transistor can be provided. Further, since the semiconductor thin film of the present invention can be formed at a relatively low temperature, it can be formed on a resin substrate to provide a flexible thin film transistor or the like.
図面の簡単な説明  Brief Description of Drawings
[0022] [図 1]本発明に係る薄膜トランジスタの実施形態の概略を示す説明図である。  FIG. 1 is an explanatory diagram showing an outline of an embodiment of a thin film transistor according to the present invention.
符号の説明  Explanation of symbols
[0023] 1 薄 S莫トランジスタ  [0023] 1 Thin S transistor
40 透明半導体薄膜  40 Transparent semiconductor thin film
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0024] 以下、本発明の好ましい実施形態について説明する。 [0024] Hereinafter, preferred embodiments of the present invention will be described.
なお、図 1は、本発明に係る薄膜トランジスタの実施形態の概略を示す説明図であ る。  FIG. 1 is an explanatory diagram showing an outline of an embodiment of a thin film transistor according to the present invention.
[0025] 図示する例において、電界効果型トランジスタとしての薄膜トランジスタ 1は、基板 6 0上にドレイン電極 10とソース電極 20とを離間して形成するとともに、ドレイン電極 10 とソース電極 20のそれぞれの少なくとも一部と接するように透明半導体薄膜 40を形 成し、さらに、透明半導体薄膜 40上に、ゲート絶縁膜 50、ゲート電極 30をこの順で 形成してなるトップゲート型の薄膜トランジスタ 1として構成されている。  In the illustrated example, a thin film transistor 1 as a field effect transistor includes a drain electrode 10 and a source electrode 20 formed on a substrate 60 so as to be separated from each other, and at least each of the drain electrode 10 and the source electrode 20. A transparent semiconductor thin film 40 is formed so as to be in contact with a part of the thin film transistor, and a gate insulating film 50 and a gate electrode 30 are formed on the transparent semiconductor thin film 40 in this order. Yes.
[0026] 本実施形態において、基板 60としては、ガラス基板のほ力、ポリエチレンテレフタレ 一 HPET)，ポリカーボネート（PC)などからなる樹脂製基板を用いることもできる。 In the present embodiment, as the substrate 60, a glass substrate, polyethylene terephthalate (1) A resin substrate made of, for example, HPET) or polycarbonate (PC) can also be used.
[0027] また、ゲート電極 30、ソース電極 20、ドレイン電極 10の各電極を形成する材料に特 に制限はなぐ本実施形態の効果を失わない範囲で一般に用いられているものを任 意に選択することができる。例えば、 ITO, IZ〇， ZnO, Sn〇2などの透明電極や、 Al ， Ag， Cr， Ni, Mo, Au, Ti, Taなどの金属電極、又はこれらを含む合金の金属電 極を用いることができる。 [0027] In addition, the material for forming each of the gate electrode 30, the source electrode 20, and the drain electrode 10 is not particularly limited. Any material that is generally used as long as the effect of the present embodiment is not lost can be arbitrarily selected. can do. For example, use transparent electrodes such as ITO, IZ ○, ZnO, and Sn2, metal electrodes such as Al, Ag, Cr, Ni, Mo, Au, Ti, Ta, or metal electrodes of alloys containing these. Can do.
ゲート電極 30、ソース電極 20、ドレイン電極 10の各電極は、異なる二層以上の導 電層を積層した多層構造とすることもでき、図示する例において、各電極 30, 20, 10 は、それぞれ第一導電層 31, 21 , 11と第二導電層 32, 22, 12とから構成されてい る。  Each of the gate electrode 30, the source electrode 20, and the drain electrode 10 may have a multilayer structure in which two or more different conductive layers are stacked.In the illustrated example, each of the electrodes 30, 20, and 10 The first conductive layers 31, 21 and 11 and the second conductive layers 32, 22, and 12 are included.
[0028] また、ゲート絶縁膜 50を形成する材料にも特に制限はない。本実施形態の発明の 効果を失わない範囲で一般に用いられているものを任意に選択できる。例えば、 Si 〇， SiNx, Al O , Ta〇， TiO , MgO, ZrO , CeO , K O, Li〇， Na〇， Rb〇 In addition, the material for forming the gate insulating film 50 is not particularly limited. Any one generally used can be selected as long as the effects of the invention of the present embodiment are not lost. For example, Si 〇, SiNx, AlO, Ta〇, TiO, MgO, ZrO, CeO, KO, Li〇, Na〇, Rb〇
2 2 3 2 5 2 2 2 2 2 2 22 2 3 2 5 2 2 2 2 2 2 2
, Sc〇， Y〇， Hf 〇 , Sc〇, Y〇, Hf〇
2 3， CaHfOなどの酸化物を用いることができる。これらのなか 23 3. Oxides such as CaHfO can be used. Among these
2 3 2 3 3 2 3 2 3 3
でも、 SiO , SiNx, Al O , Y〇  But SiO, SiNx, Al O, Y〇
2 3 2 3， Hf O , CaHfOを用いるのが好ましぐより好ま 2 3 2 3, Hf O, CaHfO is preferred over preferred
2 2 3 3 2 2 3 3
しくは SiO , SiNx, Y O , Hf 〇  Or SiO, SiNx, Y O, Hf ○
2 2 3 2 3， CaHfOであり、特に好ましくは SiO , SiNxであ  2 2 3 2 3, CaHfO, particularly preferably SiO 2 or SiNx
3 2  3 2
る。  The
このようなゲート絶縁膜 50は、異なる 2層以上の絶縁膜を積層した構造でもよい。ま た、ゲート絶縁膜 50は、結晶質であっても非晶質であってもよいが、工業的に製造し やすレ、非晶質であるのが好ましレ、。  Such a gate insulating film 50 may have a structure in which two or more different insulating films are stacked. In addition, the gate insulating film 50 may be crystalline or amorphous. However, the gate insulating film 50 is easily manufactured industrially, and is preferably amorphous.
[0029] 本実施形態において、透明半導体薄膜 40は、酸化亜鉛と酸化インジウムを含有す る非晶質からなり、ホール測定で求めたキャリア密度が 10+ 17cm— 3以下、ホール移動 度が 2cm2ZVs以上、伝導帯と価電子帯とのエネルギーバンドギャップが 2. 4eV以 上となるように形成してある。 In the present embodiment, the transparent semiconductor thin film 40 is made of an amorphous material containing zinc oxide and indium oxide, has a carrier density of 10 + 17 cm− 3 or less determined by hole measurement, and a hole mobility of 2 cm. 2 ZVS above, the energy band gap between the conduction band and the valence band 2. is formed so as to be on 4eV or more.
このような酸化亜鉛と酸化インジウムを含有する非晶質膜は、広い温度範囲で作製 しゃすいとともに、非晶質膜とすることにより大面積で均一な物性を発現しやすくなる ため、表示パネルなどの用途で特に好まし 例えば、アクティブマトリックス駆動表 示パネルに好適に利用することができる。 なお、非晶質膜であることは、 X線回折で明確なピークが現れないことで確認できる Such an amorphous film containing zinc oxide and indium oxide is manufactured in a wide temperature range, and it is easy to express uniform physical properties in a large area by using an amorphous film. For example, it can be suitably used for an active matrix drive display panel. In addition, it can be confirmed that it is an amorphous film by a clear peak not appearing by X-ray diffraction.
[0030] ここで、キャリア密度が 10+ 17cm_3より大きくなると、薄膜トランジスタ 1などの素子を 構成した際に、漏れ電流が発生してしまうとともに、ノーマリーオンになってしまったり 、 on_ off比が小さくなつてしまったりすることにより、良好なトランジスタ性能が発揮 できないおそれがある。このような不具合をより有効に回避するには、キャリア密度は 、 10+ 16cm_3以下とするのが好ましぐより好ましくは 10+ 15cm_3以下であり、 10+ 14c m_3以下とするのが特に好ましレヽ。 [0030] Here, when the carrier density is greater than 10 + 17 cm_ 3, at the time of constructing a device such as a thin film transistor 1, the leakage current is generated, or has become a normally-on, on_ off ratio If the transistor becomes too small, good transistor performance may not be exhibited. To avoid such an inconvenience more effectively, the carrier density is 10 + 16 CM_ 3 or less and preferably 10 + 15 CM_ 3 than is preferred instrument to below the 10 + 14 c m_ 3 below Especially preferred to do.
[0031] また、ホール移動度が 2cm2/Vsより小さいと、薄膜トランジスタ 1の電界効果移動 度が小さくなつてしまい、表示素子を駆動するスイッチング素子として用いる場合に、 アモルファスシリコンと同様に、スイチング速度が遅ぐ高速な動画の表示に追従でき ないおそれがある。このような不具合をより有効に回避するには、ホール移動度は、 5 cm2/Vs以上とするのが好ましぐより好ましくは 8cm2/Vs以上、さらに好ましくは 1 lcm2/Vs以上であり、 14cm2/Vs以上とするのが特に好ましい。 [0031] When the hole mobility is smaller than 2 cm 2 / Vs, the field effect mobility of the thin film transistor 1 is reduced, and when used as a switching element for driving a display element, the switching speed is similar to that for amorphous silicon. It may not be possible to follow the display of high-speed movies that are slow. In order to avoid such defects more effectively, the hole mobility is preferably 5 cm 2 / Vs or more, more preferably 8 cm 2 / Vs or more, and even more preferably 1 lcm 2 / Vs or more. It is particularly preferably 14 cm 2 / Vs or more.
[0032] このように、透明半導体薄膜 40をキャリア密度が 10+ 17cm— 3以下、ホール移動度 が 2cm2/Vs以上に形成することで、電界効果移動度とともに、 onn— off比も高ぐ また、ノーマリーオフを示し、かつ、ピンチオフが明瞭な、従来のアモルファスシリコン を用いた電界効果型トランジスタに代わる大面積化の可能な、新たな優れた電界効 果型トランジスタを得ることができる。 [0032] Thus, the transparent semiconductor thin film 40 the carrier density 10 + 17 cm- 3 or less, that the hole mobility be formed in more than 2 cm 2 / Vs, the field effect mobility, Onn- off ratio is also high In addition, it is possible to obtain a new and excellent field effect transistor capable of increasing the area instead of the conventional field effect transistor using amorphous silicon, which shows normally-off and clear pinch-off. .
[0033] また、エネルギーバンドギャップが 2. 4eVより小さレ、と、可視光が照射された際に、 価電子帯の電子が励起されて導電性を示し、漏れ電流が生じやすくなるおそれがあ る。このような不具合をより有効に回避するには、エネルギーバンドギャップは、好まし くは 2. 6eV以上、より好ましくは 2. 8eV以上、さらに好ましくは 3. Oev以上であり、 3 . 2eV以上が特に好ましい。  [0033] Also, when the energy band gap is less than 2.4 eV, when irradiated with visible light, electrons in the valence band are excited to show conductivity, and leakage current is likely to occur. The In order to avoid such defects more effectively, the energy band gap is preferably 2.6 eV or more, more preferably 2.8 eV or more, further preferably 3. Oev or more, and 3.2 eV or more. Particularly preferred.
[0034] また、透明半導体薄膜 40の比抵抗は、通常 10―1〜 10+8 Q cmである力 10―1〜 1 0+8 Ω cmであることが好ましぐ 10°〜10+6 Q cmであることがより好まし 10+ 1〜10 +4 Ω cmであることがさらに好ましぐ 10+2〜10+3 Q cmであることが特に好ましい。 [0034] The specific resistance of the transparent semiconductor thin film 40 is generally 10- 1 ~ 10 +8 Q cm and a force 10- 1 ~ 1 0 +8 Ω it is cm is preferred instrument 10 ° to 10 +6 Q cm is more preferred, and 10 + 1 to 10 + 4 Ωcm is even more preferred. 10 +2 to 10 +3 Q cm is particularly preferred.
[0035] さらに、透明半導体薄膜 40に酸化インジウムを含有させることで、高いホール移動 度を実現するとともに、成膜時における雰囲気ガス中の酸素分圧や、雰囲気ガス中 の水 H 0、又は水素 Hの含有量を制御することによって、ホール移動度を制御する[0035] Furthermore, high hole movement is achieved by adding indium oxide to the transparent semiconductor thin film 40. The hole mobility is controlled by controlling the oxygen partial pressure in the atmospheric gas during film formation and the water H 0 or hydrogen H content in the atmospheric gas during film formation.
2 2 twenty two
こと力 sできる。  That power s.
[0036] 酸化インジウムとともに、酸化亜鉛を含有させるのが有効なのは、結晶化の際に、 正三価のインジウムサイトに置換することでキャリアトラップを発生させ、ホール移動度 をあまり低下させずにキャリア密度を下げているためと推定される。  [0036] The inclusion of zinc oxide together with indium oxide is effective because carrier traps are generated by substituting positive trivalent indium sites during crystallization, and the carrier mobility is not significantly reduced. This is presumed to be due to lowering.
そして、正三価元素であるインジウムに対して正二価元素である亜鉛を含有させる ことで、キャリア濃度を減少させるとともに、後述するように、成膜後に酸化処理を施 すことによって、ホール移動度を低下させることなぐキャリア濃度を制御することも可 能となる。  By adding zinc, which is a positive divalent element, to indium, which is a positive trivalent element, the carrier concentration is reduced and, as will be described later, by performing an oxidation treatment after film formation, the hole mobility is increased. It is also possible to control the carrier concentration without decreasing it.
[0037] また、半導体薄膜 50中に含有されるインジウム [In]と亜鉛 [Zn]の原子比 [Zn/ (Z n + In) ]は、 0· 10〜0· 82とすること力 Sできる。  [0037] Further, the atomic ratio [Zn / (Zn + In)] of indium [In] and zinc [Zn] contained in the semiconductor thin film 50 can be set to 0 · 10 to 0 · 82. .
原子比 [Zn/ (Zn+In) ]が 0. 10より小さぐ亜鉛の含有率が少ないと、結晶化し やすくなり、適正な製造条件を選定しないと大面積上に均一な非晶質の膜が得られ ないおそれがある。  If the atomic ratio [Zn / (Zn + In)] is less than 0.10, the content of zinc is small, and crystallization is likely to occur. If appropriate manufacturing conditions are not selected, a uniform amorphous film over a large area is obtained. May not be obtained.
一方、原子比 [X/ (X+In) ]が 0. 82より大きくなり、亜鉛の含有率が過剰になると 、耐薬品性が低下したり、酸化亜鉛の結晶が生成して膜質が不均一となったりするお それがある。  On the other hand, if the atomic ratio [X / (X + In)] is greater than 0.82 and the zinc content is excessive, the chemical resistance is reduced, or crystals of zinc oxide are formed and the film quality is uneven. There is a possibility of becoming.
本実施形態において、上記のような不具合をより有効に回避するためには、原子比 [X/ (X + In) ] ¾0. 51〜0. 80であるのカ好ましく ίま、より好ましく ίま 0. 55〜0. 80 であり、 0. 6〜0. 75カ特に好ましレ、0 In this embodiment, in order to more effectively avoid the above-described problems, the atomic ratio [X / (X + In)] ¾0.5.51 to 0.80 is preferable, and more preferably ί. 0.5 to 0.80, 0.6 to 0.75, especially preferred, 0
[0038] また、透明半導体薄膜 40は、波長 550nmの透過率が 75%以上であるのが好まし レ、。波長 550nmの透過率が 75%より小さいと、半導体薄膜が画素電極部にはみ出 た場合に透過率を低下させ、輝度が低下したり、色調が変化したりするおそれがある 。このような不具合をより有効に回避するためには、波長 550nmの透過率は 80%以 上が好ましぐ 85%以上が特に好ましい。  [0038] The transparent semiconductor thin film 40 preferably has a transmittance of 75% or more at a wavelength of 550 nm. If the transmittance at a wavelength of 550 nm is less than 75%, when the semiconductor thin film protrudes from the pixel electrode portion, the transmittance may be lowered, and the luminance may be lowered or the color tone may be changed. In order to avoid such problems more effectively, the transmittance at a wavelength of 550 nm is preferably 80% or more, more preferably 85% or more.
[0039] また、透明半導体薄膜 40は、仕事関数が 3. 5〜6. 5eVであるのが好ましい。仕事 関数が 3. 5eVより小さいと、ゲート絶縁膜との界面で電価の注入などが生じて漏れ 電流が発生するなど、トランジスタ特性が低下するおそれがある。一方、 6. 5eVより 大きいと、ゲート絶縁膜との界面でエネルギー障壁などが発生し pinch_off特性が 悪化するなどトランジスタ特性が低下するおそれがある。このような不具合をより有効 に回避するためには、仕事関数は、 3. 8〜6. 2eVが好まし 4. 0〜6. OeVがより 好ましく、 4. 3〜5. 7eVカさらに好ましく、 4. 5〜5. 5eVカ特に好ましレ、。 [0039] The transparent semiconductor thin film 40 preferably has a work function of 3.5 to 6.5 eV. If the work function is less than 3.5 eV, leakage will occur due to charge injection at the interface with the gate insulating film. There is a possibility that transistor characteristics may be deteriorated, such as generation of current. On the other hand, if the voltage is higher than 6.5 eV, an energy barrier may be generated at the interface with the gate insulating film, and the pinch_off characteristics may be deteriorated, which may deteriorate the transistor characteristics. In order to avoid such defects more effectively, the work function is preferably 3.8 to 6.2 eV, 4.0 to 6. OeV is more preferable, and 4.3 to 5.7 eV is more preferable. 4. 5 ~ 5.5eV especially preferred.
[0040] また、透明半導体薄膜 40は、非縮退半導体薄膜であるのが好まし 縮退半導体 であるとキャリア濃度を低濃度で安定定期に制御できないおそれがある。  [0040] Further, the transparent semiconductor thin film 40 is preferably a non-degenerate semiconductor thin film. If it is a degenerate semiconductor, the carrier concentration may not be controlled stably at a low concentration.
ここで、非縮退半導体薄膜とは、キャリア濃度が温度に依存して変化する半導体薄 膜であり、これに対して、縮退半導体薄膜とは、キャリア濃度が温度に依存せずに一 定の値を示す半導体薄膜のことをいう。このキャリア濃度の温度依存性は、ホール測 定から求めることができる。  Here, the non-degenerate semiconductor thin film is a semiconductor thin film in which the carrier concentration changes depending on the temperature, whereas the degenerate semiconductor thin film is a constant value in which the carrier concentration does not depend on the temperature. It refers to a semiconductor thin film showing. The temperature dependence of this carrier concentration can be obtained from Hall measurements.
[0041] また、透明半導体薄膜 40は、非晶質膜にナノクリスタルが分散しているのが好まし レ、。非晶質膜中にナノクリスタルが分散していると、ホール移動度が向上し、電界効 果移動度が高くなりトランジスタ特性が向上する場合があり好ましい。ナノクリスタルの 存在は TEMで観察することで確認することができる。  [0041] The transparent semiconductor thin film 40 preferably has nanocrystals dispersed in an amorphous film. It is preferable that nanocrystals are dispersed in an amorphous film because hole mobility is improved, field effect mobility is increased, and transistor characteristics are improved. The presence of nanocrystals can be confirmed by observing with TEM.
[0042] ここで、透明半導体薄膜 40には、本実施形態の効果を損なわない範囲で酸化イン ジゥム、酸化亜鉛以外の第三の金属元素や、その化合物が含まれていてもよい。 ただし、この場合には、インジウム [In]と第三金属元素 [M]の原子比 [M/ (M + I n) ]を 0〜0. 5とする。原子比 [M/ (M + In) ]が 0. 5を超えると、ホール移動度が低 下するおそれがある。これは、主元素間の結合数が減り、バーコレーシヨン伝導が困 難になるためと推定される。  Here, the transparent semiconductor thin film 40 may contain a third metal element other than indium oxide and zinc oxide, or a compound thereof as long as the effects of the present embodiment are not impaired. However, in this case, the atomic ratio [M / (M + In)] between indium [In] and the third metal element [M] is set to 0 to 0.5. If the atomic ratio [M / (M + In)] exceeds 0.5, the hole mobility may decrease. This is presumed to be because the number of bonds between the main elements decreases and the bar-colation conduction becomes difficult.
このような不具合をより有効に回避するためには、原子比 [M/ (M + In) ]は、 0〜 0. 3であるのが好ましい。  In order to avoid such a problem more effectively, the atomic ratio [M / (M + In)] is preferably 0 to 0.3.
[0043] また、透明半導体薄膜 40は、 X線散乱測定より求められる動径分布関数 (RDF)に おける、原子間距離が 0. 3〜0. 36nmの間の RDFの最大値を A、原子間距離が 0. 36〜0. 42nmの間の RDFの最大値を Bとしたときに、 A/B >0. 8の関係を満たす のが好ましい。  [0043] Further, the transparent semiconductor thin film 40 has a maximum RDF value between A and A of 0.3 to 0.36 nm in the radial distribution function (RDF) obtained from X-ray scattering measurement. It is preferable that the relationship of A / B> 0.8 is satisfied, where B is the maximum value of RDF between the distances of 0.36 and 0.42 nm.
この比率 (A/B)は、インジウム 酸素 インジウムの結合形態が、陵共有と頂点 共有をなすものの比率、あるいは短距離秩序の維持比率を表しているものと推定さ れ、この比率 (A/B)が 0. 8以下だとホール移動度や電界効果移動度が低下する おそれがある。 This ratio (A / B) indicates that the bonding form of indium, oxygen, and indium is It is presumed that it represents the ratio of those that share, or the maintenance ratio of short-range order, and if this ratio (A / B) is 0.8 or less, the hole mobility and field-effect mobility may decrease. is there.
このような不具合をより有効に回避するためには、比率 (A/B)は、 AZB > 0. 9を 満たしているのがより好ましぐさらに好ましくは AZB > 1. 0であり、 A/B > 1. 1を 満たすものが最も好ましぐ比率 (A/B)が大きいことは、短い距離のインジウム—ィ ンジゥムの短距離秩序が保たれていると推定される。このため、電子の移動経路が確 保されて、ホール移動度や電界効果移動度の向上が期待される。  In order to avoid such defects more effectively, it is more preferable that the ratio (A / B) satisfies AZB> 0.9, more preferably AZB> 1.0, and A / It is presumed that the short-range indium-indium short-range order is maintained because the ratio (A / B) that satisfies B> 1.1 is most favorable. Therefore, it is expected that the electron movement route will be secured and the hole mobility and field effect mobility will be improved.
[0044] 本実施形態において、透明半導体薄膜 40を形成する成膜方法としては、スプレー 法、ディップ法、 CVD法などの化学的成膜方法のほか、物理的成膜方法も利用する こと力 Sできる。キャリア密度の制御や、膜質の向上が容易であるとう観点から、物理的 成膜方法の方が好ましい。  In the present embodiment, as a film forming method for forming the transparent semiconductor thin film 40, in addition to a chemical film forming method such as a spray method, a dip method, and a CVD method, a physical film forming method is also used. it can. From the viewpoint of easy control of carrier density and improvement of film quality, the physical film formation method is preferred.
[0045] 物理的成膜方法としては、例えば、スパッタ法、真空蒸着法、イオンプレーティング 法、パルスレーザーディポジション法などを挙げることができる力 工業的には量産性 が高レ、スパッタ法が好ましレ、。  [0045] Examples of physical film formation methods include sputtering, vacuum deposition, ion plating, and pulsed laser deposition. Industrially, mass production is high, and sputtering is used. I like it.
スパッタ法としては、例えば、 DCスパッタ法、 RFスパッタ法、 ACスパッタ法、 ECR スパッタ法、対向ターゲットスパッタ法などが挙げられる。これらのなかでも、工業的に 量産性が高ぐまた、 RFスパッタ法よりもキャリア濃度を下げやすい DCスパッタ法ゃ 、 ACスパッタ法が好ましい。また、成膜による界面の劣化を抑えて、漏れ電流を抑制 したり、 οηη—off比などの透明半導体薄膜 40の特性を向上させたりするには、膜質 の制御がしゃすレ、ECRスパッタ法や、対向ターゲットスパッタ法が好ましレ、。  Examples of the sputtering method include a DC sputtering method, an RF sputtering method, an AC sputtering method, an ECR sputtering method, and a counter target sputtering method. Among these, the DC sputtering method and the AC sputtering method are preferable because they are industrially high in mass productivity and can easily lower the carrier concentration than the RF sputtering method. In addition, in order to suppress deterioration of the interface due to film formation, to suppress leakage current, and to improve the characteristics of the transparent semiconductor thin film 40 such as οηη-off ratio, the control of the film quality is effective, the ECR sputtering method, The opposed target sputtering method is preferred.
[0046] スパッタ法を用いる場合、酸化インジウムと酸化亜鉛とを含有する焼結ターゲットを 用いても、酸化インジウムを含有する焼結ターゲットと酸化亜鉛を含有する焼結ター ゲットを用いて共スパッタしてもよレ、。また、インジウムや亜鉛からなる金属ターゲット、 あるいは合金ターゲットを用いて酸素などのガスを導入しながら、反応性スパッタを行 なってもよレ、。  [0046] When the sputtering method is used, even if a sintered target containing indium oxide and zinc oxide is used, co-sputtering is performed using a sintered target containing indium oxide and a sintered target containing zinc oxide. Anyway. Alternatively, reactive sputtering may be performed while introducing a gas such as oxygen using a metal target made of indium or zinc, or an alloy target.
再現性、大面積での均一性から酸化インジウムと正二価元素の酸化物とを含有す る焼結ターゲットを用いることが好ましい。 [0047] スパッタ法を用いる場合、雰囲気ガス中に含まれる水 H〇の分圧力 10_dPa以下 In view of reproducibility and uniformity in a large area, it is preferable to use a sintered target containing indium oxide and an oxide of a positive divalent element. [0047] When using the sputtering method, the following partial pressures 10_ d Pa water H_〇 contained in the atmosphere gas
2  2
となるようにする。水 H〇の分圧力 10_3Paより大きいと、ホール移動度が低下する To be. Larger than the minute pressure 10_ 3 Pa water H_〇, hole mobility decreases
2  2
おそれがある。これは、水素がビックスバイト構造のインジウムあるいは酸素と結合し て酸素一インジウム結合の稜共有部分を頂点共有化するためと推定される。このよう な不具合をより有効に回避するためには、 H〇の分圧は、好ましくは 8 X 10_4Pa以 There is a fear. This is presumed to be because hydrogen binds to indium or oxygen in the bixbite structure to share the ridge-sharing part of the oxygen-indium bond. In order to avoid such problems more effectively, the partial pressure of HO is preferably 8 X 10 _4 Pa or higher.
2  2
下、より好ましくは 6 X 10_4Pa以下、さらに好ましくは 4 X 10_4Pa以下であり、 2 X 10 _4Pa以下が特に好ましい。 Below, more preferably 6 × 10 — 4 Pa or less, even more preferably 4 × 10 — 4 Pa or less, particularly preferably 2 × 10 — 4 Pa or less.
[0048] また、雰囲気ガス中の水素 H分圧は、通常 10_2Pa以下、 5 X 10_3Pa以下が好ま [0048] Further, the hydrogen H partial pressure in the atmospheric gas is usually preferably 10 _2 Pa or less and 5 X 10 _3 Pa or less.
2  2
しぐ 10_3Pa以下がより好ましぐ 5 X 10_4Pa以下がさらに好ましぐ 2 X 10_4Pa以 下が特に好ましい。雰囲気ガス中に Hが存在すると、キャリア濃度が増えるば力りで Sig 10 _3 Pa or less, more preferably tool 5 X 10 _4 Pa or less and more preferably tool 2 X 10 _4 Pa hereinafter are particularly preferred. If H is present in the atmosphere gas, the carrier concentration will increase with force.
2  2
なぐホール移動度が低下するおそれがある。  There is a risk that the hole mobility will decrease.
[0049] また、雰囲気ガス中の酸素 O分圧は、通常 40 X 10_3Pa以下とする。雰囲気ガス [0049] In addition, the partial pressure of oxygen O in the atmospheric gas is usually 40 X 10 _3 Pa or less. Atmospheric gas
2  2
中の酸素分圧が 40 X 10_3Paより大きいと、ホール移動度が低下したり、ホール移動 度やキャリア濃度が不安定となったりするおそれがある。これは成膜時に雰囲気ガス 中の酸素が多すぎると、結晶格子間に取り込まれる酸素が多くなり散乱の原因となつ たり、容易に膜中から離脱し不安定化したりするためと推定される。 If the oxygen partial pressure inside is higher than 40 X 10 _3 Pa, the hole mobility may decrease, or the hole mobility and carrier concentration may become unstable. This is presumably because too much oxygen in the atmosphere gas during film formation causes more oxygen to be taken in between the crystal lattices, causing scattering, and easily leaving the film and destabilizing it.
このような不具合をより有効に回避するためには、雰囲気ガス中の酸素分圧は、好 ましくは 15 X 10_3Pa以下、より好ましくは 7 X 10_3Pa以下であり、 1 X 10_3Pa以下 であるのが特に好ましい。 In order to avoid such problems more effectively, the oxygen partial pressure in the atmospheric gas is preferably 15 X 10_ 3 Pa or less, more preferably 7 X 10_ 3 Pa or less, and 1 X 10_ 3 Particularly preferred is Pa or lower.
[0050] また、到達真空度は、通常 10— 5Pa以下とする。到達真空度が、 10— 5Paより大きい と、水 H Oの分圧が高くなり、水 H Oの分圧を 10_3Pa以下とすることができなくなる[0050] In addition, the ultimate vacuum is less usual 10- 5 Pa. Ultimate vacuum, and greater than 10- 5 Pa, the partial pressure of water HO increases, not the partial pressure of water HO be a 10_ 3 Pa or less
2 2 twenty two
おそれがある。このような不具合をより有効に回避するためには、到達圧力は、好まし くは 5 X 10— 6Pa以下であり、 10— 6Pa以下であるのが特に好ましい。 There is a fear. To avoid such an inconvenience more effectively, the ultimate pressure is preferably rather is below 5 X 10- 6 Pa, particularly preferably not more than 10- 6 Pa.
[0051] なお、大面積をスパッタ法で成膜する場合、膜質の均一性を持たせるため、基板を 固定したフォルダ一は回転させる、マグネットを動力しエロージョン範囲を広げるなど の方法をとることが好ましい。 [0051] When a large area is formed by sputtering, in order to have a uniform film quality, it is possible to take a method such as rotating the folder with the substrate fixed, or driving a magnet to widen the erosion range. preferable.
[0052] このような成膜工程において、通常は、基板温度 200°C以下で物理成膜し、成膜 工程を終えた後に、酸化インジウムと酸化亜鉛とを含有する薄膜に対して、酸化処理 を施すことで、透明半導体薄膜 40中のキャリア濃度を制御することができる。 [0052] In such a film formation step, usually, physical film formation is performed at a substrate temperature of 200 ° C or lower, and after the film formation step is completed, an oxidation treatment is performed on the thin film containing indium oxide and zinc oxide. By applying the above, the carrier concentration in the transparent semiconductor thin film 40 can be controlled.
ここで、成膜時に基板温度が 200°Cより高いと、酸化処理してもキャリア濃度が下が らなかったり、樹脂製基板を用いた場合に変形や寸法変化を起こしたりするおそれが ある。このような不具合をより有効に回避するためには、基板温度は、好ましくは 180 °C以下、より好ましくは 150°C以下、さらに好ましくは 120°C以下であり、 90°C以下で あるのが特に好ましい。  Here, if the substrate temperature is higher than 200 ° C. during film formation, there is a possibility that the carrier concentration does not decrease even when the oxidation treatment is performed, and deformation or dimensional change may occur when a resin substrate is used. In order to avoid such problems more effectively, the substrate temperature is preferably 180 ° C or lower, more preferably 150 ° C or lower, further preferably 120 ° C or lower, and 90 ° C or lower. Is particularly preferred.
[0053] このような成膜工程を終えた後に、本実施形態では、酸化インジウムと酸化亜鉛と を含有する薄膜に対して、酸化処理を施すことで、透明半導体薄膜 40中のキャリア 濃度を制御することができる。  [0053] After the film formation step is completed, in the present embodiment, the carrier concentration in the transparent semiconductor thin film 40 is controlled by subjecting the thin film containing indium oxide and zinc oxide to an oxidation treatment. can do.
なお、成膜時に酸素などのガス成分の濃度を制御して、キャリア濃度を制御する方 法もある力 このような方法では、ホール移動度が低下するおそれがある。これは、キ ャリア制御のために導入したガス成分が、膜中に取り込まれ散乱因子となっているも のと推定される。  Note that there is also a method of controlling the carrier concentration by controlling the concentration of a gas component such as oxygen during film formation. In such a method, the hole mobility may be lowered. This is presumed that the gas component introduced for carrier control is taken into the film and becomes a scattering factor.
[0054] また、酸化処理としては、酸素存在下で、通常 80〜650°C、 0. 5〜： 12000分の条 件で熱処理する。  [0054] As the oxidation treatment, heat treatment is usually performed in the presence of oxygen under the conditions of 80 to 650 ° C, 0.5 to 12000 minutes.
熱処理の温度が 80°Cより低いと処理効果が発現しな力 たり、時間がかかりすぎた りするおそれがあり、 650°Cより高いと基板が変形するおそれがある。このような不具 合をより有効に回避するために、処理温度は、好ましくは 120〜500°C、より好ましく は 150〜450。C、さらに好ましくは 180〜350°Cであり、 200〜300。C力特に好まし レ、。  If the temperature of the heat treatment is lower than 80 ° C, the treatment effect may not be exerted or it may take too much time, and if it is higher than 650 ° C, the substrate may be deformed. In order to avoid such a failure more effectively, the processing temperature is preferably 120 to 500 ° C, more preferably 150 to 450. C, more preferably 180-350 ° C, 200-300. C power is particularly preferred.
また、熱処理の時間が 0. 5分より短いと内部まで電熱する時間が不足し処理が不 十分となるおそれがあり、 12000分より長いと処理装置が大きくなり工業的に使用で きなかったり、処理中に基板が破損 *変形したりするおそれがある。このような不具合 をより有効に回避するために、処理時間は、好ましくは:!〜 600分、より好ましくは 5〜 360分、さらに好ましくは 15〜240分であり、 30〜： 120分力特に好ましレヽ。  Also, if the heat treatment time is shorter than 0.5 minutes, there is a risk that the time for electric heating to the inside will be insufficient and the treatment may be insufficient, and if it is longer than 12000 minutes, the treatment equipment will become large and cannot be used industrially. The substrate may be damaged during processing. In order to avoid such troubles more effectively, the processing time is preferably :! to 600 minutes, more preferably 5 to 360 minutes, still more preferably 15 to 240 minutes, and especially 30 to 120 minutes. I like it.
[0055] また、酸化処理としては、酸素存在下、ランプアニール装置（LA; Lamp Anne ale r)、急速熱ァニール装置（RTA;Rapid Thermal Annealer)、又はレーザーァニ ール装置により熱処理することができ、酸化処理としてオゾン処理を適用することもで きる。 [0055] Further, as the oxidation treatment, heat treatment can be performed with a lamp annealing device (LA), a rapid thermal annealing device (RTA), or a laser annealing device in the presence of oxygen. Ozone treatment can be applied as an oxidation treatment. wear.
実施例  Example
[0056] 以下、具体的な実施例を挙げて、本発明をより詳細に説明する。  [0056] Hereinafter, the present invention will be described in more detail with reference to specific examples.
[0057] [実施例 1] [0057] [Example 1]
(1)スパッタリングターゲットの製造、及び評価  (1) Production and evaluation of sputtering target
1.ターゲットの製造  1. Target manufacturing
原料として、平均粒径が 3. 4 μ ΐηの酸化インジウムと、平均粒径が 0. 6 /i mの酸ィ匕 亜鉛とを、原子比〔In/ (In+Zn)〕が 0· 28、原子比〔Ζη/ (Ιη + Ζη)〕が 0. 72となる ように混合して、これを湿式ボールミルに供給し、 72時間混合粉砕して原料微粉末を 得た。  As a raw material, indium oxide having an average particle size of 3.4 μΐη and acid / zinc having an average particle size of 0.6 / im has an atomic ratio [In / (In + Zn)] of 0.28, The mixture was mixed so that the atomic ratio [Ζη / (Ιη + Ζη)] was 0.72, then supplied to a wet ball mill, and mixed and ground for 72 hours to obtain a raw material fine powder.
得られた原料微粉末を造粒した後、直径 10cm、厚さ 5mmの寸法にプレス成形し て、これを焼成炉に入れ、酸素ガス加圧下において、 1 , 400°C, 48時間の条件で焼 成して、焼結体 (ターゲット）を得た。このとき、昇温速度は、 3°CZ分であった。  After granulating the obtained raw material fine powder, it is press-molded to a size of 10cm in diameter and 5mm in thickness, and this is put into a firing furnace, under the conditions of 1, 400 ° C and 48 hours under pressure of oxygen gas. Firing was performed to obtain a sintered body (target). At this time, the heating rate was 3 ° CZ.
2.ターゲットの評価  2. Target evaluation
得られたターゲットにっき、密度、バルタ抵抗値を測定した。その結果、理論相対密 度は 99%であり、四探針法により測定したバルタ抵抗値は、 0. 8m Ωであった。  The density and Balta resistance value were measured on the obtained target. As a result, the theoretical relative density was 99%, and the Balta resistance value measured by the four-point probe method was 0.8 mΩ.
[0058] (2)透明半導体薄膜の成膜 [0058] (2) Formation of transparent semiconductor thin film
上記（1)で得られたスパッタリングターゲットを、 DCスパッタ法の一つである DCマグ ネトロンスパッタリング法の成膜装置に装着し、ガラス基板（コーユング 1737)上に透 明導電膜を成膜した。  The sputtering target obtained in the above (1) was mounted on a DC magnetron sputtering film forming apparatus, which is one of the DC sputtering methods, and a transparent conductive film was formed on a glass substrate (Couting 1737).
ここでのスパッタ条件としては、基板温度； 25°C、到達圧力； 1 X 10_3Pa、雰囲気ガ ス； Arl00%、スパッタ圧力（全圧）；4 X 10_1Pa、投入電力 100W、成膜時間 20分 間とした。 Sputtering conditions here are as follows: substrate temperature: 25 ° C, ultimate pressure: 1 X 10 _3 Pa, atmosphere gas: Arl00%, sputtering pressure (total pressure): 4 X 10 _1 Pa, input power 100 W, film formation The time was 20 minutes.
この結果、ガラス基板上に、膜厚が約 lOOnmの透明導電性酸化物が形成された 透明導電ガラスが得られた。  As a result, a transparent conductive glass in which a transparent conductive oxide having a film thickness of about lOOnm was formed on the glass substrate was obtained.
なお、得られた膜組成を ICP法で分析したところ、原子比〔In/ (In + Zn)〕が 0. 28 、原子比〔Zn/ (In+Zn)〕が 0· 72であった。  When the obtained film composition was analyzed by ICP method, the atomic ratio [In / (In + Zn)] was 0.28 and the atomic ratio [Zn / (In + Zn)] was 0.72.
[0059] (3)透明半導体薄膜の酸化処理 上記（2)で得られた透明半導体薄膜を大気中（酸素存在下） 150°Cで、 100時間 加熱（大気下熱処理)することで酸化処理を行なった。 [0059] (3) Oxidation treatment of transparent semiconductor thin film The transparent semiconductor thin film obtained in (2) above was subjected to an oxidation treatment by heating (atmospheric heat treatment) at 150 ° C. for 100 hours in the air (in the presence of oxygen).
[0060] (4)透明半導体薄膜の物性の評価 [0060] (4) Evaluation of physical properties of transparent semiconductor thin film
上記（3)で得られた透明半導体薄膜のキャリア濃度、及びホール移動度をホール 測定装置により測定した。キャリア濃度は 2 X 1015cm_3、ホール移動度 16cm2/Vs であった。また、四端子法により測定した比抵抗値は、 200 Ω cmであった。 The carrier concentration and hole mobility of the transparent semiconductor thin film obtained in (3) above were measured with a hole measuring device. The carrier concentration was 2 × 10 15 cm _3 and the hole mobility was 16 cm 2 / Vs. The specific resistance value measured by the four probe method was 200 Ωcm.
なお、 X線回折で非晶質膜であることを確認した。  X-ray diffraction confirmed that the film was an amorphous film.
[0061] ホール測定装置、及びその測定条件は下記のとおりであった。 [0061] The Hall measurement device and the measurement conditions were as follows.
[ホール測定装置]  [Hall measuring device]
東陽テク二力製： Resi Test8310  Made by Toyo Tech Niki: Resi Test8310
[測定条件]  [Measurement condition]
室温（25°C)、 0. 5 [T]、 AC磁場ホール測定  Room temperature (25 ° C), 0.5 [T], AC magnetic field Hall measurement
[0062] さらに、この透明導電性酸化物の透明性については、分光光度計により波長 550η mの光線についての光線透過率が 85%であり、透明性においても優れたものであつ た。また、エネルギーバンドギャップは 3. 3eVと十分に大きかった。 [0062] Further, regarding the transparency of this transparent conductive oxide, the light transmittance for a light beam having a wavelength of 550 ηm was 85% by a spectrophotometer, and the transparency was also excellent. The energy band gap was 3.3 eV, which was sufficiently large.
[0063] [実施例 2〜7、比較例：!〜 4] [0063] [Examples 2 to 7, comparative examples:! To 4]
原料の組成比、成膜条件、酸化処理条件を表 1のように調整した以外は、実施例 1 と同様に作製評価した。  The production was evaluated in the same manner as in Example 1 except that the composition ratio of the raw materials, the film forming conditions, and the oxidation treatment conditions were adjusted as shown in Table 1.
[0064] [表 1] [0064] [Table 1]
Figure imgf000018_0001
Figure imgf000018_0001
[0065] また、実施例、及び比較例の半導体薄膜について、以下のように薄膜トランジスタ を製造して、その評価を行った。 [0065] Further, for the semiconductor thin films of Examples and Comparative Examples, thin film transistors were manufactured and evaluated as follows.
[0066] [トップゲート型透明薄膜トランジスタ] [0066] [Top gate type transparent thin film transistor]
PET基板上に、成膜時間以外は、前記実施例:!〜 7，比較例:!〜 4と同じ条件で作 成した 30nmの透明半導体薄膜を用レ、、図 1のような構成で、チヤネノレ長さ L= 10 μ m、チヤネノレ幅 W= 150 μ mのトップゲート型の薄膜トランジスタを構成した。  On the PET substrate, except for the film formation time, a transparent semiconductor thin film of 30 nm prepared under the same conditions as in the above examples:! To 7 and comparative examples:! To 4 was used. A top gate type thin film transistor having a channel length L = 10 μm and a channel width W = 150 μm was constructed.
このとき、ゲート絶縁膜として、誘電率の高い酸化イットリウムを厚み 170nmに積層 して用いた。また、ゲート電極、ソース電極、ドレイン電極の各電極として厚み 150nm の IZ〇を用いた。  At this time, yttrium oxide having a high dielectric constant was used as a gate insulating film with a thickness of 170 nm. In addition, IZO with a thickness of 150 nm was used as the gate electrode, the source electrode, and the drain electrode.
[0067] 得られた薄膜トランジスタについて、以下の基準で評価した。その結果を on— off 比とともに、表 1に併せて示す。  [0067] The obtained thin film transistor was evaluated according to the following criteria. The results are shown in Table 1 together with the on-off ratio.
[評価基準]  [Evaluation criteria]
良好： 10回以上動作を繰り返しても I—V特性のヒステリシスが小さい。  Good: Hysteresis of I–V characteristics is small even after 10 or more operations.
やや良好： 10回以上動作を繰り返すと I V特性に大きなヒステリシスが発生する。 不良： 10回未満の動作の繰り返しで I V特性に大きなヒステリシスが発生する。  Slightly good: Large hysteresis occurs in the IV characteristics when the operation is repeated 10 times or more. Defect: Large hysteresis occurs in the IV characteristics when the operation is repeated less than 10 times.
[0068] 以上、本発明について、好ましい実施形態を示して説明したが、本発明は、前述し た実施形態にのみ限定されるものではなぐ本発明の範囲で種々の変更実施が可能 であることはいうまでもない。  Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention. Needless to say.
[0069] 例えば、前述した実施形態では、薄膜トランジスタの例を挙げたが、本発明に係る 半導体薄膜は、種々の電界効果型トランジスタに適用することができる。  [0069] For example, in the above-described embodiment, an example of a thin film transistor has been described. However, the semiconductor thin film according to the present invention can be applied to various field effect transistors.
産業上の利用可能性  Industrial applicability
[0070] 本発明における半導体薄膜は、薄膜トランジスタなどの電界効果型トランジスタに 用いる半導体薄膜として広く利用することができる。 [0070] The semiconductor thin film in the present invention can be widely used as a semiconductor thin film used for a field effect transistor such as a thin film transistor.

Claims

請求の範囲  The scope of the claims
[I] 酸化亜鉛と酸化インジウムを含有する非晶質膜力 なる半導体薄膜であって、 キャリア密度が 10+ 17cm_3以下、ホール移動度が 2cm2/V' sec以上、エネルギー バンドギャップが 2. 4eV以上であることを特徴とする半導体薄膜。 [I] A semiconductor thin film made of amorphous film strength containing zinc oxide and indium oxide, the carrier density 10 + 17 cm_ 3 below, the hole mobility of 2 cm 2 / V 'sec or more, the energy band gap 2 . A semiconductor thin film characterized by 4 eV or more.
[2] 前記非晶質膜中の亜鉛 [Zn]とインジウム [In]の原子比力 Zn/ (Zn+ In) = 0. 1[2] Atomic specific force of zinc [Zn] and indium [In] in the amorphous film Zn / (Zn + In) = 0.1
0〜0. 82であることを特徴とする請求項 1に記載の半導体薄膜。 2. The semiconductor thin film according to claim 1, wherein the semiconductor thin film is 0 to 0.82.
[3] 前記非晶質膜中の亜鉛 Znとインジウム Inの原子比力 Zn/ (Zn+ In) = 0. 51〜[3] Atomic specific force between zinc Zn and indium In in the amorphous film Zn / (Zn + In) = 0.51〜
0. 80であることを特徴とする請求項 1に記載の半導体薄膜。 2. The semiconductor thin film according to claim 1, wherein the thickness is 0.80.
[4] 波長 550nmの透過率が 75%以上であることを特徴とする請求項 1〜3のいずれか [4] The transmittance according to any one of claims 1 to 3, wherein the transmittance at a wavelength of 550 nm is 75% or more
1項に記載の半導体薄膜。  The semiconductor thin film of item 1.
[5] 仕事関数が 3. 5〜6. 5eVの非縮退半導体薄膜であることを特徴とする請求項 1〜 [5] The non-degenerate semiconductor thin film having a work function of 3.5 to 6.5 eV.
4のいずれか 1項に記載の半導体薄膜。  5. The semiconductor thin film according to any one of 4.
[6] 非晶質膜にナノクリスタルが分散していることを特徴とする請求項 1〜5のいずれか 6. The nanocrystal is dispersed in the amorphous film, according to any one of claims 1 to 5,
1項に記載の半導体薄膜。  The semiconductor thin film of item 1.
[7] 第三の金属元素 [M]を含有し、前記第三の金属元素 [M]とインジウム [In]の原子 比 [MZ (M + In) ]が、 0〜0. 5であることを特徴とする請求項 1〜6のいずれ力 1項 に記載の半導体薄膜。 [7] It contains a third metal element [M], and the atomic ratio [MZ (M + In)] of the third metal element [M] and indium [In] is 0 to 0.5. The semiconductor thin film according to any one of claims 1 to 6, wherein:
[8] 第三の金属元素 [M]を含有し、前記第三の金属元素 [M]とインジウム [In]の原子 比 [MZ (M + In) ]が、 0〜0. 3であることを特徴とする請求項 1〜6のいずれ力 1項 に記載の透明酸化物半導体薄膜。  [8] It contains a third metal element [M], and the atomic ratio [MZ (M + In)] of the third metal element [M] and indium [In] is 0 to 0.3. The transparent oxide semiconductor thin film according to any one of claims 1 to 6, wherein:
[9] X線散乱測定より求められる動径分布関数 (RDF)における、原子間距離が 0. 3〜 [9] In the radial distribution function (RDF) obtained from X-ray scattering measurement, the interatomic distance is 0.3 ~
0. 36nmの間の RDFの最大値を A、原子間距離が 0. 36〜0. 42nmの間の RDF の最大値を Bとしたときに、 A/B > 0. 8の関係を満たすことを特徴とする請求項:!〜 8のいずれか 1項に記載の半導体薄膜。 When the maximum value of RDF between 36 nm is A and the maximum value of RDF between 0.36 and 0.42 nm is B, the relationship of A / B> 0.8 is satisfied. The semiconductor thin film according to any one of claims 8 to 8, wherein:
[10] 請求項：!〜 9のいずれか 1項に記載の半導体薄膜を製造するにあたり、  [10] Claim: In manufacturing the semiconductor thin film according to any one of! To 9,
雰囲気ガス中の水 H〇の分圧が 10_3Pa以下となる条件で、酸化亜鉛と酸化インジ Under conditions where the partial pressure of water HO in the atmospheric gas is 10 _3 Pa or less, zinc oxide and
2  2
ゥムを含有する非晶質膜を成膜することを特徴とする半導体薄膜の製造方法。  A method for producing a semiconductor thin film, comprising forming an amorphous film containing sulfur.
[I I] 基板温度 200°C以下で物理成膜した前記非晶質膜を酸化処理する工程を含むこ とを特徴とする請求項 10に記載の半導体薄膜の製造方法。 [II] including a step of oxidizing the amorphous film physically formed at a substrate temperature of 200 ° C. or lower. The method for producing a semiconductor thin film according to claim 10.
[12] 請求項:!〜 9のいずれか 1項に記載の半導体薄膜を有することを特徴とする薄膜ト ランジスタ。 [12] Claim: A thin film transistor comprising the semiconductor thin film according to any one of! To 9.
[13] 前記半導体薄膜が、樹脂基板上に設けられていることを特徴とする請求項 12に記 載の薄膜トランジスタ。  13. The thin film transistor according to claim 12, wherein the semiconductor thin film is provided on a resin substrate.
[14] 請求項 12又は 13のいずれ力 4項に記載の薄膜トランジスタを有することを特徴とす るアクティブマトリックス駆動表示パネル。  [14] An active matrix drive display panel comprising the thin film transistor according to any one of [12] or [13].
PCT/JP2006/322808 2005-11-18 2006-11-16 Semiconductor thin film, method for producing same, thin film transistor and active-matrix-driven display panel WO2007058231A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/094,228 US7998372B2 (en) 2005-11-18 2006-11-16 Semiconductor thin film, method for manufacturing the same, thin film transistor, and active-matrix-driven display panel
CN2006800429985A CN101309863B (en) 2005-11-18 2006-11-16 Semiconductor thin film, method for manufacturing the same, thin film transistor, and active matrix display panel
KR1020087011741A KR101291977B1 (en) 2005-11-18 2006-11-16 Semiconductor thin film, method for producing same, thin film transistor and active-matrix-driven display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005334501A JP5376750B2 (en) 2005-11-18 2005-11-18 Semiconductor thin film, manufacturing method thereof, thin film transistor, active matrix drive display panel
JP2005-334501 2005-11-18

Publications (1)

Publication Number Publication Date
WO2007058231A1 true WO2007058231A1 (en) 2007-05-24

Family

ID=38048615

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2006/322808 WO2007058231A1 (en) 2005-11-18 2006-11-16 Semiconductor thin film, method for producing same, thin film transistor and active-matrix-driven display panel

Country Status (5)

Country Link
JP (1) JP5376750B2 (en)
KR (1) KR101291977B1 (en)
CN (1) CN101309863B (en)
TW (1) TWI412135B (en)
WO (1) WO2007058231A1 (en)

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008300518A (en) * 2007-05-30 2008-12-11 Canon Inc Amorphous oxide, and field effect transistor
GB2457872A (en) * 2008-02-13 2009-09-02 Univ Ind & Acad Collaboration Thin-film transistor using nano-crystalline thin-film as active layer, and method for fabricating the same
US7998372B2 (en) 2005-11-18 2011-08-16 Idemitsu Kosan Co., Ltd. Semiconductor thin film, method for manufacturing the same, thin film transistor, and active-matrix-driven display panel
JP2012003832A (en) * 2010-05-20 2012-01-05 Semiconductor Energy Lab Co Ltd Driving method of semiconductor device
CN103258857A (en) * 2007-12-13 2013-08-21 出光兴产株式会社 Field-effect transistor using oxide semiconductor and method for manufacturing same
US8552425B2 (en) 2010-06-18 2013-10-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8570070B2 (en) 2009-10-30 2013-10-29 Semiconductor Energy Laboratory Co., Ltd. Logic circuit and semiconductor device
US8637863B2 (en) 2009-12-04 2014-01-28 Semiconductor Energy Laboratory Co., Ltd. Display device
US8643018B2 (en) 2009-07-18 2014-02-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising a pixel portion and a driver circuit
US8669556B2 (en) 2010-12-03 2014-03-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8742544B2 (en) 2009-11-13 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8841163B2 (en) 2009-12-04 2014-09-23 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device comprising oxide semiconductor
US8980685B2 (en) 2008-10-24 2015-03-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing thin film transistor using multi-tone mask
US8999751B2 (en) 2009-10-09 2015-04-07 Semiconductor Energy Laboratory Co., Ltd. Method for making oxide semiconductor device
KR101520024B1 (en) 2009-11-28 2015-05-14 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and method for manufacturing the same
US9082857B2 (en) 2008-09-01 2015-07-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising an oxide semiconductor layer
US9093544B2 (en) 2009-11-06 2015-07-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US9130067B2 (en) 2008-10-08 2015-09-08 Semiconductor Energy Laboratory Co., Ltd. Display device
US9129997B2 (en) 2010-12-28 2015-09-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9136389B2 (en) 2008-10-24 2015-09-15 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor, thin film transistor, and display device
US9153650B2 (en) 2013-03-19 2015-10-06 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor
US9214563B2 (en) 2009-09-24 2015-12-15 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film and semiconductor device
US9287352B2 (en) 2013-06-19 2016-03-15 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film and formation method thereof
US9306072B2 (en) 2009-10-08 2016-04-05 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor layer and semiconductor device
US9331156B2 (en) 2011-12-15 2016-05-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9366896B2 (en) 2012-10-12 2016-06-14 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and touch panel
US9406808B2 (en) 2009-10-08 2016-08-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device, and electronic appliance
US9553200B2 (en) 2012-02-29 2017-01-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9576795B2 (en) 2009-06-30 2017-02-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9583632B2 (en) 2013-07-19 2017-02-28 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film, method for forming oxide semiconductor film, and semiconductor device
US9806201B2 (en) 2014-03-07 2017-10-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9831274B2 (en) 2012-11-08 2017-11-28 Semiconductor Energy Laboratory Co., Ltd. Metal oxide film and method for forming metal oxide film
US9911858B2 (en) 2010-12-28 2018-03-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9935202B2 (en) 2009-09-16 2018-04-03 Semiconductor Energy Laboratory Co., Ltd. Transistor and display device comprising oxide semiconductor layer
US11183597B2 (en) 2009-09-16 2021-11-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof

Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5215589B2 (en) 2007-05-11 2013-06-19 キヤノン株式会社 Insulated gate transistor and display device
JP5242083B2 (en) * 2007-06-13 2013-07-24 出光興産株式会社 Crystalline oxide semiconductor and thin film transistor using the same
JP5354999B2 (en) * 2007-09-26 2013-11-27 キヤノン株式会社 Method for manufacturing field effect transistor
US8461583B2 (en) 2007-12-25 2013-06-11 Idemitsu Kosan Co., Ltd. Oxide semiconductor field effect transistor and method for manufacturing the same
JP5219529B2 (en) * 2008-01-23 2013-06-26 キヤノン株式会社 Field effect transistor and display device including the field effect transistor
KR100918404B1 (en) * 2008-03-03 2009-09-24 삼성모바일디스플레이주식회사 Organic thin film transistor and a flat panel display employing the same
US8017045B2 (en) 2008-04-16 2011-09-13 Electronics And Telecommunications Research Institute Composition for oxide semiconductor thin film and field effect transistor using the composition
JP5510767B2 (en) * 2008-06-19 2014-06-04 出光興産株式会社 Thin film transistor and manufacturing method thereof
JP5322530B2 (en) * 2008-08-01 2013-10-23 富士フイルム株式会社 Thin film field effect transistor manufacturing method and thin film field effect transistor manufactured by the manufacturing method
JP5480554B2 (en) * 2008-08-08 2014-04-23 株式会社半導体エネルギー研究所 Semiconductor device
CN103985718B (en) 2008-09-19 2019-03-22 株式会社半导体能源研究所 Display device
JPWO2010032422A1 (en) 2008-09-19 2012-02-02 出光興産株式会社 Oxide sintered body and sputtering target
KR20210135349A (en) 2008-10-03 2021-11-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Electronic appliance
US8741702B2 (en) * 2008-10-24 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
KR20130138352A (en) * 2008-11-07 2013-12-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
TWI656645B (en) * 2008-11-13 2019-04-11 日商半導體能源研究所股份有限公司 Semiconductor device and method of manufacturing same
TWI585955B (en) * 2008-11-28 2017-06-01 半導體能源研究所股份有限公司 Photosensor and display device
US8344387B2 (en) * 2008-11-28 2013-01-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP5515281B2 (en) * 2008-12-03 2014-06-11 ソニー株式会社 THIN FILM TRANSISTOR, DISPLAY DEVICE, ELECTRONIC DEVICE, AND METHOD FOR PRODUCING THIN FILM TRANSISTOR
EP2515337B1 (en) * 2008-12-24 2016-02-24 Semiconductor Energy Laboratory Co., Ltd. Driver circuit and semiconductor device
TWI654689B (en) 2008-12-26 2019-03-21 日商半導體能源研究所股份有限公司 Semiconductor device and method of manufacturing same
KR101017494B1 (en) * 2009-02-20 2011-02-25 연세대학교 산학협력단 InZnO THIN FILM AND FABRICATION METHOD THEREOF
US8704216B2 (en) 2009-02-27 2014-04-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
CN101834009B (en) * 2009-03-13 2013-05-01 中国科学院福建物质结构研究所 Low-indium doping amount zinc oxide transparent conducting film and preparation method thereof
US8378342B2 (en) 2009-03-23 2013-02-19 Samsung Electronics Co., Ltd. Oxide semiconductor and thin film transistor including the same
KR101681884B1 (en) 2009-03-27 2016-12-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device, display device, and electronic appliance
TWI489628B (en) * 2009-04-02 2015-06-21 Semiconductor Energy Lab Semiconductor device and method for manufacturing the same
KR101968855B1 (en) 2009-06-30 2019-04-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method for manufacturing semiconductor device
US8829513B2 (en) 2009-08-31 2014-09-09 Sharp Kabushiki Kaisha Oxide semiconductor including Ga, In, Zn, and O and A thin film transistor and a display with the oxide semiconductor including Ga, In, Zn, and O
KR101865546B1 (en) 2009-10-16 2018-06-11 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Liquid crystal display device and electronic device including the liquid crystal display device
WO2011046032A1 (en) * 2009-10-16 2011-04-21 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and electronic apparatus having the same
KR101893128B1 (en) * 2009-10-21 2018-08-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Analog circuit and semiconductor device
CN105702688B (en) * 2009-10-21 2020-09-08 株式会社半导体能源研究所 Liquid crystal display device and electronic apparatus including the same
CN102576172B (en) * 2009-10-30 2016-01-27 株式会社半导体能源研究所 Liquid crystal display, its driving method and comprise the electronic apparatus of this liquid crystal display
KR20230174763A (en) * 2009-11-13 2023-12-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Display device and electronic device including the same
KR101506304B1 (en) * 2009-11-27 2015-03-26 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and method for manufacturing the same
CN105739209B (en) 2009-11-30 2022-05-27 株式会社半导体能源研究所 Liquid crystal display device, method for driving the same
KR101840623B1 (en) * 2009-12-04 2018-03-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Display device and electronic device including the same
WO2011070901A1 (en) 2009-12-11 2011-06-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
KR20120101716A (en) 2009-12-24 2012-09-14 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Display device and electronic device
CN102714026B (en) 2010-01-24 2016-09-14 株式会社半导体能源研究所 Display device
US8947337B2 (en) * 2010-02-11 2015-02-03 Semiconductor Energy Laboratory Co., Ltd. Display device
CN102163691A (en) * 2010-02-22 2011-08-24 复旦大学 Mixed type oxide thin film transistor and preparation method thereof
WO2011108199A1 (en) * 2010-03-04 2011-09-09 シャープ株式会社 Method for manufacturing thin film transistor, thin film transistor manufactured by the method, and active matrix substrate
JP5491258B2 (en) * 2010-04-02 2014-05-14 出光興産株式会社 Method for forming oxide semiconductor
US9349325B2 (en) * 2010-04-28 2016-05-24 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and electronic device
JP5718072B2 (en) 2010-07-30 2015-05-13 三星ディスプレイ株式會社Ｓａｍｓｕｎｇ Ｄｉｓｐｌａｙ Ｃｏ．，Ｌｔｄ． Thin film transistor oxide for semiconductor layer and sputtering target, and thin film transistor
US8883555B2 (en) 2010-08-25 2014-11-11 Semiconductor Energy Laboratory Co., Ltd. Electronic device, manufacturing method of electronic device, and sputtering target
GB201021853D0 (en) 2010-12-23 2011-02-02 Element Six Ltd A microwave plasma reactor for manufacturing synthetic diamond material
GB201021870D0 (en) 2010-12-23 2011-02-02 Element Six Ltd A microwave plasma reactor for manufacturing synthetic diamond material
GB201021865D0 (en) 2010-12-23 2011-02-02 Element Six Ltd A microwave plasma reactor for manufacturing synthetic diamond material
GB201021855D0 (en) 2010-12-23 2011-02-02 Element Six Ltd Microwave power delivery system for plasma reactors
GB201021913D0 (en) 2010-12-23 2011-02-02 Element Six Ltd Microwave plasma reactors and substrates for synthetic diamond manufacture
GB2486778B (en) 2010-12-23 2013-10-23 Element Six Ltd Controlling doping of synthetic diamond material
GB201021860D0 (en) 2010-12-23 2011-02-02 Element Six Ltd A microwave plasma reactor for diamond synthesis
JP5189674B2 (en) * 2010-12-28 2013-04-24 出光興産株式会社 Laminated structure having oxide semiconductor thin film layer, method for producing laminated structure, thin film transistor, and display device
KR101891650B1 (en) 2011-09-22 2018-08-27 삼성디스플레이 주식회사 OXIDE SEMICONDUCTOR, THIN FILM TRANSISTOR INCLUDING THE SAME AND THIN FILM TRANSISTOR array PANEL INCLUDING THE SAME
KR20130049620A (en) 2011-11-04 2013-05-14 삼성디스플레이 주식회사 Display device
CN102509735B (en) * 2011-12-27 2013-10-02 武汉大学 Amorphous indium zinc oxide/indium oxide nanocrystalline homogeneous composite thin film transistor and preparation method thereof
KR20130111874A (en) 2012-04-02 2013-10-11 삼성디스플레이 주식회사 Thin film transistor, thin film transistor array panel and display device including the same, and manufacturing method of thin film transistor
US9553201B2 (en) 2012-04-02 2017-01-24 Samsung Display Co., Ltd. Thin film transistor, thin film transistor array panel, and manufacturing method of thin film transistor
KR20130129674A (en) 2012-05-21 2013-11-29 삼성디스플레이 주식회사 Thin film transistor and thin film transistor array panel including the same
JP5581416B2 (en) * 2013-04-03 2014-08-27 出光興産株式会社 Crystalline oxide semiconductor and thin film transistor using the same
JP6264090B2 (en) * 2013-07-31 2018-01-24 株式会社リコー FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING FIELD EFFECT TRANSISTOR
JP5678149B2 (en) * 2013-08-26 2015-02-25 出光興産株式会社 Semiconductor thin film, manufacturing method thereof, thin film transistor, active matrix drive display panel
KR102505695B1 (en) 2016-03-18 2023-03-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and system using the same
CN111302786B (en) * 2020-03-27 2022-06-21 宁波南海泰格尔陶瓷有限公司 Preparation method of transparent zinc oxide ceramic

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003016858A (en) * 2001-06-29 2003-01-17 Sanyo Electric Co Ltd Manufacturing method of indium tin oxide film
JP2003100152A (en) * 2001-09-20 2003-04-04 Teijin Ltd Transparent conductive laminate
JP2004273614A (en) * 2003-03-06 2004-09-30 Sharp Corp Semiconductor device and its fabricating process

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE60042431D1 (en) * 1999-11-25 2009-07-30 Idemitsu Kosan Co Tranparent conductive oxide
JP2002319682A (en) * 2002-01-04 2002-10-31 Japan Science & Technology Corp Transistor and semiconductor device
JP2003347400A (en) * 2002-05-30 2003-12-05 Asahi Kasei Corp Method of forming semiconductor pattern
US7067843B2 (en) * 2002-10-11 2006-06-27 E. I. Du Pont De Nemours And Company Transparent oxide semiconductor thin film transistors
JP2004235180A (en) * 2003-01-28 2004-08-19 Sanyo Electric Co Ltd Semiconductor device and its manufacturing method
EP1626416A4 (en) * 2003-05-20 2007-11-07 Idemitsu Kosan Co Amorphous transparent conductive film, sputtering target as its raw material, amorphous transparent electrode substrate, process for producing the same and color filter for liquid crystal display
US7145174B2 (en) * 2004-03-12 2006-12-05 Hewlett-Packard Development Company, Lp. Semiconductor device
EP2246894B2 (en) * 2004-03-12 2018-10-10 Japan Science and Technology Agency Method for fabricating a thin film transistor having an amorphous oxide as a channel layer
JP5126730B2 (en) * 2004-11-10 2013-01-23 キヤノン株式会社 Method for manufacturing field effect transistor
JP4981282B2 (en) * 2005-09-06 2012-07-18 キヤノン株式会社 Thin film transistor manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003016858A (en) * 2001-06-29 2003-01-17 Sanyo Electric Co Ltd Manufacturing method of indium tin oxide film
JP2003100152A (en) * 2001-09-20 2003-04-04 Teijin Ltd Transparent conductive laminate
JP2004273614A (en) * 2003-03-06 2004-09-30 Sharp Corp Semiconductor device and its fabricating process

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
TAKAGI A. ET AL.: "Carrier transport and electronic structure in amorphous oxide semiconductor, a InGaZnO4", THIN SOLID FILMS, vol. 486, no. 1-2, 22 August 2005 (2005-08-22), pages 38 - 41, XP004973608 *
TAYLOR H.P. ET AL.: "The electrical, optical and structural properties of InxZn1-xOy(0 x 1) thin films by combinatorial techniques", MEAS. SCI. TECHNOL., vol. 16, no. 1, January 2005 (2005-01-01), pages 90 - 94, XP020090375 *

Cited By (94)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7998372B2 (en) 2005-11-18 2011-08-16 Idemitsu Kosan Co., Ltd. Semiconductor thin film, method for manufacturing the same, thin film transistor, and active-matrix-driven display panel
JP2008300518A (en) * 2007-05-30 2008-12-11 Canon Inc Amorphous oxide, and field effect transistor
CN103258857A (en) * 2007-12-13 2013-08-21 出光兴产株式会社 Field-effect transistor using oxide semiconductor and method for manufacturing same
GB2457872A (en) * 2008-02-13 2009-09-02 Univ Ind & Acad Collaboration Thin-film transistor using nano-crystalline thin-film as active layer, and method for fabricating the same
US10128381B2 (en) 2008-09-01 2018-11-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with oxygen rich gate insulating layer
US9397194B2 (en) 2008-09-01 2016-07-19 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device with oxide semiconductor ohmic conatct layers
US9082857B2 (en) 2008-09-01 2015-07-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising an oxide semiconductor layer
US9703157B2 (en) 2008-10-08 2017-07-11 Semiconductor Energy Laboratory Co., Ltd. Display device
US9130067B2 (en) 2008-10-08 2015-09-08 Semiconductor Energy Laboratory Co., Ltd. Display device
US10254607B2 (en) 2008-10-08 2019-04-09 Semiconductor Energy Laboratory Co., Ltd. Display device
US9915843B2 (en) 2008-10-08 2018-03-13 Semiconductor Energy Laboratory Co., Ltd. Display device with pixel including capacitor
US9136389B2 (en) 2008-10-24 2015-09-15 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor, thin film transistor, and display device
US8980685B2 (en) 2008-10-24 2015-03-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing thin film transistor using multi-tone mask
US9576795B2 (en) 2009-06-30 2017-02-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9831101B2 (en) 2009-06-30 2017-11-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US10090171B2 (en) 2009-06-30 2018-10-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8643018B2 (en) 2009-07-18 2014-02-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising a pixel portion and a driver circuit
US11211499B2 (en) 2009-09-16 2021-12-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US9935202B2 (en) 2009-09-16 2018-04-03 Semiconductor Energy Laboratory Co., Ltd. Transistor and display device comprising oxide semiconductor layer
US11183597B2 (en) 2009-09-16 2021-11-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US11791417B2 (en) 2009-09-16 2023-10-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US9318617B2 (en) 2009-09-24 2016-04-19 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US9853167B2 (en) 2009-09-24 2017-12-26 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film and semiconductor device
US10418491B2 (en) 2009-09-24 2019-09-17 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film and semiconductor device
US9214563B2 (en) 2009-09-24 2015-12-15 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film and semiconductor device
US10115831B2 (en) 2009-10-08 2018-10-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having an oxide semiconductor layer comprising a nanocrystal
US9406808B2 (en) 2009-10-08 2016-08-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device, and electronic appliance
US9306072B2 (en) 2009-10-08 2016-04-05 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor layer and semiconductor device
US9941413B2 (en) 2009-10-09 2018-04-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having different types of thin film transistors
US9349791B2 (en) 2009-10-09 2016-05-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having oxide semiconductor channel
US9006728B2 (en) 2009-10-09 2015-04-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having oxide semiconductor transistor
US8999751B2 (en) 2009-10-09 2015-04-07 Semiconductor Energy Laboratory Co., Ltd. Method for making oxide semiconductor device
US8570070B2 (en) 2009-10-30 2013-10-29 Semiconductor Energy Laboratory Co., Ltd. Logic circuit and semiconductor device
US9722086B2 (en) 2009-10-30 2017-08-01 Semiconductor Energy Laboratory Co., Ltd. Logic circuit and semiconductor device
US10249647B2 (en) 2009-11-06 2019-04-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device comprising oxide semiconductor layer
US10868046B2 (en) 2009-11-06 2020-12-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device applying an oxide semiconductor
US9093544B2 (en) 2009-11-06 2015-07-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US11776968B2 (en) 2009-11-06 2023-10-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising oxide semiconductor layer
US11107840B2 (en) 2009-11-06 2021-08-31 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating a semiconductor device comprising an oxide semiconductor
US11107838B2 (en) 2009-11-06 2021-08-31 Semiconductor Energy Laboratory Co., Ltd. Transistor comprising an oxide semiconductor
US20210288079A1 (en) 2009-11-06 2021-09-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US11456385B2 (en) 2009-11-13 2022-09-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US10944010B2 (en) 2009-11-13 2021-03-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US11955557B2 (en) 2009-11-13 2024-04-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US10516055B2 (en) 2009-11-13 2019-12-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8742544B2 (en) 2009-11-13 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US9219162B2 (en) 2009-11-13 2015-12-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US10056494B2 (en) 2009-11-13 2018-08-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US9368640B2 (en) 2009-11-28 2016-06-14 Semiconductor Energy Laboratory Co., Ltd. Transistor with stacked oxide semiconductor films
KR101520024B1 (en) 2009-11-28 2015-05-14 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and method for manufacturing the same
US10714358B2 (en) 2009-12-04 2020-07-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US9411208B2 (en) 2009-12-04 2016-08-09 Semiconductor Energy Laboratory Co., Ltd. Display device
US11923204B2 (en) 2009-12-04 2024-03-05 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device comprising oxide semiconductor
US11456187B2 (en) 2009-12-04 2022-09-27 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor-device
US8637863B2 (en) 2009-12-04 2014-01-28 Semiconductor Energy Laboratory Co., Ltd. Display device
US9240467B2 (en) 2009-12-04 2016-01-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US9721811B2 (en) 2009-12-04 2017-08-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device having an oxide semiconductor layer
US10490420B2 (en) 2009-12-04 2019-11-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8841163B2 (en) 2009-12-04 2014-09-23 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device comprising oxide semiconductor
US8957414B2 (en) 2009-12-04 2015-02-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising both amorphous and crystalline semiconductor oxide
US10109500B2 (en) 2009-12-04 2018-10-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US9070596B2 (en) 2009-12-04 2015-06-30 Semiconductor Energy Laboratory Co., Ltd. Display device
JP2012003832A (en) * 2010-05-20 2012-01-05 Semiconductor Energy Lab Co Ltd Driving method of semiconductor device
US9685561B2 (en) 2010-06-18 2017-06-20 Semiconductor Energy Laboratories Co., Ltd. Method for manufacturing a semiconductor device
US9349820B2 (en) 2010-06-18 2016-05-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8552425B2 (en) 2010-06-18 2013-10-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9076876B2 (en) 2010-06-18 2015-07-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9331208B2 (en) 2010-12-03 2016-05-03 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film and semiconductor device
US8669556B2 (en) 2010-12-03 2014-03-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9711655B2 (en) 2010-12-03 2017-07-18 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film and semiconductor device
US10103277B2 (en) 2010-12-03 2018-10-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing oxide semiconductor film
US8680522B2 (en) 2010-12-03 2014-03-25 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film and semiconductor device
US8994021B2 (en) 2010-12-03 2015-03-31 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film and semiconductor device
US10916663B2 (en) 2010-12-03 2021-02-09 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film and semiconductor device
US9911858B2 (en) 2010-12-28 2018-03-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9129997B2 (en) 2010-12-28 2015-09-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US10153346B2 (en) 2011-12-15 2018-12-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9331156B2 (en) 2011-12-15 2016-05-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9553200B2 (en) 2012-02-29 2017-01-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9366896B2 (en) 2012-10-12 2016-06-14 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and touch panel
US10892282B2 (en) 2012-11-08 2021-01-12 Semiconductor Energy Laboratory Co., Ltd. Metal oxide film and method for forming metal oxide film
US10461099B2 (en) 2012-11-08 2019-10-29 Semiconductor Energy Laboratory Co., Ltd. Metal oxide film and method for forming metal oxide film
US11978742B2 (en) 2012-11-08 2024-05-07 Semiconductor Energy Laboratory Co., Ltd. Metal oxide film and method for forming metal oxide film
US9881939B2 (en) 2012-11-08 2018-01-30 Semiconductor Energy Laboratory Co., Ltd. Metal oxide film and method for forming metal oxide film
US9831274B2 (en) 2012-11-08 2017-11-28 Semiconductor Energy Laboratory Co., Ltd. Metal oxide film and method for forming metal oxide film
US9871058B2 (en) 2012-11-08 2018-01-16 Semiconductor Energy Laboratory Co., Ltd. Metal oxide film and method for forming metal oxide film
US11652110B2 (en) 2012-11-08 2023-05-16 Semiconductor Energy Laboratory Co., Ltd. Metal oxide film and method for forming metal oxide film
US9391146B2 (en) 2013-03-19 2016-07-12 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor
US9771272B2 (en) 2013-03-19 2017-09-26 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor
US9153650B2 (en) 2013-03-19 2015-10-06 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor
US9793414B2 (en) 2013-06-19 2017-10-17 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film
US9287352B2 (en) 2013-06-19 2016-03-15 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film and formation method thereof
US9583632B2 (en) 2013-07-19 2017-02-28 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor film, method for forming oxide semiconductor film, and semiconductor device
US9806201B2 (en) 2014-03-07 2017-10-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
TW200725907A (en) 2007-07-01
JP5376750B2 (en) 2013-12-25
CN101309863A (en) 2008-11-19
CN101309863B (en) 2011-12-28
JP2007142195A (en) 2007-06-07
TWI412135B (en) 2013-10-11
KR101291977B1 (en) 2013-08-09
KR20080069607A (en) 2008-07-28

Similar Documents

Publication Publication Date Title
JP5376750B2 (en) Semiconductor thin film, manufacturing method thereof, thin film transistor, active matrix drive display panel
TWI400806B (en) A semiconductor thin film, and a method for manufacturing the same, and a thin film transistor
US7998372B2 (en) Semiconductor thin film, method for manufacturing the same, thin film transistor, and active-matrix-driven display panel
TWI487118B (en) Semiconductor device
US8668849B2 (en) Sputtering target, oxide semiconductor film and semiconductor device
JP5372776B2 (en) Oxide semiconductor field effect transistor and manufacturing method thereof
TWI478347B (en) A thin film transistor, a thin film transistor substrate, and an image display device, and an image display device, and a semiconductor device
JP5386084B2 (en) Semiconductor thin film, manufacturing method thereof, and thin film transistor
TWI508284B (en) Field-effect transistor, method of manufacturing the same, and sputtering target
JP2009253204A (en) Field-effect transistor using oxide semiconductor, and its manufacturing method
JPWO2009075281A1 (en) Field effect transistor using oxide semiconductor and method for manufacturing the same
JP2009231664A (en) Field-effect transistor, and manufacturing method thereof
JP2010040552A (en) Thin film transistor and manufacturing method thereof
JP5702447B2 (en) Semiconductor thin film, manufacturing method thereof, and thin film transistor
JP5678149B2 (en) Semiconductor thin film, manufacturing method thereof, thin film transistor, active matrix drive display panel

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200680042998.5

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1020087011741

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 06832698

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 12094228

Country of ref document: US