TWI412135B - A semiconductor thin film, and a method of manufacturing the same, and a thin film transistor, an active matrix driving display panel - Google Patents

A semiconductor thin film, and a method of manufacturing the same, and a thin film transistor, an active matrix driving display panel Download PDF

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TWI412135B
TWI412135B TW095142654A TW95142654A TWI412135B TW I412135 B TWI412135 B TW I412135B TW 095142654 A TW095142654 A TW 095142654A TW 95142654 A TW95142654 A TW 95142654A TW I412135 B TWI412135 B TW I412135B
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thin film
film
semiconductor
semiconductor thin
indium
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TW200725907A (en
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Koki Yano
Kazuyoshi Inoue
Nobuo Tanaka
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Idemitsu Kosan Co
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133305—Flexible substrates, e.g. plastics, organic film
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

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Abstract

Disclosed is a semiconductor thin film which can be formed at a relatively low temperature even on a flexible resin substrate. Since the semiconductor thin film is stable to visible light and has high device characteristics such as transistor characteristics, it does not decrease the luminance of a display when overlapped with the pixel portion in case where the semiconductor thin film is used as a switching device for driving the display. Specifically disclosed is a transparent semiconductor thin film (40) produced by forming an amorphous film containing zinc oxide and indium oxide and then oxidizing the film so that the resulting film has a carrier density of 10<SUP>+17</SUP> cm<SUP>-3</SUP> or less, a hole mobility of 2 cm<SUP>2</SUP>/V·sec or more, and an energy band gap of 2.4 EV or more.

Description

半導體薄膜，及其製造方法，與薄膜電晶體，主動矩陣驅動顯示面板Semiconductor thin film, and its manufacturing method, and thin film transistor, active matrix driving display panel

本發明係關於由含有氧化鋅與氧化銦之非晶質膜所成的半導體薄膜、及其製造方法、及使用如此的半導體薄膜之薄膜電晶體、及適合使用如此的薄膜電晶體之主動矩陣驅動顯示面板。The present invention relates to a semiconductor thin film formed of an amorphous film containing zinc oxide and indium oxide, a method for producing the same, a thin film transistor using such a semiconductor thin film, and an active matrix driving suitable for using such a thin film transistor Display panel.

電場效果型電晶體被廣泛的使用於半導體記憶體積體電路的單元電子元件、高頻率信號增強元件、液晶驅動用元件等，現在使用於實用化之電子裝置的情況最多。The electric field effect type transistor is widely used in unit electronic components, high frequency signal enhancement elements, liquid crystal driving elements, and the like of a semiconductor memory bulk circuit, and is currently used most in practical electronic devices.

其中，近年隨著顯示裝置的驚人發展，不僅是液晶顯示裝置(LCD)，電致發光顯示裝置(EL)、或場發射顯示器(FED)等之各種顯示裝置中，作為在顯示元件外加驅動電壓後驅動顯示裝置之開關元件，多半使用薄膜電晶體(TFT)。Among them, in recent years, with the amazing development of display devices, not only liquid crystal display devices (LCDs), electroluminescent display devices (ELs), or field emission displays (FEDs) and the like have been used as driving voltages on display elements. The switching elements of the rear driving display device mostly use a thin film transistor (TFT).

此外，作為此材料，最廣泛使用矽半導體化合物，一般而言，高速操作所需要的高頻率增強元件、積體電路用元件等，使用矽單結晶，液晶驅動用元件等，應用大面積化的要求而使用非晶矽。In addition, as a material, a semiconductor compound is most widely used, and in general, a high-frequency enhancement element, an element for an integrated circuit, and the like which are required for high-speed operation, use a single crystal, a liquid crystal driving element, and the like, and a large-area application is applied. Amorphous germanium is used as required.

惟，結晶性的矽系薄膜，企圖結晶化時，例如需要800℃以上的高溫，要在玻璃基板上及有機物基板上進行構成很難，因此，不僅是只能在矽晶圓及石英等的耐熱性高的價格高的基板上形成，還有製造時需要大量能量及製程步驟數之問題。However, when a crystalline ruthenium-based film is attempted to be crystallized, for example, a high temperature of 800 ° C or higher is required, and it is difficult to form a composition on a glass substrate or an organic substrate. Therefore, it is not limited to ruthenium wafers and quartz. It is formed on a substrate having a high heat resistance and a high price, and there is a problem that a large amount of energy and a number of process steps are required at the time of manufacture.

另一方面，因為可較低溫形成的非晶性的矽半導體(非晶矽)，與結晶性者比較下開關速度慢，故作為驅動顯示裝置的開關元件使用時，會有無法跟上高速動畫的顯示之情況。On the other hand, since the amorphous germanium semiconductor (amorphous germanium) which can be formed at a lower temperature has a slower switching speed than the crystallizer, when used as a switching element for driving a display device, there is a possibility that the high-speed animation cannot be kept up. The situation of the display.

而且，半導體活性層照射可見光則顯示出導電性，會有產生漏電的錯誤操作之虞，而使作為開關元件的特性變差的問題，因此，已知有設置阻斷可見光之遮光層之方法，例如使用金屬薄膜作為遮光層。Further, when the semiconductor active layer is irradiated with visible light, it exhibits conductivity, and there is a problem that an erroneous operation for causing leakage occurs, and the characteristics of the switching element are deteriorated. Therefore, a method of providing a light shielding layer for blocking visible light is known. For example, a metal film is used as the light shielding layer.

但是，設置由金屬薄膜所成的遮光層，不僅製程步驟增加，因為持有浮游電位，故必須使遮光層成為地上層(ground level)，此時亦會產生寄生電容的問題。However, by providing a light-shielding layer made of a metal thin film, not only the process step is increased, but since the floating potential is held, it is necessary to make the light-shielding layer a ground level, and a parasitic capacitance problem occurs at this time.

此外，因為可見光的穿透率低，半導體層露出至電極部，則顯示部的穿透率下降，會有由背光的照明效率降低後畫面變暗之虞，加工精度的公差變小而成為成本增加的原因之一。Further, since the transmittance of visible light is low and the semiconductor layer is exposed to the electrode portion, the transmittance of the display portion is lowered, and the screen becomes dark after the illumination efficiency of the backlight is lowered, and the tolerance of the processing accuracy is reduced to become a cost. One of the reasons for the increase.

再者，現在作為驅動顯示裝置之開關元件，使用矽系的半導體膜之元件為主流，此仍因為矽薄膜的穩定性、加工性的優良之外，及開關速度快等之各種性能優良。而且，如此的矽系薄膜，一般藉由化學蒸氣析出法(CVD)法所製造。In addition, as a switching element for driving a display device, a device using a lanthanide-based semiconductor film is mainly used, and this is excellent in various properties such as stability and workability of a ruthenium film, and high switching speed. Further, such a ruthenium-based film is generally produced by a chemical vapor deposition (CVD) method.

此外，以往的薄膜電晶體(TFT)，玻璃等的基板上具有閘電極、閘絕緣層、氫化非晶矽(a－Si：H)等的半導體層、層合源及汲電極之逆交錯(reverse stagger)構造者，從影像感應器至大面積裝置的領域中，作為代表主動矩陣驅動型液晶顯示面板之平面顯示面板等之驅動元件使用，此等的用途，即使使用先前技術的非晶矽，隨著高機能化亦要求操作的高速化。Further, conventional thin film transistors (TFT), glass, and the like have reversed interleaving of a semiconductor layer such as a gate electrode, a gate insulating layer, hydrogenated amorphous germanium (a-Si:H), a lamination source, and a germanium electrode. The reverse stagger) is used as a driving element such as a flat display panel representing an active matrix driving type liquid crystal display panel in the field of an image sensor to a large-area device, and the like, even if a prior art amorphous germanium is used. With the high performance, the operation speed is also required.

如此的狀況下，近年來，比矽系半導體薄膜(非晶矽)穩定性優異者，由氧化鋅等的金屬氧化物所成的透明半導體薄膜受到注目，特別是由氧化鋅結晶所成的透明半導體薄膜。In such a case, in recent years, a transparent semiconductor thin film made of a metal oxide such as zinc oxide has been attracting attention, especially in the case of excellent stability of a bismuth-based semiconductor thin film (amorphous germanium), and is particularly transparent by zinc oxide crystal. Semiconductor film.

例如專利文獻1、或專利文獻2等中，記載著將氧化鋅以高溫結晶化構成薄膜電晶體之方法。For example, Patent Document 1, Patent Document 2, and the like describe a method of crystallizing zinc oxide at a high temperature to form a thin film transistor.

專利文獻1：特開2003－86808號公報專利文獻2：特開2004－273614號公報Patent Document 1: JP-A-2003-86808, Patent Document 2: JP-A-2004-273614

惟，使用氧化鋅的半導體薄膜，因為不進行精緻的結晶化控制則霍爾遷移率降低，故會有電場效果遷移率降低而開關速度變低的問題。而且，為了提高結晶性，在與矽系薄膜同樣結晶性高的特殊的基板上進行成膜，必須以500℃以上的高溫的處理，因此，於大面積進行均勻化，特別是在玻璃基板上進行有困難，液晶面板很難實用化。However, since the semiconductor thin film using zinc oxide has a Hall mobility lowering without performing fine crystallization control, there is a problem that the electric field effect mobility is lowered and the switching speed is lowered. Further, in order to improve the crystallinity, it is necessary to form a film on a special substrate having a high crystallinity similar to that of the lanthanoid film, and it is necessary to carry out a treatment at a high temperature of 500 ° C or higher. Therefore, it is uniformed over a large area, particularly on a glass substrate. It is difficult to carry out the operation, and the liquid crystal panel is difficult to be practical.

本發明係鑑於上述情況，目的在於提供為可用較低溫製作、可形成於具有彎曲性的樹脂基板上之半導體薄膜，對於可見光穩定，且電晶體特性等的元件特性高，此外作為驅動顯示裝置之開關元件使用時，即使與畫素部重疊亦不會降低顯示面板的亮度之半導體薄膜；以及如此的半導體薄膜的製造方法；及使用如此的半導體薄膜，電場效果遷移率與on－off比高，同時因為漏電的產生等之照射光所造成的影響小，提高元件特性之薄膜電晶體；適用如此的薄膜電晶體之主動矩陣驅動顯示面板。The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor thin film which can be formed on a resin substrate having flexibility and which can be formed on a resin substrate having flexibility, which is stable to visible light and has high element characteristics such as transistor characteristics, and is also used as a driving display device. When the switching element is used, the semiconductor film which does not lower the brightness of the display panel even if it overlaps with the pixel portion; and the method for manufacturing the semiconductor film; and the use of such a semiconductor film, the electric field effect mobility and the on-off ratio are high, At the same time, due to the occurrence of leakage, etc., the influence of the illumination light is small, and the thin film transistor which improves the characteristics of the element is applied; the active matrix driving display panel of such a thin film transistor is applied.

解決上述課題，本發明所相關的半導體薄膜，其為由含有氧化鋅與氧化銦之非晶質膜所成的半導體薄膜，係載子密度為10＋ 1 7 cm－ 3 以下，霍爾遷移率為2cm2 /V．sec以上，能帶間隙為2.4eV以上之構成。Solve the above problems, a semiconductor thin film related to the present invention, by which a semiconductor thin film comprising an amorphous film of zinc oxide and indium oxide formed by, based carrier density of 10 + 1 7 cm - 3 or less, the Hall mobility It is 2cm 2 /V. Above sec, the band gap can be 2.4 eV or more.

藉由使其成為如此構成，本發明相關的半導體薄膜，因為在廣範圍的溫度易製作半導體薄膜，同時在大面積中易表現出均勻的物性，故適合用於顯示面板等用途。By having such a configuration, the semiconductor thin film according to the present invention is suitable for use in a display panel or the like because it is easy to produce a semiconductor thin film over a wide range of temperatures and exhibits uniform physical properties in a large area.

本發明相關的半導體薄膜，載子密度大於10＋ 1 7 cm－ 3 ，則構成薄膜電晶體1等之元件時，因為易發生漏電，同時變成常開型(normally on)，on－off比變小，故會有無法發揮優良的電晶體性能之虞。 3, the thin film transistor 1 and the like of elements are constituted, as prone to leakage, while into the normally open (normally on), on-off ratio becomes - the semiconductor thin film related to the present invention, the carrier density of greater than 10 + 1 7 cm Small, so there will be a flaw in the performance of the excellent transistor.

此外霍爾遷移率小於2cm2 /Vs，則薄膜電晶體1的電場效果遷移率變小，作為驅動顯示元件之開關元件使用時，與非晶矽同樣，開關速度慢，會有無法跟上高速的動畫的顯示之虞。Further, when the Hall mobility is less than 2 cm 2 /Vs, the electric field effect mobility of the thin film transistor 1 is small, and when used as a switching element for driving a display element, the switching speed is slow as in the case of the amorphous germanium, and the high speed cannot be kept up. The display of the animation.

此外能帶間隙小於2.4eV，則照射可見光時，價電帶的電子被激發而顯示出導電性，會有易發生漏電之虞。Further, when the band gap is less than 2.4 eV, when the visible light is irradiated, the electrons of the valence band are excited to exhibit conductivity, and there is a possibility that electric leakage is likely to occur.

此外，本發明相關的半導體薄膜，為了在大面積上形成均勻的非晶質的膜，同時避免膜質變得不均勻，使該非晶質膜中的鋅[Zn]與銦[In]的原子比為Zn/(Zn＋In)＝0.10~0.82較佳，使該非晶質膜中的鋅Zn與銦In的原子比為Zn/(Zn＋In)＝0.51~0.80更佳。Further, in the semiconductor thin film according to the present invention, in order to form a uniform amorphous film over a large area while avoiding unevenness of the film quality, an atomic ratio of zinc [Zn] to indium [In] in the amorphous film is obtained. It is preferable that Zn/(Zn+In)=0.10 to 0.82, and the atomic ratio of zinc Zn to indium In in the amorphous film is preferably Zn/(Zn+In)=0.51 to 0.80.

此外，本發明相關的半導體薄膜，波長550nm的穿透率為75%以上為佳，藉由如此的作法，即使半導體薄膜露出至畫素電極部時，可降低穿透率及亮度，可有效的避免如色調變化等之不適合的狀況。Further, in the semiconductor thin film according to the present invention, the transmittance at a wavelength of 550 nm is preferably 75% or more, and by such a method, even when the semiconductor film is exposed to the pixel electrode portion, the transmittance and the brightness can be lowered, which is effective. Avoid situations that are not suitable for changes in color tone, etc.

此外，本發明相關的半導體薄膜，為功函數為3.5~6.5eV的非退化半導體薄膜較佳，使功函數位於上述範圍，可有效的避免因為漏電的產生、能量障壁等發生而造成的電晶體的特性降低，而且，會有無法使退化半導體之載子濃度穩定定期的控制在低濃度之虞。藉由使本發明相關的半導體薄膜成為非退化半導體薄膜，可有效的避免如此不適合的狀況。此處，非退化半導體薄膜可謂為載子濃度隨著溫度而變化之半導體薄膜，載子濃度與溫度的依賴性，可由霍爾測量計算得到。In addition, the semiconductor thin film according to the present invention is preferably a non-degenerate semiconductor film having a work function of 3.5 to 6.5 eV, and the work function is in the above range, thereby effectively preventing the transistor from being caused by leakage, energy barrier, or the like. The characteristics are lowered, and there is a possibility that the concentration of the carrier of the degraded semiconductor cannot be stabilized periodically at a low concentration. By making the semiconductor thin film according to the present invention a non-degenerate semiconductor thin film, such an unsuitable condition can be effectively avoided. Here, the non-degenerate semiconductor film can be referred to as a semiconductor film whose carrier concentration changes with temperature, and the dependence of the carrier concentration on temperature can be calculated by Hall measurement.

此外，本發明相關的半導體薄膜，非晶質膜中分散奈米晶體較佳，非晶質膜中分散奈米晶體，則會有霍爾遷移率提高、電場效果遷移率變高、電晶體特性提高之情況而較佳。Further, in the semiconductor thin film according to the present invention, it is preferable to disperse the nanocrystal in the amorphous film, and to disperse the nanocrystal in the amorphous film, the Hall mobility is improved, the electric field effect mobility is high, and the transistor characteristics are obtained. It is better to improve the situation.

此外，本發明相關的半導體薄膜，在無損於本發明的效果的範圍內，可含有氧化銦、氧化鋅以外的第三金屬元素[M]及其化合物，此時該第三金屬元素[M]與銦[In]的原子比[M/(M＋In)]為0~0.5較佳，該第三金屬元素[M]與銦[In]的原子比[M/(M＋In)]為0~0.3更佳。Further, the semiconductor thin film according to the present invention may contain a third metal element [M] other than indium oxide or zinc oxide and a compound thereof in the range which does not impair the effects of the present invention, and the third metal element [M] at this time The atomic ratio [M/(M+In)] to indium [In] is preferably 0 to 0.5, and the atomic ratio [M/(M+In)] of the third metal element [M] to indium [In] is 0 to 0.3. good.

此外，本發明相關的半導體薄膜，藉由X線散射測量所得到的徑向分佈函數(RDF)中，原子間距離為0.3~0.36nm之間的RDF的最大值定為A，原子間距離為0.36~0.42nm之間的RDF的最大值定為B時，符合A/B>0.8的關係較佳。推論此比率A/B係銦－氧－銦的鍵結形態表示成為邊共有與頂點共有者的比率，或表示短程有序的維持比率者。Further, in the semiconductor thin film according to the present invention, in the radial distribution function (RDF) obtained by X-ray scattering measurement, the maximum value of the RDF between the atoms between 0.3 and 0.36 nm is defined as A, and the distance between the atoms is When the maximum value of RDF between 0.36 and 0.42 nm is set to B, the relationship of A/B > 0.8 is preferable. It is inferred that the bonding form of the ratio A/B system indium-oxygen-indium is expressed as a ratio of the side sharing to the apex, or a short-range order maintaining ratio.

而且，此比率低於0.8以下，則會有霍爾遷移率及電場效果遷移率降低之虞。Further, when the ratio is less than 0.8, there is a possibility that the Hall mobility and the electric field effect mobility are lowered.

此外，本發明相關的半導體薄膜的製造方法，為當製造如上述的半導體薄膜，在氣體環境中的水H2 O的分壓成為10－ 3 Pa以下的條件，使含有氧化鋅與氧化銦之非晶質膜進行成膜之方法。Further, in the method for producing a semiconductor thin film according to the present invention, when the semiconductor thin film as described above is produced, the partial pressure of water H 2 O in a gas atmosphere is 10 - 3 Pa or less, and zinc oxide and indium oxide are contained. A method in which an amorphous film is formed into a film.

藉由如此的方法，可避免會有霍爾遷移率降低之虞等不適合的狀況。By such a method, it is possible to avoid an unsuitable situation in which the Hall mobility is lowered.

此外，本發明相關的半導體薄膜的製造方法，為包括將以基板溫度200℃以下經物理成膜的該非晶質膜進行氧化處理之步驟之方法較佳，基板溫度高於200℃，則即使氧化處理，載子濃度亦未下降，使用樹脂製基板時會有引起變形及尺寸變化之虞。Further, the method for producing a semiconductor thin film according to the present invention is preferably a method comprising the step of oxidizing the amorphous film which is physically formed at a substrate temperature of 200 ° C or lower, and the substrate temperature is higher than 200 ° C, even if it is oxidized. The concentration of the carrier did not decrease during the treatment, and deformation and dimensional change were caused when the resin substrate was used.

此外，使在上述範圍成膜的半導體薄膜進行氧氣存在下的熱處理及臭氧處理等的氧化處理，因為使載子密度穩定化而較佳。Further, it is preferred that the semiconductor thin film formed in the above range is subjected to heat treatment in the presence of oxygen and oxidation treatment such as ozone treatment, because the carrier density is stabilized.

熱處理時，熱處理時的膜面的溫度，比成膜時的基板溫度高100~270℃較佳，此溫度差小於100℃，則無熱處理效果，高於270℃則基板變形，會有半導體薄膜界面變質而半導體特性降低之虞。為了有效的避免如此不適合的情況，熱處理時的膜面的溫度比成膜時的基板溫度高130~240℃較佳，高160~210℃特別佳。In the heat treatment, the temperature of the film surface at the time of heat treatment is preferably 100 to 270 ° C higher than the substrate temperature at the time of film formation. When the temperature difference is less than 100 ° C, there is no heat treatment effect, and when the temperature is higher than 270 ° C, the substrate is deformed, and a semiconductor film is present. The interface deteriorates and the semiconductor characteristics are reduced. In order to effectively avoid such an unsuitable situation, the temperature of the film surface during heat treatment is preferably 130 to 240 ° C higher than the substrate temperature at the time of film formation, and particularly preferably 160 to 210 ° C.

此外，本發明相關的薄膜電晶體，可為具有如上述的半導體薄膜之構成，該半導體薄膜可為設置在樹脂基板上的構成。Further, the thin film transistor according to the present invention may have a configuration of a semiconductor thin film as described above, and the semiconductor thin film may be provided on a resin substrate.

此外，本發明相關的主動矩陣驅動顯示面板，可為具有如上述的薄膜電晶體之構成。Furthermore, the active matrix drive display panel of the present invention may be constructed with a thin film transistor as described above.

如上述，依據本發明，可提供以廣範圍的溫度形成於玻璃基板與樹脂基板等上，同時構成對於可見光穩定而不易引起錯誤操作、漏電小之優異的電場效果型電晶體之半導體薄膜；此外，可提供本發明的半導體薄膜因為可以較低溫形成，故形成於樹脂基板上，具有彎曲性的薄膜電晶體。As described above, according to the present invention, it is possible to provide a semiconductor film which is formed on a glass substrate, a resin substrate or the like in a wide range of temperatures, and which is excellent in visible light and which is less likely to cause erroneous operation and less leakage, and which is excellent in electric field effect type transistor; The semiconductor thin film of the present invention can be formed on a resin substrate and has a flexible thin film transistor because it can be formed at a relatively low temperature.

[實施發明的最佳形態][Best Mode for Carrying Out the Invention]

以下，說明關於本發明較佳實施形態。Hereinafter, preferred embodiments of the present invention will be described.

再者，圖1係表示本發明相關的薄膜電晶體的實施形態的概略之說明圖。1 is a schematic view showing an outline of an embodiment of a thin film transistor according to the present invention.

圖示之例子中，作為電場效果型電晶體的薄膜電晶體1，在基板60上間隔形成源電極10及汲電極20，同時形成與源電極10與汲電極20的各自的至少一部份相連接之透明半導體薄膜40，而且，在透明半導體薄膜40上，依序形成閘絕緣膜50、閘電極30而成的頂閘(top gate)型的薄膜電晶體1的構成。In the illustrated example, as the thin film transistor 1 of the electric field effect type transistor, the source electrode 10 and the ytterbium electrode 20 are formed on the substrate 60 at the same time, and at least a part of each of the source electrode 10 and the ytterbium electrode 20 is formed. The transparent semiconductor film 40 is connected, and a top gate type thin film transistor 1 in which the gate insulating film 50 and the gate electrode 30 are formed in this order on the transparent semiconductor film 40 is formed.

本實施形態中，基板60，除了玻璃基板之外，可使用由聚對苯二甲酸乙二醇酯(PET)、聚碳酸酯(PC)等所成的樹脂製基板。In the present embodiment, a substrate made of a resin made of polyethylene terephthalate (PET), polycarbonate (PC) or the like can be used as the substrate 60.

此外，對於形成閘電極30、源電極20、汲電極10的各電極之材料並沒有特別的限制，在不會喪失本實施形態的效果的範圍內，可任意選擇一般所使用者，例如可使用ITO、IZO、ZnO、SnO2 等之透明電極，或Al、Ag、Cr、Ni、Mo、Au、Ti、Ta等的金屬電極，或含有此等之合金的金屬電極。Further, the material of each of the electrodes forming the gate electrode 30, the source electrode 20, and the ytterbium electrode 10 is not particularly limited, and a general user can be arbitrarily selected within a range that does not lose the effect of the embodiment, and for example, it can be used. a transparent electrode such as ITO, IZO, ZnO, or SnO 2 or a metal electrode such as Al, Ag, Cr, Ni, Mo, Au, Ti, or Ta, or a metal electrode containing the alloy.

閘電極30、源電極20、汲電極10的各電極，可為層合不同的二層以上的導電層之多層構造，在圖示的例子中，各電極30、20、10，係各自由第一導電層31、21、11與第二導電層32、22、12所構成。Each of the gate electrode 30, the source electrode 20, and the drain electrode 10 may have a multilayer structure in which two or more conductive layers are laminated. In the illustrated example, each of the electrodes 30, 20, and 10 is A conductive layer 31, 21, 11 and a second conductive layer 32, 22, 12 are formed.

此外，對於形成閘絕緣膜50之材料亦沒有特別的限制，在不喪失本實施形態的發明的效果的範圍，可任意選擇一般所使用者。可使用例如SiO2 、SiNx、Al2 O3 、Ta2 O5 、TiO2 、MgO、ZrO2 、CeO2 、K2 O、Li2 O、Na2 O、Rb2 O、Sc2 O3 、Y2 O3 、Hf2 O3 、CaHfO3 等的氧化物，此等又以使用SiO2 、SiNx、Al2 O3 、Y2 O3 、Hf2 O3 、CaHfO2 較佳，更佳為SiO2 、SiNx、Y2 O3 、Hf2 O3 、CaHfO3 ，特別佳為SiO2 、SiNx。Further, the material for forming the gate insulating film 50 is not particularly limited, and a general user can be arbitrarily selected without losing the effect of the invention of the present embodiment. For example, SiO 2 , SiNx, Al 2 O 3 , Ta 2 O 5 , TiO 2 , MgO, ZrO 2 , CeO 2 , K 2 O, Li 2 O, Na 2 O, Rb 2 O, Sc 2 O 3 , Y 2 O 3, Hf 2 O 3, CaHfO 3 oxides and the like, again using such SiO 2, SiNx, Al 2 O 3, Y 2 O 3, Hf 2 O 3, CaHfO 2 preferred, more preferably SiO 2 , SiNx, Y 2 O 3 , Hf 2 O 3 , and CaHfO 3 are particularly preferably SiO 2 or SiNx.

如此的閘絕緣膜50，可為層合不同2層以上的絕緣膜之構造，此外，閘絕緣膜50可為結晶質或非晶質，較佳為工業上易製造之非晶質。Such a gate insulating film 50 may have a structure in which two or more insulating films are laminated, and the gate insulating film 50 may be crystalline or amorphous, and is preferably amorphous which is industrially easy to manufacture.

本實施形態中，透明半導體薄膜40，由含有氧化鋅及氧化銦之非晶質所成，使形成為用霍爾測量所得到的載子密度為10＋ 1 7 cm－ 3 以下，霍爾遷移率為2cm2 /Vs以上，導電帶與價電帶之能帶間隙為2.4eV以上。In this embodiment, the transparent semiconductor thin film 40, containing an amorphous indium oxide and zinc oxide formed by, formed as a Hall carrier density measurement obtained is 10 + 1 7 cm - 3 or less, a Hall mobility The rate is 2 cm 2 /Vs or more, and the energy band gap between the conductive tape and the valence band is 2.4 eV or more.

如此的含有氧化鋅及氧化銦之非晶質膜，因為在廣範圍的溫度易製作，同時藉由使其為非晶質膜，在大面積中易表現出均勻的物性，故特別適合用於顯示面板等用途，例如可適用於主動矩陣驅動顯示面板。Such an amorphous film containing zinc oxide and indium oxide is particularly suitable for use because it is easy to fabricate at a wide range of temperatures and exhibits uniform physical properties in a large area by making it an amorphous film. For display panels and the like, for example, it can be applied to an active matrix drive display panel.

再者，非晶質膜可藉由在X線繞射中未出現明確的波峰而確認。Furthermore, the amorphous film can be confirmed by the absence of a clear peak in the X-ray diffraction.

此處，載子密度大於10＋ 1 7 cm－ 3 ，則構成薄膜電晶體1等之元件時，因為易發生漏電，同時變成常開型，on－off比變小，故會有無法發揮優良的電晶體性能之虞。為了避免如此不適合的狀況，使載子密度為10＋ 1 6 cm－ 3 以下較佳，更佳為10＋ 1 5 cm－ 3 以下，特別佳為10＋ 1 4 cm－ 3 以下。Here, the carrier density of greater than 10 + 1 7 cm - 3, when the thin film transistors constitute an element etc., as prone to leakage, while becomes the normally open type, on-off ratio becomes small, so that there will not be exhibited superior The performance of the transistor. To avoid this situation is not suitable for the carrier density of 10 + 1 6 cm - 3 or less preferred, more preferably 10 + 1 5 cm - 3 or less, and particularly preferred is 10 + 1 4 cm - 3 or less.

此外霍爾遷移率小於2cm2 /Vs，則薄膜電晶體1的電場效果遷移率變小，作為驅動顯示元件之開關元件使用時，與非晶矽同樣，開關速度慢，會有無法跟上高速的動畫的顯示之虞。為了避免如此不適合的狀況，使霍爾遷移率為5cm2 /Vs以上為佳，較佳為8cm2 /Vs以上，更佳為11cm2 /Vs以上，特別佳為14cm2 /Vs以上。Further, when the Hall mobility is less than 2 cm 2 /Vs, the electric field effect mobility of the thin film transistor 1 is small, and when used as a switching element for driving a display element, the switching speed is slow as in the case of the amorphous germanium, and the high speed cannot be kept up. The display of the animation. In order to avoid such an unsuitable condition, the Hall mobility is preferably 5 cm 2 /Vs or more, preferably 8 cm 2 /Vs or more, more preferably 11 cm 2 /Vs or more, and particularly preferably 14 cm 2 /Vs or more.

像這樣，藉由使透明半導體薄膜40形成為載子密度為10＋ 1 7 cm－ 3 以下，霍爾遷移率為2cm2 /Vs以上，可得到電場效果遷移率高，同時on－off比亦高，顯示出常關型，而且，夾止(pinch off)清楚，可取代先前技術之使用非晶矽的電場效果型電晶體之可大面積化、新型優異的電場效果型電晶體。Thus, by the transparent semiconductor thin film 40 is formed as a carrier density of 10 + 1 7 cm - 3 or less, a Hall mobility of 2cm 2 / Vs or more, the electric field effect mobility is high can be obtained, and also on-off ratio High, showing a normally closed type, and clear pinch off, which can replace the large-area, new and excellent electric field effect type transistor of the prior art electric field effect type transistor using amorphous germanium.

此外能帶間隙小於2.4eV，則照射可見光時，價電帶的電子被激發而顯示出導電性，會有易發生漏電之虞。為了避免如此的不適合狀況，能帶間隙2.6eV以上為佳，較佳為2.8eV以上，更佳為3.0eV以上，特別佳為3.2eV以上。Further, when the band gap is less than 2.4 eV, when the visible light is irradiated, the electrons of the valence band are excited to exhibit conductivity, and there is a possibility that electric leakage is likely to occur. In order to avoid such an unsuitable condition, the band gap is preferably 2.6 eV or more, preferably 2.8 eV or more, more preferably 3.0 eV or more, and particularly preferably 3.2 eV or more.

此外，透明半導體薄膜40的比電阻，一般為10－ 1 ~10＋ 8 Ω cm，10－ 1 ~10＋ 8 Ω cm為佳，100 ~10＋ 6 Ω cm較佳，10＋ 1 ~10＋ 4 Ω cm更佳，10＋ 2 ~10＋ 3 Ω cm特別佳。Further, the specific resistance of the transparent semiconductor film 40 is generally 10 - 1 to 10 + 8 Ω cm, preferably 10 - 1 to 10 + 8 Ω cm, preferably 10 0 to 10 + 6 Ω cm, and 10 + 1 to 10 + 4 Ω cm is better, and 10 + 2 ~ 10 + 3 Ω cm is particularly good.

而且，藉由使透明半導體薄膜40中含有氧化銦，實現高的霍爾遷移率，同時藉由抑制成膜時的氣體環境中的氧分壓、或氣體環境中的水H2 O、或氫H2 的含量，可控制霍爾遷移率。Further, by including indium oxide in the transparent semiconductor film 40, high Hall mobility is achieved while suppressing oxygen partial pressure in a gas atmosphere at the time of film formation, or water H 2 O or hydrogen in a gas atmosphere. The H 2 content controls the Hall mobility.

與氧化銦同時含有氧化鋅之效果，推測其為結晶化時，藉由取代正三價的銦位置而使其產生載子捕獲，為了不使霍爾遷移率降太低而降低載子密度。The effect of containing zinc oxide at the same time as indium oxide is presumed to be that when the crystal is crystallization, the carrier is trapped by replacing the indium trivalent indium position, and the carrier density is lowered in order not to lower the Hall mobility.

而且，藉由相對於正三價元素之銦使其含有正二價元素之鋅，減少載子濃度，同時如後述藉由成膜後施以氧化處理，可在不使霍爾遷移率降低下控制載子濃度。Further, by reducing the carrier concentration by indium containing a positive divalent element with respect to the indium of the positive trivalent element, and controlling the oxidation by film formation after the film formation as described later, the control can be carried out without lowering the Hall mobility. Subconcentration.

此外，可使半導體薄膜50中所含有的銦[In]與鋅[Zn]的原子比為Zn/(Zn＋In)＝0.10~0.82。Further, the atomic ratio of indium [In] to zinc [Zn] contained in the semiconductor thin film 50 can be Zn / (Zn + In) = 0.10 - 0.82.

原子比[Zn/(Zn＋In)]小於0.10，鋅的含有率少，則會有易結晶化，不選定適當的製造條件，則會有大面積上無法得到均勻的非晶質的膜之虞。When the atomic ratio [Zn/(Zn+In)] is less than 0.10 and the content of zinc is small, crystallization is easy, and if an appropriate production condition is not selected, a uniform amorphous film cannot be obtained in a large area.

另一方面，原子比[X/(X＋In)]大於0.82，鋅的含有過多，則會有耐藥品性降低，生成氧化鋅的結晶後膜質變得不均勻之虞。On the other hand, when the atomic ratio [X/(X+In)] is more than 0.82, if the content of zinc is too large, the chemical resistance is lowered, and the film quality after the formation of zinc oxide becomes uneven.

本實施形態中，為了避免如上述不適合的情況，原子比[X/(X＋In)]為0.51~0.80為佳，更佳為0.55~0.80，0.6~0.75特別佳。In the present embodiment, in order to avoid the case where the above is not suitable, the atomic ratio [X/(X+In)] is preferably 0.51 to 0.80, more preferably 0.55 to 0.80, and particularly preferably 0.6 to 0.75.

此外，透明半導體薄膜40，係波長550nm的穿透率為75%以上為佳，波長550nm的穿透率小於75%，則半導體薄膜露出至畫素電極部時會有使穿透率降低、使亮度降低、色調變化之虞，為了有效的避免如此不適合的狀況，波長550nm的穿透率為80%以上為佳，85%以上特別佳。Further, the transparent semiconductor film 40 preferably has a transmittance of 75% or more at a wavelength of 550 nm, and a transmittance of 550 nm or less is less than 75%. When the semiconductor film is exposed to the pixel electrode portion, the transmittance is lowered. In order to effectively avoid such an unsuitable condition, the transmittance at a wavelength of 550 nm is preferably 80% or more, and particularly preferably 85% or more.

透明半導體薄膜40，功函數為3.5~6.5eV較佳，功函數小於3.5eV，則會有在與閘絕緣膜界面發生電價的注入等而發生漏電等之電晶體特性降低之虞，另一方面，功函數大於6.5eV，則會有在與閘絕緣膜界面發生能量障壁、pinch－off(夾止)特性惡化等之電晶體特性降低之虞。為了有效的避免如此的不適合狀況，功函數為3.8~6.2eV為佳，4.0~6.0eV較佳，4.3~5.7eV更佳，4.5~5.5eV特別佳。In the transparent semiconductor film 40, the work function is preferably 3.5 to 6.5 eV, and the work function is less than 3.5 eV, and the dielectric characteristics such as electric leakage may be caused by the injection of electricity at the interface with the gate insulating film, and the like. When the work function is more than 6.5 eV, there is a possibility that the dielectric characteristics such as energy barrier and pinch-off (deformation) deterioration at the interface with the gate insulating film are lowered. In order to effectively avoid such unsuitable conditions, the work function is preferably 3.8~6.2eV, 4.0~6.0eV is better, 4.3~5.7eV is better, and 4.5~5.5eV is especially good.

此外，透明半導體薄膜40，為非退化半導體薄膜較佳，若為退化半導體，則會有無法使載子濃度穩定定期的控制在低濃度之虞。Further, the transparent semiconductor film 40 is preferably a non-degenerate semiconductor film, and if it is a degraded semiconductor, there is a possibility that the concentration of the carrier cannot be stabilized at a low concentration.

此處，非退化半導體薄膜，可謂為載子濃度隨著溫度變化之半導體薄膜，相對於此，退化半導體薄膜，可謂為載子濃度不隨著溫度變化而顯示出一定值之半導體薄膜，此載子濃度與溫度的依賴性，可由霍爾測量計算得到。Here, the non-degenerate semiconductor thin film is a semiconductor thin film whose carrier concentration changes with temperature. On the other hand, the degraded semiconductor thin film is a semiconductor thin film in which the carrier concentration does not change with temperature and exhibits a constant value. The dependence of subconcentration on temperature can be calculated from Hall measurements.

此外，透明半導體薄膜40，非晶質膜中分散奈米晶體較佳，非晶質膜中分散奈米晶體，則會有霍爾遷移率提高、電場效果遷移率變高、電晶體特性提高之情況而較佳。奈米晶體的存在可藉由TEM觀察而確認。Further, in the transparent semiconductor thin film 40, it is preferable to disperse the nanocrystal in the amorphous film, and to disperse the nanocrystal in the amorphous film, the Hall mobility is improved, the electric field effect mobility is increased, and the transistor characteristics are improved. The situation is better. The presence of nanocrystals can be confirmed by TEM observation.

此處，透明半導體薄膜40，係在無損於本發明的效果的範圍內，可含有氧化銦、氧化鋅以外的第三金屬元素及其化合物。Here, the transparent semiconductor thin film 40 may contain a third metal element other than indium oxide or zinc oxide and a compound thereof insofar as the effects of the present invention are not impaired.

惟，此時該銦[In]與第三金屬元素[M]的原子比[M/(M＋In)]為0~0.5較佳，原子比[M/(M＋In)]超過0.5，則會有霍爾遷移率降低之虞，推論此仍因為主元素間的鍵結數減少，而使滲濾傳導變困難。However, at this time, the atomic ratio [M/(M+In)] of the indium [In] to the third metal element [M] is preferably 0 to 0.5, and the atomic ratio [M/(M+In)] exceeds 0.5, and there is a After the migration rate is lowered, it is inferred that the number of bonds between the main elements is reduced, which makes the percolation conduction difficult.

為了避免如此的不適合狀況，原子比[M/(M＋In)]為0~0.3為佳。In order to avoid such an unsuitable condition, the atomic ratio [M/(M+In)] is preferably 0 to 0.3.

此外，透明半導體薄膜40，藉由X線散射測量所得到的徑向分佈函數(RDF)中，原子間距離為0.3~0.36nm之間的RDF的最大值定為A，原子間距離為0.36~0.42nm之間的RDF的最大值定為B時，符合A/B>0.8的關係較佳。Further, in the transparent semiconductor film 40, in the radial distribution function (RDF) obtained by X-ray scattering measurement, the maximum value of the RDF between the atoms between 0.3 and 0.36 nm is set to A, and the distance between atoms is 0.36. When the maximum value of RDF between 0.42 nm is set to B, the relationship of A/B > 0.8 is preferable.

推論此比率A/B係銦－氧－銦的鍵結形態表示成為邊共有與頂點共有者的比率，或表示短距離秩序的維持比率者。此比率(A/B)為0.8以下，則會有霍爾遷移率及電場效果遷移率降低之虞。It is inferred that the bond form of the ratio A/B system indium-oxygen-indium is expressed as a ratio of the side sharing to the apex, or a maintaining ratio of the short distance order. When the ratio (A/B) is 0.8 or less, there is a possibility that the Hall mobility and the electric field effect mobility are lowered.

為了避免如此的不適合的狀況，比率(A/B)符合A/B>0.9較佳，更佳為A/B>1.0，符合A/B>1.1最佳，推論比率(A/B)大係短距離的銦－銦保持在短距離秩序，因此，期待電子的遷移路徑被確保，霍爾遷移率及電場效果遷移率提高。In order to avoid such unsuitable conditions, the ratio (A/B) is better than A/B>0.9, more preferably A/B>1.0, which is in accordance with A/B>1.1, and the inferential ratio (A/B) is large. Since the indium-indium in a short distance is maintained in a short distance order, it is expected that the electron migration path is secured, and the Hall mobility and the electric field effect mobility are improved.

本實施形態中，形成透明半導體薄膜40之成膜方法，除了噴霧法、浸漬法、CVD法等之化學的成膜法之外，亦可利用物理的成膜方法，由載子密度的控制、或膜質的提高容易之觀點而言，物理的成膜方法較佳。In the present embodiment, a film forming method for forming the transparent semiconductor film 40 may be controlled by a chemical film forming method in addition to a chemical film forming method such as a spray method, a dipping method, or a CVD method, and the carrier density may be controlled. A physical film forming method is preferred from the viewpoint of easy improvement of the film quality.

物理的成膜方法，可列舉例如濺鍍法、真空蒸鍍法、離子被覆法、脈衝雷射蒸鍍製程技術法等，但以工業上量產性高之濺鍍法為佳。The physical film formation method may, for example, be a sputtering method, a vacuum deposition method, an ion coating method, a pulsed laser evaporation process technique, or the like, but is preferably a commercially available sputtering method having high productivity.

濺鍍法可列舉例如DC濺鍍法、RF濺鍍法、AC濺鍍法、ECR濺鍍法、對向標靶濺鍍法等，此等中又以工業上量產性高，此外比RF濺鍍法更能降低載子濃度之DC濺鍍法及AC濺鍍法較佳。此外，抑制因為成膜所產生的界面劣化，抑制漏電，提高on－off比等的透明半導電膜40的特性，以易控制膜質之ECR濺鍍法、或對向標靶濺鍍法較佳。The sputtering method may, for example, be a DC sputtering method, an RF sputtering method, an AC sputtering method, an ECR sputtering method, an opposite target sputtering method, or the like, which is industrially high in mass productivity, and further than RF. DC sputtering and AC sputtering, which are more effective in reducing the concentration of the carrier by sputtering, are preferred. Further, it is preferable to suppress the deterioration of the interface due to film formation, suppress leakage, improve the characteristics of the transparent semiconductive film 40 such as on-off ratio, and to preferably control the film quality by ECR sputtering or the opposite target sputtering method. .

使用濺鍍法時，可使用含有氧化銦及氧化鋅的燒結標靶，亦可使用含有氧銦之燒結標靶與含有氧化鋅之燒結標靶進行共濺鍍，此外，由銦及鋅所成的金屬標靶或使用合金標靶，一邊導入氧氣等氣體，一邊進行反應性濺鍍亦可。When using the sputtering method, a sintered target containing indium oxide and zinc oxide may be used, or a sintered target containing indium oxynitride may be co-sputtered with a sintered target containing zinc oxide, and further, indium and zinc may be used. The metal target or the alloy target may be subjected to reactive sputtering while introducing a gas such as oxygen.

由重複性、在大面積的均勻性而言，含有氧化銦與正二價元素的氧化物之燒結標靶較佳。A sintered target containing an oxide of indium oxide and a positive divalent element is preferred from the viewpoint of repeatability and uniformity over a large area.

使用濺鍍法時，使氣體環境中所含有的水H2 O分壓成為10－ 3 Pa以下，水H2 O分壓大於10－ 3 Pa，則會有霍爾遷移率降低之虞，推測此仍因為氫與方錳鐵礦構造的銦或氧鍵結後使氧－銦鍵結的邊共有部份成為頂點共有化。為了有效避免如此不適合的狀況，H2 O分壓較佳為8×10－ 4 Pa以下，更佳為6×10－ 4 Pa以下，再更佳為4×10－ 4 Pa以下，2×10－ 4 Pa以下為特別佳。When using the sputtering method, the water contained in the atmosphere H 2 O partial pressure of 10 - 3 Pa or less, the water partial pressure of H 2 O 10 - 3 Pa, will reduce the risk of the Hall mobility, presumably This is still because the hydrogen-bonded indium or oxygen of the ferrocene structure causes the oxy-indium-bonded edge-shared portion to become the apex common. In order to avoid such a situation is not suitable, H 2 O partial pressure is preferably 8 × 10 - 4 Pa or less, more preferably 6 × 10 - 4 Pa or less, still more preferably 4 × 10 - 4 Pa or less, 2 × 10 - Below 4 Pa is especially good.

此外，氣體環境中的氫H2 分壓，一般為10－ 2 Pa以下，5×10－ 3 Pa以下為佳，10－ 3 Pa以下更佳，5×10－ 4 Pa以下又更佳，2×10－ 4 Pa以下特別佳。氣體環境的氣體中存在H2 ，則會有不只是載子濃度增加，亦會有霍爾遷移率降低之虞。In addition, the hydrogen gas H 2 partial pressure in the environment, typically 10 - 2 Pa or less, 5 × 10 - 3 Pa or less preferably, 10 - 3 Pa or less more preferably, 5 × 10 - 4 Pa or less and more preferably, 2 It is particularly preferable to be ×10 - 4 Pa or less. The presence of H 2 in the gas of the gaseous environment will not only increase the concentration of the carrier, but also reduce the mobility of the Hall.

此外，氣體環境中的氧O2 分壓，一般為40×10－ 3 Pa以下，氣體環境的氣體中的氧分壓大於40×10－ 3 Pa，則會有霍爾遷移率降低、霍爾遷移率及載子濃度變得不穩定之虞，推測此仍因為成膜時氣體環境的氣體中的氧過多，則結晶格子間進入的氧過多而成為散射的原因，容易自膜中脫離而不穩定。Further, oxygen gas atmosphere O 2 partial pressure, typically 40 × 10 - 3 Pa or less, the gas atmosphere of the oxygen partial pressure greater than 40 × 10 - 3 Pa, the Hall mobility will decrease, Hall When the mobility and the carrier concentration become unstable, it is presumed that the oxygen in the gas in the gas atmosphere at the time of film formation is excessive, and the oxygen entering between the crystal lattices is excessively scattered, which causes scattering and is easily detached from the film. stable.

為了有效的避免如此的不適合狀況，氣體環境的氣體中的氧分壓較佳為15×10－ 3 Pa以下，更佳為7×10－ 3 Pa以下，1×10－ 3 Pa以下特別佳。In order to effectively avoid such a situation is not suitable for the gas atmosphere of the oxygen partial pressure is preferably 15 × 10 - 3 Pa or less, more preferably 7 × 10 - 3 Pa or less, 1 × 10 - 3 Pa or less particularly preferred.

此外，到逹真空度一般為10－ 5 Pa以下，到逹真空度大於10－ 5 Pa，則會有H2 O分壓變高，無法使水H2 O分壓逹到10－ 3 Pa以下之虞，為了有效的避免如此的不適合狀況，到逹壓力較佳為5×10－ 6 Pa以下，10－ 6 Pa以下特別佳。In addition, the vacuum is generally 10 - 5 Pa or less, and when the vacuum is greater than 10 - 5 Pa, the partial pressure of H 2 O becomes high, and the partial pressure of water H 2 O cannot be reduced to 10 - 3 Pa or less. Thereafter, in order to effectively avoid such an unsuitable condition, the enthalpy pressure is preferably 5 × 10 - 6 Pa or less, and particularly preferably 10 - 6 Pa or less.

再者，以濺鍍法使大面積成膜時，為了使其具有膜質的均一性，較佳為採用使固定基板的夾子旋轉，使磁轉運轉擴大侵蝕範圍等之方法。Further, when a large-area film is formed by a sputtering method, in order to impart uniformity of film quality, it is preferable to use a method of rotating a clip for fixing a substrate to expand a magnetic rotation operation and the like.

如此的成膜步驟中，一般藉由以基板溫度200℃以下進行物理成膜，成膜步驟結束後，對於含有氧化銦與氧化鋅之薄膜施以氧化處理，可控制透明半導體薄膜40中的載子濃度。In such a film formation step, the film formation is generally performed at a substrate temperature of 200 ° C or lower, and after the film formation step is completed, the film containing the indium oxide and the zinc oxide is subjected to an oxidation treatment to control the load in the transparent semiconductor film 40. Subconcentration.

此處，若成膜時基板溫度高於200℃，則會有即使氧化處理載子濃度亦不會降低，使用樹脂製基板時，會有引起變形及尺寸改變之虞。為了有效的避免如此不適合的狀況，基板溫度180℃以下為佳，較佳為150℃以下，更佳為120℃以下，90℃以下特別佳。Here, when the substrate temperature is higher than 200 ° C at the time of film formation, the concentration of the carrier is not lowered even when the film is oxidized, and when the resin substrate is used, deformation and dimensional change may occur. In order to effectively avoid such an unsuitable condition, the substrate temperature is preferably 180 ° C or lower, preferably 150 ° C or lower, more preferably 120 ° C or lower, and particularly preferably 90 ° C or lower.

如此的成膜步驟結束後，本實施形態，可對於含有氧化銦與氧化鋅之薄膜，藉由施以氧化處理，而控制透明半導體薄膜40中的載子濃度。After the completion of the film formation step, in the present embodiment, the concentration of the carrier in the transparent semiconductor film 40 can be controlled by the oxidation treatment on the film containing indium oxide and zinc oxide.

再者，亦有成膜時藉由控制氧等氣體成份的濃度而控制載子濃度，惟如此之方法會有降低霍爾遷移率之虞，推測此仍因為為了控制載子而導入的氣體成份，進入膜中而成為散射的原因。Furthermore, it is also possible to control the concentration of the carrier by controlling the concentration of gas components such as oxygen during film formation. However, such a method may reduce the Hall mobility, and it is presumed that this is because of the gas component introduced for controlling the carrier. , entering the film and causing scattering.

此外，氧化處理係在氧存在下，一般以80~650℃、0.5~12000分鐘的條件進行熱處理。Further, the oxidation treatment is carried out in the presence of oxygen, and is usually heat-treated at 80 to 650 ° C for 0.5 to 12,000 minutes.

熱處理的溫度低於80℃，則會有未出現處理效果、花費過多的時間之虞，高於650℃則會有基板變形之虞。為了有效的避免如此不適合的狀況，處理溫度較佳為120~500℃，更佳為150~450℃，再更佳為較佳為180~350℃，200~300℃特別佳。When the temperature of the heat treatment is lower than 80 ° C, there is a case where no treatment effect is obtained and it takes too much time, and when it is higher than 650 ° C, the substrate is deformed. In order to effectively avoid such an unsuitable condition, the treatment temperature is preferably from 120 to 500 ° C, more preferably from 150 to 450 ° C, even more preferably from 180 to 350 ° C, and particularly preferably from 200 to 300 ° C.

此外，熱處理的時間比0.5分鐘短，則會有要傳熱至內部的時間不足而使處理不充分之虞，比12000分鐘長，則會有處理裝置過大而無法於工業上使用、處理中基板破損或變形之虞。為了有效的避免如此不適合的狀況，處理時間較佳為1~600分鐘，更佳為5~360分鐘，再更佳為較佳為15~240分鐘，30~120分鐘特別佳。In addition, when the heat treatment time is shorter than 0.5 minutes, there is a shortage of time for heat transfer to the inside, and the treatment is insufficient. If it is longer than 12,000 minutes, the processing apparatus is too large to be industrially used, and the substrate is processed. Damage or deformation. In order to effectively avoid such an unsuitable condition, the processing time is preferably from 1 to 600 minutes, more preferably from 5 to 360 minutes, even more preferably from 15 to 240 minutes, and particularly preferably from 30 to 120 minutes.

此外，氧化處理係可在氧存在，藉由燈退火裝置(LA；Lamp Annealer)、急速熱退火裝置(RTA；Rapid Thermal Annealer)、或雷射退火裝置進行熱處理，氧化處理亦適合使用臭氧處理。Further, the oxidation treatment may be performed in the presence of oxygen, by a lamp annealing apparatus (LA; Lamp Annealer), a rapid thermal annealing apparatus (RTA; Rapid Thermal Annealer), or a laser annealing apparatus, and the oxidation treatment is also suitable for ozone treatment.

實施例Example

以下，列舉具體的實施例，更詳細說明本發明。Hereinafter, the present invention will be described in more detail by way of specific examples.

[實施例1][Example 1]

(1)濺鍍靶的製造、及評估1.標靶的製造混合作為原料之平均粒徑為3.4 μ m的氧化銦、與平均粒徑為0.6 μ m的氧化鋅，使原子比為[In/(In＋Zn)成為0.28、原子比為Zn/(In＋Zn)成為0.72，將其供給至濕式球磨機，72小時混合粉碎後得到原料微粉末。(1) Manufacture and evaluation of a sputtering target 1. Preparation of a target The indium oxide having an average particle diameter of 3.4 μm and zinc oxide having an average particle diameter of 0.6 μm were mixed as a raw material, and the atomic ratio was [In / (In + Zn) was 0.28, and the atomic ratio was Zn / (In + Zn) was 0.72, and this was supplied to a wet ball mill, and mixed and pulverized in 72 hours to obtain a raw material fine powder.

將所得到的原料微粉末進行造粒後，加壓成形為直徑10cm、厚度5mm的大小，將其置入燒成爐內，在氧氣加壓下，以1,400℃、48小時的條件燒成後得到燒結體(標靶)，此時，昇溫速度為3℃/分鐘。After the obtained raw material fine powder was granulated, it was press-molded into a size of 10 cm in diameter and 5 mm in thickness, and placed in a firing furnace, and fired at 1,400 ° C for 48 hours under oxygen pressure. A sintered body (target) was obtained, and at this time, the temperature increase rate was 3 ° C /min.

2.標靶的評估對所得到的標靶，測量密度、容積電阻值，結果為理論相對密度為99%，使用四探針法所測量的容積電阻值為0.8m Ω。2. Evaluation of Targets For the obtained targets, the density and volume resistance values were measured, and the theoretical relative density was 99%, and the volume resistance value measured by the four-probe method was 0.8 m Ω.

(2)透明半導體薄膜的成膜將上述(1)所得到的濺鍍靶，裝置於DC濺鍍法之一的DC磁控管濺鍍法的成膜裝置，於玻璃基板(可尼克1737)上使透明導電膜進行成膜。(2) Film Formation of Transparent Semiconductor Film The sputtering target obtained in the above (1) was applied to a film forming apparatus of a DC magnetron sputtering method which is one of DC sputtering methods on a glass substrate (Nikko 1737). The transparent conductive film is formed into a film.

此處的濺鍍條件，係基板溫度：25℃、到逹壓力：1×10－ 3 Pa、氣體環境的氣體：Ar100%、濺鍍壓力(全壓)：4×10－ 1 Pa、投入電力100W、成膜時間20分鐘。The sputtering conditions here are substrate temperature: 25 ° C, 逹 pressure: 1 × 10 - 3 Pa, gas atmosphere: Ar 100%, sputtering pressure (full pressure): 4 × 10 - 1 Pa, input power 100W, film formation time 20 minutes.

結果得到在玻璃基板上形成了膜厚約100nm的透明導電性氧化物之透明導電玻璃。As a result, a transparent conductive glass in which a transparent conductive oxide having a film thickness of about 100 nm was formed on a glass substrate was obtained.

再者，將所得到的膜組成用ICP法分析，原子比[In/(In＋Zn)為0.28、原子比為Zn/(In＋Zn)為0.72。Further, the obtained film composition was analyzed by ICP method, and the atomic ratio [In / (In + Zn) was 0.28, and the atomic ratio was Zn / (In + Zn) was 0.72.

(3)透明半導體薄膜的氧化處理將上述(2)所得到的透明半導體薄膜，以大氣中(氧存在下)150℃，加熱(大氣下熱處理)100小時，進行氧化處理。(3) Oxidation Treatment of Transparent Semiconductor Thin Film The transparent semiconductor thin film obtained in the above (2) was heated (atmospheric heat treatment) at 150 ° C for 100 hours in the air to carry out oxidation treatment.

(4)透明半導體薄膜的物性的評估藉由霍爾測量裝置測量上述(3)所得到的透明半導體薄膜的載子濃度、及霍爾移動度，載子濃度為2×101 5 cm－ 3 、霍爾遷移率為16cm2 /Vs。此外，由四端子法所測量的比電阻值為200 Ω cm。Carrier concentration (4) Evaluation of physical properties of the transparent semiconductor thin film by a Hall measuring means measures a transparent semiconductor thin film (3) obtained above, and the Hall mobility, carrier concentration of 2 × 10 1 5 cm - 3 The Hall mobility is 16 cm 2 /Vs. In addition, the specific resistance value measured by the four-terminal method was 200 Ω cm.

再者，藉由X線繞射確認其為非晶質膜。Further, it was confirmed to be an amorphous film by X-ray diffraction.

霍爾測量裝置、及其測量條件如下述。The Hall measuring device and its measuring conditions are as follows.

[霍爾測量裝置][Hall measuring device]

東陽公司製：Resi Test8310Dongyang company system: Resi Test8310

[測量條件][Measurement conditions]

室溫(25℃)、0.5[T]、AC磁場霍爾測量Room temperature (25 ° C), 0.5 [T], AC magnetic field Hall measurement

而且，關於此透明導電性氧化物的透明性，係分光光度計所測量的波長550nm的光線的光線穿透率為85%，而透明性亦優異者，此外，能帶間隙為夠大的3.3eV。Further, regarding the transparency of the transparent conductive oxide, the light transmittance of light having a wavelength of 550 nm measured by a spectrophotometer is 85%, and the transparency is also excellent, and the band gap is sufficiently large 3.3. eV.

[實施例2~7、比較例1~4][Examples 2 to 7, Comparative Examples 1 to 4]

原料的組成比、成膜條件、氧化處理條件如表1進行調整以外，其餘與實施例1同樣的製作及評估。The composition and ratio of the raw materials, the film formation conditions, and the oxidation treatment conditions were adjusted as shown in Table 1, and the same preparation and evaluation as in Example 1 were carried out.

此外，關於實施例、及比較例的半導體薄膜，如下述作法製造薄膜電晶體，進行評估。Further, regarding the semiconductor thin films of the examples and the comparative examples, thin film transistors were produced and evaluated as follows.

[頂閘型透明薄膜電晶體][Top Gate Transparent Thin Film Transistor]

PET基板上，使用除了成膜時間以外，使用與上述實施例1~7、比較例1~4同樣條件製成的30nm的透明半導體薄膜，如圖1所表示的構成，構成通道長度L＝10 μ m、通道寬度W＝150 μ m的頂閘型的薄膜電晶體。On the PET substrate, a 30 nm transparent semiconductor film which was produced under the same conditions as in the above Examples 1 to 7 and Comparative Examples 1 to 4 except for the film formation time was used, and the channel length L = 10 was formed as shown in Fig. 1 . Top gate type thin film transistor with μ m and channel width W=150 μ m.

此時，介電率高的氧化銦層合為厚度170nm後，作為閘絕緣膜使用，此外，使用厚度150nm的IZO作為閘電極、源電極、汲電極的各電極。At this time, indium oxide having a high dielectric constant is laminated to have a thickness of 170 nm, and is used as a gate insulating film, and IZO having a thickness of 150 nm is used as each electrode of a gate electrode, a source electrode, and a germanium electrode.

將所得到的薄膜電晶體，依下述基準評估，將結果與on－off一併列示於表1。The obtained thin film transistor was evaluated according to the following criteria, and the results were shown together with on-off in Table 1.

[評估基準][Evaluation Benchmark]

佳：即使重覆10次以上操作，I－V特性的滯後現象小。Good: Even if the operation is repeated more than 10 times, the hysteresis of the I-V characteristic is small.

稍佳：重覆10次以上操作，I－V特性發生大的滯後現象。Slightly better: Repeating 10 or more operations, the I-V characteristics have a large hysteresis.

不佳：重覆未逹10次操作，I－V特性發生大的滯後現象。Poor: Repeated 10 operations, the I-V characteristics have a large hysteresis.

以上，列示較佳的實施形態說本發明，惟當然本發明並非僅拘限於述實施形態者，且在本發明的範圍內可有各種的變更實施。The present invention has been described with reference to the preferred embodiments, and the invention is not limited thereto, and various modifications may be made without departing from the scope of the invention.

例如上述的實施形態中雖列舉薄膜電晶體，但本發明的半導體薄膜可適用於各種電場效果型電晶體。For example, in the above embodiment, a thin film transistor is used, but the semiconductor film of the present invention can be applied to various electric field effect type transistors.

[產業上的可利用性][Industrial availability]

本發明中之半導體薄膜，可作為薄膜電晶體等的電場效果型電晶體所使用的半導體薄膜被廣泛利用。The semiconductor thin film of the present invention can be widely used as a semiconductor thin film used for an electric field effect type transistor such as a thin film transistor.

1‧‧‧薄膜電晶體1‧‧‧film transistor

10‧‧‧源電極10‧‧‧ source electrode

20‧‧‧汲電極20‧‧‧汲 electrode

30‧‧‧閘電極30‧‧‧ gate electrode

40‧‧‧透明半導體薄膜40‧‧‧Transparent semiconductor film

50‧‧‧閘絕緣膜50‧‧‧Brake insulation film

60‧‧‧基板60‧‧‧Substrate

[圖1]係表示本發明相關的薄膜電晶體的實施形態的概略之說明圖。Fig. 1 is an explanatory view showing an outline of an embodiment of a thin film transistor according to the present invention.

1．．．薄膜電晶體1. . . Thin film transistor

10．．．汲電極10. . . Helium electrode

20．．．源電極20. . . Source electrode

30．．．閘電極30. . . Gate electrode

40．．．透明半導體薄膜40. . . Transparent semiconductor film

50．．．閘絕緣膜50. . . Gate insulating film

60．．．基板60. . . Substrate

Claims (13)

一種半導體薄膜，其為由含有氧化鋅與氧化銦之非晶質膜所成的半導體薄膜，其特徵係載子密度為10+17 cm-3 以下，霍爾遷移率為2cm2 /V．sec以上，能帶間隙為2.4eV以上，且藉由X線散射測量所得到的徑向分佈函數(RDF)中，原子間距離為0.3~0.36nm之間的RDF的最大值定為A，原子間距離為0.36~0.42nm之間的RDF的最大值定為B時，符合A/B>0.8的關係。A semiconductor film having an amorphous semiconductor thin film by containing zinc oxide and indium oxide formed by, wherein based carrier density of 10 +17 cm -3 or less, and a Hall mobility of 2cm 2 / V. Above sec, the band gap is 2.4 eV or more, and the radial distribution function (RDF) obtained by X-ray scattering measurement has a maximum value of ADF between 0.3 and 0.36 nm. When the maximum value of RDF between 0.36 and 0.42 nm is set to B, the relationship of A/B>0.8 is satisfied. 如申請專利範圍第1項之半導體薄膜，其中該非晶質膜中的鋅[Zn]與銦[In]的原子比為Zn/(Zn+In)=0.10~0.82。 The semiconductor thin film according to claim 1, wherein an atomic ratio of zinc [Zn] to indium [In] in the amorphous film is Zn/(Zn+In)=0.10 to 0.82. 如申請專利範圍第1項之半導體薄膜，其中該非晶質膜中的鋅Zn與銦In的原子比為Zn/(Zn+In)=0.51~0.80。 The semiconductor thin film according to claim 1, wherein an atomic ratio of zinc Zn to indium In in the amorphous film is Zn/(Zn+In)=0.51 to 0.80. 如申請專利範圍第1~3項中任一項之半導體薄膜，其中波長550nm的穿透率為75%以上。 The semiconductor film according to any one of claims 1 to 3, wherein a transmittance at a wavelength of 550 nm is 75% or more. 如申請專利範圍第1~3項中任一項之半導體薄膜，其係功函數為3.5~6.5eV的非退化半導體薄膜。 The semiconductor film according to any one of claims 1 to 3, which is a non-degenerate semiconductor film having a work function of 3.5 to 6.5 eV. 如申請專利範圍第1~3項中任一項之半導體薄膜，其中非晶質膜中分散奈米晶體。 The semiconductor film according to any one of claims 1 to 3, wherein the nanocrystal is dispersed in the amorphous film. 如申請專利範圍第1~3項中任一項之半導體薄膜，其係含有第三金屬元素[M]，該第三金屬元素[M]與銦[In]的原子比[M/(M+In)]為0~0.5。 The semiconductor film according to any one of claims 1 to 3, which contains a third metal element [M], an atomic ratio of the third metal element [M] to indium [In] [M/(M+ In)] is 0~0.5. 如申請專利範圍第1~3項中任一項之半導體薄膜， 其係含有第三金屬元素[M]，該第三金屬元素[M]與銦[In]的原子比[M/(M+In)]為0~0.3。 A semiconductor film according to any one of claims 1 to 3, It contains a third metal element [M], and the atomic ratio [M/(M+In)] of the third metal element [M] to indium [In] is 0 to 0.3. 一種半導體薄膜的製造方法，其特徵係製造如申請專利範圍第1~3項中任一項之半導體薄膜時，以氣體環境中的水H2 O的分壓成為10-3 Pa以下的條件，使含有氧化鋅與氧化銦之非晶質膜進行成膜。A method for producing a semiconductor thin film, which is characterized in that, when the semiconductor thin film according to any one of claims 1 to 3 is produced, the partial pressure of water H 2 O in a gas atmosphere is 10 -3 Pa or less. An amorphous film containing zinc oxide and indium oxide is formed into a film. 如申請專利範圍第9項之半導體薄膜的製造方法，其係包括將以基板溫度200℃以下經物理成膜的該非晶質膜進行氧化處理之步驟。 The method for producing a semiconductor thin film according to claim 9, which comprises the step of oxidizing the amorphous film which is physically formed at a substrate temperature of 200 ° C or lower. 一種薄膜電晶體，其特徵係具有半導體薄膜，該半導體薄膜係由含有氧化鋅與氧化銦之非晶質膜所成的半導體薄膜，其載子密度為10+17 cm-3 以下，霍爾遷移率為2cm2 /V．sec以上，能帶間隙為2.4eV以上之半導體薄膜，且藉由X線散射測量所得到的徑向分佈函數(RDF)中，原子間距離為0.3~0.36nm之間的RDF的最大值定為A，原子間距離為0.36~0.42nm之間的RDF的最大值定為B時，符合A/B>0.8的關係。A thin film transistor characterized by a semiconductor thin film which is a semiconductor thin film formed of an amorphous film containing zinc oxide and indium oxide, having a carrier density of 10 +17 cm -3 or less, Hall migration The rate is 2cm 2 /V. Above sec, a semiconductor film having a gap of 2.4 eV or more, and a radial distribution function (RDF) obtained by X-ray scattering measurement, a maximum value of RDF between 0.3 and 0.36 nm between atoms is defined as A, when the maximum value of RDF between the atoms is between 0.36 and 0.42 nm is set to B, the relationship of A/B>0.8 is satisfied. 如申請專利範圍第11項之薄膜電晶體，其中該半導體薄膜被配置於樹脂基板上。 The thin film transistor of claim 11, wherein the semiconductor thin film is disposed on a resin substrate. 一種主動矩陣驅動顯示面板，其特徵係具有申請專利範圍第11或12項之薄膜電晶體。An active matrix driven display panel characterized by having a thin film transistor of claim 11 or 12.
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