WO2007007861A1 - 多層プリント配線板 - Google Patents
多層プリント配線板 Download PDFInfo
- Publication number
- WO2007007861A1 WO2007007861A1 PCT/JP2006/314015 JP2006314015W WO2007007861A1 WO 2007007861 A1 WO2007007861 A1 WO 2007007861A1 JP 2006314015 W JP2006314015 W JP 2006314015W WO 2007007861 A1 WO2007007861 A1 WO 2007007861A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- printed wiring
- insulating substrate
- wiring board
- multilayer printed
- group
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims abstract description 128
- 239000004020 conductor Substances 0.000 claims abstract description 97
- 238000007747 plating Methods 0.000 claims description 36
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 230000006355 external stress Effects 0.000 abstract description 14
- 230000006866 deterioration Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 193
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 75
- 229910000679 solder Inorganic materials 0.000 description 52
- 239000011889 copper foil Substances 0.000 description 49
- 238000000034 method Methods 0.000 description 38
- 238000012545 processing Methods 0.000 description 27
- 229910052802 copper Inorganic materials 0.000 description 26
- 239000010949 copper Substances 0.000 description 26
- 239000002585 base Substances 0.000 description 25
- 239000000463 material Substances 0.000 description 25
- 229920005989 resin Polymers 0.000 description 25
- 239000011347 resin Substances 0.000 description 25
- 238000005530 etching Methods 0.000 description 23
- 230000008569 process Effects 0.000 description 21
- 238000012360 testing method Methods 0.000 description 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 16
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 14
- 238000011282 treatment Methods 0.000 description 13
- 239000004744 fabric Substances 0.000 description 12
- 239000011521 glass Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 239000000243 solution Substances 0.000 description 9
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- 230000008859 change Effects 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 8
- 239000003822 epoxy resin Substances 0.000 description 8
- 229910052759 nickel Inorganic materials 0.000 description 8
- 229920000647 polyepoxide Polymers 0.000 description 8
- 239000000654 additive Substances 0.000 description 7
- 230000000996 additive effect Effects 0.000 description 7
- 239000001569 carbon dioxide Substances 0.000 description 7
- 229910002092 carbon dioxide Inorganic materials 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 238000009413 insulation Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000007797 corrosion Effects 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 230000010355 oscillation Effects 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 5
- 239000002253 acid Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000011156 evaluation Methods 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000001771 impaired effect Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 2
- KWSLGOVYXMQPPX-UHFFFAOYSA-N 5-[3-(trifluoromethyl)phenyl]-2h-tetrazole Chemical compound FC(F)(F)C1=CC=CC(C2=NNN=N2)=C1 KWSLGOVYXMQPPX-UHFFFAOYSA-N 0.000 description 2
- NLXLAEXVIDQMFP-UHFFFAOYSA-N Ammonia chloride Chemical compound [NH4+].[Cl-] NLXLAEXVIDQMFP-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910000365 copper sulfate Inorganic materials 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000013532 laser treatment Methods 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229920003192 poly(bis maleimide) Polymers 0.000 description 2
- 229920002647 polyamide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229920001955 polyphenylene ether Polymers 0.000 description 2
- 235000011962 puddings Nutrition 0.000 description 2
- 239000002683 reaction inhibitor Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000001509 sodium citrate Substances 0.000 description 2
- NLJMYIDDQXHKNR-UHFFFAOYSA-K sodium citrate Chemical compound O.O.[Na+].[Na+].[Na+].[O-]C(=O)CC(O)(CC([O-])=O)C([O-])=O NLJMYIDDQXHKNR-UHFFFAOYSA-K 0.000 description 2
- 229910001379 sodium hypophosphite Inorganic materials 0.000 description 2
- 239000004071 soot Substances 0.000 description 2
- 239000007858 starting material Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- VZSRBBMJRBPUNF-UHFFFAOYSA-N 2-(2,3-dihydro-1H-inden-2-ylamino)-N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]pyrimidine-5-carboxamide Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C(=O)NCCC(N1CC2=C(CC1)NN=N2)=O VZSRBBMJRBPUNF-UHFFFAOYSA-N 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- AFCARXCZXQIEQB-UHFFFAOYSA-N N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CCNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 AFCARXCZXQIEQB-UHFFFAOYSA-N 0.000 description 1
- 229910021586 Nickel(II) chloride Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 235000019270 ammonium chloride Nutrition 0.000 description 1
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- KRVSOGSZCMJSLX-UHFFFAOYSA-L chromic acid Substances O[Cr](O)(=O)=O KRVSOGSZCMJSLX-UHFFFAOYSA-L 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000003851 corona treatment Methods 0.000 description 1
- 229960003280 cupric chloride Drugs 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 208000028659 discharge Diseases 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- AWJWCTOOIBYHON-UHFFFAOYSA-N furo[3,4-b]pyrazine-5,7-dione Chemical compound C1=CN=C2C(=O)OC(=O)C2=N1 AWJWCTOOIBYHON-UHFFFAOYSA-N 0.000 description 1
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical compound OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QMMRZOWCJAIUJA-UHFFFAOYSA-L nickel dichloride Chemical compound Cl[Ni]Cl QMMRZOWCJAIUJA-UHFFFAOYSA-L 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- JRKICGRDRMAZLK-UHFFFAOYSA-L peroxydisulfate Chemical compound [O-]S(=O)(=O)OOS([O-])(=O)=O JRKICGRDRMAZLK-UHFFFAOYSA-L 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
- XTFKWYDMKGAZKK-UHFFFAOYSA-N potassium;gold(1+);dicyanide Chemical compound [K+].[Au+].N#[C-].N#[C-] XTFKWYDMKGAZKK-UHFFFAOYSA-N 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000005361 soda-lime glass Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09863—Concave hole or via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/31504—Composite [nonstructural laminate]
- Y10T428/31511—Of epoxy ether
Definitions
- the present invention relates to a multilayer printed wiring board for mounting electronic parts such as capacitors and ICs on a surface layer. Specifically, the electronic parts are not dropped due to dropping, and electrical connectivity and reliability are not reduced.
- the present invention relates to a multilayer printed wiring board. Background art
- components mounted on such boards include passive components such as IC chips, capacitors, resistors, and inductors, liquid crystal devices, display devices that perform digital displays, keypads, and switches. There are operation system devices or external terminals such as USB and earphones.
- an opening for a via hole is formed by laser irradiation on an insulating base material having a conductor circuit on one side or both sides, and a metal is formed in the opening.
- a circuit board connected between layers is manufactured by forming a via hole by filling paced or mated, and two or more layers of this circuit board are prepared, and these circuit boards are laminated sequentially or collectively.
- There is a type manufactured by this method (refer to Japanese Patent Laid-Open No. 10-13 028).
- the via-hole or via-hole land of one adjacent circuit board is connected to the conductor circuit or land of the other circuit board, so that the two-layer circuit boards are electrically connected to each other. Is done. In other areas that do not contribute to the electrical connection of the circuit boards, multilayering is achieved by bonding the circuit boards together with an adhesive layer or prepreg made of a thermosetting resin.
- solder resist soot layer for protecting the conductor circuit is formed, and an opening is formed in a part of the solder resist soot layer.
- a corrosion-resistant layer such as gold or nickel metal is formed on the surface of the conductor circuit exposed from the solder, and a solder body such as a solder bump is formed on the surface of the conductor circuit on which such a corrosion-resistant layer is formed.
- the electronic parts such as capacitors and ICs are mounted via these solder bodies.
- the thickness of the substrate itself used for portable electronic devices is 100 / m or less, and the number of layers is increased.
- the overall thickness of the mounting board itself is required to be thinner than before, the rigidity of the mounting board itself tends to decrease.
- the insulating layer is thin, the mounting substrate itself is soft and easily warped, so that it is susceptible to the stress generated by external impacts.
- it has been studied to increase the rigidity by using a substrate having a thickness of 600 jum or more as the central insulating substrate when stacking, but it may not fit in a case such as a portable electronic device.
- the technology of increasing the thickness of the central insulating substrate cannot be used. Therefore, the conventional multilayer circuit board for mounting as described above cannot increase the rigidity by increasing the thickness of the insulating substrate, which is the center of the stack. Therefore, the function and start-up of the board are improved compared to the drop test in the reliability test.
- the present invention proposes a multilayer printed wiring board that can improve the reliability for the reliability test, further ensure the electrical connectivity and functionality, and particularly improve the reliability for the drop test. . Disclosure of the invention
- the present inventors have paid attention to the shape and laminated form of via holes that electrically connect conductor circuits in a multilayer circuit board, and at least one of such via holes Parts are formed with swelling in a direction substantially perpendicular to the thickness direction of the insulating layer, even if the insulating substrate constituting the substrate is made thin, the rigidity of the substrate is reduced, warpage occurs, etc. Based on such knowledge, the present invention having the following contents is completed.
- the via holes are at least one of the via holes.
- the multilayer printed wiring board is characterized by having a bulge in a direction substantially perpendicular to the thickness direction of the insulating layer.
- the present invention also provides
- At least one layer of another insulating substrate having a conductor circuit is laminated on both surfaces of one insulating substrate having a conductor circuit, and the conductor circuit provided on the one insulating substrate and the other insulating substrate are provided on the other insulating substrate. Conductor circuits are connected via via holes provided in each insulating substrate.
- the multilayer printed wiring board formed by air connection In the multilayer printed wiring board formed by air connection,
- Each of the via holes is a multilayer printed wiring board characterized in that at least a part thereof is formed to have a bulge in a direction substantially perpendicular to the thickness direction of the insulating substrate.
- the present invention provides:
- the insulating layer is at least three layers
- the via hole includes a first via group and a second via group
- the first via group has a bulge in a direction substantially perpendicular to the thickness direction of the insulating layer, and is formed of a via hole including two or more stacked vias,
- the second via group is formed of a via hole having a bulge in a direction substantially perpendicular to the thickness direction of the insulating layer,
- the first via group and the second via group are multi-layer printed wiring boards arranged at opposing positions.
- the insulating layer or the insulating substrate can have a thickness of 1 O O jW m or less.
- the insulating layer or the insulating substrate may have a thickness of 50 / m or less.
- the via hole can be stacked in the form of a multistage stacked via, and the via hole provided in the insulating substrate laminated on one surface of the one insulating substrate having the conductor circuit is the first.
- One via group can be used, and a via hole provided in an insulating substrate stacked on the other surface of the one insulating layer substrate can be used as the second via group.
- the first via group is stacked in a positional relationship so as to face the second via group: and the thickness direction of the insulating layer with respect to the second peer group
- the layers can be stacked in a positional relationship shifted in a direction substantially perpendicular to the direction.
- the via holes constituting the first via group or the second via group can be stacked so as to be located on substantially the same straight line, and are mutually perpendicular to the thickness direction of the insulating layer.
- the layers can be stacked in a positional relationship shifted in the direction.
- a via hole constituting either one of the first via group or the second via group is located at two opposing vertices of a virtual square lattice on the insulating substrate, and the other via group Can be configured to be located at the other two opposite vertices of the virtual square lattice on the insulating substrate.
- a via hole constituting either one of the first via group or the second via group is located at each vertex of a virtual square lattice or a triangular lattice on the insulating substrate, and the other via group Can be configured to be positioned at the center of a virtual square lattice or a triangular lattice on the insulating substrate.
- the via holes constituting one of the first via group and the second via group are concentrated in a predetermined region of the insulating substrate, and the via holes constituting the other via group are
- the insulating substrate may be disposed in a peripheral region surrounding the predetermined region.
- each of the above-mentioned via holes can be formed in a via barrel shape in which the diameter of the portion where the bulge is maximum is 1.5 times the opening diameter on the top surface or bottom surface of the insulating layer.
- Each via hole can be formed by filling an opening in an insulating layer or an insulating substrate.
- the via hole for electrically connecting the conductor layers is formed so as to have a bulge in a direction substantially perpendicular to the thickness direction of the insulating layer at least in part. It is possible to suppress the warping of the insulating layer against the external stress generated (which refers to the impact force generated when dropped).
- each via hole can be stacked to form a multi-stage stacked via structure, so when external stress is applied to the substrate and the insulating layer warps outward, the multi-stage stacked via fits into the insulating layer.
- the insulating resin and the conductor layer forming the multistage stacked via are difficult to peel off.
- the reliability of the mounting board can be reduced, and the drop in drop resistance can be reduced.
- the multi-stage stack via functions as a pile, so that the warping of the insulating layer can be suppressed. As a result, the external stress transmitted to the insulating layer can be reduced, so that the reliability of the mounting board can be reduced and the drop resistance can be reduced.
- the multi-stage stacked via is formed inside the insulating layer, it can serve as a pile against the warping of the insulating layer, making it difficult to warp the insulating layer. Therefore, since the flatness of the substrate is not impaired, even if a reliability test such as a heat cycle condition is performed, a crack or the like does not occur at an early stage in a conductor circuit or an insulating layer including a via hole. The reliability of the mounting board does not deteriorate.
- the insulating layer or the insulating substrate has a thickness of l OO jt m or less, and a conductor circuit is provided in such an insulating layer, and the mounting substrate is formed by multilayering them, the warping of the mounting substrate is suppressed, This is useful in that flatness is ensured. The same effect can be obtained even if the thickness of the insulating layer or the insulating substrate is 5 O jum or less.
- multi-stage stacked vias (first via group and second via group) at opposite positions, it is effective against both the outer and inner warping of the insulating layer. Can do. That is, when the insulating layer warps due to external stress, the resistance to external stress does not decrease due to the presence of the multistage stacked via against the outward and inward warping. As a result, the reliability of the mounting board can be reduced, and the drop resistance can be reduced.
- the multistage stacked vias are formed at opposing positions, the rigidity of the insulating substrate itself is increased in such a region. Therefore, the warpage of the mounting substrate itself can be reduced, and the flatness of the mounting substrate can be maintained in the post-process (for example, solder resist forming process, solder layer forming process, mounting process of electronic components, etc.). There will be no disadvantages such as dropout of mounted parts. As a result, it is possible to reduce the significant decrease in electrical connectivity and reliability of the mounting board.
- FIG. 1A is a schematic view for explaining via barrel-shaped via holes in the multilayer printed wiring board of the present invention
- FIG. 1B is a print having via barrel-shaped via holes. It is a SEM photograph which shows the cross section of a wiring board.
- FIG. 2 is a schematic view showing one of the basic forms of the multi-stage stacked via in the multilayer printed selfish wire board of the present invention.
- FIGS. 3A to 3B are schematic views showing modifications of the multistage stacked via.
- FIG. 4 is a schematic view showing another basic form of the multistage stacked via in the multilayer printed wiring board of the present invention.
- FIGS. 5A to 5C are schematic views showing an example (square lattice arrangement) of planar arrangement patterns of via holes constituting a multistage stacked via.
- FIG. 6 is a schematic view showing another example (triangular lattice arrangement) of a planar arrangement pattern of via holes constituting a multistage stacked via.
- FIG. 7 is a schematic view showing still another example (linear arrangement) of the planar arrangement pattern of the via holes constituting the multistage stacked via.
- FIGS. 8A to 8B are schematic views showing still other examples (concentrated arrangement, distributed arrangement) of planar arrangement patterns of via holes constituting a multistage stacked via.
- 9A to 9E are diagrams showing a part of the process for manufacturing the multilayer printed wiring board according to Example 1 of the present invention.
- FIGS. 1A to 1 O E are diagrams showing a part of a process for manufacturing a multilayer printed wiring board according to Example 1 of the present invention.
- FIG. 11 is a diagram showing a part of a process of manufacturing the multilayer printed wiring board according to Example 1 of the present invention.
- FIGS. 12A to 12B are diagrams showing a part of a process for manufacturing a multilayer printed wiring board according to Example 1 of the present invention.
- the via hole for electrically connecting the conductor layers is formed so as to have a bulge in a direction substantially perpendicular to the thickness direction of the insulating layer at least in part. It is characterized by.
- At least one layer of another insulating substrate having a conductor circuit is laminated on both surfaces of one insulating substrate having a conductor circuit, and the conductor provided on the one insulating substrate is provided.
- a multilayer printed wiring board in which a body circuit and a conductor circuit provided on another insulating substrate are electrically connected via via holes provided on each insulating substrate, each via hole is at least partially on the insulating substrate.
- the multilayer printed wiring board is characterized by having a bulge in a direction substantially perpendicular to the thickness direction.
- Examples of the insulating layer or the insulating substrate used in the present invention include a glass cloth epoxy resin base material, a phenol resin base material, a glass cloth bismaleimide triazine resin base material, a glass cloth polyphenylene ether resin base material, and aramid. Examples thereof include a hard laminated base material selected from a nonwoven fabric-epoxy resin base material, a ramid nonwoven fabric-polyimide resin base material, and the like.
- the thickness of the substrate made of such an insulating resin is desirably 100 jum or less. Further, the thickness of the substrate made of an insulating resin may be 50 m or less.
- a circuit board in which a conductor circuit is formed on one or both sides of such an insulating layer or an insulating substrate is used as a stacking center, and insulating layers and conductor layers are alternately stacked on the surface of the circuit board to produce a multilayer print.
- a wiring board (mounting board) is obtained. Further, by reducing the thickness of the insulating layer or insulating substrate in such a mounting substrate to 100 / m or less, the thickness of the multilayer mounting substrate itself can be reduced.
- the conductor circuit and the via holes (multi-stage stacked vias) respectively constituting the first and second via groups, which are provided on the insulating substrate are formed by using a plating process.
- the reason for this is that the connection parts between the via holes constituting the first via group or the second via group and the conductor circuits that contact the upper and lower surfaces of the via holes, respectively, are formed by the same plating process. This is because peeling does not easily occur, and there is no displacement even when external stress is applied from the side surface, so that cracks or the like hardly occur in the conductor circuit or the insulating layer.
- the plating film used for forming the via hole is preferably formed by electrolytic plating or electroless plating.
- the metal used for plating may be a single metal such as copper, nickel, iron, or cobalt, or may be an alloy mainly composed of these metals.
- the via hole in the present invention is formed to have a bulge in a direction substantially perpendicular to the thickness direction of the insulating layer. However, it is desirable to form a so-called via barrel shape in which the diameter between the top surface and the bottom surface is larger.
- a bulge that has the smallest diameter on the top or bottom surface of the via hole and that has the largest diameter is formed in at least a part of the via hole, for example, just in the middle portion between the top surface and the bottom surface.
- Such a bulge is formed with a diameter that is 1.1 to 1.5 times the opening diameter (minimum diameter) on the top or bottom surface, that is, when the diameter on the top or bottom surface is D, It is desirable that the diameter of the portion where the diameter is the maximum is 1.1 D to 1.5 D.
- the reason is that if the diameter of the portion where the bulge is the maximum is less than 1.1 D, the via barrel shape is not achieved and the effect cannot be exhibited. On the other hand, if the diameter of the portion where the bulge is maximum exceeds 1.5 D, it is difficult to fill the via hole forming opening with a conductive material such as plating and the interlayer insulation between adjacent via holes. This is because it may be difficult to secure an insulation gap between layers, and as a result, connectivity and reliability will be reduced.
- the diameter on the upper surface side of the via hole in the present invention is preferably in the range of 50 to 25 50 j! M. This is because if the diameter on the upper surface side is less than 50 m, it is difficult to form a conductor layer in the via. If it exceeds 25 50; um, the via shape in the present invention (in the thickness direction of the insulating layer) This is because the formation of the conductor layer is likely to be impaired in a shape having a bulge in a substantially perpendicular direction), and it may be difficult to secure a gap between adjacent vias.
- the via diameter on the bottom side may be at least 10 jt m in diameter.
- the reason for this is that the via formation is formed by an adhesion process, and the formation of the adhesion film requires a via bottom diameter of at least about 10 wm ⁇ 2, so that the upper conductor layer (upper layer The conductor circuit and peer) can be connected to the underlying conductor circuit.
- via holes (upper layer It is preferable that the bottom surface of the via hole and the bottom surface of the inner via hole (lower via hole) overlap at the same position. That is, as shown in FIG. 2, in the plurality of via holes constituting the first via group or the second via group, the via holes can be formed so as to be on substantially the same straight line.
- the via holes are shifted to each other in a direction substantially perpendicular to the thickness direction of the insulating layer, and the bottom surfaces of the via holes are formed. However, they can be laminated at a position where at least a part of the insulating substrate overlaps in the thickness direction.
- a plurality of via holes that respectively constitute the first via group or the second via group can be stacked at positions shifted from each other by about 1/2 of the via hole diameter.
- a plurality of via holes that respectively constitute the first via group or the second via group can be stacked at a position S that is shifted from each other by substantially the via hole diameter.
- the first via group or the second via group constituting the multistage stack peer in the present invention is formed by providing at least two or more insulating substrates and laminating via holes provided in those insulating substrates. It is preferable. That is, the first via group or the second via group may be configured by stacking three, four, or more via holes.
- Each stacked via that is, the first via group and the second via group may have the same number of stacked layers (for example, first via group: three layers, second via group: three layers). However, the number of stacked layers may be different (for example, first via group: two layers, second via group: three layers).
- first and second via groups that make up the multistage stacked via By forming them in an opposing positional relationship, it is possible to achieve an effect that the electrical connectivity and reliability of the mounting substrate are not significantly reduced.
- the multistage stacked via in the present invention may be a conductor layer having electrical connection, or may be a conductor layer without electrical connection, a so-called dummy conductor layer.
- a conductor layer other than a dummy refers to a conductor layer having electrical connection in a conductor layer existing around the dummy conductor layer or an opposing multistage stack via)
- the drop resistance does not decrease and the warping of the mounting board can be reduced, so that the flatness of the mounting board can be ensured.
- the first via group and the second via group constituting the multistage stacked via in the present invention are substantially at the same position within the region where the conductor circuit of each insulating substrate is formed. Or are on the same straight line, or Figure 3A or Figure
- the resistance to warpage due to external stress can be improved by evenly distributing the first via group and the second via group over the entire area of the insulating substrate.
- first via group and / or the second via group which are most susceptible to warping due to external stress, are arranged centrally in the central part of the insulating substrate, making it resistant to warping due to external stress. Can be improved.
- first via group and / or the second via group can be arranged in a peripheral portion mainly surrounding the central portion of the insulating substrate without being arranged in the central portion of the insulating substrate.
- Such an arrangement can improve the resistance of the printed circuit board against warping, ensure the flatness of the mounting board, and provide resistance to external stress.
- first via group and the second via group are arranged opposite to each other mainly in the central portion of the insulating substrate, and the first via group and the second via group are mutually shifted in the peripheral portion. It can also be arranged in the state.
- the multi-level stack vias may be arranged in a square lattice pattern (see FIGS. 5A to 5C), a triangular lattice pattern (see FIG. 6), or a straight line pattern (see FIG. (See 7).
- a first via group and a second via group are arranged with regularity in a virtual square matrix as shown in FIG. 5A.
- the first via group can be arranged in a virtual matrix as shown in Fig. 5B, and the second via group facing the middle part of the matrix can be arranged, as shown in Fig. 5C.
- the first via group and the second via group may be arranged with a staggered virtual matrix-like regularity.
- the first via group is arranged in a virtual triangle shape as shown in FIG.
- a via group may be arranged.
- first via groups are arranged in a virtual straight line as shown in FIG. 7 and face the vicinity of the central part of the straight line.
- a second via group may be arranged.
- a multi-stage stack via can be constituted by a combination of two or more of these patterns.
- the second via group can be arranged opposite to a region where the first via group is not formed.
- the first via group is arranged in a matrix in a plan view
- the second via II is arranged in a matrix form in a region where the first via group is not formed, or the first via group is arranged.
- Examples include a pattern in which the group is arranged mainly in the center of the substrate and the second via group is arranged in the periphery of the substrate (see Fig. 8 (b)).
- the first via group is indicated by an O mark and the second via group is indicated by an X mark.
- the arrangement may be opposite to the above arrangement.
- the size of the via diameter may be the same for the first via group and the second via group, or may be different diameters.
- a circuit board as a basic unit constituting the multilayer printed wiring board has a copper foil attached to one side or both sides of an insulating substrate. Can be used as starting material.
- This insulating base material is, for example, a glass cloth epoxy resin base material, a glass cloth bismaleimide triazine resin base material, a glass cloth polyphenylene ether resin base material, a polyamide nonwoven fabric-an epoxy resin base material, a polyamide nonwoven fabric-polyimide resin base.
- a hard laminated substrate selected from materials is used, and a glass cloth epoxy resin substrate is most preferable.
- the thickness of the insulating substrate is preferably 10 Om or less, and more preferably in the range of 30 to 7 Om. The reason for this is that when the thickness exceeds 100 jum, there is a concern that the thickness of the substrate itself is too large to fit in the case when it is multi-layered.
- a direct laser method in which a copper foil and an insulating base material are simultaneously drilled by laser irradiation, and a copper foil portion corresponding to the via hole of the copper foil is etched.
- the insulating base material is perforated by laser irradiation after removal by (2), but either of them may be used in the present invention.
- the thickness of the copper foil affixed to the insulating substrate 5 ⁇ 2 0 ji m is desirable.
- the reason for this is that when the copper foil thickness is less than 5 m, the end face portion of the copper foil corresponding to the via hole position is formed when the via hole forming opening is formed in the insulating base material using laser processing as described later. This is because it is difficult to form a conductor circuit of a predetermined shape. Further, it is difficult to form a conductor circuit pattern having a fine line width by etching. On the other hand, if the thickness of the copper foil exceeds 2 O jU m, it is difficult to form a conductor circuit pattern with a fine line width by etching.
- the thickness of this copper foil may be adjusted by one fetching.
- the thickness of the copper foil is larger than the above value, and is adjusted so that the thickness of the copper foil after etching falls within the above range.
- the copper foil thickness is in the above range, but the thickness may be different on both sides. As a result, the strength can be ensured and subsequent processes can be prevented from being hindered.
- a pre-preda made into a B stage by impregnating an epoxy resin in a glass cloth, and a copper foil are laminated and heated and pressed. It is preferable to use a single-sided or double-sided copper-clad laminate obtained from the above.
- the reason is that the position of the wiring pattern and via hole is not shifted during the manufacturing process after the copper foil is etched, and the positional accuracy is excellent.
- an opening for forming a via hole is provided in the insulating base material by laser processing.
- carbon dioxide laser irradiation is performed on one surface of the insulating base material to which the copper foil is applied, and penetrates both the copper foil and the insulating base material. Forming an opening reaching the copper foil (or conductor circuit pattern) affixed to the other surface of the insulating base material, or on the surface of one copper foil affixed to the insulating base material, slightly larger than the via hole diameter.
- Such laser processing is performed by a pulse oscillation type carbon dioxide laser processing apparatus.
- the processing condition is that the side wall of the via hole forming opening swells in a direction substantially perpendicular to the thickness direction of the insulating layer, and the swell is maximum.
- the diameter at the central part is determined to be 1 1 0 to 1 5 0% of the diameter of the via hole forming opening (minimum opening diameter).
- the pulse energy is 0.5 to 1 OO m J
- the pulse width is 1 to 100 ⁇ s
- the pulse interval is 0.5 ms or more
- the number of shots is 2
- the diameter of the opening for forming a via hole that can be formed under the above processing conditions is preferably 50 to 2500 jum. Within this range, it is possible to reliably form the bulge of the opening side wall and to achieve high density wiring.
- This desmear treatment is performed by wet treatment such as chemical treatment of an acid or an oxidizing agent (for example, chromic acid, permanganic acid), dry treatment such as oxygen plasma discharge treatment, corona discharge treatment, ultraviolet laser treatment, or excimer laser treatment. Is called.
- wet treatment such as chemical treatment of an acid or an oxidizing agent (for example, chromic acid, permanganic acid)
- dry treatment such as oxygen plasma discharge treatment, corona discharge treatment, ultraviolet laser treatment, or excimer laser treatment. Is called.
- the via shape in the present invention (A shape having a bulge in a direction substantially perpendicular to the thickness direction of the insulating layer) can be reliably formed.
- the copper foil surface of the desmeared substrate is subjected to an electrolytic copper plating process using the copper foil as the lead, and the opening is completely filled with the electrolytic copper plating.
- a via (filled via) is formed.
- the electrolytic copper plating that rises above the via hole opening of the substrate may be removed by belt sander polishing, buff polishing, etching, or the like for planarization.
- an electrolytic copper plating process may be performed.
- the electroless plating film may be made of a metal such as copper, nickel or silver.
- an etching resist layer is formed on the electrolytic copper plating film formed on the substrate in (4).
- the etching resist layer may be either a method of applying a resist solution or a method of applying a film-like one in advance.
- a mask on which a circuit is drawn in advance is placed on the resist layer, and an etching resist layer is formed by exposure and development, and a metal layer in a portion where no etching resist is formed is etched to form a conductor circuit and a land.
- a conductor circuit pattern containing is formed.
- the etching solution is preferably at least one aqueous solution selected from an aqueous solution of sulfuric acid monohydrogen peroxide, persulfate, cupric chloride, and ferric chloride.
- a pretreatment for forming a conductor circuit by etching the copper foil and electrolytic copper plating film In order to easily form a fine pattern, the thickness may be adjusted in advance by etching the entire surface of the electrolytic copper plating film.
- the land as part of the conductor circuit should have an inner diameter that is almost the same as the via hole diameter, or an outer diameter that is larger than the via hole diameter, and a land diameter in the range of 75 to 35 O jU m. Is preferred. The reason is that by setting the land diameter within the above range, even if the via position is shifted, it can serve as a multistage stacked via. -An insulating resin layer and a copper foil are laminated on one side or both sides of the circuit board produced according to the steps (1) to (5) as a lamination center. As a result, a substrate in which only one or two insulating resin layers are formed is obtained.
- the insulating resin layer is multi-layered by sequentially laminating the insulating resin layer. If necessary, the insulating resin layer is laminated, and the circuit board having the insulating resin layer of one unit is formed. Two or more layers may be laminated and heated and pressed together to form a multilayer printed wiring board.
- the via hole formed in each laminated circuit board or each insulating resin layer has a diameter of an intermediate portion of the insulating layer exposed on the upper surface of the insulating layer. It is formed in a via barrel shape that is larger than the diameter of the part or the diameter of the part exposed on the lower surface of the insulating layer.
- the via hole formed in at least one insulating resin layer including the circuit board serving as the stacking center constitutes the first via group and is disposed to face the insulating resin layer constituting the first via group.
- the via holes formed in at least one other insulating resin layer to be laminated constitute a second via group. These first and second via groups constitute a multistage stacked via.
- a solder resist layer is formed on the surface of the outermost circuit board.
- apply the solder resist composition to the entire outer surface of the circuit board, and After the coating film is dried, a photomask film on which the solder pad opening is drawn is placed on this coating film, exposed, and developed, so that the conductive pad portion located immediately above the via hole of the conductor circuit A solder pad opening exposing each is formed.
- a solder resist layer in the form of a dry film may be attached, and the opening may be formed by exposure-development or laser.
- a corrosion-resistant layer such as nickel or gold is formed on the solder pad exposed from the portion where the photomask is not formed.
- the thickness of the nickel layer is preferably 1 to 7 jtim
- the thickness of the gold layer is preferably 0.01 to 0.1 jtim.
- nickel-palladium-gold, gold (single layer), silver (single layer), etc. may be formed.
- the mask layer is peeled off. As a result, a printed wiring board in which a solder pad having a corrosion-resistant layer and a solder pad having no corrosion-resistant layer are mixed is obtained.
- a solder body is supplied to the solder pad portion exposed immediately above the via hole from the opening of the solder resist obtained in the step (6), and solder bumps are formed by melting and solidifying the solder body, or A conductive pole or conductive pin is joined to the pad portion using a conductive adhesive or solder layer to form a multilayer circuit board.
- a solder transfer method or a printing method can be used as a method for supplying the solder body and the solder layer.
- solder transfer method a solder foil is bonded to a prepreg, and the solder foil is etched leaving only a portion corresponding to the opening, thereby forming a solder pattern to form a solder carrier film.
- This is a method in which a film is laminated so that the solder pattern comes into contact with the pads after the flux is applied to the solder-resist opening of the substrate, and this is heated and transferred.
- the printing method is a method in which a printing mask (metal mask) having an opening at a position corresponding to a pad is placed on a substrate, solder paste is printed, and heat treatment is performed.
- solder to form such solder bumps Sn ZA g solder, Sn / In solder, Sn ZZ n solder, S ⁇ ⁇ ⁇ solder, etc. can be used, and their melting points are It is desirable that the melting point of the conductive bumps connecting the circuit boards be lower. (Example 1)
- a circuit board is manufactured as one unit constituting a multilayer printed wiring board.
- This circuit board is the board that should be the lamination center among the multiple insulation layers that should be laminated.
- the glass cloth is impregnated with epoxy resin and a B-stage pre-preg and copper foil are laminated and heated. Is used as a starting material (see FIG. 9A).
- the insulating substrate 12 had a thickness of 60 m, and the copper foil 14 had a thickness of 12 jUm.
- the thickness of the copper foil may be adjusted to 12 m by an etching process using a copper foil of this laminated board thicker than 12 j «m.
- Double hole circuit board 10 with copper foil 14 is irradiated with carbon dioxide laser to form via holes that penetrate copper foil 14 and insulating substrate 12 to reach the copper foil on the opposite surface Opening 16 was formed, and within 1 hour after laser processing, the inside of the opening formed by laser processing was desmeared by chemical treatment with permanganic acid (see Fig. 9B).
- the via hole forming opening 16 is formed using a high peak short pulse oscillation type carbon dioxide laser processing machine manufactured by Tatetsu Via Co., Ltd., and a copper foil having a thickness of 12 ⁇ m is formed.
- the applied glass cloth epoxy resin base material with a thickness of 60 ⁇ m was irradiated with a laser beam on a copper foil under the following processing conditions.
- An opening 16 of 1 00 was formed at a speed of 1 00 holes leap second.
- the inner wall of the opening swells in a direction substantially perpendicular to the thickness direction of the insulating layer, and the diameter of the most swelled middle part is the diameter of the part exposed on the upper surface of the insulating layer.
- the shape of the via barrel was 1.2 times the diameter of the portion exposed on the lower surface of the insulating layer.
- Pulse width "! ⁇ 1 00 j « s
- Pulse interval 0.5 ms or more
- Additive A (reaction accelerator): 1 0. 0 m I / I
- Additive B (Reaction Inhibitor): 1 0. 0 m I / I
- Additive A promotes the formation of an electrolytic copper plating film in the opening for forming the rebar hole, and conversely, the additive B adheres mainly to the copper foil portion to suppress the formation of the electrolytic copper plating film. Also, when the inside of the opening for forming the via hole is completely filled with electrolytic copper plating, and when the level is almost the same as copper foil 14, additive B is attached, so that the copper plating plating is the same as the copper foil portion. Film formation is suppressed.
- a via hole 20 formed by filling electrolytic copper plating into the opening 16 is formed, and the surface of the via hole 20 and the copper foil surface are formed at substantially the same level.
- the thickness may be adjusted by etching a conductor layer made of copper foil 14 and an electrolytic copper plating film. If necessary, the thickness of the conductor layer may be adjusted by physical methods of sander belt polishing and buff polishing.
- a resist made of a photosensitive dry film is applied to a conductive layer made of copper foil 14 and an electrolytic copper plating film. It was formed to a thickness of m.
- a mask on which a conductor circuit including via-hole lands was drawn was placed on this resist, and then exposed and developed to form an etching resist layer 22 (see FIG. 9D).
- the copper foil 14 and the electrolytic copper plating film exposed from the non-etching resist forming portion were subjected to an etching process using an etching solution made of hydrogen peroxide and sulfuric acid to be dissolved and removed.
- the etching resist layer 22 is peeled off using an alkaline solution, and a conductor circuit pattern 24 including a via hole land is formed.
- a via hole 20 that electrically connects the conductor circuits on the front surface and the back surface of the substrate is formed, and a circuit board is obtained in which the via hole 20 and the copper foil portion forming the conductor circuit 24 are planarized (see FIG. 9E).
- step (3) carbon dioxide laser irradiation is performed on both surfaces of the substrate under the following processing conditions to penetrate the resin insulating layer 26 and the conductor layer 28. And reach the underlying conductor circuit 24 85 j «m0 via-pole forming opening
- the opening 30 was formed at a speed of 1 hole / second, and then the inside of the opening formed by laser processing was desmeared by chemical treatment with permanganic acid (see OB in Fig. 1).
- the opening 30 formed under such conditions has an inner wall of the opening swelled in a direction substantially perpendicular to the thickness direction of the insulating layer.
- the shape of the via barrel was 1.2 times the diameter or the diameter of the exposed portion of the insulating layer.
- Pulse width "! ⁇ 1 00 jW s
- Pulse interval 0.5ms or more
- Oscillation frequency 2000 to 3000Hz
- Additive A (Reaction accelerator) 1 0.0 m I / I
- Additive B (Reaction inhibitor) 1 0.0 m I / I
- a resist ridge made of a photosensitive dry film was formed to a thickness of 15 to 2 Ojum on the electrolytic copper plating obtained in the above (8).
- An etching resist layer 36 was formed by placing a mask on which conductive circuits, lands of via holes 34, etc. were placed on this resist, aligning the substrate, and performing exposure and development processing (see FIG. 10D). ).
- the etching resist layer 36 is peeled off with an alkali solution to form a conductor circuit 38 including the via hole 34 and its land.
- a circuit board is obtained in which the via hole 34 connecting the front and back sides of the board and the copper foil portion forming the conductor circuit 38 are flattened (see FIG. 1 OE).
- one more resin insulation layer 40 is formed, and electrolytic copper plating is filled in the opening provided in the resin insulation layer 40.
- a via hole 42 is formed, and a conductor circuit pattern 44 including a via hole land is formed.
- a multi-layered printed circuit board in which two insulating layers and conductor circuits are formed on both sides of the double-sided circuit board 10 respectively.
- a wiring board can be obtained (see Fig. 11).
- a multilayer printed wiring board with 5 insulating layers and 6 conductor circuits is formed, and the via hole formed in the double-sided circuit board and the two insulating layers stacked above it has an opening inner wall. It swells in a direction almost perpendicular to the thickness direction of the insulating layer, and the diameter of the most swollen middle part is 1.2 times the diameter of the part exposed on the top surface of the insulating layer or the diameter of the part exposed on the bottom surface of the insulating layer
- the via hole formed in the two insulating layers stacked below the double-sided circuit board is also the same via barrel as the first via group.
- a second via group having a shape was formed, and the via groups were arranged so as to face each other and to be substantially collinear.
- a solder resist layer 46 was formed on the surfaces of the two insulating layers located on the outermost sides of the substrate obtained in (1 0).
- a film-formed solder resist having a thickness of 20 to 30 m was pasted on the surface of the insulating layer on which the conductor circuit 38 was formed.
- a 5 mm thick soda lime glass with a solder resist ⁇ opening circular pattern (mask pattern) drawn by a chrome layer The side where the chrome layer was formed was brought into close contact with the solder resist layer 46 and exposed to ultraviolet rays of 1 000 mJ / cm 2 , and DMTG development processing was performed.
- a roughening layer can be provided as necessary.
- the substrate on which the Solder Regis layer 46 is formed is electroless with a pH of 5 consisting of 30 g / 1 nickel chloride, 1 OgZl sodium hypophosphite and 1 O g / 1 sodium citrate.
- a nickel plating layer having a thickness of 5 / m was formed on the surface of the conductor circuit 38 exposed from the opening 48 by being immersed in a nickel plating solution for 20 minutes.
- the substrate was composed of 2 g of potassium gold cyanide I, 75 g of ammonium chloride, 50 g / 1 of sodium citrate, and 10 g of sodium hypophosphite. Soaked in an electroless gold plating solution at 93 ° C for 23 seconds to form a gold plating layer with a thickness of 0.03 / m on the nickel plating layer.
- a conductor pad 50 covered with a metal layer composed of a cover layer was formed.
- the via holes constituting the first via group and the second via group formed in the insulating layers stacked on the front and back surfaces of the double-sided circuit board are approximately equal to each other in via hole diameter.
- a multilayer printed wiring board was manufactured in substantially the same manner as in Example 1 except that it was formed at a position shifted by a distance of 1/2.
- a multilayer pudding and wiring board was manufactured in substantially the same manner as in Example 1 except that they were formed at positions shifted from each other by about the via hole diameter.
- Multi-layer printed wiring in which two insulating layers are stacked above the double-sided circuit board, and one insulating layer is stacked below the double-sided circuit board.
- the number of insulating layers is 4 and the number of conductor circuits is 5.
- a multilayer printed wiring board was produced in substantially the same manner as in Example 1 except that the board was formed.
- a multilayer printed wiring board was manufactured in substantially the same manner as in Example 2, except that a multilayer printed wiring board having 4 insulating layers and 5 conductor circuits was formed. .
- a multi-layer printed circuit in which two insulating layers are stacked above the double-sided circuit board, and one insulating layer is stacked below the double-sided circuit board.
- the number of insulating layers is 4 and the number of conductor circuits is 5.
- a multilayer printed wiring board was manufactured in substantially the same manner as in Example 3 except that the wiring board was formed.
- the first via group formed in the double-sided circuit board and the insulating layer stacked above the double-sided circuit board is formed in the insulating layer stacked below the double-sided circuit board.
- a multilayer printed wiring board was manufactured in substantially the same manner as in Example 1 except that the layers were stacked in a positional relationship shifted in the horizontal direction by about the via hole diameter.
- a multi-layer printed circuit in which two insulating layers are stacked above the double-sided circuit board, and one insulating layer is stacked below the double-sided circuit board.
- the number of insulating layers is 4 and the number of conductor circuits is 5.
- a multilayer printed wiring board was manufactured in substantially the same manner as in Example 7 except that a wiring board was formed.
- the via hole forming the first peer group is located at two opposite vertices of a virtual square lattice (lattice spacing: 1 O mm) on the insulating substrate, and the other via group 3 ⁇ 4
- a multilayer printed wiring board was manufactured in substantially the same manner as in Example 4 except that the via hole to be formed was laminated so as to be positioned at the two opposite vertices of the virtual square lattice on the insulating substrate.
- the via hole forming the first via group is located at each vertex of a virtual square lattice (lattice spacing: 1 O mm) on the insulating substrate as shown in FIG. 5B, and forms the other via group. Except for stacking the via hole so as to be positioned at the center of the virtual square lattice Produced a multilayer printed wiring board in substantially the same manner as in Example 4.
- the via holes forming the first via group are located at the vertices of a virtual triangular lattice (lattice spacing: 20 mm) on the insulating substrate, and the via holes forming the second via group are formed.
- a multilayer printed wiring board was manufactured in substantially the same manner as in Example 4 except that was laminated at the center of the virtual triangular lattice.
- the via holes constituting the first via group are located substantially in the center of the insulating substrate, and are concentratedly arranged in a region of 4 Omm ⁇ 4 Omm. Except that the via holes that make up the group were placed in the peripheral area surrounding the central part (outside the 40 mm x 4 OmmC central area and inside the 70 mm x 100 mm area), it was almost the same as in Example 4. A multilayer printed wiring board was manufactured.
- a multilayer printed wiring board was manufactured in substantially the same manner as in 1.
- Pulse energy 0.5 ⁇ 1 00m j
- Desmear ⁇ The reason was 2 hours after laser processing.
- Example 1 A multilayer printed wiring board was manufactured. (Laser processing conditions)
- Pulse interval 0.5 ms or more
- the desmear treatment was performed 2 hours after the laser processing.
- a multilayer printed wiring board manufactured according to Examples 1 to 12 and Comparative Examples 1 to 2 is housed in a housing, and the housing is 1 m high with the liquid crystal display mounted on the board facing downward. Then let it fall naturally. The number of drops was 50, 100, and 1 50 times, and the continuity of the conductor circuit was confirmed. The results of this drop test are shown in Table 1.
- the degree of bulge of the via hole (the ratio of the diameter of the largest bulge to the opening diameter of the insulating layer) is 1.0 times, 1.1 times, 1.3 times, Simulations were performed assuming that six different types were produced: 1.5 times, 1.6 times, and 1.8 times. For these boards, assuming that 50 tests were performed in the same board load test as the items evaluated in each example and comparative example, the amount of change in resistance was calculated by simulating the amount of change in connection resistance. The results are shown in Table 2.
- a multilayer printed wiring board that can be provided can be provided.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007524716A JP4913053B2 (ja) | 2005-07-07 | 2006-07-07 | 多層プリント配線板 |
EP20060781090 EP1858308B1 (en) | 2005-07-07 | 2006-07-07 | Multilayer printed wiring board |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005-199442 | 2005-07-07 | ||
JP2005199442 | 2005-07-07 |
Publications (1)
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WO2007007861A1 true WO2007007861A1 (ja) | 2007-01-18 |
Family
ID=37637239
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP2006/314015 WO2007007861A1 (ja) | 2005-07-07 | 2006-07-07 | 多層プリント配線板 |
Country Status (7)
Country | Link |
---|---|
US (3) | US7759582B2 (ja) |
EP (1) | EP1858308B1 (ja) |
JP (1) | JP4913053B2 (ja) |
KR (1) | KR20070070224A (ja) |
CN (1) | CN101069457A (ja) |
TW (1) | TW200715932A (ja) |
WO (1) | WO2007007861A1 (ja) |
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JP2009302506A (ja) * | 2008-05-14 | 2009-12-24 | Toppan Printing Co Ltd | 半導体パッケージ用多層基板及びその製造方法 |
KR101044152B1 (ko) | 2009-10-26 | 2011-06-24 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
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Also Published As
Publication number | Publication date |
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TWI334757B (ja) | 2010-12-11 |
US7759582B2 (en) | 2010-07-20 |
CN101069457A (zh) | 2007-11-07 |
JP4913053B2 (ja) | 2012-04-11 |
EP1858308B1 (en) | 2012-04-18 |
KR20070070224A (ko) | 2007-07-03 |
US20070154741A1 (en) | 2007-07-05 |
EP1858308A4 (en) | 2010-03-31 |
EP1858308A1 (en) | 2007-11-21 |
TW200715932A (en) | 2007-04-16 |
US20100155130A1 (en) | 2010-06-24 |
US7973249B2 (en) | 2011-07-05 |
US20090255111A1 (en) | 2009-10-15 |
JPWO2007007861A1 (ja) | 2009-01-29 |
US8181341B2 (en) | 2012-05-22 |
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