WO2007004253A1 - 不揮発性記憶装置、および不揮発性記憶装置の制御方法 - Google Patents
不揮発性記憶装置、および不揮発性記憶装置の制御方法 Download PDFInfo
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- WO2007004253A1 WO2007004253A1 PCT/JP2005/012033 JP2005012033W WO2007004253A1 WO 2007004253 A1 WO2007004253 A1 WO 2007004253A1 JP 2005012033 W JP2005012033 W JP 2005012033W WO 2007004253 A1 WO2007004253 A1 WO 2007004253A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
Definitions
- Nonvolatile memory device and control method of nonvolatile memory device are control method of nonvolatile memory device
- the present invention relates to a nonvolatile memory device that stores control information necessary for a data access operation in a section of a memory cell array.
- the nonvolatile semiconductor memory device disclosed in Patent Document 1 includes a memory cell array configured by a matrix arrangement of a plurality of nonvolatile memory cells that can electrically rewrite data.
- an initial setting data area is set in advance as an area for writing various initial setting data necessary for initializing the EEPROM.
- the initial setting data is information relating to the operating conditions of the memory.
- cell block Bn is defined as an initial setting data area for storing initial setting data.
- the initial setting data is read out by selectively driving the bit line BL and the word line WLn in the same manner as in reading from a normal memory cell.
- the initial setting data read mode is set after the power supply is stabilized. As a result, the initial setting data in the initial setting data area is read, and the validity of the read initial setting data is confirmed. If the validity is confirmed (PASS), the read initial setting data is transferred.If the validity is not confirmed (FAIL), a judgment signal is output and the read initial setting data is read. The chip status is fixed to FAIL state because is invalid data.
- Patent Document 2 When the power supply is turned on, the bit line is charged to the initial potential by supplying current to the bit line not only through the read load and the path through the first transistor but also through the second transistor. It is intended to increase the speed of the time required.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2004-152413 (FIGS. 1, 2, and 7)
- Patent Document 2 Japanese Patent Laid-Open No. 11-265595
- Patent Document 1 is a measure for storing the increased amount of information in the minimum occupied area. By storing control information such as initial setting data in the memory cell array area, the increasing amount of information is stored in the minimum necessary area.
- Patent Document 2 it is possible to shorten the precharge time for charging a read path such as a bit line to an initial potential.
- the read time of the control information after precharging depends on the drive capability of the memory cell. In a situation where the driving capability of the memory cell is not sufficiently secured, it takes time to read out the control information from the memory cell array. When power is turned on or reset, the initial setting operation before shifting to normal access may take a long time, which is a problem.
- the bias voltage applied to the gate terminal of the nonvolatile memory cell is set to a high voltage when reading control information.
- a large noise compared to normal use This leads to excessive stress applied to the memory cell, which is not preferable in terms of device reliability.
- a dedicated bias generation circuit must be provided, and the complexity of the circuit configuration causes an increase in circuit scale, which is a problem.
- the present invention has been made in view of the problems of the background art described above, and in a nonvolatile memory device in which control information is stored in a memory cell array, driving of a memory cell storing control information is performed. It is an object of the present invention to provide a non-volatile memory device and a method for controlling the non-volatile memory device that can shorten the reading time by sufficiently securing the capability.
- the non-volatile storage device of the present invention made to achieve the above object is a non-volatile storage device in which a memory cell array is assigned to a control information storage area in addition to a normal data storage area.
- the control information storage area has a predetermined number of control information storage memory cells for each bit of control information, and the same data is stored in a predetermined number of control information storage memory cells and read simultaneously. It is characterized by that.
- the memory cell array is allocated to the control information storage area in addition to the normal data storage area, and the control information storage area is assigned to each bit of the control information.
- a predetermined number of control information storage memory cells are provided, and the same bit of data is stored in the predetermined number of control information storage memory cells, and reading is performed simultaneously when reading.
- the non-volatile memory device control method of the present invention made to achieve the above object is a non-volatile memory device in which a memory cell array is allocated for storing control information in addition to storing normal data.
- a control method which includes a step of allocating a predetermined number of memory cells for each bit of control information, a step of storing the same data in a predetermined number of memory cells, and data stored in the predetermined number of memory cells And a step of simultaneously reading out.
- a predetermined amount of control information is stored for each bit of the nonvolatile memory device in which control data is stored in addition to normal data in the memory cell array.
- Number of memory cells are allocated, and the same bit is assigned to a predetermined number of memory cells.
- Data is stored. At the time of reading, the same bit data stored in a predetermined number of memory cells are simultaneously read.
- the present invention when reading control information, reading is performed simultaneously with a predetermined number of memory cell forces for each bit, so that the driving capability of the reading path during reading is enhanced.
- the reading time of the control information read during the initial setting period at power-on or reset can be shortened, and the normal access operation can be quickly performed.
- FIG. 1 is a diagram showing an arrangement (bit line common arrangement) of a CAM cell array according to a first embodiment.
- FIG. 2 is a diagram showing a CAM cell array arrangement (word line common arrangement 1) according to a second embodiment.
- FIG. 3 is a diagram showing a CAM cell array arrangement (word line common arrangement 2) according to a third embodiment.
- FIG. 4 is a diagram showing a specific example of an address decoder having a switching function between selection of a normal memory cell and selection of a CAM cell array.
- FIG. 5 is a diagram showing a circuit configuration example in the case where a cascode circuit is shared for reading normal data and reading CAM data.
- FIG. 6 is a diagram showing a circuit configuration example in the case where each of normal data reading and CAM data reading includes a cascode circuit.
- FIG. 7 is a flowchart of program or erase to a CAM cell array.
- FIG. 8 is a flowchart for reading data from a CAM cell array.
- FIG. 9 is a diagram showing a timing chart when reading control information in comparison with reading normal data.
- FIG. 11 is a diagram illustrating a circuit example of a bias switching unit that switches a noise voltage of a word line at the time of reading in accordance with data to be read.
- FIG. 12 is a diagram showing a threshold voltage distribution of a reference cell during verification and a cell after verification for a CAM monitor cell.
- FIG. 13 is a flowchart of program or erase to a CAM monitor cell.
- FIG. 14 is a diagram showing a memory cell array in the background art.
- FIG. 15 is a flowchart relating to reading of control information when power is turned on in the background art.
- FIGS. 1 to 3 show a part of the memory cell array of the NOR type nonvolatile memory device.
- One section of the memory cell array stores various types of control information such as write protect information and various trimming information such as internally generated voltage and signal generation timing that are read when the power is turned on or reset.
- the memory cell array shown in FIGS. 1 to 3 includes four local bit lines LBLO-0 to LBL3-0 to LBLO-15 to LBL3 in each of the 16 global bit lines GBLO to BGL15. — A configuration with 15.
- Each local bit line LBLO—0 to: LBL3—0 to LBLO—15 to: LBL3—15 is connected to the drain terminal of a memory cell whose gate terminal is biased by 16 word lines WLO to WL15. The The source terminal is connected to ground potential as required.
- Each local bit line LBLO-0 to LBL3-0 to LBLO-15 to LBL3-15 is a global bit line via the selection switches STRO-0 to STR3-0 to STR0-15 to STR3-15. Connected to GBL0 to GBL15.
- CAM cell array a predetermined number of control information storage memory cells (hereinafter referred to as a CAM cell array) are configured by 16 CAM cells.
- memory cells connected to the local bit line LBLO-0 are assigned as CAM cells, and the CAM cell array 1 is connected by 16 CAM cells connected to the same bit line.
- Local bit line LBLO Configures CAM cell array 1 dedicated line as a common data read line.
- the 16 bits of CAM cells constituting CAM cell array 1 store the same bit data, and CAM cell array 1 stores 1-bit control information.
- bit data is simultaneously read from all the CAM cells in the CAM cell array 1, and is read out from the global bit line GBL0 via the selection switch STR0-0.
- it can be configured to read with the CAM selection switch SCO-0 connected to the local bit line LBLO-0 and connected to the outside without passing through the global bit line GBL0.
- selection of selection switch STR0-0 can be performed in the same manner as a selection operation (not shown) in a normal access operation.
- the CAM selection switch SCO-0 can be selected according to a signal (SELCAM signal described later) indicating that the control information is being read.
- SELCAM signal described later
- This signal indicates that the control information is being read and The selection may be made by a signal containing position information (SELCAM (X) signal described later).
- SELCAM (X) signal described later.
- adjacent 16 memory cells connected to the global bit lines GBLO to GBL3 are allocated as CAM cells, and the CAM cell array 2 Is configured.
- the dedicated line of CAM cell array 2 is configured as a common bias line with the word line WLO.
- the 16 bits of CAM cells that make up the CAM cell array 2 store the same bit data, and the CAM cell array 2 stores 1-bit control information.
- the control information is read from the CAM cell array 2
- the bit data is simultaneously read from all the CAM cells in the CAM cell array 2, and the selection switches STRO-0 to STR3-0 to STRO-3 to STR3-3 are set. Via the global bit lines GBL0 to GBL3.
- the data currents read to the global bit lines GBL0 to GBL3 are all added by a not-shown switch circuit and processed as 1-bit data.
- each of the local bit lines LBL 0-0 to: LBL3-0 to LBL0-3 to LBL3-3 is connected to the outside without passing through the global bit lines GBL0 to GBL3.
- a CAM selection switch can be provided for reading. In this case as well, the data current read from each CAM cell card is added and processed as 1-bit data.
- selection of word line WLO can be performed in the same manner as the selection operation (not shown) in the normal access operation.
- the selection switches STRO-0 to STR3-0, STRO-3 to STR3-3 are selected in the CAM cell array 2 and are read simultaneously for each CAM cell. Are simultaneously selected by the address decoder (Fig. 4).
- the signal can be selected according to the signal. This signal indicates that the control information is being read, and is selected by a signal (SELCAM (X) signal described later) decoded according to the position information of the CAM cell array. Just do it.
- the CAM cell array 3 is configured with the memory cells connected to the word line WLO as CAM cells.
- the data input / output bit width is a 16-bit parallel data path. Assume that each data path is assigned to each of the global bit lines GBLO to GBL15. In the CAM cell array 3, one CAM cell belonging to each 16-bit width data path is selected for each data path, and a total of 16 CAM cells are provided to form the CAM cell array 3.
- the 16 bits of CAM cells constituting the CAM cell array 3 store the same bit data, and the CAM cell array 3 stores 1-bit control information.
- bit data is read simultaneously from all the CAM cells in the CAM cell array 3.
- Data currents read to the global bit lines GBLO to GB L15 are all added by a switch circuit (not shown) and processed as 1-bit data.
- the force described in the case where a data path is assigned to each global bit line is exemplified.
- the assignment of a global bit line to each data path is not limited to this. Although not shown, it is conceivable to assign one data path for each of the plurality of global bit lines. In this case, add a switch circuit that selects the global bit line and connects it to the data path.
- a dedicated line of the CAM cell array 3 is configured as a common bias line with the word line WLO.
- the control information is read from the CAM cell array 3
- the data of each CAM cell is read out from the global bit lines GBLO to GBL15 via the selection switches STRO-0 to STRO-15.
- a configuration may be adopted in which a CAM selection switch connected to each of the individual local bit lines LBLO 0 to LBLO-15 and connected to the outside without passing through the global bit lines GBLO to GBL15 is used for reading. it can.
- selection of word line WLO can be performed in the same manner as the selection operation (not shown) in the normal access operation.
- selection switches STRO-0 to STRO-15 can be performed in the same manner as the selection operation in the normal access operation when considering a 16-bit parallel operation.
- Local bit lines LBLO— 0 to LBLO— connected every 15 The CAM selection switch can be selected in accordance with a signal (SELCAM signal described later) indicating that the control information is being read.
- the arrangement of the CAM cell array in the memory cell array can have various configurations other than the configurations shown in the first to third embodiments (FIGS. 1 to 3).
- a 16-cell memory cell connected to 4 word lines and 4 local bit lines may be configured as a set. it can. That is, in combination with I word lines ⁇ [local bit lines, a predetermined number of memory cells (in this case, 16 cells) can be selected as CAM cells.
- FIG. 4 is a specific example of an address decoder that identifies 16 CAM cells in the CAM cell arrays 1 to 3.
- the CAM cell array selection signal ZSELCAM (X) which selects the CAM cell array when reading control information, is input.
- the suffix (X) in the CAM cell array selection signal ZSELCAM (X) indicates that a plurality of sets are provided to identify the CAM cell array.
- a CAM cell array selection signal ZSELC AM (X) for identifying the corresponding CAM cell array is input to each address decoder provided in accordance with the memory cell arrangement position in the memory cell array.
- the CAM cell array selection signal ZSELCAM (X) is at a high level. Accordingly, a high-level decode signal is output from one of the 16 sets of AND gates according to the combination of the address signals ADa to ADd and their inverted signals ZA Da to ZADd. The CAM cell corresponding to the high level decode signal is selected.
- the case of selecting a CAM cell alone may be, for example, a case of programming.
- the CAM cell array selection signal ZSELCA M (X) is at a low level. Therefore, regardless of the combination of the address signals ADa to ADd and their inverted signals Z ADa to ZADd, the signals output from all 16 sets of AND gates are at a low level.
- CAM cell array selection signal ZSELCAM (X) If a circuit is provided that inverts the output signal of the AND gate according to the low level of the signal to generate the decode signals DO to Dl 5, all the decode signals DO to D15 become high level, and the 16 cells constituting the CAM cell array CAM cells can be selected. By selecting all 16 CAM cells that make up the CAM cell array, the same bit data stored in each CAM cell can be read simultaneously.
- FIG. 5 is a circuit portion when transferring the bit data read to the global bit line GBL to an output buffer (not shown) or a control information storage unit (not shown).
- bit data stored in a memory cell is stored as a threshold voltage of the memory cell.
- the memory cell becomes non-conducting or conducting depending on the threshold voltage.
- the current path to which the drain terminal of the memory cell is connected is precharged to a high voltage level (about 0.5 V to 1 V), and the source terminal of the memory cell is connected to the ground potential.
- a high voltage level about 0.5 V to 1 V
- the global bit line GBL is connected to a cascode circuit 11 that converts the presence / absence of a current flowing toward the memory cell to a low / high voltage level.
- the bit data converted into the voltage signal also outputs the terminal SAIN force as the voltage conversion signal SAIN.
- the terminal SAIN is connected to one terminal of the switch sections 13 and 15.
- the switch unit 13 is controlled by a CAM cell array selection signal ZSELCAM (X). When the CAM cell array selection signal ZSELCAM (X) is at a high level, that is, during a normal access operation that is not in the read state of the control information, the switch unit 13 becomes conductive.
- the switch unit 15 is controlled by a CAM cell array selection signal SE LCAM (X) which is an inverted signal of the CAM cell array selection signal ZSELCAM (X).
- SE LCAM CAM cell array selection signal
- SELCAM CAM cell array selection signal
- the other terminal of the switch unit 13 is connected to one input terminal of the sense amplifier 17.
- a reference voltage REF determined based on a reference cell or the like is input to the other input terminal of the sense amplifier 17.
- the other terminal of the switch unit 15 Connected to the information storage.
- the cascode circuit 11 includes PMOS transistors MP1 and MP2, NMOS transistors MNl to MN6, and resistance elements RA and RB. Resistor element RA and NMOS transistor MN5 connected in series, resistor element RB and NMOS transistor MN6 connected in series, each connected to power supply voltage VCC via PMOS transistor MP1 and NMOS transistor MN2 connected in series Connected to ground potential via MN1. As another path from the power supply voltage VCC to the ground potential, the PMOS transistor MP2 and the NMOS transistors MN4 and MN3 form a path.
- the power-down signal PD is input to the gate terminals of the PMOS transistors MP1 and MP2 and the NMOS transistor MNl.
- the gate terminal of the NMOS transistor MN2 is connected to the drain terminal of the NMOS transistor MN3, the gate terminal of the NMOS transistor MN3 is connected to the global bit line GBL, and the gate terminal of the NMOS transistor MN4 is connected to the power supply voltage VCC.
- the CAM cell array selection signals SELCAM (X) and / SELCAM (X), which are complementary signals, are input to the gate terminals of the NMOS transistors MN5 and MN6.
- a voltage conversion signal SAIN which is bit data obtained by voltage conversion, is output from a terminal SAIN at a connection point of the NMOS transistors MN2, MN5, and MN6.
- the cascode circuit 11 when the power-down signal PD is high level, the PMOS transistors MP1 and MP2 are non-conductive and the NMOS transistor MNl is conductive when the power-down signal PD is high level. Maintained. When the power down state force also shifts to the access state, the power down signal PD is inverted to low level. N MOS transistor MN1 becomes non-conductive, and PMOS transistors MP1 and MP2 conduct and terminal SAIN and global bit line GBL are precharged to high level.
- a data current from 16 CAM cells constituting the CAM cell array flows when the control information is read. That is, A data current that is 16 times the data current that flows during normal access operation will flow.
- the CAM cell array selection signal ZSELCAM (X) goes high, and a current path is formed via the resistance element RB via the NMOS transistor MN6.
- the data current from the memory cell is stepped down via the resistance element RB and output as a voltage conversion signal SAIN having a lowered voltage level.
- the voltage drop is very small, and it is necessary to compare and amplify the reference voltage REF with the sense amplifier 17 by conducting the switch section 13.
- This is a conventionally known data read operation. In other words, after detecting the data current as a small voltage drop and comparing it to the reference voltage REF and then amplifying it to a logic level signal, a logic level voltage signal is obtained through a two-stage amplification procedure. ing.
- the CAM cell array selection signal SELCAM when reading the control information, the CAM cell array selection signal SELCAM
- (X) becomes a high level, and a current path is formed via the resistance element RA via the NMOS transistor MN5.
- the data current from the CAM cell array is dropped through the resistance element RA and output as a voltage conversion signal SAIN having a lowered voltage level. Since the data current in this case has a current value 16 times the current value in normal data, the voltage conversion signal SAIN can be dropped with a logic level amplitude. That is, the data current can be directly converted into a logic level voltage signal.
- a logic level voltage signal can be obtained through a one-stage conversion procedure. The data current can be quickly converted into a logic level voltage signal.
- the cascode circuit 11 can quickly perform a precharge operation at the time of reading control information, while enabling a rapid conversion from a data current to a logic level voltage signal. This is because the terminal SAIN and the global bit line GBL are precharged via the resistor element RA, so that the low resistance key of the resistor element RA directly contributes to the high speed key during the precharge time.
- FIG. 6 shows an example of the global bit lines GBLO to GBL15 by taking the third embodiment (FIG. 3) as an example.
- 2 illustrates an example of a configuration of a cascode circuit that converts a data current read from a voltage into a voltage.
- switch sections SO to S 15 are provided on paths from individual global bit lines GBLO to GBL 15 to data lines DBO to DB 15. Each of the switch sections SO to S15 is selected by selection signals CL0 to CL15 obtained by decoding an address signal corresponding to a memory cell (not shown) to be accessed.
- FIG. 6 based on the third embodiment (FIG. 3), the force circuit configuration illustrating the case where the data lines DB0 to DB15 are provided for each of the global bit lines GBL0 to GBL15.
- the composition is not limited. Multiple global bit lines can be selected using a column selection switch, etc., and connected to a single data line.
- Each of the data lines DB 0 to DB 15 is connected to the normal access cascode circuit 21, and its output terminal is connected to the sense amplifier 17.
- the normal access cascode circuit 21 has a fixed resistance element RB in place of the resistance element RA and the N MOS transistor MN5, the resistance element RB and the NMOS transistor MN6 in the cascode circuit 11 described in FIG. It is a configuration. The same operation and effect as the cascode circuit 11 are achieved.
- the data current from which the memory cell force is read is also converted into voltage conversion signals SAIN0 to SAIN15 of a minute voltage signal in the normal access cascode circuit 21 and then compared and amplified in the sense amplifier 17.
- the global bit lines GBL0 to GBL15 from which the data current is read from the individual CAM cells are connected to the CAM data via the CAM read switch units SCO to SC15. Connected to line DBC. Since the CAM read switch units SCO to SC15 are controlled in common by the CAM cell array selection signal SELCAM (X), they are turned on simultaneously when the corresponding CAM cell array force is read.
- the CAM data line DBC is connected to the CAM cascode circuit 19, and its output terminal S AIN is connected to the control information storage unit.
- the CAM cascode circuit 19 is composed of the resistance element RA and NMOS transistor of the cascode circuit 11 described in FIG. Instead of MN5, resistance element RB, and NMOS transistor MN6, a resistance element RA is fixedly provided. The same operation and effect as the cascode circuit 11 are achieved.
- the data current read from the memory cell is converted into a voltage conversion signal SAIN at a logic level in the CAM cascode circuit 19 in a one-stage configuration.
- FIGS. 7 and 8 are flowcharts of the access operation for the CAM cell array.
- the CAM cell array is configured to store 1-bit data by a predetermined number of CAM cells (16 cells in the first to third embodiments), and 1-bit data is stored in one memory cell. An access sequence different from the access case is required.
- the flowcharts shown in Figs. 7 and 8 are executed by an internal control circuit that manages sequence control such as a state machine.
- Figure 7 shows the program or erase flow
- Figure 8 shows the data read flow.
- a predetermined number (N) of CAM cells to be programmed are selected for the CAM cell array to be programmed (erasure) (Sl).
- the first CAM cell to be programmed (erased) is designated.
- the address (AD) of the corresponding CAM cell is specified (S2).
- the program (erase) operation is performed on the CAM cell at the specified address (AD) (S3).
- word line Z is changed according to the new address (AD). Change the bit line Z data line (DQ) (S6), and perform the program (erase) operation again (S3). If the address (AD) exceeds the specified number (N) (S5: YES), the program (erase) process is terminated for all CAM cells that make up the CAM cell array, assuming that the program (erase) has been completed. To do.
- a data read flow in FIG. 8 will be described.
- a predetermined number (N) of CAM cells to be configured are selected for the CAM cell array to be read (S11).
- a control signal for ignoring an address that individually identifies a predetermined number (N) of CAM cells is activated (in this case, the CAM cell array selection signal SELC AM (X) is activated) (S12). ).
- CAM cell array selection signal SELCAM (X) leads to bit line force cascode circuit
- the switch unit for connecting the lines is controlled to select a data read path (S13).
- the data current read simultaneously from the predetermined number (N) of CAM cells is input to the CAM cascode circuit, and current-voltage conversion is performed (S14).
- the logic level voltage conversion signal SAIN is output and output to the control information storage unit.
- FIG. 9 is a diagram comparing a timing chart when reading normal data with a timing chart when reading control information.
- a nonvolatile memory device that performs a synchronous operation with respect to the clock signal CLK is shown as an example.
- the bit data is read out.
- the read bit data is converted into a voltage signal as a voltage conversion signal SAIN.
- the terminal SAIN In normal data reading, the terminal SAIN is precharged high in the clock cycle when the equalize signal EQ goes high, and the bit data stored in the memory cell is read out from the next clock cycle. It is.
- PGM memory cell program state
- ER erased state
- a data current flows and the voltage conversion signal SAIN decreases with time.
- the dotted line shown between the waveform at (PGM) and the waveform at (ER) indicates the reference voltage (REF) by the reference cell. Since the data current that is read from the memory cell force is very small, the falling speed of the voltage conversion signal SAIN in the erase state (ER) is small.
- the sense amplifier latch signal SAL is pulsed, allowing the sense amplifier to compare with the reference voltage (REF) and to amplify to the logic level. Become. As a result, it becomes valid data (valid) as the output signal OUT. Requires 5 clock cycles from the data read cycle.
- a precharge operation by the high level equalize signal EQ and a latch operation by the latch signal LCH can be performed within one clock cycle.
- FIG. 10 is a diagram showing a threshold voltage distribution of bit data stored in a CAM cell constituting a CAM cell array.
- dedicated reference cells RCCP and RCCE are provided separately from the reference cells RCP and RCE that are used for ordinary memory cells.
- the dedicated reference cell RCCP for programming has a larger threshold voltage than the reference cell RCP at the time of programming normal data. For this reason, the distribution of the threshold voltage of the CAM cell in which the program data is written is a distribution having a peak on the high threshold voltage side in the threshold voltage distribution of the normal memory cell in which the program data is written.
- the dedicated reference cell RCCE for erasure has a threshold voltage that is smaller than that of the reference cell RCE when erasing normal data. For this reason, the threshold voltage distribution of the CAM cell in which erase and data are written is a distribution having a peak on the low threshold voltage side in the threshold voltage distribution of the normal memory cell in which erase data is written.
- the CAM cell in the programmed state is in a state where the data current does not flow as compared with the normal memory cell.
- the threshold voltage is a threshold voltage that is larger than that of a normal memory cell. The current can be suppressed, and erroneous detection in the cascode circuit can be prevented.
- FIG. 11 and FIG. 12 describe a method that can adjust the bias voltage to be applied to the word line when reading the CAM cell array.
- Quickly reading out the control information, which is initialization information, at power-on or reset initialization is essential for shortening the transition time to normal access after initialization.
- circuit operation may be unstable.
- it is common to apply a boosted noise voltage to a word line during reading of a normal memory cell it is necessary to wait for a predetermined time for the boosted voltage level to stabilize. is there. Therefore, if the bias voltage applied to the CAM cell array can be set to the power supply voltage VCC that is not boosted, there is no need to wait for the stability of the voltage generation circuit.
- VCC power supply voltage
- the voltage was boosted or stepped down only when it was not appropriate to apply the power supply voltage VCC. This is a specific example of switching to a bias voltage.
- FIG. 11 shows a circuit example for switching the connection of the voltage source supplied to the word line of the CAM cell in accordance with the bias switching unit 23.
- the switch sections 29, 31, and 33 composed of PMOS transistors are used to bias the power supply voltage VCC supplied from the external terminal P, the output of the booster circuit 25, and the output of the step-down circuit 27 to the word line WL of the CAM cell.
- CAM monitor cells CA MMP and CAMME which are set in the program state and the erase state in advance are provided.
- the CAM monitor cells CAMMP and CAMME are provided as cells for monitoring the state of the data bits stored in the CAM cell array, and the CAM monitor cells CAMMP and CAMME have the same configuration as the CAM cell array.
- the CAM monitor cells CAMMP and CAMME are connected to the noise switching circuit 23 through CAM cascode circuits 35 and 37, respectively.
- the voltage conversion signals SAINMP and SAINME output from the cascode circuits 35 and 37 are logically operated via the switch unit.
- the switch unit 29 is controlled to conduct according to the NAND operation of the in-phase signal of the voltage conversion signal SAINMP and the inverted signal of the voltage conversion signal SAINME, and the in-phase signal and voltage of the voltage conversion signal SAINMP are controlled.
- Switch unit 31 is controlled to conduct according to the NAND operation of the in-phase signal of conversion signal SAINME, and switch unit 33 is controlled to conduct according to the NAND operation of the inverted signal of voltage conversion signal SAINMP and the inverted signal of voltage conversion signal SAINME. Is done.
- FIG. 12 shows threshold voltage distributions of the CAM monitor cells CAMMP and CAMME.
- the threshold voltage distribution having a peak inside the normal memory cell threshold voltage distribution is provided.
- the bias voltage applied to the word line when reading data is set to an intermediate voltage between the threshold voltage distribution in the program state and the threshold voltage distribution in the erase state, so the threshold voltage distribution of the CAM monitor cells CAMMP and CAMME Has the most severe read margin and distribution.
- the power supply voltage VCC on the CAM monitor cell CAMMP and CAMME side lines If the read data when applying is determined, the noise voltage to be applied to the CAM cell can be estimated.
- the power supply voltage VCC Prior to reading data from the CAM cell, the power supply voltage VCC is applied to the word lines of the CAM monitor cells CAMMP and CAM ME, and the data is read to the cascode circuits 35 and 37. If the data is normally read by applying the power supply voltage VCC, no data current flows through the CAM monitor cell CAMMP in the program state, and a signal having a high logic voltage level is output from the cascode circuit 35. In addition, a data current flows through the CAM motor cell CAMME in the erased state, and a signal having a low logic voltage level is output from the cascode circuit 37.
- the data current does not flow through either the CAM monitor cell CAMMP or CAMME.
- the threshold voltage distribution of the erased CAM cell is higher than the power supply voltage VCC. It is judged.
- the cascode circuits 35 and 37 both output a high level logic voltage level signal. For CAM cells, there is a risk of erroneous reading because there is not enough room for reading erased data when power supply voltage VCC is applied. It is judged that there is.
- the switch unit 31 is turned on by the bias switching circuit 23, and the voltage boosted by the boosting circuit 25 is supplied to the CAM cell.
- the threshold voltage distribution of the CAM cell in the programmed state is on the lower voltage side than the power supply voltage VCC.
- the cascode circuits 35 and 37 both output low level logic voltage level signals.
- the switch 33 is turned on by the noise switching circuit 23, and the voltage stepped down by the step-down circuit 27 is supplied to the CAM cell.
- the relaxation of the voltage stress condition is a condition such as, for example, shortening a step time width in which a voltage is applied, or reducing an increment of an applied voltage between Z and the voltage application step. .
- an upper limit threshold voltage is provided in addition to the lower limit threshold voltage as the threshold voltage at the time of verification. It is determined that the program is completed when it falls within these two threshold voltage ranges.
- the threshold voltage force of the CAM monitor cell to be programmed exceeds the lower threshold and the program processing (S23) is completed, it is determined whether or not the upper threshold voltage has been exceeded (S24). If it has exceeded (S24: YES), erase processing is performed! /, (S25), and program processing is resumed (S23).
- a lower threshold voltage is provided in addition to the upper threshold voltage as the threshold voltage during verification. Erasing is completed when it falls within these two threshold voltage ranges.
- the CAM cell array 1 is composed of 16 CAM cells (first embodiment), and the global bit among the memory cells connected to the word line WLO.
- 16 adjacent memory cells connected to lines GBLO to GBL3 are allocated as CAM cells, forming CAM cell array 2 (second embodiment), or 16 bits of memory cells connected to word line WLO 16 memory cells connected to the glow bit lines GBLO to GBL15 corresponding to the parallel data path of the width are allocated as CAM cells to form the CAM cell array 3 (third actual Form).
- bit data is stored in 16 CAM cells constituting the CAM cell arrays 1 to 3, and 1-bit control information is stored in the CAM cell arrays 1 to 3.
- control information is read from the CAM cell arrays 1 to 3
- bit data is simultaneously read from all CAM cells in the CAM cell arrays 1 to 3.
- Data current power to be read is increased to a predetermined number of times (16 times) when normal data is read, so that current-voltage conversion can be performed at high speed in the cascode circuit.
- the drive capability of the read path at the time of reading is strengthened, and the read time of the control information read during the initial setting period at power-on or reset can be shortened.
- the normal access operation can be quickly performed.
- a dedicated reference cell RC CPZRCCE is provided for verifying the program Z erase of the CAM cell, and has a threshold voltage that is large and small compared to the reference cell RCPZRCE at the time of normal data program Z erase. Therefore, the distribution of the threshold voltage of the CAM cell is a distribution having a peak outside in the distribution of the threshold voltage of the normal memory cell.
- the threshold voltage is usually larger than that of the memory cell, so that bias application is performed. Leakage current can be suppressed, and erroneous detection in the cascode circuit can be prevented.
- the bias voltage that has been boosted or stepped down is applied only when the power supply voltage VCC is inappropriate. If the configuration is switched, the circuit operation is unstable at initialization such as at power-on or reset, and control information can be read without waiting for the stability of the voltage source that has been stepped up and down. .
- the CAM monitor cell CAMMP / CAMME has the same configuration as the CAM cell array and monitors the program Z erase state, and the threshold voltage distribution peaks inside the threshold voltage distribution of the normal memory cell. Therefore, when reading the CAM monitor cell prior to reading the CAM cell array force, the reading margin is severe and the reading is performed under conditions.
- the CAM cell array has a threshold voltage distribution with a peak outside the normal memory cell threshold voltage distribution, and the power supply voltage VCC is applied to the CAM monitor cell CAMMP and CAMME by determining the read data from CAMME.
- the bias voltage to be applied to the cell can be estimated.
- a combination of CAM cells that make up a CAM cell array in a memory cell array This is not limited to the configuration of the first to third embodiments, but can be other combinations.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Security & Cryptography (AREA)
- Static Random-Access Memory (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
Claims
Priority Applications (4)
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JP2007523275A JP4762986B2 (ja) | 2005-06-30 | 2005-06-30 | 不揮発性記憶装置、および不揮発性記憶装置の制御方法 |
PCT/JP2005/012033 WO2007004253A1 (ja) | 2005-06-30 | 2005-06-30 | 不揮発性記憶装置、および不揮発性記憶装置の制御方法 |
TW095123776A TW200710851A (en) | 2005-06-30 | 2006-06-30 | Non-volatile memory device, and control method of non-volatile memory device |
US11/479,387 US7436715B2 (en) | 2005-06-30 | 2006-06-30 | Non-volatile memory device, and control method of non-volatile memory device |
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PCT/JP2005/012033 WO2007004253A1 (ja) | 2005-06-30 | 2005-06-30 | 不揮発性記憶装置、および不揮発性記憶装置の制御方法 |
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US11/479,387 Continuation-In-Part US7436715B2 (en) | 2005-06-30 | 2006-06-30 | Non-volatile memory device, and control method of non-volatile memory device |
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JP (1) | JP4762986B2 (ja) |
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Cited By (1)
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JP2008306008A (ja) * | 2007-06-08 | 2008-12-18 | Spansion Llc | 半導体装置及びその制御方法 |
Families Citing this family (11)
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JP2008192212A (ja) * | 2007-02-01 | 2008-08-21 | Spansion Llc | 半導体装置およびその制御方法 |
JP4460616B2 (ja) * | 2007-11-16 | 2010-05-12 | 株式会社エヌ・ティ・ティ・ドコモ | セル選択方法及び移動局 |
JP5086959B2 (ja) * | 2008-09-26 | 2012-11-28 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US8860117B2 (en) | 2011-04-28 | 2014-10-14 | Micron Technology, Inc. | Semiconductor apparatus with multiple tiers of memory cells with peripheral transistors, and methods |
US8964474B2 (en) | 2012-06-15 | 2015-02-24 | Micron Technology, Inc. | Architecture for 3-D NAND memory |
US9001584B2 (en) * | 2013-02-28 | 2015-04-07 | Micron Technology, Inc. | Sub-block decoding in 3D memory |
US20160189755A1 (en) * | 2015-08-30 | 2016-06-30 | Chih-Cheng Hsiao | Low power memory device |
US9679650B1 (en) | 2016-05-06 | 2017-06-13 | Micron Technology, Inc. | 3D NAND memory Z-decoder |
KR102501695B1 (ko) * | 2018-01-15 | 2023-02-21 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 그것의 동작 방법 |
US10910057B2 (en) * | 2019-04-22 | 2021-02-02 | Western Digital Technologies, Inc. | CAM storage schemes and CAM read operations for detecting matching keys with bit errors |
US11450381B2 (en) | 2019-08-21 | 2022-09-20 | Micron Technology, Inc. | Multi-deck memory device including buffer circuitry under array |
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- 2005-06-30 WO PCT/JP2005/012033 patent/WO2007004253A1/ja active Application Filing
- 2005-06-30 JP JP2007523275A patent/JP4762986B2/ja not_active Expired - Fee Related
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2006
- 2006-06-30 TW TW095123776A patent/TW200710851A/zh unknown
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JPH04192196A (ja) * | 1990-11-26 | 1992-07-10 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置 |
JPH1196781A (ja) * | 1997-09-18 | 1999-04-09 | Sanyo Electric Co Ltd | 不揮発性半導体メモリ装置 |
JP2001176290A (ja) * | 1999-12-10 | 2001-06-29 | Toshiba Corp | 不揮発性半導体記憶装置 |
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JP4762986B2 (ja) | 2011-08-31 |
US20070033333A1 (en) | 2007-02-08 |
TW200710851A (en) | 2007-03-16 |
JPWO2007004253A1 (ja) | 2009-01-22 |
US7436715B2 (en) | 2008-10-14 |
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