WO2006095890A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2006095890A1
WO2006095890A1 PCT/JP2006/304831 JP2006304831W WO2006095890A1 WO 2006095890 A1 WO2006095890 A1 WO 2006095890A1 JP 2006304831 W JP2006304831 W JP 2006304831W WO 2006095890 A1 WO2006095890 A1 WO 2006095890A1
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WIPO (PCT)
Prior art keywords
insulating film
semiconductor device
gate insulating
manufacturing
trap site
Prior art date
Application number
PCT/JP2006/304831
Other languages
French (fr)
Japanese (ja)
Inventor
Ayuka Tada
Hirohito Watanabe
Taeko Ikarashi
Hiroshi Sunamura
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Nec Corporation
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Priority to JP2007507219A priority Critical patent/JPWO2006095890A1/en
Publication of WO2006095890A1 publication Critical patent/WO2006095890A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate

Definitions

  • the present invention relates to a semiconductor device having nonvolatile memory cells and a method for manufacturing the same, and more particularly to an electrically erasable nonvolatile semiconductor memory device represented by a flash memory and a method for manufacturing the same.
  • Background technology :
  • flash EEPROM flash electrically erasable and programmable read only memory
  • the ONO memory that accumulates electric charge in the trap of silicon nitride film, it is planned to accumulate electric charge in the trap formed in the deep level of the silicon nitride film.
  • the conduction band of silicon nitride exists at a shallow depth of 1.1 eV from the end of the silicon oxide conduction band, and charges are accumulated at this level. The charge accumulated at this level is easily extracted, which causes a problem that the threshold value changes easily.
  • nanocrystal memory that accumulates electric charge in fine particle silicon has a problem that the variation in characteristics is large because the particle size variation of silicon fine particles is large. Another problem is that when one electron is injected into one particle, the probability of the injection of the next electron is reduced, making it difficult to store a large amount of electrons. Furthermore, since an interelectrode insulating film must be formed on the fine particle forming film, it is difficult to obtain a high-quality insulating film, resulting in a decrease in reliability. Disclosure of the invention:
  • the technical problem of the present invention is to solve the above-mentioned problems of the prior art.
  • the first object is to prevent the formation of shallow levels for trapping electrons in the electron storage layer.
  • Second it is possible to realize a gate insulating film with a sufficiently thin EOT.
  • a nonvolatile memory cell having a first gate electrode formed on a substrate via a gate insulating film and a source / drain region formed on the substrate surface region.
  • the semiconductor device is characterized in that the gate insulating film includes a trap site-containing layer to which an impurity including a metal that becomes a trap site is added.
  • the goot insulating film has a silicon oxide film in part or in whole.
  • the memory cell is formed on one region of the substrate, and a logic circuit is formed on another region of the substrate.
  • a semiconductor device can be obtained.
  • the semiconductor device it is preferable that a plurality of the memory cells are formed.
  • a method of manufacturing a semiconductor device having a nonvolatile memory cell wherein the manufacturing process of the gate insulating film of the memory cell includes the step of depositing an insulating film. And a step of depositing impurities that serve as trap sites, and a method for manufacturing a semiconductor device is provided.
  • the method further includes a step of thermally oxidizing the surface of the silicon substrate.
  • a method for manufacturing a semiconductor device having a non-volatile memory cell wherein the manufacturing process of the gate insulating film of the memory cell thermally oxidizes the surface of the silicon substrate.
  • a method for manufacturing a semiconductor device comprising: a step; and a step of introducing an impurity to be a trap site into the formed thermal oxide film by an ion implantation method.
  • manufacture of the semiconductor device in the said aspect of this invention In the method, a plurality of the memory cells are preferably formed.
  • a method for manufacturing a semiconductor device having a nonvolatile memory cell wherein the manufacturing process of the gate insulating film of the memory cell thermally oxidizes the surface of the silicon substrate.
  • a step of depositing a transfer film containing impurities that become trap sites on the formed thermal oxide film, a step of performing heat treatment to diffuse the impurities that become trap sites into the thermal oxide film, and a transfer film A method of manufacturing a semiconductor device, comprising: a step of removing the conductive film; and a step of forming an insulating film on the thermal oxide film.
  • a method of manufacturing a semiconductor device having a nonvolatile memory cell wherein the step of manufacturing the gate insulating film of the memory cell thermally oxidizes the surface of the silicon substrate. And a step of forming an insulating film by a vapor phase method.
  • the step of forming an insulating film by the vapor phase method an impurity that becomes a trap site during a certain period of time or in the initial stage or its A method for manufacturing a semiconductor device is provided, in which film formation is performed while supplying a compound gas.
  • nonvolatile memory of the semiconductor device of the present invention electric charges are accumulated by trap sites introduced by impurities such as metal contained in the silicon oxide film. Therefore, a shallow level is not formed as in the case of a silicon nitride film, and accumulated charge is not lost via an interface defect, and the retention characteristics can be improved.
  • the trap site is formed in the silicon oxide film, the film thickness is not used by the insulating film that becomes the charge trapping layer, and the EOT can be made thinner.
  • the process added to create the non-volatile memory having this structure is only required to deposit a thin metal on the thermal oxide film, so that it can be easily manufactured at low cost.
  • there is little difference between the manufacturing process and the normal MOS type semiconductor device it is possible to easily implement the mixed mounting with the logic circuit.
  • FIG. 1A is a cross-sectional view of a memory cell according to a first embodiment of the present invention.
  • FIG. 1B is a cross-sectional view of a memory cell according to a modification of the first embodiment of the present invention.
  • FIG. 1C is a cross-sectional view of a memory cell according to another modification of the first embodiment of the present invention.
  • FIG. 1D is a cross-sectional view of a memory cell according to still another modification of the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of a memory cell according to a second embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of a memory cell according to a third embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of a memory cell according to a fourth embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of a memory cell according to a fifth embodiment of the present invention.
  • FIG. 6 is a sectional view of a memory cell according to a sixth embodiment of the present invention.
  • FIG. 7 is a cross-sectional view of a memory cell according to a seventh embodiment of the present invention.
  • FIG. 8 is a flowchart showing a method of manufacturing a semiconductor device according to the eighth embodiment of the present invention.
  • FIG. 9 is a flowchart showing a method of manufacturing a semiconductor device according to the ninth embodiment of the present invention.
  • FIG. 10 is a flowchart showing a method of manufacturing a semiconductor device according to the tenth embodiment of the present invention.
  • FIG. 11 is a flowchart showing a method of manufacturing a semiconductor device according to the first example of the present invention.
  • FIG. 12 is a flowchart showing a method of manufacturing a semiconductor device according to the first and second embodiments of the present invention.
  • FIG. 13 is a flowchart showing a method of manufacturing a semiconductor device according to the thirteenth embodiment of the present invention.
  • FIG. 14A is a flowchart showing a method of manufacturing a semiconductor device according to the 14th embodiment of the present invention.
  • FIG. 14B is a flowchart showing a semiconductor device manufacturing method according to a modification of the 14th embodiment of the present invention.
  • FIG. 15A is a cross-sectional view in order of steps showing a method for forming a merged gate insulating film of a memory cell according to a fifteenth embodiment of the present invention.
  • FIG. 15B is a cross-sectional view in order of the steps showing the method for forming the merged gate insulating film of the memory cell according to the fifteenth embodiment of the present invention.
  • FIG. 15C is a cross-sectional view in order of the steps showing the method for forming the merged gate insulating film of the memory cell according to the 15th embodiment of the present invention.
  • FIG. 16A is a sectional view in order of steps showing a second method of forming a merged gate insulating film of a memory cell according to a sixteenth embodiment of the present invention.
  • FIG. 16B is a cross-sectional view in order of the steps showing a second method of forming the merged gate insulating film of the memory cell according to the sixteenth embodiment of the present invention.
  • FIG. 16C is a cross-sectional view in order of the steps showing a second method of forming the merged gate insulating film of the memory cell according to the sixteenth embodiment of the present invention.
  • FIG. 16D is a cross-sectional view in order of the steps showing a second method of forming the merged gate insulating film of the memory cell according to the sixteenth embodiment of the present invention.
  • FIG. 16E is a cross-sectional view in order of the steps showing a second method of forming the 'merged gate insulating film' of the memory cell according to the sixteenth embodiment of the present invention.
  • FIG. 17 is a graph showing the charge density as a measurement result of Example 1 of the present invention.
  • FIG. 18 is a C V characteristic diagram (T i) of Example 2 of the present invention.
  • FIG. 19 is a write characteristic diagram (T i) of Example 2 of the present invention.
  • FIG. 20 is a holding characteristic diagram (T i) of Example 2 of the present invention.
  • FIG. 21 is a write characteristic diagram (A 1) of Example 2 of the present invention.
  • FIG. 22 is a write characteristic diagram (A u) of Example 2 of the present invention. Best Mode for Carrying Out the Invention:
  • an n-type diffusion layer 2 serving as a source / drain region is formed on a p-type silicon substrate 1, and a silicon serving as a gate insulating film therebetween.
  • An oxide film 3 is formed.
  • Trap sites 5 are formed in the silicon oxide film 3.
  • a first gate electrode is formed of polysilicon, polycide, silicide, refractory metal, or the like.
  • the trap site 5 is a defect in which electrons are injected by CHE (channel hot electron) generated in a channel or F—N (Fowler-Nordheim) current generated by applying a high electric field. The defect is introduced by a metal which is an impurity added to the silicon oxide film 3.
  • the metal added to the silicon oxide film is not particularly limited, but it has a low diffusion coefficient in the silicon oxide film and can form deep levels in the silicon oxide film.
  • These metals do not include semiconductors such as Si, Ge, Se, and Te, and include semimetals such as B, C, P, As, Sb, Bi, and Po.
  • metal materials are Al, Au, Co, Cr, Cu, Fe, Ir, La, Mg, Mn, Ni, Ru, Sn, Ta, Ti, Ti, Zn, 'W It is. Multiple types of these metals may be included. Further, even a pure metal may be contained as a compound such as a metal oxide, a metal nitride, or a metal silicate.
  • the electron density required to change the threshold IV is about 2 X 10 12 cm 2 .
  • the threshold change necessary for bit identification is a few volts, so it is sufficient if electrons are injected to a density of about 1 X 10 13 Z cm 2 during writing. Since this density is considered to correspond to the impurity added to the oxide film, the density of the impurity (metal) added to the silicon oxide film may be 1 ⁇ 10 13 / cm 2 or less.
  • the memory cell according to the present invention does not have a charge storage layer having a thickness as in the case of the ONO memory.
  • There is a layer where trap sites are concentrated (hereinafter referred to as trap-containing layer).
  • the film thickness of the oxide film from the trap-containing layer to the substrate referred to as the tunnel oxide film
  • the film thickness of the oxide film from the trap-containing layer to the gate electrode referred to as the top oxide film
  • impurities Metal
  • the impurity is initially formed to a thickness of about a single atomic layer or several atomic layers, but has a certain spread after the heat treatment.
  • the spread range is expected to be about 1 nm and is at most 3 nm. Therefore, if the tunnel oxide film and the top oxide film are 10 nm each, the thickness of the trap-containing layer is 3/20 or less of the thickness of the gate insulating film.
  • a memory cell 20 according to a modification of the first embodiment is obtained by depositing an insulating film 4 other than a silicon oxide film on a silicon oxide film 3 including a trap site 5.
  • silicon-based insulating materials such as silicon oxynitride, silicon nitride, PSG (phosphorus glass), BPSG (boron phosphorous glass), BST (barium titanate 'strontium), oxide
  • An outer composite film that can use a high dielectric constant material such as tantalum, zirconium oxide, hafnium oxide, and aluminum oxide can also be used.
  • the insulating film may be an insulating film whose composition gradually changes, for example, S i 0 2 ⁇ S i ON ⁇ S i 3 N 4 ⁇ S i ON ⁇ S i O 2 .
  • the trap site 5 is not included in the silicon oxide film 3, but is included in the insulating film 4 side.
  • the trap site 5 is formed at the interface between the silicon oxide film 3 and the insulating film 4.
  • the goot insulating film including the trap site is formed entirely of the silicon oxide film shown in FIG. 1A. Although only the thing is demonstrated, what is shown by FIG. 1B-FIG. 1D may be sufficient. The same applies to the following embodiments.
  • the first gate electrode 6 includes a silicon oxide film 3 having a trap site 5 inside and a gate insulating film 7 in which no trap site is intentionally introduced. It is formed straddling. Silicon oxide film 3 The gate insulating film 7 is formed near one side of the source / drain region.
  • the first gate electrode 6 includes a silicon oxide film 3 having a trap site 5 inside and a trap site intentionally. It is formed across the gate insulating film 7 that has not been introduced.
  • the silicon oxide film 3 is formed at the center on the channel region, and the gate insulating film 7 is formed near the source and drain regions.
  • the first gate electrode 6 is intentionally formed by the silicon oxide film 3 having the trap site 5 and the trap site intentionally. It is formed across the gate insulating film 7 that has not been introduced.
  • the silicon oxide film 3 is formed near the source and drain regions, and the gate insulating film 7 is formed in the central portion on the channel region.
  • the first gate electrode 6 is formed on the silicon oxide film 3 having the trap site 5 therein, and the second gate The electrode 8 is formed on the goot insulating film 7 where no trap site is intentionally introduced.
  • an n-type diffusion layer serving as a source / drain region is formed on the substrate surface between the first gate electrode 6 and the second gate electrode 8. Also good.
  • the first gate electrode 6 is formed on the silicon oxide film 3 having the trap site 5 therein, and the second gate The electrode 8 is formed on the gate insulating film 7 where no trap site is intentionally introduced.
  • the second gate electrode 8 is formed so that a part of the second gate electrode 8 is placed on the first gout electrode 6.
  • the second gate electrode 8 is formed on the gate insulating film 7 where the trap site is not intentionally introduced. Yes.
  • the first gate electrode 6 is formed in a sidewall film shape on the silicon oxide film 3 having the S trap site 5 inside.
  • the insulating film between the first gate electrode 6 and the second gate electrode 8 may also be a silicon oxide film having a trap site inside.
  • a low impurity concentration region may be formed in the substrate surface region under the first gate electrode .6.
  • the memory cells according to the above embodiments are arranged in a matrix to form a memory array.
  • This memory array may be mixed with logic circuits or logic circuits and other memories (such as DRAM and SRAM), and can also be used for non-volatile memory dedicated ICs.
  • the memory cell according to the present invention can be used for an EEPROM that can be erased electrically in units of bytes or words, and can also be used for a flash memory.
  • the EEPROM can be either serial access type or parallel access type.
  • N0R type, NAND type, DI (divided bitline) NOR type, and AN D type memory can be used. It can also be used as a cell.
  • the memory cell according to the present invention can be used as a multi-value cell. Multi-leveling can be performed by changing the amount of charge injected into the trap, and multi-leveling can also be performed by changing the localized position where charge is injected.
  • Writing to the memory cell according to the present invention can be performed by generating hot electrons in the channel and capturing them in the trap site.
  • writing can be performed by injecting electrons from a substrate or a diffusion layer. Erasing may be performed by extracting electrons to the substrate or the diffusion layer, or may be performed by injecting holes from the substrate side.
  • the memory cell of the present invention is characterized by a gate insulating film, and other gate electrode forming steps and diffusion layer forming steps are not different from conventional methods, so only the gate insulating film forming method will be described below. However, it should be understood that the other processes are the same as those generally used.
  • step S 11 thermal oxidation is performed to form a dense silicon oxide film having a thickness of 5 to 15 nm.
  • a metal is deposited on the silicon oxide film by using a liquid phase method or a vapor phase method (step S 1 2).
  • the metal is deposited on the oxide film by applying a solution in which the metal is dissolved in an acid or the like by a spin method, a spray method, a dubbing method, or the like.
  • an activator electroless plating or an electroless plating solution can be used.
  • the metal can be deposited by contact with an after-treatment liquid activated with an activating agent.
  • the vapor phase methods include adsorption of metal-containing gas, vapor deposition method, ion plating method, notch method, CVD (chemical vapor deposition) method, MBE (molecular beam etch) method, ALD (atomic layer deposition) method. Can be used.
  • step S13 the metal diffuses and is taken into the silicon oxide film and becomes a trap site.
  • heat treatment the metal is oxidized easily.
  • an insulating film such as a silicon oxide film is deposited using the C V D method or the sputtering method (step S 14).
  • the thickness of the insulating film to be deposited should be 5 to 15 nm in the case of a silicon oxide film.
  • step S 2 thermal oxidation is performed to form a dense silicon oxide film having a film thickness of 2 to 15 nm.
  • step S 22 a low-density insulating film is formed on the thermal oxide film by a method such as applying silica glass by a spin coating method followed by heat treatment.
  • step S 2 3 a metal is deposited on the low density insulating film by using the method described in the eighth embodiment (step S 2 3).
  • Step S 24 metal impurities deposited by heat treatment are taken into the low-density insulating film.
  • an insulating film such as a silicon oxide film is deposited by using C V D method or sputtering method (step S 25).
  • the insulating film is deposited after the heat treatment in step S 1 3 (step S 2 4). This order may be reversed.
  • the trap site is mainly in the thermal oxide film (in the case of the eighth embodiment) or in the low-density insulating film (first 9), trapping sites are distributed on both sides of the interface between the thermal oxide film or low-density insulating film and the deposited insulating film. Will be formed.
  • thermal oxidation is performed to form a dense silicon oxide film having a thickness of 2 to 15 nm on the substrate (Step S 31 ).
  • step S32 an insulating film is deposited by a vapor phase method.
  • the film growth is continued while flowing the metal compound gas into the chamber or evaporating the metal while taking the metal into the insulating film while continuing the growth of the insulating film (Step S). 33).
  • step S34 When the processing of step S32 reaches a predetermined time, or when the thickness of the metal-containing insulating film reaches a predetermined thickness, the supply of metal is stopped and the growth of the insulating film is continued (step S34).
  • step S34 heat treatment is performed to take the metal into the insulating film.
  • the manufacturing method according to the first embodiment of the present invention is different from the ninth embodiment shown in FIG. 10 in that the deposition of the insulating film in step S 32 is omitted.
  • the insulating film containing impurities (metal) is formed immediately after the step of forming the thermal oxide film. Subsequent to the step of forming the impurity-containing insulating film, the insulating film having no impurities is deposited and heat-treated.
  • thermal oxidation is performed to form a dense silicon oxide film having a film thickness of 2 to 15 nm on the substrate. S 41).
  • step S42 silicon or a silicon compound and a metal are deposited on the thermal oxide film (step S42).
  • the metal may be a single species or a plurality of species. Moreover, a metal compound may be sufficient.
  • the method of step S42 is as follows.
  • a metal-containing silicon film is formed by sputtering.
  • step S 43 heat treatment is performed to form a metal (or metal compound) -containing silicon oxide film.
  • Step S an insulating film is deposited by CVD or sputtering.
  • Step S43 and step S44 may be reversed in order.
  • thermal oxidation is performed to form a dense silicon oxide film having a thickness of 10 to 30 nm on the substrate (Step S). 51).
  • the entire gate insulating film is formed by thermal oxidation.
  • thermal oxidation is performed to a predetermined film thickness in step S 51, and film formation is performed by a CVD method or the like in step S 52 to obtain a goot insulating film having a predetermined film thickness.
  • metal ions are implanted into the gate insulating film to a depth that does not reach the substrate surface (step S 53).
  • Step S heat treatment is performed to incorporate metal impurities into the gate insulating film.
  • thermal oxidation is performed to form a dense silicon oxide film having a thickness of 10 to 30 nm on the substrate (step S 6 1).
  • step S62 trap site forming impurities are diffused into the thermal oxide film by a thermal diffusion method or the like.
  • step S63 an insulating film is deposited thereon (step S63). Thereafter, heat treatment is performed as necessary (step S 64).
  • step S62 When the solid phase method is used as the impurity diffusion method in step S62, as shown in the modification example in FIG. 14B, after the step S61, the transfer containing impurities for trap site formation is performed. A film is formed on the thermal oxide film (step S 62 a).
  • step S 62 b heat treatment is performed to diffuse impurities in the transfer film into the thermal oxide film.
  • step S 6 2 c the transfer film is removed (step S 6 2 c), and the processes after step S 63 are performed.
  • the layer with a high impurity concentration may be removed by wet etching or the like to obtain an ideal impurity trap level.
  • FIGS. 2 to 4 a structure in which a gate insulating film having a trap site and a gate insulating film not having a trap site are provided under the first gate electrode (hereinafter referred to as a merged gate). A method for forming the insulating film will be described.
  • FIG. 15 in the method of forming a merged gate insulating film according to the 15th embodiment of the present invention, as shown in FIG. 15A using any one of the methods shown in FIGS. 8 to 13.
  • a silicon oxide film 3 including trap sites 5 is formed inside. Note that although the gate insulating film is not limited to a silicon oxide film, it is assumed here that the gate insulating film is formed of a silicon oxide film.
  • a part of the silicon oxide film 3 is etched away by using a photolithography method and a wet etching method.
  • thermal oxidation is performed again to form a gate insulating film 7 made of a thermal oxide film.
  • FIGS. 16A to E in the method of forming a merged gate insulating film according to the sixteenth embodiment of the present invention, as shown in FIG. 16A, thermal oxidation is performed on the p-type silicon substrate 1. A silicon oxide film 3 is formed. Next, as shown in FIG. 16B, a photoresist mask 9 is formed using a photolithographic method so as to cover the formation region of the gate insulating film having no intentionally introduced trap site. Next, using a method such as step S 1 2 in FIG. 8, step S 3 3 in FIG. 10, step S 4 2 in FIG. 12, etc., as shown in FIG. A material containing metal atoms 10 or a metal is deposited on the photoresist mask 9. As shown in FIG.
  • a heat treatment is performed to diffuse the metal into the silicon oxide film, thereby forming trap sites in the silicon oxide film '3.
  • an insulating film 4 is formed on the silicon oxide film 3 by a CVD method or the like.
  • the heat treatment in the step shown in FIG. 16D may be after the insulating film 4 is deposited.
  • a region to which impurities are added and a region to which impurities are not added may be formed using polycrystalline silicon as a gate electrode as a mask.
  • Example 1 is a preliminary experiment to confirm the effectiveness of the present invention.
  • a silicon oxide film having a thickness of 1 ⁇ was formed on a silicon substrate at 850 ° C by a dry method.
  • the metal solutions shown in Table 1 were prepared, and each solution was deposited on the oxide film. table 1
  • a silicon oxide film with a thickness of 7 nm is formed on the silicon substrate by thermal oxidation, and Ti, A l, and Au are each formed to a thickness of 0.7 nm by sputtering, and further, A silicon oxide film with a thickness of 10 nm was formed thereon by CVD. Then, heat treatment was performed to diffuse the metal to prepare three types of samples, and EOT was measured for each sample. The results are shown in Table 2.
  • Figure 18 shows the measurement results of the CV characteristics of the sample with Ti diffused.
  • Figure 19 shows the writing characteristics of the sample with Ti diffused when 8 V is applied to the gate and 5 V, 6 V, and 7 V are applied between the source and drain, respectively.
  • Fig. 20 shows the retention characteristics (threshold change over time) of the sample with Ti diffused, along with the retention characteristics of the ONO memory. The retention characteristics of 10 years (3.2 x 10 8 seconds) have not been obtained with ONO memory, but those with Example 2 have been fully cleared.
  • FIG. 21 and 22 show the write characteristics when, respectively, is applied. As can be seen from FIG. 21 and FIG. 22, the threshold value differs between reverse read (positive voltage applied to the drain side) and forward read (positive voltage applied to the source side). It can be seen that electron injection was performed.
  • a silicon oxide film with a thickness of 8 nm is formed on a silicon substrate by thermal oxidation, and then an A 1 containing Si film is formed with a thickness of 1 nm by sputtering using a 5% A 1 containing Si target. And then a silicon oxide film of 8 nm is deposited on it by CVD. Then, heat treatment was performed in an oxidizing atmosphere at 820 ° (: for 1 minute. Even with this method, an electron trap suitable as a nonvolatile memory could be realized. .
  • the semiconductor device and the manufacturing method thereof according to the present invention are applied to a nonvolatile semiconductor memory device such as a flash memory.

Abstract

In a memory cell (20) wherein a gate electrode (6) is formed on a p-type silicon substrate (1) via a silicon oxide film (3) and an n-type diffusion layer to be a source/drain region is formed within surface reagions of the silicon substrate (1) which are located on both sides of the gate electrode (6), an impurity to be a trap site (5) is contained in the silicon oxide film (3). A metal such as Al, Au and Ti is used as the impurity. The gate insulating film may be composed of the silicon oxide film (3) and another insulating film (4). The trap site (5) may be formed in the another insulating film (4) by doping. Alternatively, the interface between the silicon oxide film (3) and the another insulating film (4) may be mainly doped with the impurity. Consequently, there can be obtained a nonvolatile memory having good holding characteristics.

Description

明 細 書 半導体装置およびその製造方法  Description Semiconductor device and manufacturing method thereof
技術分野： Technical field:
本発明は、 不揮発性のメモリセルを有する半導体装置およびその製造方法に関 し、 特にフラッシュメモリに代表される電気的に消去が可能な不揮発性半導体記 憶装置とその製造方法に関するものである。 背景技術：  The present invention relates to a semiconductor device having nonvolatile memory cells and a method for manufacturing the same, and more particularly to an electrically erasable nonvolatile semiconductor memory device represented by a flash memory and a method for manufacturing the same. Background technology:
不揮発性半導体記憶装置としては、 様々な方式のものが実用化されているが、 なお電気的に一括消去を行うフラッシュ E E P R OM (flash electrically era sable and programmable read only memory) 王流と っている。  Various types of nonvolatile semiconductor memory devices have been put into practical use, but the flash EEPROM (flash electrically erasable and programmable read only memory) that performs batch erasing electrically is the mainstream.
フラッシュ E E P R OMのセル構造は、 いくつかの種類が発表されているが、 浮遊グート上に制御ゲート電極を重ねたスタック型が一般的である。 浮遊ゲート を有する構造のメモリセルでは、 浮遊ゲートの周囲のゲート絶縁膜が一箇所でも 欠陥が発生すると浮遊ゲートに注入された電荷がすべて失われてしまうためメモ リとして機能しなくなるという重大な問題点がある。  Several types of flash E E P R OM cell structures have been announced, but the stack type with a control gate electrode on a floating goot is common. In a memory cell with a floating gate structure, if a single gate insulating film around the floating gate has a defect, all of the charge injected into the floating gate will be lost, so it will not function as memory. There is a point.
そして、 この問題点はゲート絶縁膜の薄膜化によって近年一段と深刻化してい る。 この問題点を克服するものとして、 電荷を O N〇 （シリコン酸化膜/シリコ ン窒化膜 Zシリコン酸化膜） 構造の窒化膜のトラップに蓄積する方法 （S O N O Sメモリ） と、 浮遊ゲートに代えてシリコン微粒子を用いる方法 （ナノクリスタ ルメモリ） が提案されている。  This problem has become more serious in recent years due to the thinning of the gate insulating film. In order to overcome this problem, the charge is stored in the trap of the nitride film with the ON ○ (silicon oxide film / silicon nitride film Z silicon oxide film) structure (SONOS memory), and the silicon fine particles instead of the floating gate A method using nanocrystals (nanocrystalline memory) has been proposed.
これらのメモリでは、 一箇所の酸化膜欠陥から大量の電荷が漏れるという欠点 がないばかりでなく、 電荷を局所的に蓄積できることから少量の注入電荷で大き くしきい値を変化させることができる、 多値化が容易であるなどの利点があるの で、 活発に研究 '開発が続けられており、 多くの報告 ·提案がなされている （例 えば、 T. Ogura, et al. , Embedded Twin MONOS Flash Memories with 4ns and 1 5ns Fast Access Times 2003 Symposium on VLS丄 し ireuits Digest of .Technics 1 Papers (非特許文献 1 )、特開 2 0 0 1— 0 1 5 6 1 3号公報（特許文献 1参照）。 シリコン窒化膜のトラップに電荷を蓄積する O N Oメモリでは、 シリコン窒化 膜の深い準位に形成されるトラップに電荷を蓄積するこ'とを予定している。 窒化 シリコンのコンダクションバンドは酸化シリコンのコンダクションバンド端から 1 . 1 e Vの浅いところに存在し、 この準位にも電荷が蓄積される。 そして、 こ の準位に蓄積された電荷は容易に引き抜かれてしまうため、 しきい値が簡単に変 ィ匕してしまうという問題が起こる。 These memories not only have the disadvantage that a large amount of charge leaks from a single oxide film defect, but also because the charge can be stored locally, the threshold can be changed greatly with a small amount of injected charge. Since there is an advantage such as easy pricing, research and development are actively conducted, and many reports and proposals have been made (examples For example, T. Ogura, et al., Embedded Twin MONOS Flash Memories with 4ns and 1 5ns Fast Access Times 2003 Symposium on VLS and ireuits Digest of .Technics 1 Papers (Non-Patent Document 1), JP 0 1 5 6 1 3 (see Patent Document 1). In the ONO memory that accumulates electric charge in the trap of silicon nitride film, it is planned to accumulate electric charge in the trap formed in the deep level of the silicon nitride film. The conduction band of silicon nitride exists at a shallow depth of 1.1 eV from the end of the silicon oxide conduction band, and charges are accumulated at this level. The charge accumulated at this level is easily extracted, which causes a problem that the threshold value changes easily.
また、 一定以上の電荷を蓄積するためには窒化膜の薄膜化には限界があり、 例 えば 5 n m以上の膜厚に形成する必要があるので効果的に E O T (equivalent ox ide thickness ;等価酸化膜厚） を薄くできないという問題点があった。  In addition, there is a limit to thinning the nitride film in order to accumulate more than a certain amount of charge. For example, it is necessary to form a nitride film with a thickness of 5 nm or more. Therefore, EOT (equivalent ox ide thickness) There was a problem that the film thickness could not be reduced.
さらに、 トンネル酸化膜と窒化膜との界面に欠陥 （準位） が形成されてしまう ため、 この準位を伝って蓄積電荷が漏れてしまう問題も発生する。 すなわち、 長 期の保持特性を期待することができない。  Furthermore, since defects (levels) are formed at the interface between the tunnel oxide film and the nitride film, there also arises a problem that stored charges leak through this level. In other words, long-term retention characteristics cannot be expected.
一方、 微粒子シリコンに電荷を蓄積するナノクリスタルメモリでは、 シリコン 微粒子の粒径のばらつきが大きいため、 特性のばらつきが大きくなるという問題 がある。 また、 一微粒子に一個の電子が注入されると次の電子の注入される確率 が低くなるため、 大量の電子の蓄積が困難であるという問題もある。 さらに、 微 粒子形成膜上に電極間絶縁膜を形成しなければならないため、 高品質の絶縁膜が 得られにくく信頼性の低下が問題となっている。 発明の開示：  On the other hand, nanocrystal memory that accumulates electric charge in fine particle silicon has a problem that the variation in characteristics is large because the particle size variation of silicon fine particles is large. Another problem is that when one electron is injected into one particle, the probability of the injection of the next electron is reduced, making it difficult to store a large amount of electrons. Furthermore, since an interelectrode insulating film must be formed on the fine particle forming film, it is difficult to obtain a high-quality insulating film, resulting in a decrease in reliability. Disclosure of the invention:
発明が解決しょうとする課題：  Problems to be solved by the invention:
本発明の技術的課題は上述した従来技術の問題点を解決することであって、 そ の目的は、 第 1に、 電子蓄積層に電子を捕獲する浅い準位が形成されないように することであり、 第 2に、 E O Tの十分に薄膜化されたゲート絶縁膜を実現でき るようにすることであり、 第 3に、 十分な電荷を蓄積することができ力つ蓄積し た電荷が失われにくい信頼性の高い不揮発性メモリを提供できるようにすること である。 The technical problem of the present invention is to solve the above-mentioned problems of the prior art. The first object is to prevent the formation of shallow levels for trapping electrons in the electron storage layer. Second, it is possible to realize a gate insulating film with a sufficiently thin EOT. Third, sufficient charge can be accumulated and the accumulated charge is lost. To be able to provide hard and reliable non-volatile memory It is.
課題を解決するための手段：  Means to solve the problem:
本発明の一態様によれば、 基板上にゲート絶縁膜を介して形成された第 1のゲ ート電極と、 基板表面領域に形成されたソース · ドレイン領域とを有する不揮発 性のメモリセルを備える半導体装置において、 前記ゲート絶縁膜にはトラップサ ィトとなる金属を含む不純物が添カ卩されたトラップサイト含有層が含まれること を特徴とする半導体装置が得られる。  According to one aspect of the present invention, a nonvolatile memory cell having a first gate electrode formed on a substrate via a gate insulating film and a source / drain region formed on the substrate surface region is provided. In the semiconductor device provided, the semiconductor device is characterized in that the gate insulating film includes a trap site-containing layer to which an impurity including a metal that becomes a trap site is added.
ここで、本発明の前記態様における半導体装置において、前記グート絶縁膜は、 一部又は全部にシリコン酸化膜を有することが好ましい。  Here, in the semiconductor device according to the aspect of the present invention, it is preferable that the goot insulating film has a silicon oxide film in part or in whole.
また、 本発明の前記態様における半導体装置において、 前記メモリセルは複数 個形成されていることが好ましい。  In the semiconductor device according to the aspect of the invention, it is preferable that a plurality of the memory cells are formed.
また、 本発明のもう一つの態様によれば、 前記半導体装置において、 前記基板 の一領域上に前記メモリセルが形成されており、 更に、 前記基板の他の領域上に ロジック回路が形成されていることを特徴とする半導体装置が得られる。  According to another aspect of the present invention, in the semiconductor device, the memory cell is formed on one region of the substrate, and a logic circuit is formed on another region of the substrate. Thus, a semiconductor device can be obtained.
ここで、 本発明の前記態様における半導体装置において、 前記メモリセルは複 数個形成されていることが好ましい。  Here, in the semiconductor device according to the aspect of the present invention, it is preferable that a plurality of the memory cells are formed.
また、 本発明のさらにもう一つの態様によれば、 不揮発性のメモリセルを有す る半導体装置の製造方法であって、 メモリセルのゲート絶縁膜の製造工程が、 絶 縁膜を堆積する工程と、 トラップサイトとなる不純物を堆積する工程と、 を有し ていることを特徴とする半導体装置の製造方法が得られる。  According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a nonvolatile memory cell, wherein the manufacturing process of the gate insulating film of the memory cell includes the step of depositing an insulating film. And a step of depositing impurities that serve as trap sites, and a method for manufacturing a semiconductor device is provided.
ここで、 本発明の前記態様における半導体装置の製造方法において、 更に、 シ リコン基板表面を熱酸化する工程を有することが好ましい。  Here, in the method of manufacturing a semiconductor device according to the aspect of the present invention, it is preferable that the method further includes a step of thermally oxidizing the surface of the silicon substrate.
また、 本発明の前記態様における半導体装置の製造方法において、 前記メモリ セルは複数個形成されることが好ましい。  In the method for manufacturing a semiconductor device according to the aspect of the present invention, it is preferable that a plurality of the memory cells are formed.
また、 本発明の別の一つの態様によれば、 不揮発性のメモリセルを有する半導 体装置の製造方法であって、 メモリセルのゲート絶縁膜の製造工程が、 シリコン 基板表面を熱酸化する工程と、 形成された熱酸化膜中にイオン注入法により トラ ップサイトとなる不純物を導入する工程と、 を有することを特徴とする半導体装 置の製造方法が得られる。 ここで、 本発明の前記態様における半導体装置の製造 方法において、 前記メモリセルは複数個形成されることが好ましい。 According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device having a non-volatile memory cell, wherein the manufacturing process of the gate insulating film of the memory cell thermally oxidizes the surface of the silicon substrate. There is obtained a method for manufacturing a semiconductor device, comprising: a step; and a step of introducing an impurity to be a trap site into the formed thermal oxide film by an ion implantation method. Here, manufacture of the semiconductor device in the said aspect of this invention In the method, a plurality of the memory cells are preferably formed.
また、 本発明の別のもう一つの態様によれば、 不揮発性のメモリセルを有する 半導体装置の製造方法であって、 メモリセルのゲート絶縁膜の製造工程が、 シリ コン基板表面を熱酸化する工程と、 形成された熱酸化膜上にトラップサイトとな る不純物を含む転写膜を堆積する工程と、 熱処理を行ないトラップサイ トとなる 不純物を熱酸化膜に拡散する工程と、 転写膜を選択的に除去する工程と、 熱酸化 膜上に絶縁膜を形成する工程と、 を有することを特徴とする半導体装置の製造方 法が得られる。 ここで、 本発明の前記態様における半導体装置の製造方法におい て、 前記メモリセルは複数個形成されることが好ましい。  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device having a nonvolatile memory cell, wherein the manufacturing process of the gate insulating film of the memory cell thermally oxidizes the surface of the silicon substrate. A step of depositing a transfer film containing impurities that become trap sites on the formed thermal oxide film, a step of performing heat treatment to diffuse the impurities that become trap sites into the thermal oxide film, and a transfer film A method of manufacturing a semiconductor device, comprising: a step of removing the conductive film; and a step of forming an insulating film on the thermal oxide film. Here, in the method of manufacturing a semiconductor device according to the aspect of the present invention, it is preferable that a plurality of the memory cells are formed.
さらに、 本発明の別のさらにもう一つの態様によれば、 不揮発性のメモリセル を有する半導体装置の製造方法であって、 メモリセルのゲート絶縁膜の製造工程 が、シリコン基板表面を熱酸化する工程と、気相法にて絶縁膜を形成する工程と、 を有しており、 前記気相法にて絶縁膜を形成する工程においては途中ないし初期 の一定期間トラップサイ トとなる不純物またはその化合物ガスを供給しつつ膜形 成を行うことを特徴とする半導体装置の製造方法が得られる。 ここで、 本発明の 前記態様における半導体装置の製造方法において、 前記メモリセルは複数個形成 されていることが好ましい。  Furthermore, according to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a nonvolatile memory cell, wherein the step of manufacturing the gate insulating film of the memory cell thermally oxidizes the surface of the silicon substrate. And a step of forming an insulating film by a vapor phase method. In the step of forming an insulating film by the vapor phase method, an impurity that becomes a trap site during a certain period of time or in the initial stage or its A method for manufacturing a semiconductor device is provided, in which film formation is performed while supplying a compound gas. Here, in the method of manufacturing a semiconductor device according to the aspect of the present invention, it is preferable that a plurality of the memory cells are formed.
発明の効果：  The invention's effect:
本発明の半導体装置の不揮発性メモリにおいては、 シリコン酸化膜に含まれる 金属などの不純物によって導入されるトラップサイ トによって電荷が蓄積される。 そのためシリコン窒化膜の場合のように浅い準位が形成されることがなくなりか つ界面欠陥を介して蓄積電荷が失われることがなくなり、 保持特性を改善するこ とができる。 また、 トラップサイトがシリコン酸化膜の中に作り込まれるため、 電荷捕獲層となる絶縁膜によつて膜厚が使われることがなくなり、 E O Tの薄膜 化が可能になる。 そして、 この構造の不揮発性メモリを作成するために追加され る工程は、 熱酸化膜上に薄く金属を付着するだけでよいので、 容易に低コストで 製造することができる。 また、 通常の MO S型半導体装置との製造工程との差が 少ないので、 ロジック回路との混載を容易に実現することができる。 図面の簡単な説明： In the nonvolatile memory of the semiconductor device of the present invention, electric charges are accumulated by trap sites introduced by impurities such as metal contained in the silicon oxide film. Therefore, a shallow level is not formed as in the case of a silicon nitride film, and accumulated charge is not lost via an interface defect, and the retention characteristics can be improved. In addition, since the trap site is formed in the silicon oxide film, the film thickness is not used by the insulating film that becomes the charge trapping layer, and the EOT can be made thinner. The process added to create the non-volatile memory having this structure is only required to deposit a thin metal on the thermal oxide film, so that it can be easily manufactured at low cost. In addition, since there is little difference between the manufacturing process and the normal MOS type semiconductor device, it is possible to easily implement the mixed mounting with the logic circuit. Brief description of the drawings:
図 1 Aは本発明の第 1の実施例によるメモリセルの断面図である。  FIG. 1A is a cross-sectional view of a memory cell according to a first embodiment of the present invention.
図 1 Bは本発明の第 1の実施例の一変形例によるメモリセルの断面図である。 図 1 Cは本発明の第 1の実施例のもう一つの変形例によるメモリセルの断面図 である。  FIG. 1B is a cross-sectional view of a memory cell according to a modification of the first embodiment of the present invention. FIG. 1C is a cross-sectional view of a memory cell according to another modification of the first embodiment of the present invention.
図 1 Dは本発明の第 1の実施例のさらにもう一つの変形例によるメモリセルの 断面図である。  FIG. 1D is a cross-sectional view of a memory cell according to still another modification of the first embodiment of the present invention.
図 2は本発明の第 2の実施例によるメモリセルの断面図である。  FIG. 2 is a cross-sectional view of a memory cell according to a second embodiment of the present invention.
図 3は本発明の第 3の実施例によるメモリセルの断面図である。  FIG. 3 is a cross-sectional view of a memory cell according to a third embodiment of the present invention.
図 4は本発明の第 4の実施例によるメモリセルの断面図である。  FIG. 4 is a cross-sectional view of a memory cell according to a fourth embodiment of the present invention.
図 5は本発明の第 5の実施例によるメモリセルの断面図である。  FIG. 5 is a cross-sectional view of a memory cell according to a fifth embodiment of the present invention.
図 6は本発明の第 6の実施例によるメモリセルの断面図である。  FIG. 6 is a sectional view of a memory cell according to a sixth embodiment of the present invention.
図 7は本発明の第 7の実施例によるメモリセルの断面図である。  FIG. 7 is a cross-sectional view of a memory cell according to a seventh embodiment of the present invention.
図 8は本発明の第 8の実施例による半導体装置の製造方法を示す流れ図である。 図 9は本発明の第 9の実施例による半導体装置の製造方法を示す流れ図である。 図 1 0は本発明の第 1 0の実施例による半導体装置の製造方法を示す流れ図で ある。  FIG. 8 is a flowchart showing a method of manufacturing a semiconductor device according to the eighth embodiment of the present invention. FIG. 9 is a flowchart showing a method of manufacturing a semiconductor device according to the ninth embodiment of the present invention. FIG. 10 is a flowchart showing a method of manufacturing a semiconductor device according to the tenth embodiment of the present invention.
図 1 1は本発明の第 1 1の実施例による半導体装置の製造方法を示す流れ図で ある。  FIG. 11 is a flowchart showing a method of manufacturing a semiconductor device according to the first example of the present invention.
図 1 2は本発明の第 1 2の実施例による半導体装置の製造方法を示す流れ図で ある。  FIG. 12 is a flowchart showing a method of manufacturing a semiconductor device according to the first and second embodiments of the present invention.
図 1 3は本発明の第 1 3の実施例による半導体装置の製造方法を示す流れ図で ある。  FIG. 13 is a flowchart showing a method of manufacturing a semiconductor device according to the thirteenth embodiment of the present invention.
図 1 4 Aは本発明の第 1 4の実施例による半導体装置の製造方法を示す流れ図 である。  FIG. 14A is a flowchart showing a method of manufacturing a semiconductor device according to the 14th embodiment of the present invention.
図 1 4 Bは本発明の第 1 4の実施例の変形例による半導体装置の製造方法を示 す流れ図である。  FIG. 14B is a flowchart showing a semiconductor device manufacturing method according to a modification of the 14th embodiment of the present invention.
図 1 5 Aは本発明の第 1 5の実施例よるメモリセルの併合ゲート絶縁膜の形成 方法を示す工程順の断面図である。 図 1 5 Bは本発明の第 1 5の実施例よるメモリセルの併合ゲート絶縁膜の形成 方法を示す工程順の断面図である。 FIG. 15A is a cross-sectional view in order of steps showing a method for forming a merged gate insulating film of a memory cell according to a fifteenth embodiment of the present invention. FIG. 15B is a cross-sectional view in order of the steps showing the method for forming the merged gate insulating film of the memory cell according to the fifteenth embodiment of the present invention.
図 1 5 Cは本発明の第 1 5の実施例よるメモリセルの併合ゲート絶縁膜の形成 方法を示す工程順の断面図である。  FIG. 15C is a cross-sectional view in order of the steps showing the method for forming the merged gate insulating film of the memory cell according to the 15th embodiment of the present invention.
図 1 6 Aは本発明の第 1 6の実施例によるメモリセルの併合ゲート絶縁膜の第 2の形成方法を示す工程順の断面図である。  FIG. 16A is a sectional view in order of steps showing a second method of forming a merged gate insulating film of a memory cell according to a sixteenth embodiment of the present invention.
図 1 6 Bは本発明の第 1 6の実施例によるメモリセルの併合ゲート絶縁膜の第 2の形成方法を示す工程順の断面図である。  FIG. 16B is a cross-sectional view in order of the steps showing a second method of forming the merged gate insulating film of the memory cell according to the sixteenth embodiment of the present invention.
図 1 6 Cは本発明の第 1 6の実施例によるメモリセルの併合ゲート絶縁膜の第 2の形成方法を示す工程順の断面図である。  FIG. 16C is a cross-sectional view in order of the steps showing a second method of forming the merged gate insulating film of the memory cell according to the sixteenth embodiment of the present invention.
図 1 6 Dは本発明の第 1 6の実施例によるメモリセルの併合ゲート絶縁膜の第 2の形成方法を示す工程順の断面図である。  FIG. 16D is a cross-sectional view in order of the steps showing a second method of forming the merged gate insulating film of the memory cell according to the sixteenth embodiment of the present invention.
図 1 6 Eは本発明の第 1 6の実施例によるメモリセルの'併合ゲート絶縁膜の第 2の形成方法を示す工程順の断面図である。  FIG. 16E is a cross-sectional view in order of the steps showing a second method of forming the 'merged gate insulating film' of the memory cell according to the sixteenth embodiment of the present invention.
図 1 7は本発明の具体例 1の測定結果である電荷密度を示すダラフ。  FIG. 17 is a graph showing the charge density as a measurement result of Example 1 of the present invention.
図 1 8は本発明の具体例 2の C V特性図 （ T i ) である。  FIG. 18 is a C V characteristic diagram (T i) of Example 2 of the present invention.
図 1 9は本発明の具体例 2の書き込み特性図 （T i ) である。  FIG. 19 is a write characteristic diagram (T i) of Example 2 of the present invention.
図 2 0は本発明の具体例 2の保持特性図 （T i ) である。  FIG. 20 is a holding characteristic diagram (T i) of Example 2 of the present invention.
図 2 1は本発明の具体例 2の書き込み特性図 （A 1 ) である。  FIG. 21 is a write characteristic diagram (A 1) of Example 2 of the present invention.
図 2 2は本発明の具体例 2の書き込み特性図 （A u ) である。 発明を実施するための最良の形態：  FIG. 22 is a write characteristic diagram (A u) of Example 2 of the present invention. Best Mode for Carrying Out the Invention:
次に、 本発明を添付した図面を参照しながら、 詳細に説明する。  Next, the present invention will be described in detail with reference to the accompanying drawings.
図 1 Aを参照すると、 第 1の実施例によるメモリセル 2 0は、 p型シリコン基 板 1にソース ' ドレイン領域となる n型拡散層 2が形成され、 その間にゲート絶 縁膜となるシリコン酸化膜 3が形成されている。 シリコン酸化膜 3には、 トラッ プサイト 5が形成されている。 このシリコン酸化膜 3上に、 ポリシリコン、 ポリ サイド、 シリサイド、 高融点金属などによって第 1のゲート電極が形成されてい る。 トラップサイト 5は、 チャネルに発生する CHE (channel hot electron)や高 電界印加によつて発生する F— N (Fowler-Nordheim)電流などにより電子が注入 される欠陥である。 その欠陥はシリコン酸化膜 3に添加された不純物である金属 によって導入されるものである。 Referring to FIG. 1A, in the memory cell 20 according to the first embodiment, an n-type diffusion layer 2 serving as a source / drain region is formed on a p-type silicon substrate 1, and a silicon serving as a gate insulating film therebetween. An oxide film 3 is formed. Trap sites 5 are formed in the silicon oxide film 3. On the silicon oxide film 3, a first gate electrode is formed of polysilicon, polycide, silicide, refractory metal, or the like. The trap site 5 is a defect in which electrons are injected by CHE (channel hot electron) generated in a channel or F—N (Fowler-Nordheim) current generated by applying a high electric field. The defect is introduced by a metal which is an impurity added to the silicon oxide film 3.
本発明において、 シリコン酸化膜に添カ卩される金属は特に限定はされないが、 シリコン酸化膜中での拡散係数が低くかつシリコン酸化膜において深い準位を形 成できることである。 この条件を満たす金属として、 Mgと、 元素の周期表にお いて 3A族 （3族） から 6B族 （1 6族） （（ ） 内は、 I UPAC無機化学命名 法改訂版 （1 989) による） までに含まれる金属 （すなわち、 1A族 （1族） と Mg以外の 2A族 （2族） の金属を除く金属） が挙げられる。 これらの金属に は、 S i， Ge， S e , T e等の半導体は含まれず、 また、 B， C， P， A s, S b, B i， P o等の半金属は含まれる。 特に好ましい金属材料は、 A l、 Au、 Co、 C r、 Cu、 F e、 I r、 L a、 Mg、 Mn、 N i、 Ru、 Sn、 Ta、 T i、 T l、 Zn、 'Wである。 これらの金属の複数種が含まれていてもよい。 ま た、 純金属であっても酸化金属ゃ窒化金属あるいは金属シリケートなどの化合物 として含まれていてもよい。  In the present invention, the metal added to the silicon oxide film is not particularly limited, but it has a low diffusion coefficient in the silicon oxide film and can form deep levels in the silicon oxide film. As a metal that satisfies this condition, Mg and Group 3A (Group 3) to Group 6B (Group 16) in the periodic table of elements (in parentheses are from I UPAC inorganic chemical nomenclature revised edition (1 989)) ) (Ie, metals excluding Group 1A (Group 1) and Group 2A (Group 2) metals other than Mg). These metals do not include semiconductors such as Si, Ge, Se, and Te, and include semimetals such as B, C, P, As, Sb, Bi, and Po. Particularly preferred metal materials are Al, Au, Co, Cr, Cu, Fe, Ir, La, Mg, Mn, Ni, Ru, Sn, Ta, Ti, Ti, Zn, 'W It is. Multiple types of these metals may be included. Further, even a pure metal may be contained as a compound such as a metal oxide, a metal nitride, or a metal silicate.
トラップサイト 5が存在している箇所より上の酸化膜の膜厚を 10 nmとした とき、しきい値を IV変化させるに必要な電子密度は 2 X 1012ノ cm2程度であ る。 通常、 ビット識別に必要なしきい値変化は数 Vであるので、 書き込み時に 1 X 1013Z cm2程度の密度に電子が注入されれば十分である。 この密度は、酸化 膜に添加される不純物に対応すると考えられるので、 シリコン酸化膜に添カ卩され る不純物 （金属） の密度は 1 X 1013/cm2以下であってよい。 When the thickness of the oxide film above the site where the trap site 5 exists is 10 nm, the electron density required to change the threshold IV is about 2 X 10 12 cm 2 . Usually, the threshold change necessary for bit identification is a few volts, so it is sufficient if electrons are injected to a density of about 1 X 10 13 Z cm 2 during writing. Since this density is considered to correspond to the impurity added to the oxide film, the density of the impurity (metal) added to the silicon oxide film may be 1 × 10 13 / cm 2 or less.
トラップサイトは離散的に酸化膜中に存在するものであるので、 本発明に係る メモリセルは、 ONOメモリの場合のように膜厚のある電荷蓄積層を有していな い。 し力、し、 トラップサイトが集中的に存在している層 （以下、 トラップ含有層 と記す） は存在している。 トラップ含有層から基板までの酸化膜 （トンネル酸化 膜とする） の膜厚とトラップ含有層からゲート電極までの酸化膜 （トップ酸化膜 とする） の膜厚は電荷保持のため一定以上の厚さが必要であるので、 ゲート絶縁 膜の膜厚を薄くするにはトラップ含有層を極力薄くすることが好ましい。 不純物 (金属） は、 例えばスパッタ法などにより酸化膜上に付着されその後の熱処理に より拡散して酸化膜に取り込まれるものである。 したがって、 不純物は当初単原 子層ないし数原子層程度の膜厚に形成されるが熱処理後には一定の広がりを持つ。 その広がり範囲 （層厚） は 1 n m程度と見込まれせいぜい 3 n mである。 したが つて、 トンネル酸化膜とトツプ酸化膜とがそれぞれ 1 0 n mであるとすると、 ト ラップ含有層の膜厚はゲート絶縁膜の膜厚の 3 / 2 0以下ということになる。 Since the trap sites are discretely present in the oxide film, the memory cell according to the present invention does not have a charge storage layer having a thickness as in the case of the ONO memory. There is a layer where trap sites are concentrated (hereinafter referred to as trap-containing layer). The film thickness of the oxide film from the trap-containing layer to the substrate (referred to as the tunnel oxide film) and the film thickness of the oxide film from the trap-containing layer to the gate electrode (referred to as the top oxide film) are more than a certain thickness to retain the charge. Therefore, it is preferable to make the trap-containing layer as thin as possible in order to reduce the thickness of the gate insulating film. impurities (Metal) is deposited on the oxide film by, for example, sputtering, and diffused and taken into the oxide film by subsequent heat treatment. Therefore, the impurity is initially formed to a thickness of about a single atomic layer or several atomic layers, but has a certain spread after the heat treatment. The spread range (layer thickness) is expected to be about 1 nm and is at most 3 nm. Therefore, if the tunnel oxide film and the top oxide film are 10 nm each, the thickness of the trap-containing layer is 3/20 or less of the thickness of the gate insulating film.
図 1 Bを参照すると、 第 1の実施例の一変形例によるメモリセル 2 0は、 トラ ップサイト 5を含むシリコン酸化膜 3上にシリコン酸化膜以外の絶縁膜 4を堆積 したものである。 絶縁膜 4の材料としては、 酸窒化シリコン、 窒化シリコン、 P S G (リンガラス）、 B P S G (ボロンリンガラス） などのシリコン系絶縁材料を 用いることができ、 また B S T (チタン酸バリウム 'ストロンチウム）、 酸化タン タル、 酸化ジルコニウム、 酸化ハフニウム、 酸化アルミニウム等の高誘電率材料 を用いることができる外複合膜を用いることもできる。 また、 組成が、 例えば、 S i 0 2→S i O N→S i 3 N 4→S i O N→S i O 2と徐々に変化する絶縁膜であ つてもよい。 Referring to FIG. 1B, a memory cell 20 according to a modification of the first embodiment is obtained by depositing an insulating film 4 other than a silicon oxide film on a silicon oxide film 3 including a trap site 5. As the material of the insulating film 4, silicon-based insulating materials such as silicon oxynitride, silicon nitride, PSG (phosphorus glass), BPSG (boron phosphorous glass), BST (barium titanate 'strontium), oxide An outer composite film that can use a high dielectric constant material such as tantalum, zirconium oxide, hafnium oxide, and aluminum oxide can also be used. Further, the insulating film may be an insulating film whose composition gradually changes, for example, S i 0 2 → S i ON → S i 3 N 4 → S i ON → S i O 2 .
図 1 Cに示す第 1の実施例のもう一つの変形例によるメモリセル 2 0では、 ト ラップサイト 5はシリコン酸化膜 3には含まれておらず、 絶縁膜 4側に含まれて いる。  In the memory cell 20 according to another modification of the first embodiment shown in FIG. 1C, the trap site 5 is not included in the silicon oxide film 3, but is included in the insulating film 4 side.
また、 図 1 Dに示す第 1の実施例のさらにもう一つの変形例では、 トラップサ ィト 5はシリコン酸化膜 3と絶縁膜 4との界面に形成されている。 この例の場合、 シリコン酸化膜 3と絶縁膜 4との界面に形成される界面準位が少ない材料を選択 することが好ましい。  In yet another modification of the first embodiment shown in FIG. 1D, the trap site 5 is formed at the interface between the silicon oxide film 3 and the insulating film 4. In the case of this example, it is preferable to select a material having a low interface state formed at the interface between the silicon oxide film 3 and the insulating film 4.
図 2を参照すると、 本発明の第 2の実施例によるメモリセル 2 1においては、 トラップサイトを含むグート絶縁膜は図 1 Aに示されるグート絶縁膜の全体がシ リコン酸化膜で形成されたものについてのみ説明するが、 図 1 B〜図 1 Dに示さ れるものであってもよい。 このことは以下の実施の形態についても同様である。 第 2の実施例によるメモリセル 2 1においては、 第 1のゲート電極 6は、 トラ ップサイト 5を内部に有するシリコン酸化膜 3と トラップサイトが意図的に導入 されてはいないゲート絶縁膜 7とに跨って形成されている。 シリコン酸化膜 3は ソース ' ドレイン領域の一方寄りに、 ゲート絶縁膜 7は他方寄りに形成されてい る。 Referring to FIG. 2, in the memory cell 21 according to the second embodiment of the present invention, the goot insulating film including the trap site is formed entirely of the silicon oxide film shown in FIG. 1A. Although only the thing is demonstrated, what is shown by FIG. 1B-FIG. 1D may be sufficient. The same applies to the following embodiments. In the memory cell 21 according to the second embodiment, the first gate electrode 6 includes a silicon oxide film 3 having a trap site 5 inside and a gate insulating film 7 in which no trap site is intentionally introduced. It is formed straddling. Silicon oxide film 3 The gate insulating film 7 is formed near one side of the source / drain region.
図 3を参照すると、 本発明の第 3の実施例によるメモリセル 2 2においては、 第 1のゲート電極 6は、 トラップサイト 5を内部に有するシリコン酸化膜 3とト ラップサイトが意図的には導入されてはいないゲート絶縁膜 7とに跨って形成さ れている。 シリコン酸化膜 3はチャネル領域上の中央部に、 ゲート絶縁膜 7はソ ースおよびドレイン領域寄りに夫々形成されている。  Referring to FIG. 3, in the memory cell 22 according to the third embodiment of the present invention, the first gate electrode 6 includes a silicon oxide film 3 having a trap site 5 inside and a trap site intentionally. It is formed across the gate insulating film 7 that has not been introduced. The silicon oxide film 3 is formed at the center on the channel region, and the gate insulating film 7 is formed near the source and drain regions.
図 4を参照すると、 本発明の第 4の実施例によるメモリセル 2 3においては、 第 1のゲート電極 6は、 トラップサイト 5を内部に有するシリコン酸化膜 3とト ラップサイトが意図的には導入されてはいないゲート絶縁膜 7とに跨って形成さ れている。 シリコン酸化膜 3はソースおよびドレイン領域寄りに、 ゲート絶縁膜 7はチヤネル領域上の中央部に夫々形成されている。  Referring to FIG. 4, in the memory cell 23 according to the fourth embodiment of the present invention, the first gate electrode 6 is intentionally formed by the silicon oxide film 3 having the trap site 5 and the trap site intentionally. It is formed across the gate insulating film 7 that has not been introduced. The silicon oxide film 3 is formed near the source and drain regions, and the gate insulating film 7 is formed in the central portion on the channel region.
図 5を参照すると、 本発明の第 5の実施例によるメモリセル 2 5においては、 第 1のゲート電極 6は、 トラップサイト 5を内部に有するシリコン酸化膜 3上に 形成され、 第 2のゲート電極 8は、 トラップサイトが意図的には導入されてはい ないグート絶縁膜 7上形成されている。  Referring to FIG. 5, in the memory cell 25 according to the fifth embodiment of the present invention, the first gate electrode 6 is formed on the silicon oxide film 3 having the trap site 5 therein, and the second gate The electrode 8 is formed on the goot insulating film 7 where no trap site is intentionally introduced.
この第 5の実施例による構造の一変形例として、 第 1のゲート電極 6と第 2の ゲート電極 8との間の基板表面にソース · ドレイン領域となる n型拡散層を形成 するようにしてもよい。  As a modification of the structure according to the fifth embodiment, an n-type diffusion layer serving as a source / drain region is formed on the substrate surface between the first gate electrode 6 and the second gate electrode 8. Also good.
図 6を参照すると、 本発明の第 6の実施例によるメモリセル 2 5においては、 第 1のゲート電極 6は、 トラップサイト 5を内部に有するシリコン酸化膜 3上に 形成され、 第 2のゲート電極 8は、 トラップサイトが意図的には導入されてはい ないゲート絶縁膜 7上形成されている。 そして、 第 2のゲート電極 8は、 その一 部が第 1のグート電極 6上に載り上げるように形成されている。  Referring to FIG. 6, in the memory cell 25 according to the sixth embodiment of the present invention, the first gate electrode 6 is formed on the silicon oxide film 3 having the trap site 5 therein, and the second gate The electrode 8 is formed on the gate insulating film 7 where no trap site is intentionally introduced. The second gate electrode 8 is formed so that a part of the second gate electrode 8 is placed on the first gout electrode 6.
図 7を参照すると、 本発明の第 7の実施例によるメモリセル 2 6においては、 第 2のゲート電極 8は、 トラップサイトが意図的には導入されてはいないゲート 絶縁膜 7上形成されている。 第 1のゲート電極 8の両サイドに、 第 1のゲート電 極 6力 Sトラップサイト 5を内部に有するシリコン酸化膜 3上に側壁膜形状に形成 されている。 第 1のゲート電極 6と第 2のゲート電極 8との間の絶縁膜もトラップサイ トを 内部に有するシリコン酸化膜であってもよい。 また、 第 1のゲート電極 .6下の基 板表面領域内に低不純物濃度領域が形成されていてもよい。 Referring to FIG. 7, in the memory cell 26 according to the seventh embodiment of the present invention, the second gate electrode 8 is formed on the gate insulating film 7 where the trap site is not intentionally introduced. Yes. On both sides of the first gate electrode 8, the first gate electrode 6 is formed in a sidewall film shape on the silicon oxide film 3 having the S trap site 5 inside. The insulating film between the first gate electrode 6 and the second gate electrode 8 may also be a silicon oxide film having a trap site inside. A low impurity concentration region may be formed in the substrate surface region under the first gate electrode .6.
上記の各実施例によるメモリセルは、 マトリクス状に配置されてメモリアレイ を構成する。 このメモリアレイはロジック回路またはロジック回路および他のメ モリ （D R AMや S R AMなど） と混載されていてもよく、 また不揮発性メモリ 専用 I Cに用いることもできる。  The memory cells according to the above embodiments are arranged in a matrix to form a memory array. This memory array may be mixed with logic circuits or logic circuits and other memories (such as DRAM and SRAM), and can also be used for non-volatile memory dedicated ICs.
本発明に係るメモリセルは、 電気的にバイ トないしワード単位で消去可能な E E P R OM用に用いることもできまたフラッシュメモリ用に用いることもできる。 E E P R OMとしては、 シリアルアクセス型、 パラレルアクセス型のいずれであ つてもよく、 またフラッシュメモリの場合、 N〇R型、 N A N D型、 D I (divid ed bitline) N O R型、 AN D型のいずれのメモリのセルとしても用いることがで さる。  The memory cell according to the present invention can be used for an EEPROM that can be erased electrically in units of bytes or words, and can also be used for a flash memory. The EEPROM can be either serial access type or parallel access type. In the case of flash memory, N0R type, NAND type, DI (divided bitline) NOR type, and AN D type memory can be used. It can also be used as a cell.
本発明に係るメモリセルは、多値のセルとして用いることができる。多値化は、 トラップに注入される電荷量を変えることによって行うことができ、 また電荷の 注入される局在位置を変えることによって多値化することもできる。  The memory cell according to the present invention can be used as a multi-value cell. Multi-leveling can be performed by changing the amount of charge injected into the trap, and multi-leveling can also be performed by changing the localized position where charge is injected.
本発明に係るメモリセルに対する書き込みは、 チャネルにホットエレクトロン を発生させてこれをトラップサイ トに捕獲させることによって行うことができる。 あるいは、 基板ないし拡散層から電子注入を行って書き込むことも'できる。 消去 は、 基板または拡散層へ電子を引き抜くことによって行ってもよいし、 ホールを 基板側から注入して行ってもよい。 · 次に、 本発明の半導体装置の製造方法の具体例について説明する。 本発明のメ モリセルはゲート絶縁膜に特徴があり、 その他のゲート電極の形成工程、 拡散層 の形成工程は、 従来の方法と変わらないので、 以下ゲート絶縁膜の形成方法につ いてのみ説明するが、 その他の工程は一般的に用いられている手法と同様である ものと理解されたい。  Writing to the memory cell according to the present invention can be performed by generating hot electrons in the channel and capturing them in the trap site. Alternatively, writing can be performed by injecting electrons from a substrate or a diffusion layer. Erasing may be performed by extracting electrons to the substrate or the diffusion layer, or may be performed by injecting holes from the substrate side. Next, a specific example of the method for manufacturing a semiconductor device of the present invention will be described. The memory cell of the present invention is characterized by a gate insulating film, and other gate electrode forming steps and diffusion layer forming steps are not different from conventional methods, so only the gate insulating film forming method will be described below. However, it should be understood that the other processes are the same as those generally used.
図 8を参照すると、 第 8の実施例による製造方法では、 まず、 熱酸化を行って 膜厚 5〜1 5 n mの緻密なシリコン酸化膜を形成する （ステップ S 1 1 )。 このェ 程は、 MO S トランジスタの製造工程で通常行っている工程と同じである。 次に、シリコン酸化膜上に液相法あるいは気相法を用いて金属を付着させる（ス テツプ S 1 2 )。 液相法では、 金属を酸などに溶解した溶液をスピン法、 スプレイ 法、 ディッビング法などにより塗布することによって金属を酸化膜上に付着させ る。 溶液として無電解めつき用の活性化剤 (キヤタリス ト) や無電解めつき液を 用いることもできる。 さらに、 活性化剤で活性化した後めつき液と接触させて金 属を堆積することもできる。 気相法としては、 金属含有ガスの吸着、 蒸着法、 ィ オンプレーティング法、 スノ ッタ法、 C V D (chemical vapor deposition)法、 MB E (molecular beam e itaxy) 法、 A L D (atomic layer deposition) 法な どを用いることができる。 Referring to FIG. 8, in the manufacturing method according to the eighth embodiment, first, thermal oxidation is performed to form a dense silicon oxide film having a thickness of 5 to 15 nm (step S 11). This process is the same as the process normally performed in the manufacturing process of the MO S transistor. Next, a metal is deposited on the silicon oxide film by using a liquid phase method or a vapor phase method (step S 1 2). In the liquid phase method, the metal is deposited on the oxide film by applying a solution in which the metal is dissolved in an acid or the like by a spin method, a spray method, a dubbing method, or the like. As the solution, an activator (electrolyte) for electroless plating or an electroless plating solution can be used. In addition, the metal can be deposited by contact with an after-treatment liquid activated with an activating agent. The vapor phase methods include adsorption of metal-containing gas, vapor deposition method, ion plating method, notch method, CVD (chemical vapor deposition) method, MBE (molecular beam etch) method, ALD (atomic layer deposition) method. Can be used.
その後、 必要に応じて中和処理、 洗浄を行った後、 熱処理を行う （ステップ S 1 3 )。 これにより、 金属は拡散しシリコン酸ィヒ膜に取り込まれ、 トラップサイト となる。 この熱処理により酸ィヒされやすレ、金属は酸化される。  Thereafter, neutralization and cleaning are performed as necessary, followed by heat treatment (step S13). As a result, the metal diffuses and is taken into the silicon oxide film and becomes a trap site. By this heat treatment, the metal is oxidized easily.
続いて、 C V D法やスパッタ法を用いてシリコン酸化膜などの絶縁膜を堆積す る （ステップ S 1 4 )。 堆積する絶縁膜の膜厚は、 シリコン酸化膜の場合で 5〜 1 5 n mでめる。  Subsequently, an insulating film such as a silicon oxide film is deposited using the C V D method or the sputtering method (step S 14). The thickness of the insulating film to be deposited should be 5 to 15 nm in the case of a silicon oxide film.
図 9を参照すると、 本発明の第 9の実施例による製造方法では、 まず、 熱酸化 を行って膜厚 2〜1 5 n mの緻密なシリコン酸ィヒ膜を形成する （ステップ S 2 1 )。 次に、 シリカガラスをスピンコート法にて塗布した後に熱処理を行う等の方法 により熱酸化膜上に低密度の絶縁膜を形成する （ステップ S 2 2 )。  Referring to FIG. 9, in the manufacturing method according to the ninth embodiment of the present invention, first, thermal oxidation is performed to form a dense silicon oxide film having a film thickness of 2 to 15 nm (step S 2 1). . Next, a low-density insulating film is formed on the thermal oxide film by a method such as applying silica glass by a spin coating method followed by heat treatment (step S 22).
次に、 低密度絶縁膜上に第 8の実施例で述べた方法を用いて金属を付着させる (ステップ S 2 3 )。  Next, a metal is deposited on the low density insulating film by using the method described in the eighth embodiment (step S 2 3).
次に、 熱処理を行って付着させた金属不純物を低密度絶縁膜内に取り込む （ス テツプ S 2 4 )。  Next, metal impurities deposited by heat treatment are taken into the low-density insulating film (Step S 24).
続いて、 C V D法やスパッタ法を用いてシリコン酸化膜などの絶縁膜を堆積す る （ステップ S 2 5 )。  Subsequently, an insulating film such as a silicon oxide film is deposited by using C V D method or sputtering method (step S 25).
図 8及び図 9に示した本発明の第 8及び第 9の実施例による製造方法では、 ス テツプ S 1 3 (ステップ S 2 4 )で熱処理を行った後に絶縁膜を堆積していたが、 この順序は逆にしてもよい。 図示されたとおりの製造方法によると、 トラップサ イトは主として熱酸化膜中 （第 8の実施例の場合） あるいは低密度絶縁膜中 （第 9の実施例の場合）に形成されるが、絶縁膜堆積後に熱処理を行うようにすると、 トラップサイトは、 熱酸化膜あるいは低密度絶縁膜と堆積絶縁膜との界面を中心 としてその両側に分布するように形成されることになる。 In the manufacturing methods according to the eighth and ninth embodiments of the present invention shown in FIGS. 8 and 9, the insulating film is deposited after the heat treatment in step S 1 3 (step S 2 4). This order may be reversed. According to the manufacturing method as shown in the figure, the trap site is mainly in the thermal oxide film (in the case of the eighth embodiment) or in the low-density insulating film (first 9), trapping sites are distributed on both sides of the interface between the thermal oxide film or low-density insulating film and the deposited insulating film. Will be formed.
図 10を参照すると、 本発明の第 10の実施例による製造方法では、 まず、 熱 酸化を行って基板上に膜厚 2〜1 5 nmの緻密なシリコン酸化膜を形成する （ス テツプ S 31)。  Referring to FIG. 10, in the manufacturing method according to the tenth embodiment of the present invention, first, thermal oxidation is performed to form a dense silicon oxide film having a thickness of 2 to 15 nm on the substrate (Step S 31 ).
次に、 気相法にて絶縁膜を堆積する （ステップ S 32)。  Next, an insulating film is deposited by a vapor phase method (step S32).
絶縁膜を所定の膜厚にまで成長させた後、 絶縁膜の成長を続けながらチェンバ 内に金属化合物ガスを流しあるいは金属を蒸発させて絶縁膜中に金属を取り込み ながら膜成長を続ける （ステップ S 33)。  After the insulating film is grown to a predetermined thickness, the film growth is continued while flowing the metal compound gas into the chamber or evaporating the metal while taking the metal into the insulating film while continuing the growth of the insulating film (Step S). 33).
ステップ S 32の処理が所定の時間に達したら、 あるいは金属含有絶縁膜の膜 厚が所定の厚さに達したら金属の供給を停止して絶縁膜の成長を続ける （ステツ プ S 34)。  When the processing of step S32 reaches a predetermined time, or when the thickness of the metal-containing insulating film reaches a predetermined thickness, the supply of metal is stopped and the growth of the insulating film is continued (step S34).
その後、 熱処理を行って金属を絶縁膜内に取り込む （ステップ S 34)。  Thereafter, heat treatment is performed to take the metal into the insulating film (step S34).
図 1 1を参照すると、 本発明の第 1 1の実施例による製造方法は、 図 10に示 される第 9の実施例と相違する点は、 ステップ S 32の絶縁膜の堆積が省略され て、 熱酸化膜の形成工程の後直ちに不純物 （金属） 含有絶縁膜を形成している点 である。 この不純物含有絶縁膜の形成工程に続けて不純物を有しない絶縁膜の堆 積と熱処理を行う。  Referring to FIG. 11, the manufacturing method according to the first embodiment of the present invention is different from the ninth embodiment shown in FIG. 10 in that the deposition of the insulating film in step S 32 is omitted. The insulating film containing impurities (metal) is formed immediately after the step of forming the thermal oxide film. Subsequent to the step of forming the impurity-containing insulating film, the insulating film having no impurities is deposited and heat-treated.
図 1 2を参照すると、 本発明の第 1 2の実施例による製造方法では、 まず、 熱 酸化を行って基板上に膜厚 2〜 1 5 nmの緻密なシリコン酸化膜を形成する （ス テツプ S 41)。  Referring to FIG. 12, in the manufacturing method according to the first and second embodiments of the present invention, first, thermal oxidation is performed to form a dense silicon oxide film having a film thickness of 2 to 15 nm on the substrate. S 41).
次に、 熱酸化膜上にシリコンまたはシリコン化合物と金属とを堆積する （ステ ップ S 42)。  Next, silicon or a silicon compound and a metal are deposited on the thermal oxide film (step S42).
金属は単一種であっても複数種であっても良い。 また、 金属化合物であっても よい。 ステップ S 42の方法としては以下のものがある。  The metal may be a single species or a plurality of species. Moreover, a metal compound may be sufficient. The method of step S42 is as follows.
(a) 金属を含むシリコンターゲットを用い、 スパッタ法にして金属含有シリ コン膜を形成する。  (a) Using a silicon target containing metal, a metal-containing silicon film is formed by sputtering.
(b) CVD法で金属 （または金属化合物） 含有シリコン （または酸化シリコ ン） を成長させる。 (b) Silicon (or silicon oxide) containing metal (or metal compound) by CVD Grow).
(c) シラノール 〔S i (OH) 4〕 などのシリコン化合物と水酸化アルミニゥ ムなどの金属化合物とが溶解した溶液を塗布する。 (c) Apply a solution in which a silicon compound such as silanol [S i (OH) 4 ] and a metal compound such as aluminum hydroxide are dissolved.
次に、 熱処理を行って金属 （または金属化合物） 含有シリコン酸化膜を形成す る （ステップ S 43)。  Next, heat treatment is performed to form a metal (or metal compound) -containing silicon oxide film (step S 43).
続いて、 CVD法またはスパッタ法などにより絶縁膜を堆積する （ステップ S Subsequently, an insulating film is deposited by CVD or sputtering (Step S).
44)。 ステップ S 43とステップ S 44とは順序が逆であってもよい。 44). Step S43 and step S44 may be reversed in order.
図 1 3を参照する本発明の第 1 3の実施例による製造方法では、 まず、 熱酸化 を行って基板上に膜厚 10〜30 nmの緻密なシリコン酸化膜を形成する （ステ ップ S 51)。  In the manufacturing method according to the first to third embodiments of the present invention with reference to FIG. 13, first, thermal oxidation is performed to form a dense silicon oxide film having a thickness of 10 to 30 nm on the substrate (Step S). 51).
第 1 3の実施例においては、 ゲート絶縁膜の全体を熱酸化により形成する。 あ るいは、 ステップ S 5 1にて所定の膜厚にまで熱酸化を行い、 ステップ S 52に て CVD法などにより膜形成を行って所定の膜厚のグート絶縁膜を得る。  In the 13th embodiment, the entire gate insulating film is formed by thermal oxidation. Alternatively, thermal oxidation is performed to a predetermined film thickness in step S 51, and film formation is performed by a CVD method or the like in step S 52 to obtain a goot insulating film having a predetermined film thickness.
次に、基板表面に達しない深さにゲート絶縁膜中に金属のイオン注入を行う （ス テツプ S 53)。  Next, metal ions are implanted into the gate insulating film to a depth that does not reach the substrate surface (step S 53).
続いて、 熱処理を行ってゲート絶縁膜中に金属不純物を取り込む （ステップ S Subsequently, heat treatment is performed to incorporate metal impurities into the gate insulating film (Step S
54)。 54).
図 14Aを参照すると、 本発明の第 14の実施の形態による製造方法では、 ま ず、 熱酸化を行って基板上に膜厚 10〜 30 n mの緻密なシリコン酸化膜を形成 する （ステップ S 6 1)。  Referring to FIG. 14A, in the manufacturing method according to the fourteenth embodiment of the present invention, first, thermal oxidation is performed to form a dense silicon oxide film having a thickness of 10 to 30 nm on the substrate (step S 6 1).
次に、 熱拡散法などにより、 熱酸化膜中にトラップサイト形成用不純物を拡散 する （ステップ S 62)。  Next, trap site forming impurities are diffused into the thermal oxide film by a thermal diffusion method or the like (step S62).
次いで、 その上に絶縁膜を堆積する （ステップ S 63)。 その後、 必要に応じて 熱処理を行う （ステップ S 64)。  Next, an insulating film is deposited thereon (step S63). Thereafter, heat treatment is performed as necessary (step S 64).
上記ステップ S 62の不純物拡散の方法に固相法を用いた場合、 図 14Bの変 形例に示すように、 ステップ S 6 1の工程の終了後に、 トラップサイト形成用不 純物を含有する転写膜を熱酸化膜上に形成する （ステップ S 62 a)。  When the solid phase method is used as the impurity diffusion method in step S62, as shown in the modification example in FIG. 14B, after the step S61, the transfer containing impurities for trap site formation is performed. A film is formed on the thermal oxide film (step S 62 a).
次に、 熱処理を行って転写膜中の不純物を熱酸化膜中に拡散させる （ステップ S 62 b)0 次いで、 転写膜を除去し （ステップ S 6 2 c )、 ステップ S 6 3以降の工程を実 施する。 Next, heat treatment is performed to diffuse impurities in the transfer film into the thermal oxide film (step S 62 b) 0 Next, the transfer film is removed (step S 6 2 c), and the processes after step S 63 are performed.
上記方法において、 熱酸化膜に拡散されたトラップサイト形成用不純物の濃度 が高すぎる場合には、 不純物濃度の高い層をゥエツトエッチング等により除去し て、 理想的な不純物トラップレベルにしてもよい。  In the above method, if the concentration of the trap site forming impurity diffused in the thermal oxide film is too high, the layer with a high impurity concentration may be removed by wet etching or the like to obtain an ideal impurity trap level. .
次に、 図 2〜図 4に示されるような、 第 1のゲート電極の下にトラップサイト を有するゲート絶縁膜とトラップサイトを有しないゲート絶縁膜とが備えられて いる構造 （以下、 併合ゲート絶縁膜） を形成する方法について説明する。  Next, as shown in FIGS. 2 to 4, a structure in which a gate insulating film having a trap site and a gate insulating film not having a trap site are provided under the first gate electrode (hereinafter referred to as a merged gate). A method for forming the insulating film will be described.
図 1 5を参照すると、 本発明の第 1 5の実施例による併合ゲート絶縁膜の形成 方法では、 図 8〜図 1 3に示されるいずれかの方法を用いて図 1 5 Aに示すよう に、 内部にトラップサイト 5を含むシリコン酸化膜 3を形成する。 なお、 ゲート 絶縁膜はシリコン酸化膜に限定されないが、 ここでは、 ゲート絶縁膜はシリコン 酸化膜により形成されているものとする。  Referring to FIG. 15, in the method of forming a merged gate insulating film according to the 15th embodiment of the present invention, as shown in FIG. 15A using any one of the methods shown in FIGS. 8 to 13. A silicon oxide film 3 including trap sites 5 is formed inside. Note that although the gate insulating film is not limited to a silicon oxide film, it is assumed here that the gate insulating film is formed of a silicon oxide film.
次に、 図 1 5 Bに示すように、 フォトリソグラフィ法と湿式エッチング法など を用いてシリコン酸化膜 3の一部をエッチング除去する。  Next, as shown in FIG. 15B, a part of the silicon oxide film 3 is etched away by using a photolithography method and a wet etching method.
図 1 5 Cに示すように、 再度熱酸化を行って熱酸化膜からなるゲート絶縁膜 7 を形成する。  As shown in FIG. 15C, thermal oxidation is performed again to form a gate insulating film 7 made of a thermal oxide film.
図 1 6 A乃至 Eを参照すると、 本発明の第 1 6の実施例による併合ゲート絶縁 膜の形成方法では、 図 1 6 Aに示すように、 熱酸化を行って p型シリコン基板 1 上にシリコン酸化膜 3を形成する。 次に、 図 1 6 Bに示すように、 フォトリソグ ラフィ法を用いて、 意図的に導入されたトラップサイトを有しないゲート絶縁膜 の形成領域上を覆うようにフォトレジストマスク 9を形成する〕。 次に、 図 8のス テツプ S 1 2、 図 1 0のステップ S 3 3、 図 1 2のステップ S 4 2などの方法を 用いて、 図 1 6 Cに示すように、 シリコン酸化膜 3およびフォトレジストマスク 9上に金属原子 1 0または金属を含む材料を堆積させる。 図 1 6 Dに示すように、 フォトレジストマスク 9を除去した後、 熱処理を行って金属をシリコン酸化膜中 へ拡散させてシリコン酸ィ匕膜' 3中にトラップサイトを形成する。 その後、 図 1 6 Eに示すように、 シリコン酸化膜 3上に C V D法などにより絶縁膜 4を形成する。 図 1 6 Dに示す工程での熱処理は絶縁膜 4を堆積した後であってもよい。 また、 ゲート電極である多結晶シリコンをマスクに不純物の添加される領域と 添加されない領域を形成してもよいことは言うまでもない。 Referring to FIGS. 16A to E, in the method of forming a merged gate insulating film according to the sixteenth embodiment of the present invention, as shown in FIG. 16A, thermal oxidation is performed on the p-type silicon substrate 1. A silicon oxide film 3 is formed. Next, as shown in FIG. 16B, a photoresist mask 9 is formed using a photolithographic method so as to cover the formation region of the gate insulating film having no intentionally introduced trap site. Next, using a method such as step S 1 2 in FIG. 8, step S 3 3 in FIG. 10, step S 4 2 in FIG. 12, etc., as shown in FIG. A material containing metal atoms 10 or a metal is deposited on the photoresist mask 9. As shown in FIG. 16D, after removing the photoresist mask 9, a heat treatment is performed to diffuse the metal into the silicon oxide film, thereby forming trap sites in the silicon oxide film '3. Thereafter, as shown in FIG. 16 E, an insulating film 4 is formed on the silicon oxide film 3 by a CVD method or the like. The heat treatment in the step shown in FIG. 16D may be after the insulating film 4 is deposited. Needless to say, a region to which impurities are added and a region to which impurities are not added may be formed using polycrystalline silicon as a gate electrode as a mask.
次に、 本発明の具体例について説明する。  Next, specific examples of the present invention will be described.
(例 1 )  (Example 1 )
例 1では、 本発明の有効性を確認するための予備的な実験である。 乾式法によ り 850°Cにてシリコン基板上に膜厚 1 Οηπιのシリコン酸化膜を形成した。 表 1の金属溶液を用意して、 各溶液を酸化膜上に付着させた。 表 1  Example 1 is a preliminary experiment to confirm the effectiveness of the present invention. A silicon oxide film having a thickness of 1 Οηπι was formed on a silicon substrate at 850 ° C by a dry method. The metal solutions shown in Table 1 were prepared, and each solution was deposited on the oxide film. table 1
Figure imgf000016_0001
クリーン'ベンチ内で乾燥させた後、 ァニール炉内に搬入し、 N2を 3 1、 02を 50m lずつ供給しつつ 800°Cで 1分間の熱処理を行い、 金属を酸化膜中に拡 散させた。 シリコン酸化膜上に A uを膜厚 100 nm蒸着し、 形成された各試料 について、 シリコン酸化膜に電圧を印加し、 リーク電流を流して電子注入を行い 電荷密度測定を行った。 なお、 電荷密度は、 リーク電流供給前後の CV特性から 換算したものである。 各試料について得られた結果を図 1 7に示す。 実施例 1に より、 簡単な方法を用いてゲート絶縁膜中にトラップサイ トを形成することがで きることが確認された。
Figure imgf000016_0001
After drying in a clean bench, it was carried into an annealing furnace and heat-treated at 800 ° C for 1 minute while supplying N 2 3 1 and 02 50 ml each to diffuse the metal into the oxide film I let you. Au was deposited on the silicon oxide film to a thickness of 100 nm. For each sample formed, a voltage was applied to the silicon oxide film, a leakage current was applied, and electrons were injected to measure the charge density. The charge density is calculated from the CV characteristics before and after supplying the leakage current. Figure 17 shows the results obtained for each sample. According to Example 1, it was confirmed that a trap site can be formed in the gate insulating film using a simple method.
(例 2 )  (Example 2)
熱酸化によりシリコン基板上に 7 nmの膜厚のシリコン酸化膜を形成し、 その 上にスパッタ法により、 T i、 A l、 A uをそれぞれ 0. 7 nmの膜厚に成膜し、 さらにその上に CVD法によりシリコン酸化膜を 10 nmの膜厚にて成膜した。 そして、 熱処理を行って金属を拡散させて 3種類の試料を作成し、 各試料につい て EOTを測定した。 その結果を表 2に示す。 A silicon oxide film with a thickness of 7 nm is formed on the silicon substrate by thermal oxidation, and Ti, A l, and Au are each formed to a thickness of 0.7 nm by sputtering, and further, A silicon oxide film with a thickness of 10 nm was formed thereon by CVD. Then, heat treatment was performed to diffuse the metal to prepare three types of samples, and EOT was measured for each sample. The results are shown in Table 2.
表 2  Table 2
Figure imgf000017_0001
Figure imgf000017_0001
T iと A 1については熱処理により酸化物が形成されたものと考えられるが、 gOTの増加はみられない。 また、 金属がそのまま拡散したものと考えられる A uについても EOTは増加していない。 For Ti and A1, it is considered that oxides were formed by heat treatment, but no increase in gOT was observed. In addition, the EOT has not increased for Au, which is thought to have diffused as it is.
T iを拡散させた試料についての CV特性の測定結果を図 18に示す。 また、 T iを拡散させた試料についての、 ゲートに 8Vを印加し、 ソース一ドレイン間 にそれぞれ 5 V、 6V、 7 Vを印加した場合の書き込み特性を図 1 9に示す。 ま た、 T iを拡散させた試料についての 150°Cでの保持特性 （しきい値の経時変 化）を ONOメモリの保持特性と共に図 20に示す。 ONOメモリでは 10年（3. 2X 108秒） の保持特性は得られていないが、 実施例 2のものでは十分にクリ了 している。 Figure 18 shows the measurement results of the CV characteristics of the sample with Ti diffused. Figure 19 shows the writing characteristics of the sample with Ti diffused when 8 V is applied to the gate and 5 V, 6 V, and 7 V are applied between the source and drain, respectively. In addition, Fig. 20 shows the retention characteristics (threshold change over time) of the sample with Ti diffused, along with the retention characteristics of the ONO memory. The retention characteristics of 10 years (3.2 x 10 8 seconds) have not been obtained with ONO memory, but those with Example 2 have been fully cleared.
酸化されやすい金属の典型例である A 1 と酸化されにくい金属の典型例である Auを拡散させた試料についての、 ゲートに 8 Vを印加し、 ソース一ドレイン間 にそれぞれ 5V、 6V、 7 Vを印加した場合の書き込み特性をそれぞれ図 2 1と 図 22に示す。 図 21と図 22から分かるように、 リバースリード （ドレイン側 に正電圧印加） とフォワードリード （ソース側に正電圧印加） とでしきい値が異 なっており、 ホットエレクトロンを用いた書き込みでは局所的に電子注入が行わ れたことが分かる。  Apply 8 V to the gate and 5 V, 6 V, and 7 V between the source and drain of a sample in which A 1, which is a typical example of a metal that is easily oxidized, and Au, which is a typical example of a metal that is not easily oxidized, are diffused. Figures 21 and 22 show the write characteristics when, respectively, is applied. As can be seen from FIG. 21 and FIG. 22, the threshold value differs between reverse read (positive voltage applied to the drain side) and forward read (positive voltage applied to the source side). It can be seen that electron injection was performed.
(例 3 )  (Example 3)
熱酸化によりシリコン基板上に 8 nmの膜厚のシリコン酸化膜を形成し、 その 上に 5%A 1含有 S iターゲットを用いてスパッタ法により、 A 1含有 S i膜を 1 nmの膜厚に成膜し、 さらにその上に CVD法によりシリコン酸化膜を 8 nm の膜厚に成膜した後、 酸化性雰囲気中で 8 2 0 ° (：、 1分間の熱処理を行った。 本 方法を用いても、 不揮発性メモリとして適する電子トラップを実現することがで きた。 A silicon oxide film with a thickness of 8 nm is formed on a silicon substrate by thermal oxidation, and then an A 1 containing Si film is formed with a thickness of 1 nm by sputtering using a 5% A 1 containing Si target. And then a silicon oxide film of 8 nm is deposited on it by CVD. Then, heat treatment was performed in an oxidizing atmosphere at 820 ° (: for 1 minute. Even with this method, an electron trap suitable as a nonvolatile memory could be realized. .
産業上の利用可能性：  Industrial applicability:
以上の説明の通り、 本発明の半導体装置及びその製造方法は、 フラッシュメモ リ等の不揮発性半導体記憶装置に適用される。  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are applied to a nonvolatile semiconductor memory device such as a flash memory.

Claims

請 求 の 範 囲 The scope of the claims
1. 基板上にゲート絶縁膜を介して形成された第 1のゲート電極と、 基板表 面領域に形成されたソース · ドレイン領域とを有する不揮発性のメモリセルを備 える半導体装置において、 前記ゲート絶縁膜には、 トラップサイトとなる金属を 含む不純物が添加されたトラップサイト含有層が含まれることを特徴とする半導 体装置。 1. In a semiconductor device comprising a nonvolatile memory cell having a first gate electrode formed on a substrate via a gate insulating film and a source / drain region formed in a substrate surface region, the gate A semiconductor device, wherein the insulating film includes a trap site-containing layer to which an impurity including a metal to be a trap site is added.
2. 請求項 1 に記載の半導体装置において、 前記ゲート絶縁膜は、 一部又は 全部にシリコン酸化膜を有することを特徴とする半導体装置。  2. The semiconductor device according to claim 1, wherein the gate insulating film has a silicon oxide film in part or in whole.
3. 請求項 2に記載の半導体装置において、 前記トラップサイト含有層は前 記シリコン酸化膜内部、 外部、 または境界領域に形成されていることを特徴とす る半導体装置。  3. The semiconductor device according to claim 2, wherein the trap site-containing layer is formed inside, outside, or in a boundary region of the silicon oxide film.
4. 請求項 1に記載の半導体装置において、 前記トラップサイト含有層の膜 厚は、 3 nm以下であることを特徴とする半導体装置。  4. The semiconductor device according to claim 1, wherein a thickness of the trap site-containing layer is 3 nm or less.
5. 請求項 1に記載の半導体装置において、 前記トラップサイト含有層の膜 厚は、 ゲート絶縁膜の膜厚の 3/20以下であることを特徴とする半導体装置。  5. The semiconductor device according to claim 1, wherein a film thickness of the trap site-containing layer is 3/20 or less of a film thickness of the gate insulating film.
6. 請求項 1に記載の半導体装置において、 添加された不純物が金属単体及 ぴ金属化合物の内の少なくとも一種であることを特徴とする半導体装置。  6. The semiconductor device according to claim 1, wherein the added impurity is at least one of a simple metal and a metal compound.
7. 請求項 6に記載の半導体装置において、 前記金属化合物が金属酸化物及 ぴ金属シリケ一トの内のいずれか一方であることを特徴とする半導体装置。  7. The semiconductor device according to claim 6, wherein the metal compound is one of a metal oxide and a metal silicate.
8. 請求項 1に記載の半導体装置において、 前記金属が、 Mg及び元素の周 期表において 3 A族から 6 B族までに含まれる金属であることを特徴とする半導 体装置。  8. The semiconductor device according to claim 1, wherein the metal is a metal included in groups 3A to 6B in the periodic table of Mg and elements.
9. 請求項 8に記載の半導体装置において、前記金属が、 A 1、 Au、 Co, C r、 Cu、 F e、 I r、 La、 Mg、 Mn、 N i、 Ru、 Sn、 Ta、 T i、 T 1、 Zn、及び Wの中の一種または複数種であることを特徴とする半導体装置。  9. The semiconductor device according to claim 8, wherein the metal is A1, Au, Co, Cr, Cu, Fe, Ir, La, Mg, Mn, Ni, Ru, Sn, Ta, T A semiconductor device characterized by being one or more of i, T1, Zn, and W.
10. 請求項 1に記載の半導体装置において、 前記第 1のゲート電極の全体 が、 前記トラップサイ ト含有層を有するゲート絶縁膜上に形成されていることを 特徴とする半導体装置。 10. The semiconductor device according to claim 1, wherein the entire first gate electrode is formed on a gate insulating film having the trap site-containing layer. A featured semiconductor device.
1 1 . 請求項 1に記載の半導体装置において、 前記ゲート絶縁膜は複数層を 備え、 前記ゲート絶縁膜の一つの層はトラップサイト含有層を有し、 前記ゲート 絶縁膜のもう一つの層は、 トラップサイト含有層を有さず、 前記第 1のゲート電 極の一部が前記トラップサイ ト含有層を有するゲート絶縁膜層の上に、 他の一部 がトラップサイト含有層を有しないゲート絶縁膜層上に形成されていることを特 徴とする半導体装置。  11. The semiconductor device according to claim 1, wherein the gate insulating film includes a plurality of layers, one layer of the gate insulating film has a trap site-containing layer, and the other layer of the gate insulating film is A gate that does not have a trap site-containing layer, a part of the first gate electrode is on the gate insulating film layer that has the trap site-containing layer, and another part does not have a trap site-containing layer. A semiconductor device characterized by being formed on an insulating film layer.
1 2 . 請求項 1に記載の半導体装置において、 前記ゲート絶縁膜は複数層を 備え、 前記ゲート絶縁膜の一つの層はトラップサイト含有層を有し、 前記ゲート 絶縁膜のもうひとつの層はトラップサイト含有層を有さず、 前記トラップサイト 含有層を有するゲート絶縁膜層がソース · ドレイン領域の一方寄りに形成され、 前記トラップサイト含有層を有しないゲート絶縁膜層がソース · ドレイン領域の 他方寄りに形成されていることを特徴とする半導体装置。  1 2. The semiconductor device according to claim 1, wherein the gate insulating film includes a plurality of layers, one layer of the gate insulating film includes a trap site-containing layer, and the other layer of the gate insulating film includes A gate insulating film layer having no trap site containing layer is formed on one side of the source / drain region, and a gate insulating film layer having no trap site containing layer is formed on the source / drain region. A semiconductor device characterized by being formed closer to the other side.
1 3 . 請求項 1に記載の半導体装置において、 前記ゲート絶縁膜は複数層を 備え、 前記ゲート絶縁膜の一つの層はトラップサイト含有層を有し、 前記ゲート 絶縁膜のもう一つの層は、 トラップサイト含有層を有さず、 前記トラップサイト 含有層を有するゲート絶縁膜層及び前記トラップサイト含有層を有しないゲート 絶縁膜層の内の一方がソース · ドレイン領域間の中央部上に形成され、 他方がそ の両側に形成されていることを特徴とする半導体装置。  1 3. The semiconductor device according to claim 1, wherein the gate insulating film includes a plurality of layers, one layer of the gate insulating film includes a trap site-containing layer, and the other layer of the gate insulating film includes One of the gate insulating film layer having no trap site containing layer and the gate insulating film layer not having the trap site containing layer is formed on the central portion between the source / drain regions without the trap site containing layer. And the other is formed on both sides of the semiconductor device.
1 4 . 請求項 1に記載の半導体装置において、 前記ゲート絶縁膜は複数層を 備え、 前記ゲート絶縁膜の一つの層はトラップサイト含有層を有し、 前記ゲート 絶縁膜のもう一つの層は、 トラップサイト含有層を有さず、 前記メモリセルは、 ソース . ドレイン領域間上に第 1のゲート電極と第 2のゲート電極とを有してお り、 第 2のゲート電極はトラップサイト含有層を有しないゲート絶縁膜層上に形 成されていることを特徴とする半導体装置。  14. The semiconductor device according to claim 1, wherein the gate insulating film includes a plurality of layers, one layer of the gate insulating film has a trap site-containing layer, and the other layer of the gate insulating film is The memory cell does not have a trap site containing layer, and the memory cell has a first gate electrode and a second gate electrode between the source and drain regions, and the second gate electrode contains the trap site. A semiconductor device formed on a gate insulating film layer having no layer.
1 5 . 請求項 1 4に記載の半導体装置において、 前記第 2のゲート電極は、 その一部が前記第 1のゲート電極上に載り上げるように形成されていることを特 徴とする半導体装置。  15. The semiconductor device according to claim 14, wherein the second gate electrode is formed so that a part of the second gate electrode is placed on the first gate electrode. .
1 6 . 請求項 1 4に記載の半導体装置において、 前記第 2のゲート電極が、 ソース ' ドレイン領域間の中央部上に形成され、 前記第 2のゲート電極を挟んで その両側に前記第 1のゲート電極が形成されていることを特徴とする半.導体装置。 16. The semiconductor device according to claim 14, wherein the second gate electrode is A semiconductor device, characterized in that it is formed on a central portion between a source and a drain region, and the first gate electrode is formed on both sides of the second gate electrode.
1 7 . 請求項 1に記載の半導体装置において、 前記基板の一領域上に前記メ モリセルが形成されており、 更に、 前記基板の他の領域上にロジック回路が形成 されていることを特徴とする半導体装置。  17. The semiconductor device according to claim 1, wherein the memory cell is formed on one area of the substrate, and a logic circuit is formed on another area of the substrate. Semiconductor device.
1 8 . 不揮発性のメモリセルを有する半導体装置の製造方法であって、 メモ リセルのゲート絶縁膜の製造工程が、 絶縁膜を堆積する工程と、 トラップサイト となる不純物を堆積する工程と、 を有していることを特徴とする半導体装置の製 造方法。  1 8. A method of manufacturing a semiconductor device having a non-volatile memory cell, wherein a manufacturing process of a gate insulating film of a memory cell includes a process of depositing an insulating film and a process of depositing impurities serving as trap sites. A method for manufacturing a semiconductor device, comprising:
1 9 . 請求項 1 8に記載の半導体装置の製造方法において、 更に、 シリコン 基板表面を熱酸化する工程を備えていることを特徴とする半導体装置の製造方法。  19. The method for manufacturing a semiconductor device according to claim 18, further comprising a step of thermally oxidizing the surface of the silicon substrate.
2 0 . 請求項 1 9に記載の半導体装置の製造方法において、 前記シリコン基 板表面を熱酸化する工程の後に、 更に、 不純物を取り込みやすい密度の低いシリ コン酸化膜を形成する工程を備えていることを特徴とする半導体装置の製造方法。  20. The method of manufacturing a semiconductor device according to claim 19, further comprising a step of forming a low-density silicon oxide film that easily takes in impurities after the step of thermally oxidizing the surface of the silicon substrate. A method for manufacturing a semiconductor device, comprising:
2 1 . 請求項 1 8に記載の半導体装置の製造方法において、 前記トラップサ ィトとなる不純物を堆積する工程の後、 絶縁膜を堆積する工程に先だって若しく は絶縁膜を堆積する工程の後に、 熱処理が行われることを特徴とする半導体装置 の製造方法。  21. The method of manufacturing a semiconductor device according to claim 18, wherein after the step of depositing the impurity serving as the trap site, the step of depositing the insulating film prior to the step of depositing the insulating film or after the step of depositing the insulating film. A method for manufacturing a semiconductor device, characterized in that a heat treatment is performed.
2 2 . 請求項 2 1に記載の半導体装置の製造方法において、 前記熱処理が酸 化性雰囲気中で行われることを特徴とする半導体装置の製造方法。  2 2. The method of manufacturing a semiconductor device according to claim 21, wherein the heat treatment is performed in an oxidizing atmosphere.
2 3 . 請求項 1 8に記載の半導体装置の製造方法において、 前記トラップサ ィトとなる不純物の堆積が、 その不純物を含む溶液への接触及びその不純物を含 むプラズマに晒すことのうちのいずれか一つのプロセスによって行われることを 特徴とする半導体装置の製造方法。  23. The method of manufacturing a semiconductor device according to claim 18, wherein the deposition of the impurity serving as the trap site includes any one of contact with a solution containing the impurity and exposure to a plasma containing the impurity. A method of manufacturing a semiconductor device, characterized by being performed by one process.
2 4 . 請求項 1 8に記載の半導体装置の製造方法において、 前記トラップサ ィトとなる不純物の堆積が、 前記トラップサイトとなる不純物を含むシリカ溶液 の塗布または前記トラップサイトとなる不純物を含むシリカ溶液への浸漬によつ て、 前記溶液への接触がなされることを特徴とする半導体装置の製造方法。  24. The method of manufacturing a semiconductor device according to claim 18, wherein the deposition of the impurity serving as the trap site is performed by applying a silica solution containing the impurity serving as the trap site or the silica including the impurity serving as the trap site. A method of manufacturing a semiconductor device, wherein the contact with the solution is made by immersion in the solution.
2 5 . 請求項 1 8に記載の半導体装置の製造方法において、 前記トラップサ ィトとなる不純物の堆積が、 蒸着法、 スパッタ法、 MBE (mo l e c u l a r b e am e p i t a x y) 法、 C VD (c h em i c a l v a p o r d e p o s i t i o n) 法、 ガスの表面吸着及び A LD (a t om i c l a y e r d e p o s i t i o n) 法の内のレ、ずれか一つのプロセスによって行われる ことを特徴とする半導体装置の製造方法。 25. The method of manufacturing a semiconductor device according to claim 18, wherein the trap support is provided. The deposition of impurities to be the light is determined by vapor deposition, sputtering, MBE (molecular beam am epitaxy), C VD (chemical vapor deposition), gas surface adsorption, and A LD (at om ic layer deposition). A method of manufacturing a semiconductor device, wherein the method is performed by one process.
26. 請求項 25に記載の半導体装置の製造方法において、 前記トラップサ ィトとなる不純物の堆積が、 トラップサイトとなる不純物を含むシリコンターゲ ットを用いたスパッタ法によって行われることを特徴とする半導体装置の製造方 法。  26. The method for manufacturing a semiconductor device according to claim 25, wherein the deposition of the impurity serving as the trap site is performed by a sputtering method using a silicon target including the impurity serving as a trap site. A method for manufacturing semiconductor devices.
27. 請求項 1 8に記載の半導体装置の製造方法において、 前記トラップサ ィトとなる不純物の堆積と共にシリコンまたはその化合物の堆積が同時に行われ ることを特徴とする半導体装置の製造方法。  27. The method for manufacturing a semiconductor device according to claim 18, wherein silicon or a compound thereof is simultaneously deposited together with the deposition of the impurity serving as the trap site.
28. 請求項 1 9に記載の半導体装置の製造方法において、 前記熱酸化工程 の後トラップサイトとなる不純物の堆積工程に先立ってマスクが形成され、 該マ スクを前記不純物の堆積工程の後に除去することを特徴とする半導体装置の製造 方法。  28. The method of manufacturing a semiconductor device according to claim 19, wherein a mask is formed prior to an impurity deposition step that becomes a trap site after the thermal oxidation step, and the mask is removed after the impurity deposition step. A method for manufacturing a semiconductor device.
29. 請求項 1 8に記載された半導体装置の製造方法において、 前記ゲート 絶縁膜の製造工程に従ってゲート絶縁膜を形成した後、 該ゲート絶縁膜の一部を 除去し、 その除去された領域にトラップサイトとなる不純物を含まないゲート絶 縁膜を形成する工程を更に備えていることを特徴とする半導体装置の製造方法。  29. The method of manufacturing a semiconductor device according to claim 18, wherein after forming the gate insulating film according to the manufacturing process of the gate insulating film, a part of the gate insulating film is removed, and the removed region is formed in the removed region. A method for manufacturing a semiconductor device, further comprising a step of forming a gate insulating film that does not contain impurities that serve as trap sites.
30. 不揮発性のメモリセルを有する半導体装置の製造方法であって、'メモ リセルのゲート絶縁膜の製造工程が、 シリコン基板表面を熱酸化する工程と、 形 成された熱酸化膜中にイオン注入法により トラップサイトとなる不純物を導入す る工程と、 を有することを特徴とする半導体装置の製造方法。  30. A method of manufacturing a semiconductor device having a non-volatile memory cell, wherein a manufacturing process of a gate insulating film of a memory cell includes a process of thermally oxidizing a surface of a silicon substrate and an ion in a formed thermal oxide film. And a step of introducing an impurity which becomes a trap site by an implantation method.
31. 請求項 30に記載された半導体装置の製造方法において、 前記ゲート 絶縁膜の製造工程に従ってゲート絶縁膜を形成した後、 前記ゲート絶縁膜の一部 を除去し、 その除去された領域にトラップサイ トとなる不純物を含まないゲート 絶縁膜を形成する工程をさらに備えていることを特徴とする半導体装置の製造方 法。 31. The method for manufacturing a semiconductor device according to claim 30, wherein after forming the gate insulating film according to the manufacturing process of the gate insulating film, a part of the gate insulating film is removed and trapped in the removed region A method for manufacturing a semiconductor device, further comprising a step of forming a gate insulating film that does not include impurities that serve as sites.
3 2 . 不揮発性のメモリセルを有する半導体装置の製造方法であって、 メモ リセルのゲート絶縁膜の製造工程が、 シリコン基板表面を熱酸化する工程と、 形 成された熱酸化膜上にトラップサイトとなる不純物を含む転写膜を堆積する工程 と、 熱処理を行ないトラップサイトとなる不純物を熱酸化膜に拡散する工程と、 転写膜を選択的に除去する工程と、 熱酸化膜上に絶縁膜を形成する工程と、 を有 することを特徴とする半導体装置の製造方法。 3 2. A method of manufacturing a semiconductor device having a non-volatile memory cell, wherein the manufacturing process of the gate insulating film of the memory cell includes a process of thermally oxidizing the surface of the silicon substrate and a trap on the formed thermal oxide film. A step of depositing a transfer film containing impurities as sites, a step of performing heat treatment to diffuse impurities as trap sites into the thermal oxide film, a step of selectively removing the transfer film, and an insulating film on the thermal oxide film And a method of manufacturing a semiconductor device, comprising:
3 3 . 請求項 3 2に記載の半導体装置の製造方法において、 前記ゲート絶縁 膜の製造工程に従ってゲート絶縁膜を形成した後、 前記ゲート絶縁膜の一部を除 去し、 その除去された領域にトラップサイトとなる不純物を含まないゲート絶縁 膜を形成する工程を更に備えていることを特徴とする半導体装置の製造方法。  3. The method of manufacturing a semiconductor device according to claim 3, wherein after the gate insulating film is formed according to the manufacturing process of the gate insulating film, a part of the gate insulating film is removed, and the removed region is formed. A method for manufacturing a semiconductor device, further comprising: forming a gate insulating film that does not contain impurities that serve as trap sites.
3 4 . 不揮発性のメモリセルを有する半導体装置の製造方法であって、 メモ リセルのゲート絶縁膜の製造工程が、 シリコン基板表面を熱酸化する工程と、 気 相法にて絶縁膜を形成する工程と、 を有しており、 前記気相法にて絶縁膜を形成 する工程においては途中ないし初期の一定期間トラップサイトとなる不純物また はその化合物ガスを供給しつつ膜形成を行うことを特徴とする半導体装置の製造 方法。  34. A method of manufacturing a semiconductor device having a non-volatile memory cell, wherein the manufacturing process of the gate insulating film of the memory cell includes a process of thermally oxidizing the surface of the silicon substrate and an insulating film formed by a gas phase method. A step of forming an insulating film by the vapor phase method, and forming the film while supplying impurities or compound gas serving as trap sites for a certain period of time or in the initial stage. A method for manufacturing a semiconductor device.
3 5 . 請求項 3 4に記載の半導体装置の製造方法において、 前記ゲート絶縁 膜の製造工程に従ってゲート絶縁膜を形成した後、 前記ゲート絶縁膜の一部を除 去し、 その除去された領域にトラップサイトとなる不純物を含まないゲート絶縁 膜を形成することを特徴とする半導体装置の製造方法。  35. The method of manufacturing a semiconductor device according to claim 34, wherein after the gate insulating film is formed according to the manufacturing process of the gate insulating film, a part of the gate insulating film is removed, and the removed region is formed. Forming a gate insulating film that does not contain impurities that serve as trap sites.
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JP2013131772A (en) * 2006-12-15 2013-07-04 Nec Corp Nonvolatile storage device
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