WO2006075427A1 - Pile solaire à jonction de renfort et procédé de fabrication idoine - Google Patents

Pile solaire à jonction de renfort et procédé de fabrication idoine Download PDF

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Publication number
WO2006075427A1
WO2006075427A1 PCT/JP2005/019384 JP2005019384W WO2006075427A1 WO 2006075427 A1 WO2006075427 A1 WO 2006075427A1 JP 2005019384 W JP2005019384 W JP 2005019384W WO 2006075427 A1 WO2006075427 A1 WO 2006075427A1
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WO
WIPO (PCT)
Prior art keywords
diffusion layer
type diffusion
semiconductor substrate
type
back surface
Prior art date
Application number
PCT/JP2005/019384
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English (en)
Japanese (ja)
Inventor
Tsutomu Onishi
Takeshi Akatsuka
Shunichi Igarashi
Original Assignee
Naoetsu Electronics Co., Ltd.
Shin-Etsu Chemical Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Naoetsu Electronics Co., Ltd., Shin-Etsu Chemical Co., Ltd. filed Critical Naoetsu Electronics Co., Ltd.
Publication of WO2006075427A1 publication Critical patent/WO2006075427A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/03529—Shape of the potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Definitions

  • the present invention relates to a structure of a back junction type (back contact type) solar cell in which positive and negative electrodes are arranged on the back surface opposite to a light receiving surface, and a manufacturing method thereof.
  • a back junction solar cell in which linear p + type diffusion layers and n + type diffusion layers are alternately formed on the back surface of a semiconductor substrate, and positive and negative back electrodes are separately connected to both diffusion layers, and its manufacture Regarding the method.
  • an oxide silicon film is formed as a mask for impurity diffusion on the back side of a silicon substrate, and a predetermined portion thereof is removed by etching.
  • a p-type diffusion layer is formed, on which an n-type diffusion layer is formed.
  • a back electrode in contact with the diffusion layer in the form of dots and an electrode in contact with the P-type diffusion layer in the form of dots are formed, and these diffusion layers and the electrodes are joined together at the opposing portions on the back side of the silicon substrate.
  • a line-shaped n + -type diffusion layer and a p + -type diffusion layer are alternately formed at the same interval (pitch) on the back surface of the semiconductor substrate (see, for example, Patent Document 2).
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2002-164556 (Page 2-3, Fig. 1, 4)
  • Patent Document 2 Japanese Patent Laid-Open No. 2004-71828 (Page 2, Fig. 1 (a))
  • linear p + type diffusion layers and n + type diffusion layers are arranged close to each other for the purpose of improving photoelectric conversion efficiency. It is desirable that U be thermally diffused with p-type and n-type impurities placed close to each other on the back side of the semiconductor substrate, so that the diffusion of impurities into the semiconductor substrate is isotropic. If there is an impurity in contact with the substrate, the substrate part is also auto-doped (auto-doped In this case, the outer edges of the p + type diffusion layer and the n + type diffusion layer are in contact with the outside of the substrate, and the current cannot be extracted from the positive and negative electrodes. There was a title.
  • the p + type diffusion layer and the n + type diffusion layer must be separated to a distance that does not come into contact with each other even if they are diffused and grown.
  • the distance that electrons and holes move to the P + type diffusion layer and the n + type diffusion layer becomes long, and there is a problem that the photoelectric conversion efficiency decreases.
  • the inventions described in claims 1 and 2 are aimed at arranging the p + type diffusion layer and the n + type diffusion layer in contact with each other without contact.
  • the invention described in claim 3 is intended to interconnect the back electrode regardless of the position where the concave groove is formed.
  • the invention according to claim 1 of the present invention is such that a p + -type diffusion layer and an n + -type diffusion layer are formed on the back surface of a semiconductor substrate at the same time.
  • the back surface force of the semiconductor substrate is also formed by forming a groove toward the boundary where the outer ends of the P + type diffusion layer and the n + type diffusion layer are in contact with each other, and the outer ends of the p + type diffusion layer and the n + type diffusion layer are It is characterized by having been separated.
  • the invention described in claim 2 includes the step of forming a p + type diffusion layer and an n + type diffusion layer close to each other on the back surface of the semiconductor substrate and simultaneously forming the p + type diffusion layer and the n + type diffusion layer from the back surface of the semiconductor substrate.
  • the process power of separately connecting the positive and negative back electrodes to the exposed surface of the substrate is also characterized.
  • the invention according to claim 3 is the structure according to the invention according to claim 2, wherein the concave groove is formed over the entire length of the back surface of the semiconductor substrate, and the back electrodes are connected to each other by intersecting the concave groove. It is characterized by having added.
  • the inventions according to claims 1 and 2 include a p + type diffusion layer and an n + on the back surface of the semiconductor substrate.
  • the mold diffusion layers are formed close to each other at the same time, and concave grooves are formed from the back surface of the semiconductor substrate toward the boundary portion where the outer ends of the P + diffusion layer and the n + diffusion layer are in contact with each other.
  • the p + -type diffusion layer and the n + -type diffusion layer are arranged close to each other across the concave groove.
  • the P + type diffusion layer and the n + type diffusion layer without striking them.
  • the p + type diffusion layer and the n + type diffusion layer are separated from each other by a distance where they do not contact each other even if they are diffused and grown.
  • the photoelectric conversion efficiency can be improved.
  • the p + type diffusion layer and the n + type diffusion layer are formed at the same time, it can be easily manufactured in a short time and at a low cost as compared with the conventional one in which these both diffusion layers are formed separately.
  • the invention of claim 3 forms a groove over the entire length of the back surface of the semiconductor substrate, and connects the back electrodes by crossing over the groove. Thus, the formation of the groove does not interfere with the wiring connection of the back electrode.
  • the back electrode can be connected to the wiring regardless of the formation position of the concave groove.
  • it is not necessary to control the position of the concave groove in detail, so it can be formed mechanically by a cutting machine such as a multi-blade machine, and the groove formation time can be greatly shortened and productivity is improved. If it is improved, the manufacturing cost can be further reduced.
  • the back junction solar cell A of the present invention has a linear p + type diffusion layer 2 and an n + type diffusion on the back side la of a p-type (or ⁇ type) semiconductor substrate 1 as shown in FIGS.
  • Layers 3 are alternately formed at the same time, and a concave groove lb is formed from the back surface la of the semiconductor substrate 1 toward the boundary where the outer ends of the p + type diffusion layer 2 and the n + type diffusion layer 3 are in contact with each other.
  • the p + type diffusion layer 2 and the n + type diffusion layer 3 are separated from each other at the outer ends, and the exposed surface 2a of the separated p + type diffusion layer 2 and the exposed surface 3a of the n + type diffusion layer 3 are positive or negative.
  • the p + type diffusion layer 2 and the n + type diffusion layer 3 have a silicon single crystal or polycrystalline silicon force.
  • a paste 2 ' such as boron as a p-type impurity and a paste 3' such as phosphorus as an n-type impurity are applied to the back surface la of the semiconductor substrate 1 in a desired shape by a method such as pattern printing. .
  • the p-type impurity paste ⁇ and the n-type impurity paste 3 ' are arranged close to each other in a substantially parallel line shape, and the semiconductor substrate 1 including the p-type impurity paste 3' is heated to a predetermined temperature by firing.
  • the p-type impurity ⁇ and the n-type impurity are simultaneously thermally diffused into the semiconductor substrate 1, respectively, so that the p + type diffusion layer 2 region and the n + type diffusion layer 3 region remain alternately close to each other. Simultaneously formed.
  • the diffusion of the p-type impurity 2 'and the n-type impurity 3' into the semiconductor substrate 1 is isotropic, and the p-type impurity 2 'and the n-type impurity Since diffusion growth occurs from 3 'to the substrate portion lc by auto-doping (auto-doping), the outer end of the p + type diffusion layer 2 and the n + type diffusion layer 3 are the same on the back surface la side of the semiconductor substrate 1. Contact.
  • the groove lb is partially formed along the boundary line.
  • the outer end of the P + type diffusion layer 2 and the outer end of the n + type diffusion layer 3 are completely separated, and the silicon force of the semiconductor substrate 1 is formed at the bottom of the concave groove lb.
  • the substrate part lc is exposed.
  • a cutting force such as a multi-blade machine is used to cut the wire into a linear shape by mechanically cutting it, or by cutting with a laser beam or the like to make a linear shape.
  • a cutting force such as a multi-blade machine is used to cut the wire into a linear shape by mechanically cutting it, or by cutting with a laser beam or the like to make a linear shape.
  • the exposed surface 2a of the p + type diffusion layer 2 and the exposed surface 3a of the n + type diffusion layer 3 separated by the groove forming step are positive and negative formed in the same line as the exposed surfaces 2a and 3a.
  • the back electrodes 4 and 5 are connected to each other.
  • the p-type impurity paste 2 ′ and the n-type impurity paste 3 ′ are printed in a comb-teeth pattern and thermally diffused to form a P + type diffusion layer.
  • 2 and n + type diffusion layer 3 regions are simultaneously formed in a comb-teeth shape and p +
  • the same comb-shaped back electrodes 4 and 5 are formed in the type diffusion layer 2 and the n + type diffusion layer 3.
  • n + type light receiving side diffusion layer 6 is formed, and the semiconductor substrate 1 is n_ type.
  • an n + type light-receiving side diffusion layer 6 is formed, and an antireflection film 7 as shown in the figure can be formed on the surface side as necessary.
  • the p-type impurity paste ⁇ and the n-type impurity paste 3 ' are linearly approached to the back surface la of the semiconductor substrate 1 as shown in FIGS. 3 (a) and 4 (a), respectively. Then, it is applied in a comb-teeth shape as shown in the figure, or by a method such as pattern printing.
  • n-type or P-type impurity paste 6 ′ for forming the light-receiving side diffusion layer 6 is applied to the light-receiving surface Id of the semiconductor substrate 1.
  • a concave groove lb is partially formed along the boundary line by a cutting machine such as a multi-blade machine or laser beam irradiation toward the matching boundary part.
  • the exposed surface 2a of the p + type diffusion layer 2 separated by the groove forming step and the n + type The positive and negative back electrodes 4 and 5 formed in the same line shape are connected to the exposed surface 3a of the diffusion layer 3 to complete the manufacturing process on the back surface la side.
  • the P + type diffusion layer 2 and the n + type diffusion layer 3 are arranged close to each other across the concave groove lb.
  • the distance at which electrons and holes generated by the incidence of light travel to the p-type diffusion layer 2 and the n-type diffusion layer 3 becomes much shorter, and the photoelectric conversion efficiency is improved.
  • the semiconductor substrate 1 Even if the groove lb is formed over the entire length in the width direction of the back surface la of the back surface, if the back electrodes 4 and 5 are connected to each other by crossing over the groove lb in the subsequent process, the formation of the groove lb is achieved. Since it does not interfere with the wiring connection of the electrodes 4 and 5, there is an advantage that the back electrodes 4 and 5 can be connected to each other regardless of the position where the concave groove lb is formed.
  • the n + type or p + type light receiving side diffusion layer 6 is formed on the light receiving surface Id side of the semiconductor substrate 1 and the antireflection film 7 is formed on the surface side thereof.
  • the structure on the light receiving surface Id side is not limited, and may be another conventionally well-known structure.
  • FIG. 1 is a longitudinal side view showing an embodiment of a back junction solar cell according to the present invention, with its main part partially enlarged.
  • FIG. 2 A bottom view of the same, partially cut away.
  • FIG. 3 is a longitudinal side view showing an embodiment of a method for manufacturing a back junction solar cell of the present invention, the steps are sequentially shown in (a) to (c), with the main part partially enlarged. ing.
  • FIG. 4 is a reduced bottom view corresponding to (a) to (c) of FIG.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Sustainable Development (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Power Engineering (AREA)
  • Sustainable Energy (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Photovoltaic Devices (AREA)

Abstract

L’invention concerne une configuration précise d’une couche de diffusion de type p+ et d’une couche de diffusion de type n+ sans contact l’une avec l’autre. Au dos (1a) d’un substrat semi-conducteur (1), sont formées simultanément une couche de diffusion de type p+ (2) et une couche de diffusion de type n+ (3) très près l’une de l’autre. Une rainure en retrait (1b) est constituée à partir du dos (1a) du substrat semi-conducteur (1) vers une partie bordure où les bords externes de la couche de diffusion de type p+ (2) et de la couche de diffusion de type n+ (3) sont mis au contact l’un de l’autre pour alors séparer les bords externes de la couche de diffusion de type p+ (2) et de la couche de diffusion de type n+ (3) les uns des autres. Ainsi, la couche de diffusion de type p+ (2) et la couche de diffusion de type n+ (3) sont disposées très près l’une de l’autre, avec la rainure en retrait (1b) interposée entre celles-ci.
PCT/JP2005/019384 2004-12-27 2005-10-21 Pile solaire à jonction de renfort et procédé de fabrication idoine WO2006075427A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004376604A JP2008066316A (ja) 2004-12-27 2004-12-27 裏面接合型太陽電池及びその製造方法
JP2004-376604 2004-12-27

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WO2006075427A1 true WO2006075427A1 (fr) 2006-07-20

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TW (1) TW200635057A (fr)
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008071937A (ja) * 2006-09-14 2008-03-27 Dainippon Printing Co Ltd 有機薄膜太陽電池
WO2009025147A1 (fr) * 2007-08-23 2009-02-26 Sharp Kabushiki Kaisha Cellule solaire du type à connexion par la surface arrière, cellule solaire du type à connexion par la surface arrière ayant une carte de câblage, chaîne de cellules solaires et module de cellule solaire
KR101149173B1 (ko) 2010-12-17 2012-05-25 현대중공업 주식회사 후면전극형 태양전지 및 그 제조방법
EP2161757A3 (fr) * 2008-09-09 2016-02-10 Palo Alto Research Center Incorporated Cellules solaires en silicium à contact arrière interdigité avec des rainures obtenues par ablation laser

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102132422A (zh) * 2008-08-27 2011-07-20 应用材料股份有限公司 利用印刷介电阻障的背接触太阳能电池
US9150966B2 (en) 2008-11-14 2015-10-06 Palo Alto Research Center Incorporated Solar cell metallization using inline electroless plating
US8962424B2 (en) 2011-03-03 2015-02-24 Palo Alto Research Center Incorporated N-type silicon solar cell with contact/protection structures
US9812592B2 (en) * 2012-12-21 2017-11-07 Sunpower Corporation Metal-foil-assisted fabrication of thin-silicon solar cell
JP5708695B2 (ja) * 2013-04-12 2015-04-30 トヨタ自動車株式会社 太陽電池セル
US9231129B2 (en) 2014-03-28 2016-01-05 Sunpower Corporation Foil-based metallization of solar cells

Citations (4)

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JPH09172196A (ja) * 1995-11-22 1997-06-30 Ebara Solar Inc アルミニウム合金接合自己整合裏面電極型シリコン太陽電池の構造および製造
JP2002057352A (ja) * 2000-06-02 2002-02-22 Honda Motor Co Ltd 太陽電池およびその製造方法
JP2003124483A (ja) * 2001-10-17 2003-04-25 Toyota Motor Corp 光起電力素子
JP2004071763A (ja) * 2002-08-05 2004-03-04 Toyota Motor Corp 光起電力素子

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09172196A (ja) * 1995-11-22 1997-06-30 Ebara Solar Inc アルミニウム合金接合自己整合裏面電極型シリコン太陽電池の構造および製造
JP2002057352A (ja) * 2000-06-02 2002-02-22 Honda Motor Co Ltd 太陽電池およびその製造方法
JP2003124483A (ja) * 2001-10-17 2003-04-25 Toyota Motor Corp 光起電力素子
JP2004071763A (ja) * 2002-08-05 2004-03-04 Toyota Motor Corp 光起電力素子

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008071937A (ja) * 2006-09-14 2008-03-27 Dainippon Printing Co Ltd 有機薄膜太陽電池
WO2009025147A1 (fr) * 2007-08-23 2009-02-26 Sharp Kabushiki Kaisha Cellule solaire du type à connexion par la surface arrière, cellule solaire du type à connexion par la surface arrière ayant une carte de câblage, chaîne de cellules solaires et module de cellule solaire
JP5093821B2 (ja) * 2007-08-23 2012-12-12 シャープ株式会社 配線基板付き裏面接合型太陽電池、太陽電池ストリングおよび太陽電池モジュール
EP2161757A3 (fr) * 2008-09-09 2016-02-10 Palo Alto Research Center Incorporated Cellules solaires en silicium à contact arrière interdigité avec des rainures obtenues par ablation laser
KR101149173B1 (ko) 2010-12-17 2012-05-25 현대중공업 주식회사 후면전극형 태양전지 및 그 제조방법

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