WO2006075427A1 - Back junction solar cell and process for producing the same - Google Patents

Back junction solar cell and process for producing the same Download PDF

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Publication number
WO2006075427A1
WO2006075427A1 PCT/JP2005/019384 JP2005019384W WO2006075427A1 WO 2006075427 A1 WO2006075427 A1 WO 2006075427A1 JP 2005019384 W JP2005019384 W JP 2005019384W WO 2006075427 A1 WO2006075427 A1 WO 2006075427A1
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WIPO (PCT)
Prior art keywords
diffusion layer
type diffusion
semiconductor substrate
type
back surface
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PCT/JP2005/019384
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French (fr)
Japanese (ja)
Inventor
Tsutomu Onishi
Takeshi Akatsuka
Shunichi Igarashi
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Naoetsu Electronics Co., Ltd.
Shin-Etsu Chemical Co., Ltd.
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Application filed by Naoetsu Electronics Co., Ltd., Shin-Etsu Chemical Co., Ltd. filed Critical Naoetsu Electronics Co., Ltd.
Publication of WO2006075427A1 publication Critical patent/WO2006075427A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/03529—Shape of the potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Definitions

  • the present invention relates to a structure of a back junction type (back contact type) solar cell in which positive and negative electrodes are arranged on the back surface opposite to a light receiving surface, and a manufacturing method thereof.
  • a back junction solar cell in which linear p + type diffusion layers and n + type diffusion layers are alternately formed on the back surface of a semiconductor substrate, and positive and negative back electrodes are separately connected to both diffusion layers, and its manufacture Regarding the method.
  • an oxide silicon film is formed as a mask for impurity diffusion on the back side of a silicon substrate, and a predetermined portion thereof is removed by etching.
  • a p-type diffusion layer is formed, on which an n-type diffusion layer is formed.
  • a back electrode in contact with the diffusion layer in the form of dots and an electrode in contact with the P-type diffusion layer in the form of dots are formed, and these diffusion layers and the electrodes are joined together at the opposing portions on the back side of the silicon substrate.
  • a line-shaped n + -type diffusion layer and a p + -type diffusion layer are alternately formed at the same interval (pitch) on the back surface of the semiconductor substrate (see, for example, Patent Document 2).
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2002-164556 (Page 2-3, Fig. 1, 4)
  • Patent Document 2 Japanese Patent Laid-Open No. 2004-71828 (Page 2, Fig. 1 (a))
  • linear p + type diffusion layers and n + type diffusion layers are arranged close to each other for the purpose of improving photoelectric conversion efficiency. It is desirable that U be thermally diffused with p-type and n-type impurities placed close to each other on the back side of the semiconductor substrate, so that the diffusion of impurities into the semiconductor substrate is isotropic. If there is an impurity in contact with the substrate, the substrate part is also auto-doped (auto-doped In this case, the outer edges of the p + type diffusion layer and the n + type diffusion layer are in contact with the outside of the substrate, and the current cannot be extracted from the positive and negative electrodes. There was a title.
  • the p + type diffusion layer and the n + type diffusion layer must be separated to a distance that does not come into contact with each other even if they are diffused and grown.
  • the distance that electrons and holes move to the P + type diffusion layer and the n + type diffusion layer becomes long, and there is a problem that the photoelectric conversion efficiency decreases.
  • the inventions described in claims 1 and 2 are aimed at arranging the p + type diffusion layer and the n + type diffusion layer in contact with each other without contact.
  • the invention described in claim 3 is intended to interconnect the back electrode regardless of the position where the concave groove is formed.
  • the invention according to claim 1 of the present invention is such that a p + -type diffusion layer and an n + -type diffusion layer are formed on the back surface of a semiconductor substrate at the same time.
  • the back surface force of the semiconductor substrate is also formed by forming a groove toward the boundary where the outer ends of the P + type diffusion layer and the n + type diffusion layer are in contact with each other, and the outer ends of the p + type diffusion layer and the n + type diffusion layer are It is characterized by having been separated.
  • the invention described in claim 2 includes the step of forming a p + type diffusion layer and an n + type diffusion layer close to each other on the back surface of the semiconductor substrate and simultaneously forming the p + type diffusion layer and the n + type diffusion layer from the back surface of the semiconductor substrate.
  • the process power of separately connecting the positive and negative back electrodes to the exposed surface of the substrate is also characterized.
  • the invention according to claim 3 is the structure according to the invention according to claim 2, wherein the concave groove is formed over the entire length of the back surface of the semiconductor substrate, and the back electrodes are connected to each other by intersecting the concave groove. It is characterized by having added.
  • the inventions according to claims 1 and 2 include a p + type diffusion layer and an n + on the back surface of the semiconductor substrate.
  • the mold diffusion layers are formed close to each other at the same time, and concave grooves are formed from the back surface of the semiconductor substrate toward the boundary portion where the outer ends of the P + diffusion layer and the n + diffusion layer are in contact with each other.
  • the p + -type diffusion layer and the n + -type diffusion layer are arranged close to each other across the concave groove.
  • the P + type diffusion layer and the n + type diffusion layer without striking them.
  • the p + type diffusion layer and the n + type diffusion layer are separated from each other by a distance where they do not contact each other even if they are diffused and grown.
  • the photoelectric conversion efficiency can be improved.
  • the p + type diffusion layer and the n + type diffusion layer are formed at the same time, it can be easily manufactured in a short time and at a low cost as compared with the conventional one in which these both diffusion layers are formed separately.
  • the invention of claim 3 forms a groove over the entire length of the back surface of the semiconductor substrate, and connects the back electrodes by crossing over the groove. Thus, the formation of the groove does not interfere with the wiring connection of the back electrode.
  • the back electrode can be connected to the wiring regardless of the formation position of the concave groove.
  • it is not necessary to control the position of the concave groove in detail, so it can be formed mechanically by a cutting machine such as a multi-blade machine, and the groove formation time can be greatly shortened and productivity is improved. If it is improved, the manufacturing cost can be further reduced.
  • the back junction solar cell A of the present invention has a linear p + type diffusion layer 2 and an n + type diffusion on the back side la of a p-type (or ⁇ type) semiconductor substrate 1 as shown in FIGS.
  • Layers 3 are alternately formed at the same time, and a concave groove lb is formed from the back surface la of the semiconductor substrate 1 toward the boundary where the outer ends of the p + type diffusion layer 2 and the n + type diffusion layer 3 are in contact with each other.
  • the p + type diffusion layer 2 and the n + type diffusion layer 3 are separated from each other at the outer ends, and the exposed surface 2a of the separated p + type diffusion layer 2 and the exposed surface 3a of the n + type diffusion layer 3 are positive or negative.
  • the p + type diffusion layer 2 and the n + type diffusion layer 3 have a silicon single crystal or polycrystalline silicon force.
  • a paste 2 ' such as boron as a p-type impurity and a paste 3' such as phosphorus as an n-type impurity are applied to the back surface la of the semiconductor substrate 1 in a desired shape by a method such as pattern printing. .
  • the p-type impurity paste ⁇ and the n-type impurity paste 3 ' are arranged close to each other in a substantially parallel line shape, and the semiconductor substrate 1 including the p-type impurity paste 3' is heated to a predetermined temperature by firing.
  • the p-type impurity ⁇ and the n-type impurity are simultaneously thermally diffused into the semiconductor substrate 1, respectively, so that the p + type diffusion layer 2 region and the n + type diffusion layer 3 region remain alternately close to each other. Simultaneously formed.
  • the diffusion of the p-type impurity 2 'and the n-type impurity 3' into the semiconductor substrate 1 is isotropic, and the p-type impurity 2 'and the n-type impurity Since diffusion growth occurs from 3 'to the substrate portion lc by auto-doping (auto-doping), the outer end of the p + type diffusion layer 2 and the n + type diffusion layer 3 are the same on the back surface la side of the semiconductor substrate 1. Contact.
  • the groove lb is partially formed along the boundary line.
  • the outer end of the P + type diffusion layer 2 and the outer end of the n + type diffusion layer 3 are completely separated, and the silicon force of the semiconductor substrate 1 is formed at the bottom of the concave groove lb.
  • the substrate part lc is exposed.
  • a cutting force such as a multi-blade machine is used to cut the wire into a linear shape by mechanically cutting it, or by cutting with a laser beam or the like to make a linear shape.
  • a cutting force such as a multi-blade machine is used to cut the wire into a linear shape by mechanically cutting it, or by cutting with a laser beam or the like to make a linear shape.
  • the exposed surface 2a of the p + type diffusion layer 2 and the exposed surface 3a of the n + type diffusion layer 3 separated by the groove forming step are positive and negative formed in the same line as the exposed surfaces 2a and 3a.
  • the back electrodes 4 and 5 are connected to each other.
  • the p-type impurity paste 2 ′ and the n-type impurity paste 3 ′ are printed in a comb-teeth pattern and thermally diffused to form a P + type diffusion layer.
  • 2 and n + type diffusion layer 3 regions are simultaneously formed in a comb-teeth shape and p +
  • the same comb-shaped back electrodes 4 and 5 are formed in the type diffusion layer 2 and the n + type diffusion layer 3.
  • n + type light receiving side diffusion layer 6 is formed, and the semiconductor substrate 1 is n_ type.
  • an n + type light-receiving side diffusion layer 6 is formed, and an antireflection film 7 as shown in the figure can be formed on the surface side as necessary.
  • the p-type impurity paste ⁇ and the n-type impurity paste 3 ' are linearly approached to the back surface la of the semiconductor substrate 1 as shown in FIGS. 3 (a) and 4 (a), respectively. Then, it is applied in a comb-teeth shape as shown in the figure, or by a method such as pattern printing.
  • n-type or P-type impurity paste 6 ′ for forming the light-receiving side diffusion layer 6 is applied to the light-receiving surface Id of the semiconductor substrate 1.
  • a concave groove lb is partially formed along the boundary line by a cutting machine such as a multi-blade machine or laser beam irradiation toward the matching boundary part.
  • the exposed surface 2a of the p + type diffusion layer 2 separated by the groove forming step and the n + type The positive and negative back electrodes 4 and 5 formed in the same line shape are connected to the exposed surface 3a of the diffusion layer 3 to complete the manufacturing process on the back surface la side.
  • the P + type diffusion layer 2 and the n + type diffusion layer 3 are arranged close to each other across the concave groove lb.
  • the distance at which electrons and holes generated by the incidence of light travel to the p-type diffusion layer 2 and the n-type diffusion layer 3 becomes much shorter, and the photoelectric conversion efficiency is improved.
  • the semiconductor substrate 1 Even if the groove lb is formed over the entire length in the width direction of the back surface la of the back surface, if the back electrodes 4 and 5 are connected to each other by crossing over the groove lb in the subsequent process, the formation of the groove lb is achieved. Since it does not interfere with the wiring connection of the electrodes 4 and 5, there is an advantage that the back electrodes 4 and 5 can be connected to each other regardless of the position where the concave groove lb is formed.
  • the n + type or p + type light receiving side diffusion layer 6 is formed on the light receiving surface Id side of the semiconductor substrate 1 and the antireflection film 7 is formed on the surface side thereof.
  • the structure on the light receiving surface Id side is not limited, and may be another conventionally well-known structure.
  • FIG. 1 is a longitudinal side view showing an embodiment of a back junction solar cell according to the present invention, with its main part partially enlarged.
  • FIG. 2 A bottom view of the same, partially cut away.
  • FIG. 3 is a longitudinal side view showing an embodiment of a method for manufacturing a back junction solar cell of the present invention, the steps are sequentially shown in (a) to (c), with the main part partially enlarged. ing.
  • FIG. 4 is a reduced bottom view corresponding to (a) to (c) of FIG.

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  • Microelectronics & Electronic Packaging (AREA)
  • Sustainable Development (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
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Abstract

A minute arrangement of p+ type diffusion layer and n+ type diffusion layer without contact with each other. On the backside (1a) of semiconductor substrate (1), there are simultaneously formed p+ type diffusion layer (2) and n+ type diffusion layer (3) in close vicinity of each other. Recessed groove (1b) is formed from the backside (1a) of the semiconductor substrate (1) to a border portion where outer edges of the p+ type diffusion layer (2) and n+ type diffusion layer (3) are brought into contact with each other to thereby separate the outer edges of the p+ type diffusion layer (2) and n+ type diffusion layer (3) from each other. As a result, the p+ type diffusion layer (2) and n+ type diffusion layer (3) are arranged in close vicinity of each other with the recessed groove (1b) interposed therebetween.

Description

明 細 書  Specification
裏面接合型太陽電池及びその製造方法  Back junction solar cell and manufacturing method thereof
技術分野  Technical field
[0001] 本発明は、受光面と反対の裏面に正負の電極が配置される裏面接合型 (バックコン タクト型)太陽電池の構造及びその製造方法に関する。  TECHNICAL FIELD [0001] The present invention relates to a structure of a back junction type (back contact type) solar cell in which positive and negative electrodes are arranged on the back surface opposite to a light receiving surface, and a manufacturing method thereof.
詳しくは、半導体基板の裏面に、線状の p+型拡散層と n+型拡散層を夫々交互に 形成し、これら両拡散層に正負の裏面電極を別々に接続する裏面接合型太陽電池 及びその製造方法に関する。  Specifically, a back junction solar cell in which linear p + type diffusion layers and n + type diffusion layers are alternately formed on the back surface of a semiconductor substrate, and positive and negative back electrodes are separately connected to both diffusion layers, and its manufacture Regarding the method.
背景技術  Background art
[0002] 従来、この種の裏面接合型太陽電池及び製造方法として、シリコン基板の裏面側 に不純物拡散のマスクとして酸ィ匕シリコン膜を形成し、その所定部分をエッチング除 去してから、 n型拡散層（n+領域)を形成し、次に不純物拡散のマスクとしての酸ィ匕シ リコン膜を除去してから、 p型拡散層 (p+領域)を形成し、その上には、 n型拡散層と点 状に接触する裏面電極と、 P型拡散層と点状に接触する電極が夫々形成され、これ ら両拡散層と両電極とを、シリコン基板の裏面側の対向部で夫々合流するように櫛歯 状に形成したものがある（例えば、特許文献 1参照)。  Conventionally, as this type of back junction solar cell and manufacturing method, an oxide silicon film is formed as a mask for impurity diffusion on the back side of a silicon substrate, and a predetermined portion thereof is removed by etching. After forming an n-type diffusion layer (n + region) and then removing the silicon oxide film as a mask for impurity diffusion, a p-type diffusion layer (p + region) is formed, on which an n-type diffusion layer is formed. A back electrode in contact with the diffusion layer in the form of dots and an electrode in contact with the P-type diffusion layer in the form of dots are formed, and these diffusion layers and the electrodes are joined together at the opposing portions on the back side of the silicon substrate. Some of them are formed in a comb-like shape (see, for example, Patent Document 1).
また、半導体基板の裏面にライン状の n+型拡散層と p+型拡散層とが、夫々交互に 同一の間隔 (ピッチ)で形成されたものもある (例えば、特許文献 2参照)。  In some cases, a line-shaped n + -type diffusion layer and a p + -type diffusion layer are alternately formed at the same interval (pitch) on the back surface of the semiconductor substrate (see, for example, Patent Document 2).
[0003] 特許文献 1 :特開 2002— 164556号公報（第 2— 3頁、図 1, 4)  [0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2002-164556 (Page 2-3, Fig. 1, 4)
特許文献 2：特開 2004— 71828号公報 (第 2頁、図 1 (a) )  Patent Document 2: Japanese Patent Laid-Open No. 2004-71828 (Page 2, Fig. 1 (a))
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0004] しかし乍ら、このような従来の裏面接合型太陽電池及び製造方法では、光電変換 効率の向上を図る目的から、線状の p+型拡散層と n+型拡散層を互いに接近させて 配置することが望ま U、が、半導体基板の裏面側に p型及び n型の不純物を互 ヽに 接近させて配置した状態で熱拡散させると、半導体基板内部への不純物の拡散が 等方性であることと、不純物が接して 、な 、基板部分へもオートドープ (オートドーピ ング）によって拡散成長するため、これら p+型拡散層及び n+型拡散層の外側端部同 士が基板外側にぉ 、て接触してしま 、、正負の電極から電流を取り出せな ヽと 、う問 題があった。 However, in such conventional back junction solar cells and manufacturing methods, linear p + type diffusion layers and n + type diffusion layers are arranged close to each other for the purpose of improving photoelectric conversion efficiency. It is desirable that U be thermally diffused with p-type and n-type impurities placed close to each other on the back side of the semiconductor substrate, so that the diffusion of impurities into the semiconductor substrate is isotropic. If there is an impurity in contact with the substrate, the substrate part is also auto-doped (auto-doped In this case, the outer edges of the p + type diffusion layer and the n + type diffusion layer are in contact with the outside of the substrate, and the current cannot be extracted from the positive and negative electrodes. There was a title.
この問題を解決するには、 p+型拡散層と n+型拡散層を夫々が拡散成長しても互い に接触しない距離まで離さなければならず、このような配置では、光の入射により発 生した電子と正孔が P+型拡散層及び n+型拡散層まで移動する距離が長くなるため 、光電変換効率が低下するという問題があった。  In order to solve this problem, the p + type diffusion layer and the n + type diffusion layer must be separated to a distance that does not come into contact with each other even if they are diffused and grown. The distance that electrons and holes move to the P + type diffusion layer and the n + type diffusion layer becomes long, and there is a problem that the photoelectric conversion efficiency decreases.
[0005] 本発明のうち請求項 1、 2記載の発明は、 p+型拡散層と n+型拡散層を接触させず に細力べ配置することを目的としたものである。 [0005] Among the present inventions, the inventions described in claims 1 and 2 are aimed at arranging the p + type diffusion layer and the n + type diffusion layer in contact with each other without contact.
請求項 3記載の発明は、請求項 2に記載の発明の目的に加えて、凹溝の形成位置 に関係なく裏面電極を配線連絡することを目的としたものである。  In addition to the object of the invention described in claim 2, the invention described in claim 3 is intended to interconnect the back electrode regardless of the position where the concave groove is formed.
課題を解決するための手段  Means for solving the problem
[0006] 前述した目的を達成するために、本発明のうち請求項 1記載の発明は、半導体基 板の裏面に、 p+型拡散層と n+型拡散層を互いに接近させて同時に形成し、この半 導体基板の裏面力も P+型拡散層と n+型拡散層の外側端部同士が接触する境界部 分へ向け凹溝を形成して、これら p+型拡散層及び n+型拡散層の外側端部同士を分 離させたことを特徴とするものである。 [0006] In order to achieve the above-mentioned object, the invention according to claim 1 of the present invention is such that a p + -type diffusion layer and an n + -type diffusion layer are formed on the back surface of a semiconductor substrate at the same time. The back surface force of the semiconductor substrate is also formed by forming a groove toward the boundary where the outer ends of the P + type diffusion layer and the n + type diffusion layer are in contact with each other, and the outer ends of the p + type diffusion layer and the n + type diffusion layer are It is characterized by having been separated.
請求項 2記載の発明は、半導体基板の裏面に p+型拡散層と n+型拡散層を互いに 接近させて同時に形成する工程と、この半導体基板の裏面から P+型拡散層と n+型 拡散層の外側端部同士が接触する境界部分へ向け凹溝を形成して両拡散層の外 側端部同士を分離させる工程と、この溝形成工程により分離した p+型拡散層の露出 面と n+型拡散層の露出面に正負の裏面電極を別々に接続する工程力もなることを 特徴とするものである。  The invention described in claim 2 includes the step of forming a p + type diffusion layer and an n + type diffusion layer close to each other on the back surface of the semiconductor substrate and simultaneously forming the p + type diffusion layer and the n + type diffusion layer from the back surface of the semiconductor substrate. A step of separating the outer end portions of both diffusion layers by forming a concave groove toward a boundary portion where the end portions contact each other, and an exposed surface of the p + type diffusion layer and the n + type diffusion layer separated by the groove forming step. Further, the process power of separately connecting the positive and negative back electrodes to the exposed surface of the substrate is also characterized.
請求項 3記載の発明は、請求項 2記載の発明の構成に、前記凹溝を半導体基板の 裏面の全長に亘つて形成し、この凹溝の上に交差させて裏面電極同士を連結した構 成を加えたことを特徴とする。  The invention according to claim 3 is the structure according to the invention according to claim 2, wherein the concave groove is formed over the entire length of the back surface of the semiconductor substrate, and the back electrodes are connected to each other by intersecting the concave groove. It is characterized by having added.
発明の効果  The invention's effect
[0007] 本発明のうち請求項 1、 2記載の発明は、半導体基板の裏面に、 p+型拡散層と n+ 型拡散層を互いに接近させて同時に形成し、この半導体基板の裏面から P+型拡散 層及び n+型拡散層の外側端部同士が接触する境界部分へ向け凹溝を形成して、こ れら P+型拡散層及び n+型拡散層の外側端部同士を分離させることにより、この凹溝 を挟んで P+型拡散層と n+型拡散層が互いに接近して配置される。 [0007] Of the present invention, the inventions according to claims 1 and 2 include a p + type diffusion layer and an n + on the back surface of the semiconductor substrate. The mold diffusion layers are formed close to each other at the same time, and concave grooves are formed from the back surface of the semiconductor substrate toward the boundary portion where the outer ends of the P + diffusion layer and the n + diffusion layer are in contact with each other. By separating the outer end portions of the n-type diffusion layer and the n + -type diffusion layer, the p + -type diffusion layer and the n + -type diffusion layer are arranged close to each other across the concave groove.
従って、 P+型拡散層と n+型拡散層を接触させずに細力べ配置することができる。 その結果、 p+型拡散層と n+型拡散層を夫々が拡散成長しても互いに接触しない 距離まで離す必要がある従来のものに比べ、光の入射により発生した電子と正孔カ ¾ 型拡散層及び n型拡散層まで移動する距離が格段に短くなるため、光電変換効率を 向上できる。  Therefore, it is possible to arrange the P + type diffusion layer and the n + type diffusion layer without striking them. As a result, the p + type diffusion layer and the n + type diffusion layer are separated from each other by a distance where they do not contact each other even if they are diffused and grown. In addition, since the distance traveled to the n-type diffusion layer is remarkably shortened, the photoelectric conversion efficiency can be improved.
更に、 p+型拡散層と n+型拡散層を同時に形成するので、これら両拡散層を別々に 形成する従来のものに比べ、簡単に短時間でし力も安価で製造できる。  Furthermore, since the p + type diffusion layer and the n + type diffusion layer are formed at the same time, it can be easily manufactured in a short time and at a low cost as compared with the conventional one in which these both diffusion layers are formed separately.
[0008] 請求項 3の発明は、請求項 2の発明の効果に加えて、凹溝を半導体基板の裏面の 全長に亘つて形成し、この凹溝の上に交差させて裏面電極同士を連結することにより 、凹溝の形成が裏面電極の配線連絡と邪魔にならない。 [0008] In addition to the effect of the invention of claim 2, the invention of claim 3 forms a groove over the entire length of the back surface of the semiconductor substrate, and connects the back electrodes by crossing over the groove. Thus, the formation of the groove does not interfere with the wiring connection of the back electrode.
従って、凹溝の形成位置に関係なく裏面電極を配線連絡することができる。 その結果、凹溝の位置制御を詳細に行う必要がないから、マルチブレードマシンな どの切断機により機械的に形成することが可能となって、溝形成時間を大幅に短縮 化できて生産性が向上するば力りでなぐ製造コストの更なる低減も図れる。  Therefore, the back electrode can be connected to the wiring regardless of the formation position of the concave groove. As a result, it is not necessary to control the position of the concave groove in detail, so it can be formed mechanically by a cutting machine such as a multi-blade machine, and the groove formation time can be greatly shortened and productivity is improved. If it is improved, the manufacturing cost can be further reduced.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0009] 以下、本発明の一実施例を図面に基づいて説明する。  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
本発明の裏面接合型太陽電池 Aは、図 1〜図 4に示す如ぐ p—型 (又は ι 型)の半 導体基板 1の裏面 laに、線状の p+型拡散層 2と n+型拡散層 3を夫々交互に接近さ せて同時に形成し、この半導体基板 1の裏面 laから p+型拡散層 2と n+型拡散層 3の 外側端部同士が接触し合う境界部分へ向け凹溝 lbを形成して、これら p+型拡散層 2 及び n+型拡散層 3の外側端部同士を分離させると共に、この分離した p+型拡散層 2 の露出面 2aと n+型拡散層 3の露出面 3aに正負の裏面電極 4, 5を夫々接続すること で、受光面 Idと反対側力も通電可能にしている。  The back junction solar cell A of the present invention has a linear p + type diffusion layer 2 and an n + type diffusion on the back side la of a p-type (or ι type) semiconductor substrate 1 as shown in FIGS. Layers 3 are alternately formed at the same time, and a concave groove lb is formed from the back surface la of the semiconductor substrate 1 toward the boundary where the outer ends of the p + type diffusion layer 2 and the n + type diffusion layer 3 are in contact with each other. The p + type diffusion layer 2 and the n + type diffusion layer 3 are separated from each other at the outer ends, and the exposed surface 2a of the separated p + type diffusion layer 2 and the exposed surface 3a of the n + type diffusion layer 3 are positive or negative. By connecting the back electrodes 4 and 5, respectively, it is possible to energize the force opposite to the light receiving surface Id.
[0010] 上記 p+型拡散層 2及び n+型拡散層 3は、シリコン単結晶や多結晶シリコン力 なる の半導体基板 1の裏面 laに、 p型の不純物として例えばボロンなどのペースト 2' と、 n型の不純物として例えばリンなどのペースト 3' を、パターン印刷するなどの手法で 夫々所望形状に塗布する。 [0010] The p + type diffusion layer 2 and the n + type diffusion layer 3 have a silicon single crystal or polycrystalline silicon force. For example, a paste 2 'such as boron as a p-type impurity and a paste 3' such as phosphorus as an n-type impurity are applied to the back surface la of the semiconductor substrate 1 in a desired shape by a method such as pattern printing. .
[0011] これら p型不純物のペースト ^ と n型不純物のペースト 3' は、ほぼ平行な線状に 夫々接近して配置され、それを含め半導体基板 1全体を焼成するなどして所定温度 まで加熱することにより、これら p型不純物 ^ 及び n型不純物 が半導体基板 1の 内部に夫々同時に熱拡散して、 p+型拡散層 2の領域と n+型拡散層 3の領域が夫々 交互に接近したままで同時形成される。  [0011] The p-type impurity paste ^ and the n-type impurity paste 3 'are arranged close to each other in a substantially parallel line shape, and the semiconductor substrate 1 including the p-type impurity paste 3' is heated to a predetermined temperature by firing. As a result, the p-type impurity ^ and the n-type impurity are simultaneously thermally diffused into the semiconductor substrate 1, respectively, so that the p + type diffusion layer 2 region and the n + type diffusion layer 3 region remain alternately close to each other. Simultaneously formed.
[0012] そして、上記熱拡散工程では、半導体基板 1内部への p型不純物 2' の拡散及び n 型不純物 3' の拡散が等方性であることと、 p型不純物 2' 及び n型不純物 3' から 基板部分 lcへもオートドープ (オートドーピング）によって拡散成長するため、この半 導体基板 1の裏面 la側において、これら p+型拡散層 2と n+型拡散層 3の外側端部同 士が接触してしまう。  [0012] In the thermal diffusion step, the diffusion of the p-type impurity 2 'and the n-type impurity 3' into the semiconductor substrate 1 is isotropic, and the p-type impurity 2 'and the n-type impurity Since diffusion growth occurs from 3 'to the substrate portion lc by auto-doping (auto-doping), the outer end of the p + type diffusion layer 2 and the n + type diffusion layer 3 are the same on the back surface la side of the semiconductor substrate 1. Contact.
[0013] そこで、この半導体基板 1の裏面 laから上記 p+型拡散層 2と n+型拡散層 3の外側 端部同士が接触し合う境界部分へ向け、その境界線に沿って凹溝 lbを部分的に形 成することにより、これら P+型拡散層 2の外側端部と n+型拡散層 3の外側端部とを完 全に分離して、該凹溝 lbの底部に半導体基板 1のシリコン力 なる基板部分 lcが露 出するようにしている。  [0013] Therefore, from the back surface la of the semiconductor substrate 1 toward the boundary portion where the outer end portions of the p + type diffusion layer 2 and the n + type diffusion layer 3 are in contact with each other, the groove lb is partially formed along the boundary line. Thus, the outer end of the P + type diffusion layer 2 and the outer end of the n + type diffusion layer 3 are completely separated, and the silicon force of the semiconductor substrate 1 is formed at the bottom of the concave groove lb. The substrate part lc is exposed.
[0014] この凹溝 lbの形成方法としては、例えばマルチブレードマシンなどの切断機により 機械的に切断加工して直線状に凹設する力、又はレーザー光線などの照射により切 断加工して直線状に凹設する方法が一般的であるが、それ以外にエッチング液など による化学的な方法で部分的に凹設することも可能である。  [0014] As a method of forming the concave groove lb, for example, a cutting force such as a multi-blade machine is used to cut the wire into a linear shape by mechanically cutting it, or by cutting with a laser beam or the like to make a linear shape. However, it is also possible to make a partial recess by a chemical method using an etchant or the like.
[0015] 更に、上記溝形成工程によって分離した p+型拡散層 2の露出面 2aと n+型拡散層 3 の露出面 3aには、これら露出面 2a, 3aと同じ線状に形成された正負の裏面電極 4, 5を夫々接続している。  [0015] Furthermore, the exposed surface 2a of the p + type diffusion layer 2 and the exposed surface 3a of the n + type diffusion layer 3 separated by the groove forming step are positive and negative formed in the same line as the exposed surfaces 2a and 3a. The back electrodes 4 and 5 are connected to each other.
[0016] なお、図示例の場合には、上記 p型不純物のペースト 2' と n型不純物のペースト 3 ' とが櫛歯形状にパターン印刷され、これらを熱拡散させることにより、 P+型拡散層 2 及び n+型拡散層 3の領域が櫛歯形状に同時形成され、これら櫛歯状に嚙み合う p+ 型拡散層 2及び n+型拡散層 3に、同じ櫛歯形状の裏面電極 4, 5を形成している。 In the illustrated example, the p-type impurity paste 2 ′ and the n-type impurity paste 3 ′ are printed in a comb-teeth pattern and thermally diffused to form a P + type diffusion layer. 2 and n + type diffusion layer 3 regions are simultaneously formed in a comb-teeth shape and p + The same comb-shaped back electrodes 4 and 5 are formed in the type diffusion layer 2 and the n + type diffusion layer 3.
[0017] また、上記半導体基板 1の受光面 Id側には、この半導体基板 1が p—型である場合 には P+型の受光側拡散層 6を形成し、半導体基板 1が n_型の場合には n+型の受光 側拡散層 6を形成しており、その表面側には必要に応じて図示せる如ぐ反射防止 膜 7を形成することも可能である。 [0017] Further, on the light receiving surface Id side of the semiconductor substrate 1, when the semiconductor substrate 1 is p-type, a P + type light receiving side diffusion layer 6 is formed, and the semiconductor substrate 1 is n_ type. In this case, an n + type light-receiving side diffusion layer 6 is formed, and an antireflection film 7 as shown in the figure can be formed on the surface side as necessary.
[0018] 次に、本発明の裏面接合型太陽電池 Aの製造方法について、特に半導体基板 1 の裏面 la側を中心に工程順に従って説明する。 [0018] Next, a method for manufacturing the back junction solar cell A of the present invention will be described in the order of processes, particularly focusing on the back surface la side of the semiconductor substrate 1.
先ず、図 3 (a)及び図 4 (a)に示す如ぐ半導体基板 1の裏面 laに、 p型不純物のぺ 一スト ^ と n型不純物のペースト 3' を線状に夫々交互に接近させて、パターン印 刷するなどの手法により、ほぼ平行に塗布する力、又は図示せる如く櫛歯状に塗布 する。  First, the p-type impurity paste ^ and the n-type impurity paste 3 'are linearly approached to the back surface la of the semiconductor substrate 1 as shown in FIGS. 3 (a) and 4 (a), respectively. Then, it is applied in a comb-teeth shape as shown in the figure, or by a method such as pattern printing.
また、この際、半導体基板 1の受光面 Idには、受光側拡散層 6を形成するための n 型又は P型の不純物ペースト 6' を塗布する。  At this time, n-type or P-type impurity paste 6 ′ for forming the light-receiving side diffusion layer 6 is applied to the light-receiving surface Id of the semiconductor substrate 1.
[0019] その後、図 3 (b)及び図 4 (b)に示す如ぐ少なくとも p型不純物のペースト ^ 及び n型不純物のペースト 3' を加熱して同時に熱拡散させると、半導体基板 1の内部に P+型拡散層 2の領域と n+型拡散層 3の領域が同時に形成される。  Thereafter, when at least the p-type impurity paste ^ and the n-type impurity paste 3 ′ as shown in FIGS. 3 (b) and 4 (b) are heated and simultaneously thermally diffused, the interior of the semiconductor substrate 1 is obtained. In addition, the P + type diffusion layer 2 region and the n + type diffusion layer 3 region are simultaneously formed.
[0020] この際、半導体基板 1内部への p型不純物 ^ の拡散及び n型不純物 の拡散が 等方性であることと、 p型不純物 ^ 及び n型不純物 力 基板部分 lcへもオートド ープ (オートドーピング）によって拡散成長するため、半導体基板 1の裏面 la側で、こ れら P+型拡散層 2と n+型拡散層 3の外側端部同士が接触する。  [0020] At this time, diffusion of p-type impurity ^ and n-type impurity into the semiconductor substrate 1 is isotropic, and p-type impurity ^ and n-type impurity force are also automatically doped into the substrate portion lc. Since diffusion growth occurs by (auto-doping), the outer ends of the P + type diffusion layer 2 and the n + type diffusion layer 3 are in contact with each other on the back surface la side of the semiconductor substrate 1.
[0021] この状態で、図 3 (c)及び図 4 (c)に示す如ぐこの半導体基板 1の裏面 laから上記 P+型拡散層 2と n+型拡散層 3の外側端部同士が接触し合う境界部分へ向け、その 境界線に沿って凹溝 lbを、マルチブレードマシンなどの切断機やレーザー光線の照 射などによって部分的に形成する。  In this state, the outer end portions of the P + type diffusion layer 2 and the n + type diffusion layer 3 are in contact with each other from the back surface la of the semiconductor substrate 1 as shown in FIGS. 3 (c) and 4 (c). A concave groove lb is partially formed along the boundary line by a cutting machine such as a multi-blade machine or laser beam irradiation toward the matching boundary part.
それにより、これら P+型拡散層 2の外側端部と n+型拡散層 3の外側端部とを完全に 分離して、該凹溝 lbの底部に半導体基板 1のシリコン力 なる基板部分 lcが露出す る。  As a result, the outer end portion of the P + type diffusion layer 2 and the outer end portion of the n + type diffusion layer 3 are completely separated, and the substrate portion lc that is the silicon force of the semiconductor substrate 1 is exposed at the bottom of the concave groove lb. The
[0022] それ以降は、上記溝形成工程によって分離した p+型拡散層 2の露出面 2aと n+型 拡散層 3の露出面 3aに、同じ線状に形成された正負の裏面電極 4, 5を夫々接続し て、裏面 la側の製造工程が完了する。 Thereafter, the exposed surface 2a of the p + type diffusion layer 2 separated by the groove forming step and the n + type The positive and negative back electrodes 4 and 5 formed in the same line shape are connected to the exposed surface 3a of the diffusion layer 3 to complete the manufacturing process on the back surface la side.
[0023] 従って、本発明の裏面接合型太陽電池 A及び製造方法は、上記凹溝 lbを挟んで P+型拡散層 2と n+型拡散層 3が互いに接近して細力べ配置されるため、光の入射に より発生した電子と正孔が p型拡散層 2及び n型拡散層 3まで移動する距離が格段に 短くなつて、光電変換効率が向上する。  Accordingly, in the back junction solar cell A and the manufacturing method of the present invention, the P + type diffusion layer 2 and the n + type diffusion layer 3 are arranged close to each other across the concave groove lb. The distance at which electrons and holes generated by the incidence of light travel to the p-type diffusion layer 2 and the n-type diffusion layer 3 becomes much shorter, and the photoelectric conversion efficiency is improved.
[0024] 更に、 p+型拡散層 2と n+型拡散層 3を同時に形成するため、これら両拡散層 2, 3を 簡単に短時間で製造できるという利点がある。  [0024] Furthermore, since the p + -type diffusion layer 2 and the n + -type diffusion layer 3 are formed at the same time, there is an advantage that both the diffusion layers 2 and 3 can be easily manufactured in a short time.
[0025] また特に図示例の如ぐ p+型拡散層 2及び n+型拡散層 3の領域と裏面電極 4, 5が 夫々櫛歯形状などのように折れ曲がって形成される場合には、半導体基板 1の裏面 laの幅方向全長に亘つて凹溝 lbを形成しても、その後工程で該凹溝 lbの上に交差 させて裏面電極 4, 5同士を連結すれば、凹溝 lbの形成が裏面電極 4, 5の配線連 絡と邪魔にならないため、凹溝 lbの形成位置に関係なく裏面電極 4, 5を配線連絡 できるという利点がある。  [0025] Further, when the regions of the p + type diffusion layer 2 and the n + type diffusion layer 3 and the back electrodes 4 and 5 are bent like a comb tooth shape as shown in the illustrated example, the semiconductor substrate 1 Even if the groove lb is formed over the entire length in the width direction of the back surface la of the back surface, if the back electrodes 4 and 5 are connected to each other by crossing over the groove lb in the subsequent process, the formation of the groove lb is achieved. Since it does not interfere with the wiring connection of the electrodes 4 and 5, there is an advantage that the back electrodes 4 and 5 can be connected to each other regardless of the position where the concave groove lb is formed.
[0026] 尚、前示実施例では、半導体基板 1の受光面 Id側に n+型又は p+型の受光側拡散 層 6を形成し、その表面側に反射防止膜 7を形成したが、これに限定されず、受光面 Id側の構造はそれ以外の従来周知な他の構造であっても良い。  In the previous embodiment, the n + type or p + type light receiving side diffusion layer 6 is formed on the light receiving surface Id side of the semiconductor substrate 1 and the antireflection film 7 is formed on the surface side thereof. The structure on the light receiving surface Id side is not limited, and may be another conventionally well-known structure.
図面の簡単な説明  Brief Description of Drawings
[0027] [図 1]本発明の裏面接合型太陽電池の一実施例を示す縦断側面図で、その要部を 部分拡大して示している。  FIG. 1 is a longitudinal side view showing an embodiment of a back junction solar cell according to the present invention, with its main part partially enlarged.
[図 2]同縮小底面図であり、その一部を切欠して示している。  [Fig. 2] A bottom view of the same, partially cut away.
[図 3]本発明の裏面接合型太陽電池の製造方法の一実施例を示す縦断側面図で、 その工程を (a)〜（c)に順次示しており、要部を部分拡大して示している。  FIG. 3 is a longitudinal side view showing an embodiment of a method for manufacturing a back junction solar cell of the present invention, the steps are sequentially shown in (a) to (c), with the main part partially enlarged. ing.
[図 4]図 3の（a)〜（c)に対応する縮小底面図である。  4 is a reduced bottom view corresponding to (a) to (c) of FIG.
符号の説明  Explanation of symbols
[0028] A 裏面接合型太陽電池 1 半導体基板  [0028] A Back junction solar cell 1 Semiconductor substrate
la 裏面 lb 凹溝  la back side lb groove
lc 基板部分 Id 受光面 p+型拡散層 2' p型不純物（ペースト）a 露出面 3 n+型拡散層lc substrate part Id light receiving surface p + type diffusion layer 2 'p type impurity (paste) a exposed surface 3 n + type diffusion layer
' n型不純物（ぺ 3a 露出面 'n-type impurities (exposed surface)
裏面電極 5 裏面電極  Back electrode 5 Back electrode
受光側拡散層 6' n型又は p型の不純物べ 反射防止膜  Light-receiving side diffusion layer 6 'n-type or p-type impurity antireflection film

Claims

請求の範囲 The scope of the claims
[1] 半導体基板 (1)の裏面（la)に、線状の P+型拡散層（2)と n+型拡散層（3)を夫々交 互に形成し、これら両拡散層（2, 3)に正負の裏面電極 (4, 5)を別々に接続する裏 面接合型太陽電池において、  [1] A linear P + diffusion layer (2) and an n + diffusion layer (3) are alternately formed on the back surface (la) of the semiconductor substrate (1), and both diffusion layers (2, 3) are formed. In the back junction solar cell where the positive and negative back electrodes (4, 5) are connected separately to
前記半導体基板 (1)の裏面（la)に、 p+型拡散層（2)と n+型拡散層（3)を互いに 接近させて同時に形成し、この半導体基板（1)の裏面（la)力も p+型拡散層（2)と n+ 型拡散層（3)の外側端部同士が接触する境界部分へ向け凹溝 (lb)を形成して、こ れら P+型拡散層（2)及び n+型拡散層（3)の外側端部同士を分離させたことを特徴と する裏面接合型太陽電池。  A p + type diffusion layer (2) and an n + type diffusion layer (3) are formed close to each other on the back surface (la) of the semiconductor substrate (1), and the back surface (la) force of the semiconductor substrate (1) is also p +. Grooves (lb) are formed toward the boundary where the outer edges of the n-type diffusion layer (2) and n + type diffusion layer (3) contact each other, and these p + type diffusion layer (2) and n + type diffusion are formed. A back junction solar cell characterized in that outer end portions of the layer (3) are separated from each other.
[2] 半導体基板 (1)の裏面（la)に、線状の p+型拡散層（2)と n+型拡散層（3)を夫々交 互に形成し、これら両拡散層（2, 3)に正負の裏面電極 (4, 5)を別々に接続する裏 面接合型太陽電池の製造方法にぉ 、て、  [2] A linear p + type diffusion layer (2) and an n + type diffusion layer (3) are alternately formed on the back surface (la) of the semiconductor substrate (1), and both diffusion layers (2, 3) are formed. In the manufacturing method of a back junction solar cell in which positive and negative back electrodes (4, 5) are separately connected to each other,
前記半導体基板 (1)の裏面（la)に p+型拡散層（2)と n+型拡散層（3)を互いに接 近させて同時に形成する工程と、この半導体基板（1)の裏面（la)力 p+型拡散層（ 2)と n+型拡散層（3)の外側端部同士が接触する境界部分へ向け凹溝 (lb)を形成 して両拡散層（2, 3)の外側端部同士を分離させる工程と、この溝形成工程により分 離した P+型拡散層（2)の露出面 (2a)と n+型拡散層（3)の露出面 (3a)に正負の裏 面電極 (4, 5)を別々に接続する工程からなることを特徴とする裏面接合型太陽電池 の製造方法。  Forming a p + type diffusion layer (2) and an n + type diffusion layer (3) in close contact with each other on the back surface (la) of the semiconductor substrate (1), and forming the back surface (la) of the semiconductor substrate (1); Force P + type diffusion layer (2) and n + type diffusion layer (3) are formed with a groove (lb) toward the boundary where the outer ends contact each other, and the outer ends of both diffusion layers (2, 3) And the exposed surface (2a) of the P + type diffusion layer (2) and the exposed surface (3a) of the n + type diffusion layer (3) separated by this groove forming step, the positive and negative back electrodes (4, 5. A method for producing a back junction solar cell, comprising the step of separately connecting 5).
[3] 前記凹溝（lb)を半導体基板（1)の裏面（la)の全長に亘つて形成し、この凹溝（lb) の上に交差させて裏面電極 (4, 5)同士を連結した請求項 2記載の裏面接合型太陽 電池の製造方法。  [3] The groove (lb) is formed over the entire length of the back surface (la) of the semiconductor substrate (1), and the back surface electrodes (4, 5) are connected to each other by crossing over the groove (lb). The method for producing a back junction solar cell according to claim 2.
PCT/JP2005/019384 2004-12-27 2005-10-21 Back junction solar cell and process for producing the same WO2006075427A1 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008071937A (en) * 2006-09-14 2008-03-27 Dainippon Printing Co Ltd Organic thin film solar cell
WO2009025147A1 (en) * 2007-08-23 2009-02-26 Sharp Kabushiki Kaisha Rear surface bonding type solar cell, rear surface bonding type solar cell having wiring board, solar cell string and soar cell module
KR101149173B1 (en) 2010-12-17 2012-05-25 현대중공업 주식회사 Back contact solar cell and method for fabricating the same
EP2161757A3 (en) * 2008-09-09 2016-02-10 Palo Alto Research Center Incorporated Interdigitated Back Contact Silicon Solar Cells with Laser Ablated Grooves

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201027766A (en) * 2008-08-27 2010-07-16 Applied Materials Inc Back contact solar cells using printed dielectric barrier
US9150966B2 (en) 2008-11-14 2015-10-06 Palo Alto Research Center Incorporated Solar cell metallization using inline electroless plating
US8962424B2 (en) 2011-03-03 2015-02-24 Palo Alto Research Center Incorporated N-type silicon solar cell with contact/protection structures
US9812592B2 (en) * 2012-12-21 2017-11-07 Sunpower Corporation Metal-foil-assisted fabrication of thin-silicon solar cell
JP5708695B2 (en) * 2013-04-12 2015-04-30 トヨタ自動車株式会社 Solar cells
US9231129B2 (en) 2014-03-28 2016-01-05 Sunpower Corporation Foil-based metallization of solar cells

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09172196A (en) * 1995-11-22 1997-06-30 Ebara Solar Inc Structure of aluminum alloy junction self-alignment rear surface electrode type silicon solar cell and its manufacture
JP2002057352A (en) * 2000-06-02 2002-02-22 Honda Motor Co Ltd Solar battery and manufacturing method
JP2003124483A (en) * 2001-10-17 2003-04-25 Toyota Motor Corp Photovoltaic element
JP2004071763A (en) * 2002-08-05 2004-03-04 Toyota Motor Corp Photovoltaic element

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09172196A (en) * 1995-11-22 1997-06-30 Ebara Solar Inc Structure of aluminum alloy junction self-alignment rear surface electrode type silicon solar cell and its manufacture
JP2002057352A (en) * 2000-06-02 2002-02-22 Honda Motor Co Ltd Solar battery and manufacturing method
JP2003124483A (en) * 2001-10-17 2003-04-25 Toyota Motor Corp Photovoltaic element
JP2004071763A (en) * 2002-08-05 2004-03-04 Toyota Motor Corp Photovoltaic element

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008071937A (en) * 2006-09-14 2008-03-27 Dainippon Printing Co Ltd Organic thin film solar cell
WO2009025147A1 (en) * 2007-08-23 2009-02-26 Sharp Kabushiki Kaisha Rear surface bonding type solar cell, rear surface bonding type solar cell having wiring board, solar cell string and soar cell module
JP5093821B2 (en) * 2007-08-23 2012-12-12 シャープ株式会社 Back junction solar cell with wiring board, solar cell string and solar cell module
EP2161757A3 (en) * 2008-09-09 2016-02-10 Palo Alto Research Center Incorporated Interdigitated Back Contact Silicon Solar Cells with Laser Ablated Grooves
KR101149173B1 (en) 2010-12-17 2012-05-25 현대중공업 주식회사 Back contact solar cell and method for fabricating the same

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