WO2006035504A1 - レイアウト適性確認装置及び方法並びにプログラム - Google Patents
レイアウト適性確認装置及び方法並びにプログラム Download PDFInfo
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- WO2006035504A1 WO2006035504A1 PCT/JP2004/014264 JP2004014264W WO2006035504A1 WO 2006035504 A1 WO2006035504 A1 WO 2006035504A1 JP 2004014264 W JP2004014264 W JP 2004014264W WO 2006035504 A1 WO2006035504 A1 WO 2006035504A1
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- layout
- suitability
- fan
- check
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Definitions
- the present invention relates to a layout suitability confirmation apparatus and layout suitability confirmation method, and a layout suitability confirmation program that determine layout suitability based on design assets for designing a semiconductor integrated circuit.
- RTL Register Transfer Level
- Patent Document 1 US Pat. No. 6,145,117
- the layout design and floor plan design data is used, and the upstream design such as logic synthesis is performed in accordance with the data. It was necessary to change the specifications on the upstream design side, such as logic synthesis conditions, each time.
- the present invention has been made to solve the above-described problems, and an object thereof is to obtain a layout suitability confirmation apparatus, method, and program capable of confirming layout suitability without depending on layout design.
- the layout suitability confirmation apparatus includes a layout suitability determination unit that inputs layout design information for layout design and outputs suitability information indicating the suitability of layout based on the information. Is.
- FIG. 1 is a configuration diagram showing a layout suitability confirmation apparatus according to Embodiment 1 of the present invention.
- FIG. 2 is an explanatory diagram when the layout suitability confirmation apparatus according to the first embodiment of the present invention is applied to layout design.
- FIG. 3 is a flowchart showing the operation of the layout suitability confirmation apparatus according to embodiment 1 of the present invention.
- FIG. 4 is an explanatory diagram when the layout suitability confirmation apparatus according to the second embodiment of the present invention is applied to layout design.
- FIG. 5 is an explanatory diagram showing twist of wiring.
- FIG. 6 is a circuit diagram of a module in which wiring twist may occur.
- FIG. 7 is a configuration diagram of a layout suitability confirmation apparatus according to Embodiment 3 of the present invention.
- FIG. 8 is a flowchart showing the operation of the layout suitability confirmation apparatus according to embodiment 3 of the present invention.
- FIG. 9 is an explanatory diagram showing layout suitability information of a layout suitability confirmation apparatus according to Embodiment 3 of the present invention.
- FIG. 10 is a configuration diagram of a layout suitability confirmation apparatus according to Embodiment 4 of the present invention.
- FIG. 11 is a flowchart showing the operation of the layout suitability confirmation apparatus according to embodiment 4 of the present invention.
- FIG. 12 is an explanatory diagram of wiring twist in the fifth embodiment of the present invention.
- FIG. 13 is an explanatory diagram of a specific example of wiring twist in the fifth embodiment of the present invention.
- FIG. 14 is a configuration diagram of a layout suitability confirmation apparatus according to Embodiment 5 of the present invention.
- FIG. 15 is a flowchart showing the operation of the layout suitability confirmation apparatus according to embodiment 5 of the present invention.
- FIG. 1 is a configuration diagram showing a layout suitability confirmation apparatus according to Embodiment 1 of the present invention.
- the layout suitability determination unit 2 inputs layout design information 3, and based on the layout design information 3, the layout indicating the suitability of the input layout It is configured to output aptitude information 4.
- the non-layer design information 3 indicates design assets for the non-layer design of the semiconductor integrated circuit.
- information on logic and circuits such as a hardware description language and a net list, and a logic synthesis execution file Includes groups, synthesis log files, timing reports, wire load models, and more.
- the layout suitability information 4 is information indicating an improper module, for example, if there is a fear that the module cannot meet the design speed!
- the layout suitability confirmation device 1 is realized by a computer, and the layout suitability judgment unit 2 is composed of software corresponding to layout suitability judgment processing and hardware such as a CPU and a memory for executing this! RU
- FIG. 2 is an explanatory diagram when the layout suitability confirmation apparatus according to the first embodiment is applied to layout design.
- RTL5 is a level description expressed by flip-flops and combinational logic circuits for designing an actual circuit, and corresponds to the layout design information 3 in FIG.
- the layout suitability determination unit 2 determines the layout suitability based on the information contained in the RTL5 description, the logic synthesis file group 10, the timing report 11, and the netlist 7, and outputs the layout suitability information 4. have.
- Information included in the logic synthesis file group 10, the timing report 11, and the netlist 7 is also information corresponding to the layout design information 3 in FIG.
- the logic synthesis tool 6 is a functional unit that converts the netlist 7 that is the level of the actual gate circuit based on the description of the RTL 5 and the logic synthesis execution file group 10.
- the logic synthesis tool 6 has a function of outputting the timing report 11.
- the netlist 7 is information representing the connection relation of the circuit in text.
- the layout tool 8 is a functional unit that arranges circuit components (cells) on a module based on the netlist 7, and the layout data 9 is an output thereof.
- the logic synthesis execution file group 10 is a group of various files indicating a synthesis script for executing logic synthesis and the restrictions for logic synthesis. Timing Report 11 shows the result of logic synthesis under any condition such as operating frequency. Information.
- the ratio of the number of ports to the number of gates of the module (PG ratio) can be considered.
- the ratio of the number of ports to the number of gates in a module is large!
- the layout of cells included in the module tends to be scattered. This is because when the number of ports is large, there are many cases where the connection modules are diversified. This trend is stronger as the number of gates in the module is smaller.
- a problem when the layout arrangement is dispersed includes speed degradation. If the arrangement is dispersed, the wiring becomes longer and the load capacity increases. If the timing of a path including a long wiring (flip-flop (hereinafter simply referred to as FF and! And signal path to FF) is critical, the desired speed may not be achieved due to the long wiring. .
- a module having a large PG ratio and a small number of gates is determined as a layout inappropriate module based on the PG ratio and the number of gates included in the netlist 7.
- the number of ports indicates the number of input / output terminals of the module.
- FIG. 3 is a flowchart showing the operation for determining the suitability for layout according to the first embodiment.
- the layout suitability determination unit 2 reads the PG ratio of the target module based on the layout design information 3. (Step ST101).
- the PG ratio is greater than or equal to the threshold in step ST102
- the number of gates is read based on the layout design information 3 (step ST103), and it is determined whether the number of gates is smaller than the predetermined threshold (step ST1 04). If the number of gates is greater than or equal to the threshold value in step ST104, the process is terminated. If the number is smaller than the threshold value, this module is determined as an inappropriate module and output to the inappropriate module list (step ST105).
- the force is determined first by the PG ratio and then by the number of gates. This order may be reversed. In addition, the determination based on the PG ratio may be sufficient for both the PG ratio and the number of gates.
- suitability information indicating the suitability of the input layout is input based on the information for layout design. Since the layout suitability determination unit that outputs is provided, the layout suitability can be confirmed without depending on the layout design.
- the layout suitability determination unit is configured to determine the layout suitability based on the ratio between the circuit scale of the module and the number of ports. Can be extracted easily and reliably.
- the layout suitability determination unit is configured to determine the layout suitability based on the ratio between the circuit scale of the module and the number of ports and the number of gates. Modules to be extracted as inappropriate modules can be further narrowed down, and inappropriate modules can be extracted more reliably.
- the layout suitability confirmation method of Embodiment 1 the step of inputting layout design information for layout design, the step of determining the suitability of layout based on the layout design information, And a step of outputting the determination result as suitability information indicating the suitability of the layout, so that a layout suitability confirmation method can be realized without depending on the layout design.
- the suitability of layout is determined based on the layout design information for layout design input to the computer. Since the step of judging and the step of outputting the judgment result as suitability information indicating the suitability of layout are executed, a device that can check layout suitability without depending on layout design is realized. Can be made.
- FIG. 4 is an explanatory diagram showing the second embodiment.
- the layout suitability determination unit 2 shown in FIG. 1 is composed of a first layout suitability determination unit 2a and a second layout suitability determination unit 2b.
- the first layout suitability determination unit 2a has a function of determining layout suitability based on the information of RTL5 before execution of logic synthesis
- the second layout suitability determination unit 2b is information after the logic synthesis is executed. It has the function of determining the suitability for layout based on the above.
- the second layout suitability determination unit 2b has a function of outputting an inappropriate module list based on the PG ratio and the number of gates.
- the layout suitability is determined based on whether the layout is suitable or not when the module determined as an inappropriate module by the first layout suitability determination unit 2a is given conditions more severe than the target condition. It has a function to do.
- the logic synthesis tool 6 is configured to give conditions that are stricter than the target conditions, and to determine layout suitability based on the timing report 11 output under these conditions.
- the clock frequency is increased will be described as an example of conditions that are stricter than the target conditions described above.
- the design condition is a clock frequency of 50 MHz
- the logic synthesis tool 6 performs logic synthesis at a clock frequency of 55 MHz, which is 10% higher, and outputs the timing report 11.
- the second layout suitability determination unit 2b lays out a module improper list indicating that the module does not meet the desired timing. Output as aptitude information 4.
- the designer changes the synthesis script so as to set, for example, a large wire load model based on the layout suitability information 4, and gives this to the logic synthesis tool 6.
- the description of RTL5 is changed as in the first embodiment.
- the case where the clock frequency is increased is described as an example of conditions that are stricter than the target conditions.
- the present invention is not limited to this.
- the temperature conditions are stricter.
- Various methods can be used, such as a large wire load model or lowering the power supply voltage.
- the layout suitability determination unit gives a condition that is stricter than the target condition
- the layout suitability is determined based on whether or not the layout has suitability. Since it is configured, it is possible to extract an inappropriate module more reliably, and accordingly, further appropriate correction can be performed.
- the layout suitability has been confirmed based on the PG ratio or the like, but the layout suitability includes, for example, wiring twist.
- FIG. 5 is an explanatory diagram showing such twisting of the wiring.
- FIG. 6 is a circuit diagram of a module in which wiring twisting may occur.
- the register array section is composed of a path for inputting a register value from an input terminal I from a programmable control circuit (not shown) such as a CPU, and a terminal J for reading out the register value.
- a programmable control circuit such as a CPU
- a terminal J for reading out the register value.
- the tournament-type tree circuit 100 of the selector (MUX) is generated.
- a module having a possibility of twisting of wiring is determined using a layout suitability confirmation apparatus as described below.
- FIG. 7 is a configuration diagram of the layout suitability confirmation apparatus according to the third embodiment.
- a layout suitability determination unit 2c is a functional unit that determines layout suitability based on layout design information 3 and outputs layout suitability information 4 as a result.
- the layout suitability determination unit 2c includes a first fan inch checking means 21, a list-up means 22, a second fan inch checking means 23, and a port extracting means 24.
- the first fan inch check means 21 is a functional unit that investigates branching by using a check reference circuit such as FF or the input side of a signal from a port.
- the list-up means 22 is a functional unit that lists up the check reference circuit that is the starting point of the signal when there is a branch exceeding the specified value.
- the second fan inch check means 23 is a functional unit that checks the fan-in on the input side with the extracted start point as the end point.
- the port extraction unit 24 has a function of extracting a port name when the start point is a port in the fan inch check by the second fan inch check means 23.
- fan inch check means such as the first fan inch check means 21 and the second fan inch check means 23 can be realized by an existing EDA tool.
- check criteria A circuit is a force that is a reference FF when performing a fan inch check. Any circuit other than a FF can be applied in the same manner as long as it is a reference circuit in such a check process.
- FIG. 8 is a flowchart showing the operation of the third embodiment.
- FIG. 9 is an explanatory diagram showing the layout suitability information 4 of the third embodiment.
- the first fan inch check means 21 extracts all FFs and output ports (step ST201).
- the first fan inch check means 21 checks the number of fan-ins for each of the extracted FF and output port (step ST202). Note that this is equivalent to extracting the data of the end point name and fan-in number fields in FIG. 9, respectively.
- list-up means 22 extracts all FFs and output ports whose fan-in number exceeds a specified value (for example, 31), and lists all FF names that are starting points (step ST203). This is equivalent to extracting the data of the starting point name field in FIG. For example, the module shown in Figure 6 is listed because the number of fan-ins from output port J is 32 (FF1—FF32).
- the port extracting means 24 When the second fan inch check means 23 traces to the fan-in side from the “starting FF” extracted in step ST203 and reaches the port instead of the FF, the port extracting means 24 The port name is extracted (step ST204). Further, the port extracting means 24 extracts the module name of the module connected to the extracted port (step ST205). These processes correspond to data extraction in the fields of “next start point name” and “connection destination module name” in FIG.
- the layout suitability determination unit 2c outputs a thread file indicating data as shown in FIG.
- this layout aptitude information 4 it is possible to describe the structure of the selector tree in a way that is conscious of the connection module, and it is possible to reduce wiring congestion.
- the layout suitability determination unit is directed to the input side of the signal from the check reference circuit or the port to investigate the branch.
- Fan-in-check means and signal when there is a branch exceeding the specified value A list-up means for listing the check reference circuit that is the starting point of the second, a second fan-in-check means that checks the fan-in on the input side with the extracted start point as the end-point, and a second fan-in-check means It is composed of a port extraction means that extracts the port name when the starting point is a port in Fan Inch, so it is possible to extract modules that may be twisted and contribute to alleviating wiring congestion can do.
- the fourth embodiment an example in which the FF is first extracted and the port may be extracted suddenly is shown as the fourth embodiment. That is, even in such a selector tree structure, the circuit on the tree is created without considering the layout arrangement. On the other hand, because ports have layout layout constraints that depend on the layout of modules, they become a cause of twisting as in the third embodiment.
- FIG. 10 is a configuration diagram of the fourth embodiment.
- the layout suitability determination unit 2d includes a fan inch check unit 25 and a list unit 26.
- the fan inch check means 25 has the same function as the first fan inch check means 21 in the third embodiment. In other words, it is a functional unit that investigates branching by force toward the input side of the signal from the check reference circuit or port such as FF.
- the list-up means 26 is a functional unit that, when there is a branch exceeding the specified value in the fan inch check, lists the port that becomes the starting point of the signal and outputs this as layout suitability information 4 .
- FIG. 11 is a flowchart showing the operation of the fourth embodiment.
- the fan inch check means 25 extracts all FFs and output ports (step ST 301).
- the fan inch check means 25 checks the fan-in number for each of the extracted FFs and output ports (step ST302). This is equivalent to extracting the data of the end point name and fan-in number fields in Fig. 9, respectively.
- the list-up means 26 extracts all FFs and output ports whose fan-in number exceeds a specified value (for example, 31), and lists all the port names that are the starting points (step S). T303). This is equivalent to extracting the data of the next starting point name field in FIG.
- the list-up means 26 extracts the module name of the module connected to the extracted port (step ST304). This process corresponds to the data extraction of the “connected module name” field in FIG.
- the layout aptitude determination unit is directed to the check reference circuit or the input side of the signal from the port to check the branch, and the specified value or more.
- the signal becomes the starting point of the signal! /
- the list-up means for listing the ports to be listed the possibility of twisting of wiring for various modules with layout layout restrictions It is possible to extract modules that have
- connection between the cells E—H and the cells A—D is 1: 1, but there may be a plurality of wiring connections between these cells. .
- FIG. 12 is an explanatory diagram showing such an example.
- FIG. 13 is a circuit diagram showing a specific example in such a case.
- the module shown in FIG. 13 is basically the same as that of FIG. 6 in the third embodiment, except that all input ports EH from the external modules are connected to the register FF.
- a module having a possibility of twisting of wiring is determined using a layout suitability confirmation apparatus as described below.
- FIG. 14 is a configuration diagram of the layout suitability confirmation apparatus according to the fifth embodiment.
- a layout suitability determination unit 2e is a functional unit that determines layout suitability based on layout design information 3 and outputs layout suitability information 4 as a result.
- This layout aptitude determination unit 2e includes a fan inch check means 27, a fan-in list-up means 28, a fan-in appearance frequency counting means 29, a fan-out check frequency means 30, a fan-out list-up means 31, a fan-out appearance frequency counting means 32, Judgment means 33 is provided.
- the fan inch check unit 27 is a functional unit that investigates a branch by using a check reference circuit such as FF or a signal input side from a port.
- the fan-in list-up means 28 is a functional unit that lists up the check reference circuit that becomes the starting point of the signal when there is a branch exceeding the specified value in the fan inch check.
- the fan-in appearance frequency counting means 29 is a function unit that counts the appearance frequency of the check reference circuit extracted as the starting point.
- the fan-out check means 30 is a functional unit that investigates a branch from the check reference circuit or port toward the output side.
- the fan-out list-up means 31 is a functional unit that lists up the check reference circuit that is the end point of the signal when there is a branch exceeding the specified level in the fan-out check.
- the fanout appearance frequency counting unit 32 is a functional unit that counts the appearance frequency of the check reference circuit extracted as the end point.
- the determination unit 33 is a functional unit that extracts a check reference circuit that exists at both the start point and the end point and has a sum of appearance frequencies of 3 or more.
- FIG. 15 is a flowchart showing the operation of the fifth embodiment.
- the fan inch check means 27 extracts all FFs and output ports, and checks the number of fan-ins for each of these FFs and output ports (step ST301).
- the fan-in list-up means 28 extracts all FFs and output ports whose fan-in number exceeds the specified value, and lists all the FF names that are the starting points (step ST302).
- the fan-in appearance frequency counting means 29 lists the number of appearances of the “starting FF” extracted in step ST302 (step ST303).
- fan-out check means 30 extracts all FFs and input ports, and checks the number of fan-outs for each of these FFs and input ports (step ST304).
- the fan-out list-up means 31 extracts all FFs and input ports whose fan-out number exceeds the specified value, and lists all the FF names that are the end points (step ST305).
- the fan-out appearance frequency counting means 32 lists the number of appearances of the “end point FF” extracted in step ST305 (step ST306).
- step ST303 and step ST306 when the appearance frequency of the FF by the fan inch check and the appearance frequency of the FF by the fan-out check are obtained, the determination means 33 FFs that appear in both the fan-in and fan-out, and the number of appearances is 3 or more are extracted and output as a twisted FF file (step ST307). It should be noted that here, it appears in both fan-in and fan-out, and the number of appearances is 3 times or more. In such a case, at least one of the FF input side and output side is 2 minutes. It is the power to become more than a cross.
- the determination condition of the determination means 33 is a force that appears in both fan-in and fan-out, and the number of appearances is three or more. Fan-in and fan It may be conditional on appearing in both outs. In other words, the number of appearances in this case is 2 or more. Even with such a configuration, it is possible to obtain a certain effect of extracting modules that may cause wiring congestion.
- the layout aptitude determination unit is directed to the check reference circuit or the input side of the signal from the port, and the fan inch check means for investigating the branch and the specified value or more Fan-in list-up means to list the check reference circuit that becomes the starting point of the signal when there is a branch, and the fan-in appearance frequency count to count the appearance frequency of the check reference circuit extracted as the start point Lists the checkout circuit, the fanout check means that checks the branch from the check reference circuit or port to the output side, and the check reference circuit that is the end point of the signal when there are more branches than specified.
- Fanout list-up means to count up, and fanout to count the appearance frequency of the check reference circuit extracted as the end point Since it consists of the current frequency counting means and the judgment means that extracts the check reference circuit that exists at both the start and end points and the sum of the appearance frequencies is 3 or more, there are multiple wiring connections between cells in the module. Even in such a case, it is possible to extract modules that may be twisted.
- the layout suitability determination unit includes a fan inch check means for investigating a branch by force toward the input side of the signal from the check reference circuit or the port, Fan-in list-up means for listing the check reference circuit that becomes the starting point of the signal when there is a branch exceeding the value, and a fan for counting the frequency of occurrence of the check reference circuit extracted as the starting point In-appearance frequency counting means and a fan-out monitor that checks branches from the check reference circuit or port toward the output side
- the checkout means, the fan-out list-up means that lists the check reference circuit that becomes the end point of the signal when there are more branches than specified, and the appearance frequency of the check reference circuit extracted as the end point Since it consists of a fanout appearance frequency counting means that counts and a judgment means that extracts check reference circuits that exist at both the start and end points, even if there are multiple wiring connections between cells in the module It is possible to extract modules that may be twisted.
- the layout suitability confirmation apparatus confirms layout suitability based on design assets such as hardware description language, netlist, and other logic and circuits in layout design of semiconductor integrated circuits. It is suitable for use in a semiconductor integrated circuit design apparatus.
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CN117852485A (zh) * | 2024-03-01 | 2024-04-09 | 芯能量集成电路(上海)有限公司 | 一种fpga布局布线方法及*** |
Citations (2)
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JP2002117089A (ja) * | 2000-10-04 | 2002-04-19 | Hitachi Ltd | 論理回路の設計方法 |
JP2003233636A (ja) * | 2002-02-06 | 2003-08-22 | Fujitsu Ltd | 回路検証装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2002117089A (ja) * | 2000-10-04 | 2002-04-19 | Hitachi Ltd | 論理回路の設計方法 |
JP2003233636A (ja) * | 2002-02-06 | 2003-08-22 | Fujitsu Ltd | 回路検証装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN117852485A (zh) * | 2024-03-01 | 2024-04-09 | 芯能量集成电路(上海)有限公司 | 一种fpga布局布线方法及*** |
CN117852485B (zh) * | 2024-03-01 | 2024-06-07 | 芯能量集成电路(上海)有限公司 | 一种fpga布局布线方法及*** |
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