WO2006001369A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2006001369A1 WO2006001369A1 PCT/JP2005/011623 JP2005011623W WO2006001369A1 WO 2006001369 A1 WO2006001369 A1 WO 2006001369A1 JP 2005011623 W JP2005011623 W JP 2005011623W WO 2006001369 A1 WO2006001369 A1 WO 2006001369A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 278
- 150000004767 nitrides Chemical class 0.000 claims description 41
- 230000005669 field effect Effects 0.000 claims description 20
- 239000000758 substrate Substances 0.000 abstract description 42
- 238000009413 insulation Methods 0.000 abstract description 9
- 239000012535 impurity Substances 0.000 description 69
- 229910052710 silicon Inorganic materials 0.000 description 43
- 229910052749 magnesium Inorganic materials 0.000 description 32
- 230000000694 effects Effects 0.000 description 31
- 239000000969 carrier Substances 0.000 description 23
- 239000013078 crystal Substances 0.000 description 22
- 239000002184 metal Substances 0.000 description 22
- 229910052751 metal Inorganic materials 0.000 description 22
- 229910052711 selenium Inorganic materials 0.000 description 22
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 22
- 229910052717 sulfur Inorganic materials 0.000 description 22
- 229910052799 carbon Inorganic materials 0.000 description 21
- 229910052719 titanium Inorganic materials 0.000 description 21
- 229910052782 aluminium Inorganic materials 0.000 description 20
- 230000001681 protective effect Effects 0.000 description 20
- 230000015556 catabolic process Effects 0.000 description 19
- 239000000203 mixture Substances 0.000 description 19
- 230000007423 decrease Effects 0.000 description 18
- 230000005684 electric field Effects 0.000 description 18
- 229910052814 silicon oxide Inorganic materials 0.000 description 18
- 229910010271 silicon carbide Inorganic materials 0.000 description 17
- 229910002704 AlGaN Inorganic materials 0.000 description 16
- 229910052735 hafnium Inorganic materials 0.000 description 16
- 239000000126 substance Substances 0.000 description 15
- 229910052715 tantalum Inorganic materials 0.000 description 15
- 238000005530 etching Methods 0.000 description 12
- 239000010931 gold Substances 0.000 description 12
- 150000002739 metals Chemical class 0.000 description 11
- 229910052594 sapphire Inorganic materials 0.000 description 10
- 239000010980 sapphire Substances 0.000 description 10
- 239000011368 organic material Substances 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 230000006911 nucleation Effects 0.000 description 7
- 238000010899 nucleation Methods 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 6
- 229910002601 GaN Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 229910052750 molybdenum Inorganic materials 0.000 description 5
- 229910052758 niobium Inorganic materials 0.000 description 5
- 229910052697 platinum Inorganic materials 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000012141 concentrate Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000002441 reversible effect Effects 0.000 description 4
- 230000037303 wrinkles Effects 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 238000013517 stratification Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- the present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of high voltage operation and capable of realizing high output.
- AlGaNZGaN HJFETs can reduce gate leakage current, increase the gate bias to be applied positively, and easily obtain large currents, which is expected to be applied to high power applications.
- a MISFET structure in which an insulating film is formed between the source and drain and a gate electrode is formed on the insulating film has been reported.
- FIG. 6 is a cross-sectional view showing the structure of a field effect transistor reported by Ajibarahan et al.
- a source electrode 10 05, TiZAlZTiZAu is stacked as the drain electrode 1006, and heat treatment is performed at 850 ° C for 1 minute.
- a gate electrode 1008 having NiZAu force is formed.
- a protective film 1009 is formed by the Si N film.
- the gate leakage current can be reduced, and the gate bias that can be applied positively can be increased, resulting in high output.
- the present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to reduce the gate leakage current and suppress the current collab, thereby enabling a high voltage operation. Another object of the present invention is to provide a semiconductor device capable of realizing high output.
- the semiconductor device of the present invention is a semiconductor device of the present invention.
- a field effect transistor comprising a group V nitride semiconductor substrate and having an insulating film between the gate electrode and the semiconductor layer
- the thickness of the insulating film provided between the gate electrode and the semiconductor layer changes in two or more steps.
- the semiconductor device of the present invention comprises:
- a field effect transistor comprising a group V nitride semiconductor substrate and having an insulating film between the gate electrode and the semiconductor layer
- a recess structure in which a part of the III-V nitride semiconductor layer or a part of the insulating film is removed is removed
- the gate electrode and the insulating film are disposed in part or all of the recess region.
- the thickness of the insulating film in the recess region is smaller than the thickness of the insulating film other than the recess region. It is a sign.
- the III-V nitride semiconductor layer includes a carrier traveling layer or a carrier supply layer that also has a III-V nitride semiconductor power,
- the recess structure is formed by removing 30% to 90% of the carrier traveling layer or the carrier supply layer that is the group III-V nitride semiconductor power.
- the recess structure is formed by removing 30% to 90% of the insulating film.
- the semiconductor device is characterized in that the gate electrode force other than the closest portion between the gate electrode and the semiconductor layer is longer on the drain electrode side than on the source electrode side.
- the insulating film between the gate electrode and the semiconductor layer has a thin part at the closest part and a thicker part, and only the closest part serves as the gate electrode, and the thicker part is the gate electrode. Since it works to alleviate the electric field concentration at the drain end, the dielectric breakdown voltage does not decrease even if the insulating film in the nearest part is thinned.
- the recess structure is used in the present invention, similarly, the electric field concentration is relaxed at the drain end of the recess, so that the breakdown voltage can be prevented from lowering. Furthermore, in nitride semiconductors, the influence of current collabs is large due to the piezo effect, but by using a recess structure, only the vicinity of the gate electrode is close to the carrier traveling layer, and other regions are separated from the carrier traveling layer. Therefore, in addition to the effect of reducing the influence of current collabs, the recess structure also has the effect of improving the gain.
- FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.
- FIG. 2 is a cross-sectional view showing a structure of a semiconductor device in a second embodiment according to the present invention.
- FIG. 3 is a sectional view showing a structure of a semiconductor device in a third embodiment according to the present invention.
- FIG. 4 is a cross-sectional view showing a structure of a semiconductor device in a fourth embodiment according to the present invention.
- FIG. 5 is a cross-sectional view showing a structure of a semiconductor device in a fifth embodiment according to the present invention.
- FIG. 6 is a cross-sectional view showing the structure of a semiconductor device in the prior art.
- the semiconductor device of the present invention may have, for example, a configuration in which the thickness of the insulating film disposed between the gate electrode and the semiconductor layer changes between at least two different film thicknesses.
- the two different film thicknesses t and t (where t> t) are expressed as 10 ⁇ 7 ⁇ ( ⁇ -t) / as the ratio of the dielectric constant ⁇ of each insulating film and the product ( ⁇ • t) with the film thickness t. ( ⁇ 't)
- the region in which the thickness of the insulating film disposed between the gate electrode and the semiconductor layer varies may include a region that continuously varies.
- the thickness t of the insulating film in the recess region is
- the ratio of ⁇ -t) is 10 ⁇ 7 ⁇ ( ⁇ -t) / ( ⁇ 't
- the recess structure is formed by removing the carrier traveling layer or carrier supply layer that also has the III-V nitride semiconductor power, the surface of the carrier traveling layer or carrier supply layer of the recess structure is usually The gate insulating film is in contact with the gate insulating film.
- FIG. 1 is a cross-sectional structure diagram showing an embodiment of the present invention.
- the field effect transistor of the present embodiment includes a buffer layer 102 that also has a first GaN-based semiconductor force, a carrier traveling layer 103 that also has a second GaN-based semiconductor force, and a carrier supply layer that also has a third GaN-based semiconductor force.
- 104 is formed. After that, the source electrode 105 and the drain electrode 106 are formed, and further the first insulating film 107 is formed. Film.
- a part of the insulating film 107 between the source electrode 105 and the drain electrode 106 and a part of the carrier supply layer 104 are removed, and the recess structure 108 is manufactured.
- a gate insulating film 109 is formed, and further, the recessed portion 108 is embedded, and the drain electrode side is longer than the source electrode side in the remaining region of the first insulating film.
- Electrode 110 is formed.
- a field effect transistor is manufactured by forming a protective film 111.
- Examples of the substrate 101 of the present embodiment include sapphire, silicon carbide, GaN, and A1N.
- the first GaN-based semiconductor 102 for example, a group III nitride semiconductor of GaN, InN, and A1N, and In Al Ga _ _ N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 There is a GaN-based semiconductor mixed crystal represented by ⁇ x + y ⁇ 1).
- a group III nitride semiconductor of GaN, InN, A1N, or In Al Ga N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 ⁇ x + y ⁇ l)
- a nucleation layer of GaN-based semiconductor mixed crystal force may be sandwiched.
- the second GaN-based semiconductor 103 for example, a group III nitride semiconductor of GaN, InN, and A1N, and In Al Ga N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x There is a GaN-based semiconductor mixed crystal represented by + y ⁇ 1). Further, it is also possible to add, for example, Si, S, Se, etc., as the n-type impurity, and Be, C, Mg, etc., as the p-type impurity, in the second GaN-based semiconductor 103. However, if the impurity concentration in the second GaN-based semiconductor 103 increases, the mobility of electrons decreases due to the effect of Coulomb scattering, so the impurity concentration is preferably 1 ⁇ 10 17 cm _3 or less.
- the third GaN-based semiconductor 104 for example, a group III nitride semiconductor of GaN, InN, and A1N, and InAlGa__N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 There is a GaN-based semiconductor mixed crystal represented by ⁇ x + y ⁇ 1).
- it is a substance or composition having an electron affinity smaller than that of the second GaN-based semiconductor 103.
- n-type impurities such as Si, S, Se, etc.
- p-type impurities such as Be, C, etc. It is also possible to add Mg and the like.
- a heterojunction is formed at the interface between the carrier traveling layer 103 that also has the second GaN-based semiconductor force and the carrier supply layer 104 that includes the third GaN-based semiconductor.
- the conduction band energy Ec of the second GaN-based semiconductor is set lower than the conduction band energy Ec of the third GaN-based semiconductor, so An embodiment in which continuous A Ec exists is preferable.
- the valence band energy Ev of the second GaN-based semiconductor is set higher than the valence band energy ⁇ of the third GaN-based semiconductor, and the band It is preferable that the discontinuity ⁇ exists.
- the first insulating film 107 there is a substance that has a force of at least one of Si, Mg, Hf, Al, Ti, and Ta, and at least one of O and N.
- the gate insulating film 109 there is a substance that has a force of 1 or more of Si, Mg, Hf, Al, Ti, and Ta and 1 or more of 0 or N.
- the protective film 111 One or more of Si, Mg, Hf, Al, Ti, and Ta, 0, N, or a material that has more than 1 force, or an organic material.
- the field-effect transistor of this example has a c-plane ((0001) plane) silicon carbide (SiC) substrate as the substrate 101, an A1N layer (thickness 200 nm) as the first GaN-based semiconductor 102, and a second GaN-based semiconductor 103.
- GaN carrier running layer film thickness 500-2000 nm
- AlGaN carrier supply layer AlGaN carrier supply layer (A1 composition ratio 0.3, film thickness 35 nm), as the source and drain electrodes
- TiZAl Ti layer film 10 ⁇ m thick, A1 layer thickness 200nm
- SiON film film thickness 80nm
- the protective film 111 Is done.
- the AlGaN carrier supply layer can be thinned by recessing only under the gate electrode, and a high gain can be obtained.
- the AlGaN layer outside the recess region is thick !, the influence of the potential fluctuation at the SiON film ZAIGaN interface is transmitted to the carrier supply layer. Nigaku current collabs can also be suppressed.
- the portion extending to the drain electrode side of the gate electrode alleviates electric field concentration at the drain end of the gate electrode, so that even a thin gate insulating film of lOnm can achieve a breakdown voltage of 200 V or more. .
- SiC is used as the substrate, but any other substrate such as sapphire can be used.
- the c-plane ((0001) plane) of the SiC substrate was used.
- the GaN-based semiconductor grows with c-axis orientation, and the piezo effect is generated in the same direction as the present embodiment. If so, it can be tilted up to about 55 ° in any desired direction. However, since it becomes difficult to obtain good crystallinity when the tilt angle becomes large, it is preferable to set the tilt within 10 ° in any direction.
- a force using a GaN layer as a carrier traveling layer includes a group III nitride semiconductor of GaN, InN, and A1N, such as an InGaN layer, and In Al Ga.
- a GaN-based semiconductor mixed crystal represented by _ _ N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 ⁇ x + y ⁇ l) can be used.
- the thickness of each layer can be set to a desired thickness.
- the lattice constant of each of the second and third layers in this example is different from the lattice constant of the first layer, it is preferable to set it to a critical film thickness or less where dislocation occurs.
- impurities are added to the GaN carrier traveling layer, but n-type impurities such as Si, S, Se, etc., p-type impurities such as Be, C, etc. It is also possible to add. However, when the impurity concentration of the carrier transit layer is increased, to decrease the mobility due to the influence of Coulomb scattering, impurity concentration 1 X 10 17 cm_ 3 or less.
- TiZAl was used as the source electrode 105 and the drain electrode 106.
- the source electrode and the drain electrode were in gold contact with AlGaN that is the carrier supply layer 104 in this example.
- metals such as W, Mo, Si, Ti, Pt, Nb, Al, and Au can be used, and a structure in which a plurality of the above metals are stacked can also be used.
- a force using NiZAu as the gate metal 110 since the gate electrode is not in direct contact with the semiconductor layer, a desired metal can be obtained. However, it is desirable not to react with the gate insulating film.
- the semiconductor thickness removed by the recess can be set to an arbitrary thickness.
- GaN series It is possible to remove to the thickness of the semiconductor.
- the semiconductor thickness to be removed is thin, the effect of improving the withstand voltage and the effect of reducing current collabs by the recess structure are reduced, and if the semiconductor thickness to be removed is thick, the resistance increases due to the decrease in carriers under the gate.
- the semiconductor thickness is preferably 30% to 90% of the originally deposited semiconductor thickness.
- a minute gap may be formed between the gate electrode and the recess side wall portion in the process of force production described as embedding the recess portion 108 with the gate electrode 110.
- the force on the source side is formed so that the gate electrode has a longer edge on the drain electrode side than on the source electrode side. Since ⁇ does not relate to the effect of the present invention, it can be equal to or longer than ⁇ on the drain electrode side. However, when the source side ridge lengthens, the gain drop due to the increase in gate capacitance increases with respect to the effect of improving the breakdown voltage and reducing current collabs. ,.
- a recess structure is formed by removing a part of the first insulating film and the carrier supply layer.
- High gain can be obtained by thinning the carrier supply layer in the recess region.
- a high breakdown voltage can be realized by reducing the concentration of the drain electric field by extending the gate electrode to the drain electrode side.
- FIG. 2 is a cross-sectional structure diagram showing an embodiment of the present invention.
- a buffer layer 202 that also has a first GaN-based semiconductor force and a carrier traveling layer 203 that also has a second GaN-based semiconductor force are formed on a substrate 201.
- a source electrode 204 and a drain electrode 205 are formed, and a first insulating film 206 is further formed.
- a part of the insulating film 206 between the source electrode 204 and the drain electrode 205 is removed so as to be tapered by isotropic etching or the like, and a part of the carrier traveling layer 203 is further removed to produce a recess structure 207. To do.
- a gate insulating film 208 is formed, a recess portion 207 is embedded, and the first A gate electrode 209 is formed in a region where the insulating film remains so that the drain electrode side is longer than the source electrode side.
- a field effect transistor is manufactured by forming a protective film 210.
- Examples of the substrate 201 of the present embodiment include sapphire, silicon carbide, GaN, and A1N.
- the first GaN-based semiconductor 202 includes, for example, group III nitride semiconductors of GaN, InN, and A1N, and In Al Ga _ _ N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 ⁇ x + There is a GaN-based semiconductor mixed crystal represented by y ⁇ l).
- a group III nitride semiconductor of GaN, InN, A1N or In Al Ga N (0 ⁇ x ⁇ l, 0 ⁇ GaN-based semiconductor mixed crystal represented by y ⁇ l, 0 ⁇ x + y ⁇ 1) 1 -xy
- the nucleation layer 211 may be sandwiched.
- the first GaN-based semiconductor 202 may be supplemented with n-type impurities such as Si, S, and Se, and p-type impurities such as Be, C, and Mg.
- the second GaN-based semiconductor 203 for example, a group III nitride semiconductor of GaN, InN, and A1N, and In Al Ga N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x There is a GaN-based semiconductor mixed crystal represented by + y ⁇ 1). It is also possible to add n-type impurities, for example, Si, S, Se, etc., and p-type impurities, for example, Be, C, Mg, etc., to the second GaN-based semiconductor 203.
- n-type impurities for example, Si, S, Se, etc.
- p-type impurities for example, Be, C, Mg, etc.
- a heterojunction is formed at the interface between the buffer layer 202 having the first GaN-based semiconductor force and the carrier traveling layer 203 made of the second GaN-based semiconductor.
- the conduction band energy Ec of the second GaN-based semiconductor is set lower than the conduction band energy Ec of the first GaN-based semiconductor, and the band discontinuity A
- Ec is present is preferable.
- the valence band energy Ev of the second GaN-based semiconductor is set to be higher than the valence band energy ⁇ ⁇ of the first GaN-based semiconductor, so It is preferable to have an aspect in which a continuous ⁇ V exists.
- the first insulating film 206 includes Si, Mg, Hf, Al, Ti, Ta !, a substance that has one or more forces and one or more of O or N.
- As the gate insulating film 208 there is a substance that has a force of 1 or more of Si, Mg, Hf, Al, Ti, and Ta and 1 or more of 0 or N.
- As the protective film 210 there is a substance that has at least one of Si, Mg, Hf, Al, Ti, and Ta, a substance that has a force of at least one of 0 and N, or an organic material.
- the field-effect transistor of this example has a c-plane ((0001) plane) silicon carbide (SiC) substrate as the substrate 201, an A1N layer (thickness lOOnm) as the nucleation layer 211, and a GaN layer as the first GaN-based semiconductor 202 (Film thickness 2000 nm), GaN carrier running layer with Si added as the second GaN-based semiconductor 203 (film thickness 100 nm, Si addition amount 1 X 10 18 cm_ 3 ), source electrode and drain electrode TiZAl (Ti Layer thickness 10nm, A1 layer thickness 200nm), first insulating film 206 as SiON film (thickness 80nm), recess as isotropic etching, dry etching using SF gas as the first insulating film Remove and BC
- 50 nm of the second GaN-based semiconductor 203 is removed by dry etching using 1 gas.
- SiON film thickness 20 nm
- NiZAu thickness 10 nm, Au thickness 200 nm
- SiON film thickness 80 nm
- the GaN carrier traveling layer can be thinned only by a recess just under the gate electrode, and a high gain can be obtained.
- the GaN carrier running layer other than the recess region is thick, it is possible to suppress current collabs in which the influence of the potential fluctuation at the SiON film ZAIGaN interface is not easily transmitted to the carrier supply layer.
- the portion extending to the drain electrode side of the gate electrode relaxes the electric field concentration at the drain end of the gate electrode, a breakdown voltage of 200 V or more can be achieved even with a thin gate insulating film of 20 nm. It was.
- SiC is used as the substrate, but any other substrate such as sapphire can be used.
- the c-plane ((0001) plane) of the SiC substrate was used.
- the GaN-based semiconductor grows with c-axis orientation, and the piezo effect is generated in the same direction as the present embodiment. If so, it can be tilted up to about 55 ° in any desired direction. However, since it becomes difficult to obtain good crystallinity when the tilt angle is increased, it is preferable to set the tilt within 10 ° in any direction.
- a force carrier running layer using a GaN layer as a carrier running layer and Such as InGaN layer, GaN, InN, A1N group III nitride semiconductors, or In Al Ga
- a GaN-based semiconductor mixed crystal represented by _ _ N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 ⁇ x + y ⁇ l) can be used.
- the thickness of each layer can be set to a desired thickness.
- 1 ⁇ 10 18 cm — 3 Si was added in the GaN carrier traveling layer, but as n-type impurities, for example, Si, S, Se, etc. as p-type impurities, For example, Be, C, etc. can be added.
- n-type impurities for example, Si, S, Se, etc.
- p-type impurities For example, Be, C, etc.
- the impurity concentration in the carrier traveling layer increases, mobility tends to decrease due to the influence of Coulomb scattering, and the breakdown voltage also tends to decrease, and when the impurity concentration in the carrier traveling layer decreases, the traveling carrier since the current density decreases less, the impurity concentration is desired to 1 X 10 17 cm_ 3 or 3 X 10 18 cm_ 3 or less U,.
- TiZAl is used as the source electrode 204 and the drain electrode 205.
- the source electrode and the drain electrode are made of a metal that is in ohmic contact with GaN, which is the carrier running layer 203 in this embodiment.
- metals such as W, Mo, Si, Ti, Pt, Nb, Al, and Au can be used, and a structure in which a plurality of the above metals are stacked can also be used.
- the semiconductor thickness removed by the recess can be set to an arbitrary thickness. It is possible to remove up to the thickness of GaN-based semiconductors. However, if the semiconductor thickness to be removed is thin, the effect of improving the withstand voltage and the effect of reducing current collabs by the recess structure are reduced, and if the semiconductor thickness to be removed is thick, the resistance increases due to the decrease in carriers under the gate.
- the semiconductor thickness is preferably 30% to 90% of the originally deposited semiconductor thickness.
- the recess portion 207 is embedded with the gate electrode 209, and a minute gap may be formed between the gate electrode and the recess side wall portion in the process of producing the force.
- the force on the source side is formed so that the gate electrode has a longer edge on the drain electrode side than on the source electrode side. Since it is not involved in the effect of the present invention, it can be equal to or longer than the ridge on the drain electrode side. However, if the source-side ridge becomes longer, it will improve the breakdown voltage and reduce current collabs. On the other hand, since the gain decrease due to the increase in gate capacitance becomes large, it is preferable that the length be shorter than that on the drain electrode side.
- a recess structure is formed by removing a part of the first insulating film and the carrier traveling layer.
- High gain can be obtained by thinning the carrier travel layer in the recess region.
- a high breakdown voltage can be realized by reducing the concentration of the drain electric field by extending the gate electrode to the drain electrode side.
- the portion where the electric field is concentrated is reversed from the embodiment in which electrons are selected as the traveling carriers, so that the gate electrode has a ridge. Also reverse the side.
- FIG. 3 is a cross-sectional structure diagram showing an embodiment of the present invention.
- the field effect transistor of the present embodiment includes a buffer layer 302 that also has a first GaN-based semiconductor power, a carrier traveling layer 303 that also has a second GaN-based semiconductor power, and a carrier supply layer that is made of a third GaN-based semiconductor. 304 is formed.
- a source electrode 305 and a drain electrode 306 are formed, and a gate insulating film 307 is further formed.
- a part of the gate insulating film 307 between the source electrode 305 and the drain electrode 306 is removed to form a groove 308 in which the gate electrode is embedded.
- the gate electrode 309 is formed so that the drain electrode side is longer than the source electrode side in a region where the groove portion 308 is buried and a part of the gate insulating film 307 is not removed.
- a field effect transistor is manufactured by forming a protective film 310.
- Examples of the substrate 301 of the present embodiment include sapphire, silicon carbide, GaN, and A1N.
- the first GaN-based semiconductor 302 for example, a group III nitride semiconductor of GaN, InN, and A1N, and In Al Ga__N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 There is a GaN-based semiconductor mixed crystal represented by ⁇ x + y ⁇ 1).
- a group III nitride semiconductor of GaN, InN, A1N or In Al Ga _ _ N (0 ⁇ x ⁇ l, 0 between the substrate 301 and the first semiconductor 302 ⁇ y ⁇ l, 0 ⁇ x + y ⁇ l)
- a stratification may be sandwiched.
- an n-type impurity in the first GaN-based semiconductor 302 for example, Be, C, Mg, etc. can be added as p-type impurities such as Si, S, Se.
- the second GaN-based semiconductor 303 for example, a group III nitride semiconductor of GaN, InN, and A1N, and InAlGa__N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 There is a GaN-based semiconductor mixed crystal represented by ⁇ x + y ⁇ 1).
- the impurity concentration in the second GaN-based semiconductor 303 increases, the mobility of electrons decreases due to the effect of Coulomb scattering, so the impurity concentration is desirably 1 ⁇ 10 17 cm _3 or less.
- the third GaN-based semiconductor 304 for example, a group III nitride semiconductor of GaN, InN, and A1N, and InAlGa__N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 There is a GaN-based semiconductor mixed crystal represented by ⁇ x + y ⁇ 1).
- the material or composition has a lower electron affinity than that of the second GaN-based semiconductor 303.
- a heterojunction is formed at the interface between the carrier traveling layer 303 having the second GaN-based semiconductor force and the carrier supply layer 304 also having the third GaN-based semiconductor force.
- the conduction band energy Ec of the second GaN-based semiconductor is made lower than the conduction band energy Ec of the third GaN-based semiconductor, and the band discontinuity A
- Ec is present is preferable.
- the valence band energy Ev of the second GaN-based semiconductor is set higher than the valence band energy ⁇ of the third GaN-based semiconductor, and the band It is preferable that the discontinuity ⁇ exists.
- the gate insulating film 307 there is a substance that has a force of Si, Mg, Hf, Al, Ti, Ta!
- the protective film 310 includes a material that has at least one of Si, Mg, Hf, A 1, Ti, and Ta and one or more of 0 and N, or an organic material.
- the field-effect transistor of this example includes a c-plane ((0001) plane) silicon carbide (SiC) substrate as the substrate 301, an A1N layer (thickness 200 nm) as the first GaN-based semiconductor 302, and a second GaN-based semiconductor 303.
- GaN carrier running layer film thickness 500-2000nm
- third GaN-based semiconductor 304 AlGaN carrier supply layer A1 composition ratio 0.3, film thickness 35nm
- source electrode 305, drain electrode 306 as TiZAl (Ti layer) 10 nm, A1 layer thickness 200 nm), SiON film (thickness 80 nm) as the gate insulating film 307, 70 nm of the gate insulating film 307 is removed as the gate electrode trench, and the gate electrode 30 9 It is manufactured by using NiZAu (Ni layer thickness 10 nm, Au layer thickness 200 nm) and SiO N film (film thickness 80 nm) as the protective film 310.
- NiZAu Ni layer thickness 10 nm, Au layer thickness 200 nm
- SiO N film film thickness 80 nm
- the insulating film can be made thin only directly under the gate electrode, and a high profit was obtained. At the same time, current gates can be reduced because the gate insulating film other than the trench is thick. In addition, in order to alleviate the electric field concentration at the drain end of the partial force gate electrode extending to the drain electrode side of the gate electrode, a breakdown voltage of 200 V or higher was achieved even with a thin gate insulating film of 10 nm.
- SiC is used as the substrate, but any other substrate such as sapphire can be used.
- the c-plane ((0001) plane) of the SiC substrate was used.
- the GaN-based semiconductor grows with c-axis orientation, and the piezo effect is generated in the same direction as the present embodiment. If so, it can be tilted up to about 55 ° in any desired direction. However, since it becomes difficult to obtain good crystallinity when the tilt angle is increased, it is preferable to set the tilt within 10 ° in any direction.
- a force using a GaN layer as a carrier traveling layer includes a group III nitride semiconductor of GaN, InN, and A1N, such as an InGaN layer, or In Al Ga
- a GaN-based semiconductor mixed crystal represented by _ _ N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 ⁇ x + y ⁇ l) can be used.
- the thickness of each layer can be set to a desired thickness.
- the lattice constant of each of the second and third layers in this example is different from the lattice constant of the first layer, it is preferable to set it to a critical film thickness or less where dislocation occurs.
- impurities may be added to the GaN carrier traveling layer, but n-type impurities such as Si, S, and Se, and p-type impurities such as Be , C, etc. Both are possible. However, when the impurity concentration of the carrier transit layer is increased, to decrease the mobility due to the influence of Coulomb scattering, impurity concentration 1 X 10 17 cm_ 3 or less.
- TiZAl is used as the source electrode 305 and the drain electrode 306.
- the source electrode and the drain electrode are in metal contact with AlGaN as the carrier supply layer 304 in this example. If so, for example, metals such as W, Mo, Si, Ti, Pt, Nb, Al, and Au can be used, and a structure in which a plurality of the above metals are stacked can also be used.
- the force using NiZAu as the gate metal 309 since the gate electrode is not in direct contact with the semiconductor, a desired metal can be obtained. However, it is desirable not to react with the gate insulating film.
- the gate insulating film thickness to be removed for forming the groove in which the gate electrode is disposed is It can be of any thickness. However, if the gate insulating film thickness to be removed is thin, the insulating film directly under the gate electrode will be thick, or the insulating film thickness other than the trench will be thin, so that high gain and current collab reduction can be realized at the same time. Since it becomes difficult, the thickness of the gate insulating film to be removed is preferably 30% to 90% of the originally formed gate insulating film thickness.
- the gate electrode and the recess are formed in the process of force production described as embedding the groove portion 308 with the gate electrode 309. A minute gap may be formed in the side wall portion.
- the force source side wrinkle formed so as to be longer from the repulsive source electrode side to the drain electrode side of the gate electrode is not involved in the effect of the present invention. It can also be equal to or longer than the heel on the side.
- the source-side ridge lengthens the gain drop due to the increase in gate capacitance increases for the effect of improving the breakdown voltage and reducing current collabs. Therefore, it is preferable that the length is shorter than that on the drain electrode side.
- a recess structure is formed by removing a part of the gate insulating film.
- High gain can be obtained by thinning the gate oxide film in the recess region and reducing the distance between the gate electrode and the carrier travel layer. Further, by extending the gate electrode to the drain electrode side, the concentration of the drain electric field is alleviated, whereby a high breakdown voltage can be realized.
- FIG. 4 is a cross-sectional structure diagram showing an embodiment of the present invention.
- the field effect transistor according to the present embodiment includes a buffer layer 402 having a first GaN-based semiconductor force, a carrier traveling layer 403 having a second GaN-based semiconductor force, and a carrier supply layer including a third GaN-based semiconductor on a substrate 401.
- 404, an etching 'stopper layer 405 made of a fourth GaN-based semiconductor and an ohmic' contact layer 406 made of a fifth GaN-based semiconductor are formed.
- a source electrode 407 and a drain electrode 408 are formed, and a first insulating film 409 is further formed. Thereafter, a part of the insulating film 409 between the source electrode 407 and the drain electrode 408 is removed in a tapered manner by isotropic etching or the like, and the ohmic contact layer 406 in the region where the insulating film 409 is opened is further removed.
- the recess structure 410 is produced.
- a gate insulating film 411 is formed, and further, the recessed portion 410 is embedded, and the drain electrode side is longer than the source electrode side in the remaining region of the first insulating film.
- a gate electrode 412 is formed. Finally, a field effect transistor is manufactured by forming a protective film 413.
- Examples of the substrate 401 in this embodiment include sapphire, silicon carbide, GaN, and A1N.
- the first GaN-based semiconductor 402 for example, a group III nitride semiconductor of GaN, InN, and A1N, and InAlGa__N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 There is a GaN-based semiconductor mixed crystal represented by ⁇ x + y ⁇ 1).
- a nucleation layer 414 made of GaN, InN, A1N, a mixture of the above three types of GaN-based semiconductors, or the like may be sandwiched between the substrate 401 and the first semiconductor 402 for forming the first semiconductor.
- the second GaN-based semiconductor 403 for example, a group III nitride semiconductor of GaN, InN, and A1N, and In Al Ga N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 ⁇ x + v ⁇ 1)
- GaN-based semiconductor mixed crystals there are GaN-based semiconductor mixed crystals.
- the impurity concentration in the second GaN-based semiconductor increases, the mobility of electrons decreases due to the effect of Coulomb scattering, so the impurity concentration is desirably 1 X 10 17 cm _3 or less.
- the third GaN-based semiconductor 404 for example, a group III nitride semiconductor of GaN, InN, and A1N, and InAlGa__N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 There is a GaN-based semiconductor mixed crystal represented by ⁇ x + y ⁇ 1).
- it is a substance or composition having a smaller electron affinity than the second GaN-based semiconductor 403.
- it is also possible to add, for example, Si, S, Se, etc. as n-type impurities and, for example, Be, C, Mg, etc. as p-type impurities into the third GaN-based semiconductor 404.
- a heterojunction is formed at the interface between the carrier traveling layer 403 having the second GaN-based semiconductor force and the carrier supply layer 404 having the third GaN-based semiconductor force.
- the conduction band energy Ec of the second GaN-based semiconductor is made lower than the conduction band energy Ec of the third GaN-based semiconductor so that the band discontinuity A
- Ec is present is preferable.
- the valence band energy Ev of the second GaN-based semiconductor is set higher than the valence band energy ⁇ of the third GaN-based semiconductor, and the band It is preferable that the discontinuity ⁇ exists.
- the fourth GaN-based semiconductor 405 for example, a group III nitride semiconductor of GaN, InN, and A1N, and InAlGa__N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 There is a GaN-based semiconductor mixed crystal represented by ⁇ x + y ⁇ 1).
- the constituent material or the composition must be different from the third and fifth GaN-based semiconductors.
- the fifth GaN-based semiconductor 406 includes, for example, a group III nitride semiconductor of GaN, InN, and A1N, and In Al Ga _ _ N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 There is a GaN-based semiconductor mixed crystal represented by ⁇ x + y ⁇ 1).
- the fourth GaN semiconductor Body 405 must be different in composition or composition.
- the first insulating film 409 there is a substance that has Si, Mg, Hf, Al, Ti, Ta !, a displacement of 1 or more, and an O or N force of 1 or more.
- the gate insulating film 411 includes a substance that has a force of 1 or more of Si, Mg, Hf, Al, Ti, and Ta and a force of 1 or more of 0 and N.
- the protective film 413 there is a substance or an organic material that has a force of 1 or more of Si, Mg, Hf, Al, Ti, and Ta and a force of 1 or more of 0 or N, or an organic material.
- the field-effect transistor of this example includes a substrate 401 as a c-plane ((0001) plane) silicon carbide (SiC) substrate, a nucleation layer 414 as an A1N layer (thickness 200 nm), and a first GaN-based semiconductor 402 as a GaN layer.
- substrate 401 as a c-plane ((0001) plane) silicon carbide (SiC) substrate
- a nucleation layer 414 as an A1N layer (thickness 200 nm)
- a first GaN-based semiconductor 402 as a GaN layer.
- Second GaN-based semiconductor 403 as InGaN carrier running layer (In composition ratio 0.15, film thickness 15 nm), third GaN-based semiconductor 404 as AlGaN carrier supply layer (A1 composition ratio 0.2) AlGaN etching / stow layer (A1 composition ratio 0.6, film thickness 5 nm) as the fourth GaN-based semiconductor 405, AlGaN ohmic contact with Si added as the fifth GaN-based semiconductor 406 Layer (A1 composition ratio 0.3, film thickness 10 nm, Si addition amount 1 X 10 19 cm “ 3 ), source electrode 407, drain electrode 408 as TiZAl (Ti layer film thickness 10 nm, A1 layer film thickness 200 nm), SiON film (thickness 80 nm) was used as the first insulating film 40 9 and SF gas was used as the recess and isotropic etching.
- AlGaN carrier supply layer AlGaN carrier supply layer
- AlGaN etching / stow layer AlG
- the first insulating film is removed by dry etching and dry using a mixed gas of BC1 and SF.
- Etching removes fifth GaN-based semiconductor 406, gate insulating film 411 as SiON film (film thickness 10 nm), gate electrode 412 as ⁇ 7 8 11 (? ⁇ Layer thickness 1011111, Au layer thickness 200 nm)
- the protective film 413 is manufactured by using a SiON film (film thickness 60 nm).
- the distance between the electrode and the carrier travel layer can be reduced by the recess only under the gate electrode, and a high gain can be obtained.
- the distance between the semiconductor surface and the carrier traveling layer is far away, so that it is possible to suppress current collabs that are difficult to transmit to the carrier supply layer due to the potential fluctuation at the SiON film ZAIGaN interface.
- the portion extending to the drain electrode side of the gate electrode alleviates electric field concentration at the drain end of the gate electrode, a breakdown voltage of 200 V or more can be realized even with a thin gate insulating film of lOnm. done.
- the recess depth was controlled by the etching and stagger layer, so that in-plane uniformity and reproducibility could be improved.
- any other substrate such as force sapphire using SiC as the substrate can be used.
- the c-plane ((0001) plane) of the SiC substrate was used.
- the GaN-based semiconductor grows in the c-axis orientation, and the piezo effect is generated in the same direction as the present embodiment. If so, it can be tilted up to about 55 ° in any desired direction. However, since it becomes difficult to obtain good crystallinity when the tilt angle is increased, it is preferable to set the tilt within 10 ° in any direction.
- an InGaN layer having an In composition ratio of 0.15 was used as a carrier transit layer.
- a group III nitride semiconductor of GaN, InN, and A1N, and In A 1 Ga N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 ⁇ x + y ⁇ 1)
- the forbidden band width of the semiconductor used for the carrier traveling layer is at least equal to or smaller than the forbidden band width of the carrier supply layer for carrier accumulation.
- each layer can be set to a desired thickness.
- the lattice constants of the second, third, fourth, and fifth layers of this example are different from the lattice constant of the first layer, it is preferable to set the critical film thickness to be less than the critical film thickness at which dislocation occurs.
- impurities are added in the InGaN carrier traveling layer, but n-type impurities such as Si, S, Se, etc., p-type impurities such as Be, C, etc. It is also possible to add.
- the impurity concentration in the carrier transit layer increases, the mobility decreases due to the influence of Coulomb scattering, so the impurity concentration is preferably 1 X 10 17 cm _3 or less.
- TiZAl was used as the source electrode 407 and the drain electrode 408.
- the source electrode and the drain electrode are made of a metal that is in ohmic contact with AlGaN that is the ohmic contact layer 406 in this example.
- metals such as W, Mo, Si, Ti, Pt, Nb, Al, and Au can be used, and a structure in which a plurality of the above metals are stacked can also be used.
- the force using NiZAu as the gate electrode 412 in the present invention, Since the gate electrode is not in direct contact with the semiconductor, a desired metal can be obtained. However, it is desirable not to react with the gate insulating film.
- a minute gap may be formed between the gate electrode and the recess side wall portion in the process of force production described as embedding the recess portion 410 with the gate electrode 412.
- the force on the source electrode side is formed so that the gate electrode side is longer from the source electrode side to the drain electrode side. Is not involved in the effect of the present invention, and can be equal to or longer than the ridge on the drain electrode side.
- the source side ridge lengthens the gain drop due to the increase in gate capacitance increases with respect to the effect of improving the breakdown voltage and reducing current collabs. ,.
- the first insulating film and the ohmic contact layer are removed to obtain a recess structure.
- High gain can be obtained by reducing the distance between the gate electrode in the recess region and the carrier transit layer.
- a high breakdown voltage can be realized by relaxing the concentration of the drain electric field by extending the gate electrode to the drain electrode side.
- FIG. 5 is a cross-sectional structure diagram showing an embodiment of the present invention.
- the field effect transistor according to the present embodiment includes a buffer layer 502 that also has a first GaN-based semiconductor force, a carrier traveling layer 503 that also has a second GaN-based semiconductor force, and a carrier supply layer that also has a third GaN-based semiconductor force. 504, an ohmic contact layer 505 having a fourth GaN-based semiconductor force is formed.
- a source electrode 506 and a drain electrode 507 are formed, and a first insulating film 508 is further formed.
- a part of the insulating film 508 and the ohmic contact layer 505 between the source electrode 506 and the drain electrode 507 are removed, and a first recess region 509 is formed.
- a second insulating film 510 is formed, and a part of the insulating film 510 in the recess region 509 is removed in a tapered manner by isotropic etching or the like, and the insulating film 509 is further opened.
- Carrier supply Layer 504 is removed to produce second recess structure 511.
- the gate insulating film 512 is formed, and the recessed portion 511 is embedded, and the region where the second insulating film 510 remains is longer on the drain electrode side than on the source electrode side.
- a gate electrode 513 is formed.
- a field effect transistor is manufactured by forming a protective film 514.
- Examples of the substrate 501 in this embodiment include sapphire, silicon carbide, GaN, and A1N.
- the first GaN-based semiconductor 502 for example, a group III nitride semiconductor of GaN, InN, and A1N, and In Al Ga _ _ N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 There is a GaN-based semiconductor mixed crystal represented by ⁇ x + y ⁇ 1).
- a group III nitride semiconductor of GaN, InN, A1N, or In Al Ga _ _ N (0 ⁇ x ⁇ l, 0 between the substrate 501 and the first semiconductor 502 ⁇ y ⁇ l, 0 ⁇ x + y ⁇ l)
- the stratification 515 may be sandwiched. Further, it is also possible to add, for example, Si, S, Se, etc. as n-type impurities, and Be, C, Mg, etc. as p-type impurities, in the first GaN-based semiconductor 502.
- the second GaN-based semiconductor 503 includes, for example, a group III nitride semiconductor of GaN, InN, and A1N, and In Al Ga N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x There is a GaN-based semiconductor mixed crystal represented by + y ⁇ 1).
- a GaN-based semiconductor mixed crystal represented by + y ⁇ 1).
- the impurity concentration in the second GaN-based semiconductor 503 increases, the mobility of electrons decreases due to the effect of Coulomb scattering, so the impurity concentration is preferably 1 ⁇ 10 17 cm _3 or less.
- the third GaN-based semiconductor 504 includes, for example, a group III nitride semiconductor of GaN, InN, and A1N, and In Al Ga _ _ N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 There is a GaN-based semiconductor mixed crystal represented by ⁇ x + y ⁇ 1).
- the material or composition has a lower electron affinity than the second GaN-based semiconductor 503.
- a heterojunction is formed at the interface between the carrier traveling layer 503 also having the second GaN-based semiconductor force and the carrier supply layer 504 also having the third GaN-based semiconductor force.
- the conduction band energy Ec of the second GaN-based semiconductor is set lower than the conduction band energy Ec of the third GaN-based semiconductor, and the band discontinuity A An embodiment in which Ec is present is preferable.
- the valence band energy Ev of the second GaN-based semiconductor is set higher than the valence band energy ⁇ of the third GaN-based semiconductor, and the band It is preferable that the discontinuity ⁇ exists.
- the fourth GaN-based semiconductor 505 includes, for example, a group III nitride semiconductor of GaN, InN, and A1N, and In Al Ga _ _ N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 There is a GaN-based semiconductor mixed crystal represented by ⁇ x + y ⁇ 1).
- the third GaN-based semiconductor 504 needs to have a different constituent material or composition.
- the first insulating film 508 and the second insulating film 510 are made of a substance that has a force of at least one of Si, Mg, Hf, Al, Ti, Ta and at least one of 0, N. is there.
- the gate insulating film 512 there is a substance composed of one or more of Si, Mg, Hf, Al, Ti, and Ta and one or more of 0 and N.
- the protective film 514 there is a substance or an organic material that has a force of 1 or more of Si, Mg, Hf, Al, Ti, and Ta and a force of 1 or more of 0 or N, or an organic material.
- the field effect transistor of this example has a c-plane ((0001) plane) silicon carbide (SiC) substrate as the substrate 501, an A1N layer (thickness 200 nm) as the nucleation layer 515, and a GaN layer as the first GaN-based semiconductor 502 (Film thickness 2000 nm), second GaN-based semiconductor 503 as InGaN carrier running layer (In composition ratio 0.15, film thickness 15 nm), third GaN-based semiconductor 504 as AlGaN carrier supply layer (A1 composition ratio 0.
- SiC silicon carbide
- GaN Omikku 'contact layer that ⁇ Ka ⁇ Si as fourth GaN-based semiconductor 505 (thickness 50Ita m, Si amount 1 X 10 19 cm “3) , a source electrode 506, drain electrode 507 as Ti / Al (Ti layer 10 nm, A1 layer thickness 200 nm), first insulating film 508 as SiON film (thickness 80 ⁇ m), first recess 509 as first insulating film by dry etching using SF gas
- the fourth GaN semiconductor is removed by dry etching using a mixed gas of BC1 and SF.
- the body 505 is removed, and the SiON film (thickness 80 nm) is used as the second insulating film 510, and the first insulating film is formed as the second recess 511 by dry etching using SF gas as the isotropic etching.
- the gate insulating film 512 is a SiON film (thickness 10 nm)
- the gate electrode 513 is Ni / Au (Ni layer thickness 10 nm, the Au layer thickness 200 nm)
- the protective film 514 is a SiON film (thickness 50 nm).
- the distance between the electrode and the carrier travel layer can be reduced by recessing only under the gate electrode, and a high gain can be obtained.
- the distance between the semiconductor surface and the carrier traveling layer is long in the region other than the recess region, it is possible to suppress current collabs in which the influence of potential fluctuation at the SiON film ZAIGaN interface is not easily transmitted to the carrier supply layer.
- the n-type ohmic contact layer added with Si and the gate electrode are not close to each other, high breakdown voltage can be achieved while maintaining low contact resistance.
- SiC is used as the substrate, but any other substrate such as sapphire can be used.
- the c-plane ((0001) plane) of the SiC substrate was used in this example, the GaN-based semiconductor grows with c-axis orientation, and the piezo effect is generated in the same direction as in this embodiment. It can be tilted up to about 55 ° in any desired direction. However, since it becomes difficult to obtain good crystallinity when the tilt angle becomes large, it is preferable to set the tilt within 10 ° in any direction.
- an InGaN layer having an In composition ratio of 0.15 was used as the carrier traveling layer.
- the carrier traveling layer a group III nitride semiconductor of GaN, InN, and A1N, and In A 1 Ga N (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 ⁇ x + y ⁇ 1)
- the forbidden band width of the semiconductor used for the carrier traveling layer is at least equal to or smaller than the forbidden band width of the carrier supply layer for carrier accumulation.
- each layer can be set to a desired thickness.
- the lattice constant of each of the second, third, and fourth layers in this example is different from the lattice constant of the first layer, it is preferable to set it to a critical film thickness or less where dislocation occurs.
- n-type impurities for example, Si, S, Se, etc.
- p-type impurities for example, Be, C, etc. It is also possible to add a supplement.
- the impurity concentration in the carrier transit layer increases, the mobility decreases due to the effect of Coulomb scattering, so the impurity concentration is preferably l x 10 17 cm _3 or less.
- the source electrode and the drain electrode are metals that are in ohmic contact with GaN that is the ohmic contact layer 505 in this example.
- metals such as W, Mo, Si, Ti, Pt, Nb, Al, and Au can be used, and a structure in which a plurality of the above metals are stacked can also be used.
- the force using NiZAu as the gate electrode 513 since the gate electrode is not in direct contact with the semiconductor, a desired metal can be obtained. However, it is desirable not to react with the gate insulating film.
- the semiconductor thickness removed by the recess can be any thickness. It is possible to remove up to the thickness of the third GaN-based semiconductor. However, if the semiconductor thickness to be removed is thin, the effect of improving the withstand voltage and the effect of reducing current collabs by the recess structure are reduced, and if the semiconductor thickness to be removed is thick, the resistance increases due to the reduction of carriers under the gate.
- the thickness is preferably 30% to 90% of the originally deposited semiconductor thickness.
- the second recess portion 511 is embedded with the gate electrode 513, but a minute gap may be formed between the gate electrode and the recess side wall portion in the manufacturing process. .
- the gate power The force formed so that the pole wrinkle is longer from the source electrode side to the drain electrode side.
- the source side wrinkle is not involved in the effect of the present invention, and can be equal to or longer than the drain electrode side wrinkle. is there.
- the gain drop due to the increase in gate capacitance increases with respect to the effect of improving the breakdown voltage and reducing current collabs. ,.
- the recess structure is obtained by removing the second insulating film and a part of the carrier supply layer.
- High gain can be obtained by thinning the carrier supply layer in the recess region.
- the concentration of the drain electric field is alleviated, so that a high breakdown voltage can be realized.
- the present invention has been specifically described above based on the embodiments, the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the scope of the invention. Needless to say.
- the first insulating film, the second insulating film, and the gate insulating film are made of a material having a force 1 or more of Si, Mg, Hf, Al, Ti, or Ta and 1 or more of 0 or N. It is explained that it is formed.
- the protective film is formed of one or more of Si, Mg, Hf, Al, Ti and Ta and one or more of 0 and N, or an organic material.
- the first insulating film, the second insulating film, the gate insulating film, and the protective film can be formed of two or more types of layers described above.
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Abstract
Description
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PCT/JP2005/011623 WO2006001369A1 (ja) | 2004-06-24 | 2005-06-24 | 半導体装置 |
Country Status (4)
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US (1) | US7859014B2 (ja) |
JP (1) | JP5084262B2 (ja) |
CN (1) | CN100508212C (ja) |
WO (1) | WO2006001369A1 (ja) |
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US7859014B2 (en) | 2010-12-28 |
US20070158692A1 (en) | 2007-07-12 |
CN101002332A (zh) | 2007-07-18 |
CN100508212C (zh) | 2009-07-01 |
JP5084262B2 (ja) | 2012-11-28 |
JPWO2006001369A1 (ja) | 2008-04-17 |
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