WO2005060000A3 - Steg-feldeffekttransistor-speicherzellen-anordnung und herstellungsverfahren - Google Patents

Steg-feldeffekttransistor-speicherzellen-anordnung und herstellungsverfahren Download PDF

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Publication number
WO2005060000A3
WO2005060000A3 PCT/DE2004/002739 DE2004002739W WO2005060000A3 WO 2005060000 A3 WO2005060000 A3 WO 2005060000A3 DE 2004002739 W DE2004002739 W DE 2004002739W WO 2005060000 A3 WO2005060000 A3 WO 2005060000A3
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WO
WIPO (PCT)
Prior art keywords
storage cell
effect transistor
bridge field
transistor storage
bridge
Prior art date
Application number
PCT/DE2004/002739
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English (en)
French (fr)
Other versions
WO2005060000A2 (de
Inventor
Johannes Kretz
Franz Kreupl
Michael Specht
Gernot Steinlesberger
Original Assignee
Infineon Technologies Ag
Johannes Kretz
Franz Kreupl
Michael Specht
Gernot Steinlesberger
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10359889A external-priority patent/DE10359889A1/de
Priority claimed from DE102004023301A external-priority patent/DE102004023301A1/de
Application filed by Infineon Technologies Ag, Johannes Kretz, Franz Kreupl, Michael Specht, Gernot Steinlesberger filed Critical Infineon Technologies Ag
Priority to JP2006544208A priority Critical patent/JP2007517386A/ja
Priority to EP04802942A priority patent/EP1704595A2/de
Publication of WO2005060000A2 publication Critical patent/WO2005060000A2/de
Publication of WO2005060000A3 publication Critical patent/WO2005060000A3/de
Priority to US11/455,907 priority patent/US20070018218A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Eine Steg-Feldeffekttransistor-Speicherzelle enthält einen ersten und einen zweiten Source-/Drain-Bereich und einen dazwischen angeordneten Kanal-Bereich, welche Source-/Drain- und Kanal-Bereiche in einem Halbleiter-Steg gebildet sind. Die Speicherzelle enthält ferner eine Ladungsspeicherschicht, die zumindest teilweise auf dem Halbleiter-Steg angeordnet ist, und einen metallisch leitfähigen Gate-Bereich auf zumindest einem Teil der Ladungsspeicherschicht, die derart eingerichtet ist, dass mittels Anlegens vorgebbarer elektrischer Potentiale an die Steg-Feldeffekttransistor-Speicherzelle in die Ladungsspeicherschicht elektrische Ladungsträger selektiv einbringbar oder daraus entfernbar sind.
PCT/DE2004/002739 2003-12-19 2004-12-14 Steg-feldeffekttransistor-speicherzellen-anordnung und herstellungsverfahren WO2005060000A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2006544208A JP2007517386A (ja) 2003-12-19 2004-12-14 ブリッジ電界効果トランジスタメモリセル、上記セルを備えるデバイス、および、ブリッジ電界効果トランジスタメモリセルの製造方法
EP04802942A EP1704595A2 (de) 2003-12-19 2004-12-14 Steg-feldeffekttransistor-speicherzellen-anordnung und herstellungsverfahren
US11/455,907 US20070018218A1 (en) 2003-12-19 2006-06-19 Fin field effect transistor memory cell, fin field effect transistor memory cell arrangement and method for producing the fin field effect transistor memory cell

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10359889A DE10359889A1 (de) 2003-12-19 2003-12-19 Steg-Feldeffekttransistor-Speicherzelle, Steg-Feldeffekttransistor-Speicherzellen-Anordnung und Verfahren zum Herstellen einer Steg-Feldeffekttransistor-Speicherzelle
DE10359889.8 2003-12-19
DE102004023301.2 2004-05-11
DE102004023301A DE102004023301A1 (de) 2004-05-11 2004-05-11 Steg-Feldeffekttransistor-Speicherzelle, Steg-Feldeffekttranistor-Speicherzellen-Anordnung und Verfahren zum Herstellen einer Steg-Feldeffekttransitor-Speicherzelle

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/455,907 Continuation US20070018218A1 (en) 2003-12-19 2006-06-19 Fin field effect transistor memory cell, fin field effect transistor memory cell arrangement and method for producing the fin field effect transistor memory cell

Publications (2)

Publication Number Publication Date
WO2005060000A2 WO2005060000A2 (de) 2005-06-30
WO2005060000A3 true WO2005060000A3 (de) 2005-10-27

Family

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PCT/DE2004/002739 WO2005060000A2 (de) 2003-12-19 2004-12-14 Steg-feldeffekttransistor-speicherzellen-anordnung und herstellungsverfahren

Country Status (5)

Country Link
US (1) US20070018218A1 (de)
EP (1) EP1704595A2 (de)
JP (1) JP2007517386A (de)
KR (1) KR20060103455A (de)
WO (1) WO2005060000A2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7439594B2 (en) * 2006-03-16 2008-10-21 Micron Technology, Inc. Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors
KR101177282B1 (ko) * 2006-03-24 2012-08-24 삼성전자주식회사 반도체 메모리 소자의 제조 방법
JP2009535800A (ja) * 2006-04-26 2009-10-01 エヌエックスピー ビー ヴィ 不揮発性メモリデバイス
US7452776B1 (en) * 2007-04-24 2008-11-18 Promos Technoloies Pte. Ltd. Integrated circuits with substrate protrusions, including (but not limited to) floating gate memories
US20080296674A1 (en) * 2007-05-30 2008-12-04 Qimonda Ag Transistor, integrated circuit and method of forming an integrated circuit
US8343189B2 (en) * 2007-09-25 2013-01-01 Zyga Technology, Inc. Method and apparatus for facet joint stabilization
US8143665B2 (en) * 2009-01-13 2012-03-27 Macronix International Co., Ltd. Memory array and method for manufacturing and operating the same
US8394125B2 (en) * 2009-07-24 2013-03-12 Zyga Technology, Inc. Systems and methods for facet joint treatment
US8212295B2 (en) * 2010-06-30 2012-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. ROM cell circuit for FinFET devices
US8900883B1 (en) 2012-03-22 2014-12-02 Iii Holdings 1, Llc Methods for manufacturing carbon ribbons for magnetic devices
CA2887215A1 (en) 2012-11-15 2014-05-22 Zyga Technology, Inc. Systems and methods for facet joint treatment
US9312183B1 (en) * 2014-11-03 2016-04-12 Globalfoundries Inc. Methods for forming FinFETS having a capping layer for reducing punch through leakage
US9911727B2 (en) 2015-03-16 2018-03-06 Taiwan Semiconductor Manufacturing Company, Ltd. Strapping structure of memory circuit
US9305974B1 (en) * 2015-04-16 2016-04-05 Stmicroelectronics, Inc. High density resistive random access memory (RRAM)
CN109791945B (zh) * 2016-09-24 2022-11-08 英特尔公司 具有共享栅的量子点阵列设备

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5045490A (en) * 1990-01-23 1991-09-03 Texas Instruments Incorporated Method of making a pleated floating gate trench EPROM
US5071782A (en) * 1990-06-28 1991-12-10 Texas Instruments Incorporated Vertical memory cell array and method of fabrication
EP0783180A1 (de) * 1996-01-08 1997-07-09 Siemens Aktiengesellschaft Elektrisch programmierbare Speicherzellenanordnung und Verfahren zu deren Herstellung
US5889304A (en) * 1996-06-28 1999-03-30 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
DE19856294A1 (de) * 1998-02-27 1999-09-09 Fraunhofer Ges Forschung Chemischer Feldeffekttransistor und Verfahren zu seiner Herstellung
US20030042531A1 (en) * 2001-09-04 2003-03-06 Lee Jong Ho Flash memory element and manufacturing method thereof
US20030119254A1 (en) * 2001-12-20 2003-06-26 Boaz Eitan Reducing secondary injection effects
WO2003096424A1 (de) * 2002-05-10 2003-11-20 Infineon Technologies Ag Nicht-flüchtiger flash-halbleiterspeicher und herstellungsverfahren

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0128063B1 (ko) * 1988-01-29 1998-04-02 엔.라이스 머레르 플로팅 게이트 메모리셀 및 디바이스 및 이들의 제조 방법
JP2851968B2 (ja) * 1991-04-26 1999-01-27 キヤノン株式会社 改良された絶縁ゲート型トランジスタを有する半導体装置及びその製造方法
JPH06163921A (ja) * 1992-11-19 1994-06-10 Nippondenso Co Ltd 不揮発性半導体記憶装置
US5411905A (en) * 1994-04-29 1995-05-02 International Business Machines Corporation Method of making trench EEPROM structure on SOI with dual channels
US6204103B1 (en) * 1998-09-18 2001-03-20 Intel Corporation Process to make complementary silicide metal gates for CMOS technology
JP4044276B2 (ja) * 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US7352024B2 (en) * 2001-02-22 2008-04-01 Sharp Kabushiki Kaisha Semiconductor storage device and semiconductor integrated circuit
US6800905B2 (en) * 2001-12-14 2004-10-05 International Business Machines Corporation Implanted asymmetric doped polysilicon gate FinFET
KR100432889B1 (ko) * 2002-04-12 2004-05-22 삼성전자주식회사 2비트 기입가능한 비휘발성 메모리 소자, 그 구동방법 및그 제조방법
US7098502B2 (en) * 2003-11-10 2006-08-29 Freescale Semiconductor, Inc. Transistor having three electrically isolated electrodes and method of formation

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5045490A (en) * 1990-01-23 1991-09-03 Texas Instruments Incorporated Method of making a pleated floating gate trench EPROM
US5071782A (en) * 1990-06-28 1991-12-10 Texas Instruments Incorporated Vertical memory cell array and method of fabrication
EP0783180A1 (de) * 1996-01-08 1997-07-09 Siemens Aktiengesellschaft Elektrisch programmierbare Speicherzellenanordnung und Verfahren zu deren Herstellung
US5889304A (en) * 1996-06-28 1999-03-30 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
DE19856294A1 (de) * 1998-02-27 1999-09-09 Fraunhofer Ges Forschung Chemischer Feldeffekttransistor und Verfahren zu seiner Herstellung
US20030042531A1 (en) * 2001-09-04 2003-03-06 Lee Jong Ho Flash memory element and manufacturing method thereof
US20030119254A1 (en) * 2001-12-20 2003-06-26 Boaz Eitan Reducing secondary injection effects
WO2003096424A1 (de) * 2002-05-10 2003-11-20 Infineon Technologies Ag Nicht-flüchtiger flash-halbleiterspeicher und herstellungsverfahren

Also Published As

Publication number Publication date
KR20060103455A (ko) 2006-09-29
US20070018218A1 (en) 2007-01-25
WO2005060000A2 (de) 2005-06-30
JP2007517386A (ja) 2007-06-28
EP1704595A2 (de) 2006-09-27

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