WO2005034512A1 - 画像投射システム及び画像投射システム用の駆動回路 - Google Patents
画像投射システム及び画像投射システム用の駆動回路 Download PDFInfo
- Publication number
- WO2005034512A1 WO2005034512A1 PCT/JP2004/013959 JP2004013959W WO2005034512A1 WO 2005034512 A1 WO2005034512 A1 WO 2005034512A1 JP 2004013959 W JP2004013959 W JP 2004013959W WO 2005034512 A1 WO2005034512 A1 WO 2005034512A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- pixel
- image
- overlapping area
- element image
- screen
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
- G03B37/00—Panoramic or wide-screen photography; Photographing extended surfaces, e.g. for surveying; Photographing internal surfaces, e.g. of pipe
- G03B37/04—Panoramic or wide-screen photography; Photographing extended surfaces, e.g. for surveying; Photographing internal surfaces, e.g. of pipe with cameras or projectors providing touching or overlapping fields of view
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
- G03B21/00—Projectors or projection-type viewers; Accessories therefor
- G03B21/13—Projectors for producing special effects at the edges of picture, e.g. blurring
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/12—Picture reproducers
- H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
- H04N9/3141—Constructional details thereof
- H04N9/3147—Multi-projection systems
Definitions
- Image projection system and drive circuit for image projection system are Image projection system and drive circuit for image projection system
- the present invention relates to an image projection system that displays an image to a user by projecting an image on a screen, and a drive circuit used in the image projection system.
- a multi-image projection system (multi-projector) that displays an image larger than an image displayed by one projection device on a screen by projecting a plurality of element images arranged on a screen is known.
- a multi-projector if there is a gap between element images or if there is a large difference in luminance between the element images, the seam becomes conspicuous and the image becomes difficult to see as a whole.
- the luminance of the overlapping area of the element images can be changed by, for example, providing a filter in each projector that projects each element image.
- this multi-projector it is necessary to change filters and the like in order to adjust or change the width of the overlapping range, which is complicated.
- the present invention is an image projection system that displays a composite image larger than one element image on a screen by projecting a plurality of element images on one screen.
- n (n n X n) element images and scales them up to the specified screen format.
- the dividing and enlarging means for outputting the n image signals composed of the divided element images and an adjusting section for adjusting the signal level of the image signals are provided by the dividing and enlarging means.
- the data processing means provided for each of them, and the n image signals whose levels have been adjusted by the data processing means are projected at the positions of the respective elemental images on one screen, and the synthesized image is formed.
- the dividing and enlarging means constituting this drive circuit generates each element image such that the peripheral portion overlaps with the adjacent element image, and each adjustment unit of the data processing means adjusts the overlapping area on the left side of the element image.
- Each pixel is multiplied by the pixel position from the left side of the pixel and the reciprocal of the number of pixels in the left overlapping area in the horizontal direction. Multiply the pixel position from the right side and the reciprocal of the number of pixels in the horizontal direction of the overlap area on the right side, and for each pixel in the overlap area on the upper side of the element image, determine the pixel position from the upper side of that pixel and the overlap area on the upper side.
- the drive circuit according to the present invention is a drive circuit in an image projection system that projects a plurality of element images on one screen to display a composite image larger than one element image on the screen.
- Dividing and enlarging means for generating an element image and outputting n image signals each having an element image power enlarged to a predetermined screen format and an adjusting unit for adjusting the signal level of the image signal are divided into Data processing means provided corresponding to each of the n image signals output from the enlarging means card, and n image signals whose levels have been adjusted by the data processing means are respectively converted to one screen.
- the dividing and enlarging means generates each element image such that a peripheral portion overlaps with an adjacent element image. Further, each adjustment unit of the data processing means multiplies each pixel of the left overlapping area of the element image by a pixel position from the left side of the pixel and the reciprocal of the number of pixels in the horizontal direction of the left overlapping area, Each pixel of the overlapping area on the right side of the element image is multiplied by the pixel position from the right side of the pixel and the reciprocal of the number of pixels in the horizontal direction of the overlapping area on the right side, and each pixel of the upper overlapping area of the element image is multiplied.
- the element is multiplied by the pixel position from the upper side of the pixel and the reciprocal of the number of pixels in the vertical direction of the upper overlapping area. And the reciprocal of the number of pixels in the vertical direction of the lower overlapping area. Further, the reciprocal multiplication is performed by a table for generating a coefficient corresponding to the overlap area width, a multiplier for multiplying the coefficient by the pixel value, and a right shift circuit for shifting the multiplication result by the right bit to the right. , And the multiplication value of the coefficient and the right shift amount is adjusted to be the reciprocal.
- the gap between the element images is eliminated by generating each element image such that the peripheral portion overlaps with the adjacent element image.
- each pixel in the overlapping area of the element image is multiplied by the reciprocal of the pixel position from the edge of the pixel and the number of pixels in the overlapping area to adjust the brightness of the pixel.
- the luminance of the overlapping area of each element image is gradually reduced in the direction toward the periphery, and the element images are smoothly connected to each other.
- each pixel in the overlapping area of the elemental image is multiplied by the pixel position of the edge force of the pixel and the reciprocal of the number of pixels in the overlapping area. , The brightness of the pixel is adjusted.
- FIG. 1 is a block diagram showing a multi-projector to which the present invention has been applied.
- FIG. 2 is a diagram for explaining an image dividing method in a multi-projector.
- FIG. 3 is a diagram for explaining an image before being divided.
- FIG. 4 is a diagram for describing an element image after division.
- FIG. 5 is a diagram for explaining an overlapping area of an element image.
- FIG. 6 is a block diagram showing an edge portion.
- FIG. 7 is a diagram for explaining a scanning order in a screen.
- FIG. 8A to FIG. 8C are diagrams showing an area specifying pulse and a counter value in an overlap area on the left end.
- FIG. 9A to FIG. 9C are diagrams showing a pulse for specifying an area and a counter value in the overlap area on the right end.
- FIG. 10 is a diagram showing a multiplication coefficient in the leftmost overlapping region when the width of the overlapping region on the left side is 64 dots.
- FIG. 11 is a diagram showing a multiplication coefficient in the rightmost overlapping region when the width of the overlapping region on the left side is 64 dots.
- FIG. 12A to FIG. 12C are diagrams showing an area specifying pulse and a counter value in an overlapping area at the upper end.
- FIGS. 13A to 13C show a pulse and a count for specifying an area in the overlapping area at the lower end.
- FIG. 14 is a diagram showing a multiplication coefficient in an upper end overlapping region when the width of the overlapping region on the upper side is 64 dots.
- FIG. 15 is a diagram showing a multiplication coefficient in a lower overlap region when the width of the overlap region on the upper side is 64 dots.
- FIG. 16 is a diagram showing an internal configuration of a horizontal processing unit and a vertical processing unit.
- FIG. 17 is a diagram showing an internal configuration of a left end operation unit, a right end operation unit, an upper end operation unit, and a lower end operation unit.
- FIG. 18 is a diagram showing coefficients when a multiplication coefficient for an overlap region in the horizontal direction and the vertical direction is obtained at the same time.
- the multi-projector is a system that displays a plurality of images projected by a plurality of projection devices side by side on one screen and displays a composite image having a size larger than usual on the screen.
- FIG. 1 shows a block diagram of a multi-projector 10 to which the present invention is applied.
- the multi-projector 10 shown in FIG. 1 includes a division unit 11 that divides an input image signal, that is, an input image signal Vin into n image signals, and performs signal adjustment on the n divided image signals.
- An adjustment unit 12 that performs the adjustment
- a projection unit 13 that projects the n image signals whose signals have been adjusted by the adjustment unit 12 onto the screen 1
- a control unit 14 that controls each unit.
- the image G displayed in each divided area is hereinafter referred to as an element image.
- the division unit 11 extracts an element image from one rectangular area, enlarges the element image into an image of a predetermined screen format (for example, SVGA, XGA, etc.), and generates one image signal.
- the dividing unit 11 performs the above extraction and Perform enlargement processing for all divided areas! ⁇ Outputs n image signals.
- the dividing unit 11 generates each element image such that an area (overlap area) that always overlaps with an adjacent element image always occurs.
- the original image 21 is divided into two in the horizontal direction and two in the vertical direction.
- the upper left element image 22 has an overlapping region 22R with the upper right element image 23 at the right end and an overlapping region 22B with the lower left element image 24 at the lower end.
- the lower right corner there is an overlapping area 22M with the upper right, lower left, and lower right element images 23, 24, and 25.
- the upper right element image 23 has an overlapping area 23L with the upper left element image 22 at the left end, an overlapping area 23B with the lower right element image 25 at the lower end, and an upper left and lower left corner at the lower left corner.
- an overlapping region 24R with the lower right element image 25 exists at the right end portion
- an overlapping region 24T with the upper left element image 22 exists at the upper end portion, and the upper right corner and the upper left corner at the upper right corner portion
- the lower right element image 25 has an overlapping area 25L with the lower left element image 24 at the left end, an overlapping area 25T with the upper right element image 23 at the upper end, and an upper left corner at the upper left corner.
- the upper right and lower left element images 22, 23 and 24 have an overlapping area 25M.
- the dividing unit 11 divides the original image so that the adjacent element images 22 to 25 overlap each other, and generates each of the element images 22 to 25.
- the number of dots in the vertical and horizontal directions is the same in all of the n divided element images.
- the width of the force overlapping area may be different in each overlapping area. For example, as shown in FIG. 3, the width X dots (length in the horizontal direction) of the overlap region in the vertical direction may be different from the width Y line (length in the vertical direction) of the overlap region in the horizontal direction.
- the control unit 14 controls the division position, the position and the width of the overlapping area, and the like.
- the adjustment unit 12 receives n image signals composed of the element image colors output from the division unit 11.
- the adjusting unit 12 includes n edge cards 15-1-15-n provided corresponding to each of the n image signals.
- Each edge processing circuit 15-1—15-n has a corresponding one of n element image signals.
- An element image signal is input.
- the edge mask circuit 15-1-15-n processes the element image so that the luminance of the overlapping area of the element image gradually decreases in the direction toward the outer periphery. .
- each element image has a different position and size of the overlapping area according to the position in the original image. For this reason, information indicating the occurrence position and size of the overlapping area of each element image is given from the control unit 14 to each edge controller 15-1-15-n, and the occurrence position and size are specified based on the information. Then, the image processing is performed.
- the detailed inside of each edge circuit 15-1-15-n will be described later.
- the projection unit 13 receives the n element image signals output from the adjustment unit 12.
- the projection unit 13 includes n projection devices 16-1-16-n provided corresponding to each of the n element image signals.
- One corresponding element image signal is input to each of the projection devices 13-1-13-n.
- Each of the projection devices 13-1-13-n emits light according to the input element image signal, projects an image on the screen 1, and displays the image on the screen 1.
- the element image projected by each of the projection devices 13-1—13-n has a different projection position on the screen 1 according to the position of the element image on the original image.
- the projection angles of the projection devices 13-1 to 13-n with respect to the screen 1 are adjusted according to the position of the element image input thereto on the original image. Therefore, when the element images are projected, all the projection devices 13-1-13-n form one composite image, and the image is displayed to the user as one image on the screen 1.
- the multi-projector 10 divides an input image to generate a plurality of element images, and projects the generated plurality of element images on one screen 1 using the projection device 13-1—13-n. I do. At this time, images to be projected from the respective projection devices 13-1-13-n are arranged on the screen 1 in the order of arrangement with respect to the original image. As a result, a larger image can be displayed on the screen 1 than when an image is displayed using only one projection device.
- the multi-projector 10 when the element images projected from the respective projection devices are displayed side by side on the screen 1, an overlapping area is formed between the element images and the overlapping area is formed.
- the caroage is applied so that the brightness gradually decreases in the direction toward the outer periphery. For this reason, in the multi-projector 10, the connection between the element images The seams can be displayed smoothly.
- the edge circuits 15-1-15-n are collectively referred to as the edge circuits 15 and will be described together.
- the scanning order of the image signal within one screen is the same as that of the normal image format. That is, the upper left pixel of the screen is set as a start point Ss, scanning is started in the horizontal direction from the start point S, horizontal scanning is performed from the left end to the right end, and horizontal scanning is performed from the upper end to the lower end. It is assumed that the scan proceeds in the opposite direction, and finally the pixel at the lower right of the screen ends at the end point Se.
- the edge processing circuit 15 includes a first path 31 that performs signal processing on an area other than the overlapping area (non-overlapping area) in the screen and a second path 31 that performs signal processing on the overlapping area in the screen.
- the first pass 31 has a gamma correction unit 34 for performing gamma correction on an input image signal.
- the second pass 32 multiplies the input image signal by a coefficient (horizontal coefficient C or C).
- HI H2 A horizontal multiplication processing unit 35 for calculating and a coefficient (vertical coefficient C or
- It has a visual correction section 37 for performing visual correction, and a gain and bright processing section 38 for performing gain and brightness processing on the image signal subjected to visual correction.
- the edge processing circuit 15 receives a predetermined one of the n element image signals divided by the division unit 11.
- the input element image signal is supplied to a first path 31 and a second path 32.
- the gamma correction unit 34 performs gamma correction processing on the input element image signal.
- the second pass 32 the input element image signal is subjected to signal processing by the horizontal and vertical multiplication processing sections 35 and 36 such that the luminance decreases as the overlapping area of the element image moves toward the outer periphery. After that, the level is adjusted by the visual correction unit 37 and the gain and brightness processing unit 38.
- selector 33 To output the image signal in the non-overlapping area, select the signal output from the first path 31.To output the image signal in the overlapping area, select the signal output from the second path 32. Then, the selected signal is output to the outside.
- the edge processing circuit 15 includes a horizontal counter 41, a left end overlapping area specifying circuit 42, a right end overlapping area specifying circuit 43, a left end coefficient counter 44, and a right end coefficient counter 45.
- the horizontal counter 41 is a counter that counts up an internal count value by one by a signal clock of an input image signal (CLK: a clock generated in a cycle of a pixel (dot) of the image signal).
- CLK a clock generated in a cycle of a pixel (dot) of the image signal.
- the internal count value is reset to 0 by the pulse (HSYNC). Therefore, the count value of the horizontal counter 41 indicates the horizontal dot position (pixel position) of the image signal currently being processed.
- the number of dots XI (width) from the left side of the overlapping area 46 (see FIG. 8A) on the left side of the screen of the element image input to the edge processing circuit 15 is set from the control unit 14 in the left end overlapping area specifying circuit 42.
- the left end overlapping area specifying circuit 42 refers to the count value of the horizontal counter 41, and if the horizontal dot position of the image signal currently being processed is within the overlapping area 46 on the left end of the screen. Generates a signal that is high, otherwise low.
- the left end overlapping area specifying circuit 42 generates a flag (left end flag) for specifying the position of the left end overlapping area 46.
- the left end overlapping area specifying circuit 42 outputs the number of dots X (width) from the left side of the overlapping area 46 on the right side of the screen. If there is no overlapping area 46 on the left end of the screen in the element image input to the edge circuit 15, the left end flag is always low and the left end width value X is set to “0”. Is set.
- the right end overlapping area specifying circuit 43 the number of dots X (width) from the right side of the overlapping area 47 (see FIG. 9A) on the right end side of the screen of the element image input to the edge processing circuit 15 is set from the control unit 14. Have been.
- the right end overlapping area specifying circuit 43 refers to the count value of the horizontal counter 41, and if the horizontal dot position of the image signal currently being processed is within the overlapping area 47 on the right end of the screen. Generates a signal that is high, otherwise low. That is, the right end overlap area specifying circuit 43 generates a flag (right end flag) for specifying the position of the right end overlap area 47.
- the right end overlapping area specifying circuit 43 is provided at the right end of the screen. The number of dots X (width) from the right side of the overlap area 47 on the side is output.
- the edge force the edge force
- the right end flag is always low, and the right end width value X is set to "0".
- the left end coefficient counter 44 is a counter that counts up the internal count value CH1 by a signal clock (CLK), and the count value CH1 is reset to 0 by a horizontal synchronization pulse (HSYNC). Further, the left end coefficient counter 44 is input as a left end flag force enable signal generated from the left end overlap region specifying circuit 42. Therefore, as shown in FIG. 10, the count value of the left end coefficient counter 44 indicates the distance (the number of dots) of the left side force of each dot in the left end overlapping area.
- the right end coefficient counter 45 is a counter that counts down the internal count value CH2 by the signal clock (CLK), and the count value C is shifted to the right end by the horizontal synchronization pulse (HSYNC).
- the right end flag generated from the end overlap area specifying circuit 43 is input as an enable signal. Therefore, as shown in FIG. 11, the count value of the right end coefficient counter 45 indicates the distance (the number of dots) of the right side force of each dot in the overlap region on the right end.
- Counter value C and left edge width value X and counter value C and right edge width value X are for horizontal
- the edge processing circuit 15 includes a vertical counter 51, an upper end overlapping area specifying circuit 52, a lower end overlapping area specifying circuit 53, an upper coefficient counter 54, and a lower coefficient counter 55.
- the vertical counter 51 is a counter that counts up the internal count value by one by a horizontal synchronization pulse (HSYNC) of an input image signal, and the internal count value is reset to 0 by a vertical synchronization pulse (VSYNC). Therefore, the count value of the vertical counter 51 indicates the vertical line position (pixel position) of the image signal currently being processed.
- the number of lines Y (width) of the upper side force of the overlapping area 56 (see FIG. 12A) on the upper end side of the screen of the element image input to the edge processing circuit 15 from the control unit 14 is set. Have been. As shown in FIG.
- the upper end overlapping area specifying circuit 52 refers to the count value of the vertical force counter 51 and determines the vertical line position of the image signal currently being processed. A high signal is generated if the signal is within the overlapping area 56 on the upper edge of the screen, and a low signal is generated otherwise. That is, the upper end overlapping area specifying circuit 52 generates a flag (upper end flag) for specifying the position of the upper end overlapping area 56. Further, the upper end overlapping area specifying circuit 52 outputs the number of lines Y (width) from the upper side of the overlapping area 56 on the upper end side of the screen. When there is no overlapping area 56 at the upper end of the screen in the element image input to the edge color circuit 15, the upper end flag is always low and the upper end width value Y is set to "0". I have.
- the lower end overlapping area specifying circuit 53 the number of lines Y (width) of the lower side of the overlapping area 57 (see FIG. 13A) on the lower end side of the screen of the element image input to the edge processing circuit 15 from the control unit 14 is set. Have been.
- the lower end overlapping area specifying circuit 53 refers to the count value of the vertical force counter 51, and if the vertical line position of the image signal currently being processed is within the overlapping area 57 on the lower end side of the screen. Generates a signal that is high, otherwise low. That is, the lower end overlapping area specifying circuit 53 generates a flag (lower end flag) for specifying the position of the lower end overlapping area 57. Further, the lower end overlapping area specifying circuit 53 outputs the number of lines Y (width) from the lower side of the overlapping area 57 on the lower end side of the screen.
- the lower end flag When there is no overlap area 57 on the lower end of the screen in the element image input to the circuit 15, the lower end flag is always low, and the lower end width value Y is set to "0".
- the upper coefficient counter 54 counts the internal count value C by the horizontal synchronization pulse (HSYNC).
- the upper end coefficient counter 54 is inputted as an upper end flag force enable signal generated from the upper end overlap region specifying circuit 52. Therefore, as shown in FIG. 14, the count value of the upper end coefficient counter 54 indicates the distance (the number of lines) of the upper side force of each line in the overlap region at the upper end!
- the lower coefficient counter 55 counts the internal count value C by the horizontal synchronization pulse (HSYNC).
- V2 This is a counter that counts down, and count value C is calculated by vertical sync panel (VSYNC).
- the lower end flag generated from the lower end overlapping area specifying circuit 53 is input as an enable signal. Therefore, as shown in FIG. 15, the count value of the lower end coefficient counter 55 indicates the distance (the number of lines) of the lower side force of each line in the overlapping area at the lower end.
- Counter value C and top width value Y and counter value C and bottom width value ⁇ are for vertical
- the horizontal multiplication processing unit 35 is configured by connecting a left end operation unit 61 and a right end operation unit 62 in series.
- the counter value C, the left end flag, and the left end width value X output from the left end coefficient counter 44 are input to the left end operation unit 61. Also, the rightmost operation
- the vertical multiplication unit 36 is configured by connecting an upper end operation unit 63 and a lower end operation unit 64 in series.
- the counter value C, the upper end flag, and the upper end width value Y output from the upper end coefficient counter 54 are input to the upper end operation unit 63. Also, the lower end operation
- the left end operation unit 61, the right end operation unit 62, the upper end operation unit 63, and the lower end operation unit 64 all have the same configuration. Specifically, as shown in FIG. 17, a switching switch 65, a multiplier 66, And a divider 67.
- the pixel value of the preceding stage color element image signal is input to the switching switch 65 for each dot.
- the switch 65 is switched according to a flag (left end flag, right end flag, upper end flag or lower end flag).
- the switch 65 supplies the input pixel value to the multiplier 66 when the flag is high, and outputs the input pixel value to the outside without any processing when the flag is low.
- the multiplier 66 calculates the counter value C (the leftmost counter value C, the rightmost counter value C,
- the multiplier 66 multiplies the counter value by the pixel value and outputs a weighted pixel value X.
- the weighted pixel value X is supplied to the divider 67.
- the divider 67 receives the weighted pixel value X output from the multiplier 66 and the width value (left end width value X, right end width value X, upper end width value Y or lower end width value Y). Divider 67 is weighted
- the divider 67 includes a table 68 for generating the multiplication coefficient C and a multiplication coefficient C A multiplication circuit 69 for multiplying the pixel value X by the spotting pixel value, and a right bit shift circuit 70 for right bit shifting the multiplication result by the multiplication circuit 69 by the shift amount S.
- Table 68 shows the entered width values (left edge width value X, right edge width value X, top edge width value Y or
- the right bit shift circuit 70 is a circuit that performs division processing in powers of two units. In other words, the input value is set to "1Z2" when shifting right by 1 bit, the input value is set to "1Z4" when shifting right by 2 bits, and the input value is shifted when shifting right by 3 bits This is a circuit that is set to "1Z8" and the input value is set to "1Z256" when shifted right by 8 bits.
- the table 68 stores the optimum coefficient C so that the output result is “1Z width value” in accordance with the right shift amount S. That is, the right bit shift circuit 70 can perform only in powers of two units. Therefore, in the divider 67, the coefficient C is generated from the table 68, and the pixel value is multiplied by the coefficient C by the multiplier 69, so that the “1Z width value” is obtained by multiplying the coefficient C and the right shift amount S. Processing similar to that of.
- the overlap area is 3 dots or 3 lines.
- the following coefficient C is realized in order to set the input value to 1Z3.
- the horizontal multiplication processing unit 35 multiplies the count value C of the left end coefficient counter 44 by the reciprocal of the left end width 1ZX ( The input image signal is multiplied by the horizontal coefficient CH). Further, when the left end flag is low, that is, when the left end is outside the overlapping area, the horizontal multiplication processing unit 35 outputs the input image signal without performing any processing.
- the horizontal coefficient CH linearly increases with the distance of the left side force for pixels in the leftmost overlapping region, and remains constant at 1 for the other pixels. Function. Therefore, the horizontal multiplication processing unit 35 can gradually decrease the luminance of the overlapping area of each element image in the direction toward the periphery with respect to the leftmost overlapping area, and the element adjacent to the left The seam with the image can be smoothed.
- the processing unit 35 When the right end flag is low, that is, when the right end flag is outside the overlapping area, the processing unit 35 outputs the input image signal without any processing. That is, as shown in FIG. 9C, the horizontal coefficient CH linearly increases with the distance from the right side for pixels in the rightmost overlapping region, and remains constant at 1 for other pixels. Function. Therefore, the horizontal multiplication processing unit 35 can gradually reduce the luminance of the overlapping area of each element image in the direction toward the periphery with respect to the overlapping area at the right end, and can reduce the luminance of the overlapping area on the right side. The seam with the raw image can be smoothed.
- the vertical multiplication processing unit 36 calculates a value (vertical coefficient CV) obtained by multiplying the count value CV1 of the upper end coefficient counter 54 by the reciprocal of the upper end width 1ZY (vertical coefficient CV) in the case of the upper end flag, i.e., in the case of the upper end overlap area. , And the input image signal.
- the vertical multiplication processing unit 36 outputs the input image signal without performing any processing. That is, as shown in Fig. 12C, the vertical coefficient CV increases linearly with the distance from the upper side for the pixels in the upper overlap region, and remains 1 for the other pixels. It is a constant function!
- the vertical multiplication processing unit 36 can gradually reduce the luminance of the overlapping region of each element image in the direction toward the periphery with respect to the overlapping region at the upper end, and the luminance of the overlapping region with the element image adjacent to the upper side can be reduced.
- the seam can be smoothed.
- the vertical multiplication processing unit 36 when the lower end flag is “1”, that is, in the overlapping area at the lower end, the count value CV2 of the lower end coefficient counter 55 and the reciprocal of the lower end width 1ZY
- the value obtained by multiplying by 2 (vertical coefficient CV) is multiplied to the input image signal.
- the vertical multiplication processing unit 36 outputs the input image signal without performing any processing.
- the vertical coefficient CV increases linearly with the distance from the lower side for the pixels in the overlap region at the lower end, and remains constant at 1 for the other pixels. Be a function! Therefore, the vertical multiplication processing unit 36 can gradually decrease the luminance of the overlapping area of each element image in the direction toward the periphery with respect to the overlapping area at the lower end, and reduce the luminance of the overlapping area with the element image adjacent to the lower side. Seams can be smoothed.
- the edge processing circuit 15 divides the overlapping region of the element image into the horizontal direction and the vertical direction, and multiplies the overlapping region in the horizontal direction by using the horizontal counter 41 indicating the pixel position in the horizontal direction.
- the coefficient is obtained, and a coefficient for multiplying the vertical overlapping area is obtained using a vertical counter 51 indicating the pixel position in the vertical direction. Therefore, the corner portion Cc where the horizontal overlap region and the vertical overlap region overlap as shown in FIG. 18 can be obtained simply by multiplying the horizontal coefficient and the vertical coefficient. Processing can be performed for all areas.
- the enable signal is generated from the left end overlapping region specifying circuit 42, the right end overlapping region specifying circuit 43, the upper end overlapping region specifying circuit 52 and the upper end overlapping region specifying circuit 53, and the coefficient counter is generated only in the overlapping region.
- the counter values of 44, 45, 54 and 55 are operated, and the width of the overlap area (X, X, Y, Y)
- the visual correction is performed by the visual correction unit 37 after multiplying the overlap area of the element image by the coefficient. Even if the luminance level is changed linearly by multiplying the overlapping area of the element image by a coefficient, the change in the amount of light perceived by the human eye is not linear. For this reason, the visual correction unit 37 adjusts the brightness using a look-up table that indicates the brightness at which the human eye perceives the amount of light linearly with respect to the input brightness. ing.
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Projection Apparatus (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Controls And Circuits For Display Device (AREA)
- Transforming Electric Information Into Light Information (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003-347444 | 2003-10-06 | ||
JP2003347444A JP2005117266A (ja) | 2003-10-06 | 2003-10-06 | 画像投写システムの駆動回路 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005034512A1 true WO2005034512A1 (ja) | 2005-04-14 |
Family
ID=34419582
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/013959 WO2005034512A1 (ja) | 2003-10-06 | 2004-09-24 | 画像投射システム及び画像投射システム用の駆動回路 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2005117266A (ja) |
WO (1) | WO2005034512A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8727538B2 (en) | 2009-11-27 | 2014-05-20 | Canon Kabushiki Kaisha | Image processing apparatus and image processing method |
CN109285116A (zh) * | 2018-08-21 | 2019-01-29 | 成都市极米科技有限公司 | 投影无缝拼接融合方法、投影设备及投影*** |
CN114584747A (zh) * | 2022-03-04 | 2022-06-03 | 大连海事大学 | 一种360°环幕无缝投影软矫正方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4760288B2 (ja) | 2005-10-13 | 2011-08-31 | ソニー株式会社 | 画像表示システム、表示装置、画像再合成装置、画像再合成方法及びプログラム |
JP5169406B2 (ja) * | 2008-04-09 | 2013-03-27 | セイコーエプソン株式会社 | 演算処理装置及びそれを用いた画像表示装置、並びに演算処理方法 |
CN102508397A (zh) * | 2011-10-27 | 2012-06-20 | 王悦 | 一种图像比边缘融合投影方法 |
JP6300444B2 (ja) | 2013-02-12 | 2018-03-28 | キヤノン株式会社 | 画像処理装置、画像処理方法およびプログラム |
KR102529828B1 (ko) | 2016-10-31 | 2023-05-08 | 엘지디스플레이 주식회사 | 표시장치 및 다면 표시장치 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62195984A (ja) * | 1986-02-24 | 1987-08-29 | Sony Corp | プロジエクタ |
JPH0385879A (ja) * | 1989-08-29 | 1991-04-11 | Seiko Epson Corp | 投射型表示装置 |
JP2003067182A (ja) * | 2001-08-28 | 2003-03-07 | Matsushita Electric Works Ltd | 演算装置および演算方法 |
-
2003
- 2003-10-06 JP JP2003347444A patent/JP2005117266A/ja not_active Withdrawn
-
2004
- 2004-09-24 WO PCT/JP2004/013959 patent/WO2005034512A1/ja active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62195984A (ja) * | 1986-02-24 | 1987-08-29 | Sony Corp | プロジエクタ |
JPH0385879A (ja) * | 1989-08-29 | 1991-04-11 | Seiko Epson Corp | 投射型表示装置 |
JP2003067182A (ja) * | 2001-08-28 | 2003-03-07 | Matsushita Electric Works Ltd | 演算装置および演算方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8727538B2 (en) | 2009-11-27 | 2014-05-20 | Canon Kabushiki Kaisha | Image processing apparatus and image processing method |
CN109285116A (zh) * | 2018-08-21 | 2019-01-29 | 成都市极米科技有限公司 | 投影无缝拼接融合方法、投影设备及投影*** |
CN114584747A (zh) * | 2022-03-04 | 2022-06-03 | 大连海事大学 | 一种360°环幕无缝投影软矫正方法 |
CN114584747B (zh) * | 2022-03-04 | 2023-10-31 | 大连海事大学 | 一种360°环幕无缝投影软矫正方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2005117266A (ja) | 2005-04-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI486936B (zh) | 使用於一顯示裝置之時序控制器及其相關方法 | |
TWI430009B (zh) | 投影機、影像顯示裝置、及影像處理裝置 | |
US7667415B2 (en) | Backlight control device and display apparatus | |
JP4470824B2 (ja) | 残像補償表示 | |
JP2006184896A (ja) | 画像表示方法及び装置、並びにプロジェクタ | |
JP2006259403A (ja) | 画像処理装置、画像表示装置、画像処理方法、その方法をコンピュータに実行させるプログラム、および記録媒体 | |
US7489323B2 (en) | Display apparatus adapted for a display wall, image adjustment method therefor and display wall therewith | |
US7123273B2 (en) | Overlay of plural images | |
JP2003069961A (ja) | フレームレートの変換 | |
US6507346B1 (en) | Image processing method and image display | |
JPH09244611A (ja) | 映像信号の処理装置及びこれを用いた表示装置 | |
WO2005034512A1 (ja) | 画像投射システム及び画像投射システム用の駆動回路 | |
JP4956980B2 (ja) | 画像表示方法及び装置、並びにプロジェクタ | |
US20060176311A1 (en) | Image display device and image display method | |
TWI545540B (zh) | 拼接屏顯示裝置以及其顯示驅動方法 | |
JP2006033672A (ja) | 曲面マルチスクリーン投射方法及び曲面マルチスクリーン投射装置 | |
JP6635748B2 (ja) | 表示装置、表示装置の制御方法及びプログラム | |
JP2002006795A (ja) | カラー表示装置 | |
EP0840275A2 (en) | Luminance correction circuit and video display monitor thereof | |
JP2000165908A (ja) | カラリメトリ変換装置 | |
US8928689B2 (en) | Pixel data conversion apparatus and method for display with delta panel arrangement | |
JP5207832B2 (ja) | 表示装置 | |
EP1331815A2 (en) | Projection-type display device having distortion correcting function | |
JP2000023180A (ja) | コンバージェンス調整方法、信号発生装置および投写型表示装置 | |
JP4165590B2 (ja) | 画像データ処理装置、画像表示装置、駆動画像データ生成方法、およびコンピュータプログラム |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
122 | Ep: pct application non-entry in european phase |