WO2004077447A1 - フラッシュメモリ及びメモリ制御方法 - Google Patents
フラッシュメモリ及びメモリ制御方法 Download PDFInfo
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- WO2004077447A1 WO2004077447A1 PCT/JP2003/002404 JP0302404W WO2004077447A1 WO 2004077447 A1 WO2004077447 A1 WO 2004077447A1 JP 0302404 W JP0302404 W JP 0302404W WO 2004077447 A1 WO2004077447 A1 WO 2004077447A1
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- WIPO (PCT)
- Prior art keywords
- flash memory
- ratio
- data
- state
- notification information
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
Definitions
- the present invention relates to a flash memory and a memory control method for controlling the operation of the flash memory. More particularly, the present invention relates to a memory cell array including a plurality of user areas for storing data and a plurality of flag areas indicating a state of a user area. The present invention relates to a flash memory and a memory control method for controlling such a flash memory. Background art
- Flash memory is electrically erasable (rewritable) non-volatile memory, and is mounted on various electronic products.
- FRAM Ferroelectric Random Access Memory
- MRAM Magnetoresistive Random Access Memory
- UM Ovonics Unified Memory
- flash memory is still dominant in terms of cost, especially for camera-equipped mobile phones and digital cameras.
- FIG. 18 is a flowchart showing the flow of processing when rewriting data using a conventional flash memory.
- the following processing is performed under the control of a central processing unit (CPU) installed outside the flash memory.
- CPU central processing unit
- This problem can be solved by executing the flash memory data rewriting process and the garbage collection process at different timings. For that purpose, it is necessary to obtain the timing to execute the garbage collection process.
- Patent Document 1
- the present invention has been made in view of such a point, and an object of the present invention is to provide a flash memory capable of notifying an external device of an evening which erases unnecessary data such as a garbage collection. .
- a flash area 10 having a memory cell array 11 composed of fn. f2, f3,... ⁇ Refers to fn to generate the status notification information for notifying the information corresponding to the status of the user regions ul, u2, u3,..., un to the outside.
- Notification information A flash memory 10 characterized by having a report generation unit 12 and an output unit 13 for outputting status notification information is provided.
- the status notification information generation unit 12 refers to the flag areas f1, f2, f3,..., Fn, and refers to the user areas u1 u2, u3, '
- the output unit 13 generates status notification information for notifying the information corresponding to the statuses of the flash memory and the external device to the outside, and the output unit 13 outputs the status notification information to the outside, thereby externally storing the flash memory 10 in the flash memory 10. Notify the status.
- FIG. 1 is a principle configuration diagram for explaining the principle of the flash memory of the present invention.
- FIG. 2 is a configuration diagram showing a flash memory according to the first embodiment of the present invention and circuits arranged outside the flash memory.
- FIG. 3 is a timing chart when writing data to the flash memory.
- Figure 4 shows a timing chart for invalidating (or deleting) data in the flash memory.
- FIG. 5 is a timing chart when an interrupt signal is output to the outside.
- FIG. 6 is a timing chart when the ratio is rewritten.
- FIG. 7 is a flowchart showing a processing flow when rewriting data in the flash memory.
- FIG. 8 is a flowchart showing a flow of processing at the time of a write operation.
- FIG. 9 is a flowchart showing the invalidation processing.
- FIG. 10 is a flowchart showing the flow of a process for erasing data.
- FIG. 11 is a flowchart showing the flow of processing in the flash memory when an interrupt signal is output.
- FIG. 12 is a flowchart showing the flow of the garbage collection process.
- FIG. 13 shows the flash memory according to the second embodiment of the present invention and the external arrangement thereof.
- 1 is a configuration diagram showing a circuit to be performed.
- FIG. 14 is a timing chart when the ratio is output after the writing process.
- FIG. 15 is a timing chart when the ratio is output after the invalidation processing.
- C FIG. 16 is a flowchart showing a processing flow in the configuration of the second embodiment.
- FIG. 17 is a timing chart when the ratio is output according to the ratio command.
- FIG. 18 is a flowchart showing the flow of processing when rewriting data using a conventional flash memory.
- FIG. 1 is a principle configuration diagram for explaining the principle of the flash memory of the present invention.
- the flash memory 10 has a plurality of user areas u1, u2, u3,..., Un in which data is stored, and a plurality of flag areas indicating states of the user areas ul, u2, u3,.
- the memory cell array 11 composed of f1, f2, f3,..., fn, and the flag regions fl, f2, f3,..., fn
- the user regions u1, u2, u3 ,..., And un comprise a status notification information generating unit 12 for generating status notification information for notifying the information to the outside, and an output unit 13 for outputting the status notification information.
- the flag area ⁇ y corresponding to the user area ux has a value indicating validity, and when the data is invalidated, the flag area fy has a value indicating nullity. It becomes.
- the state notification information generation unit 12 refers to the value of the flag area ⁇ y, and notifies the external according to the information corresponding to the state of the user area ux corresponding thereto, for example, the user area uX is invalid. Is Generate a ratio (see below for details). After that, the output unit 13 outputs the status notification information to the outside of the flash memory 10.
- a control unit such as a CPU disposed outside the flash memory 10 for performing garbage collection is in a state within the flash memory (such as a ratio of the user area ux in an invalid state). Can be easily known, and it can be determined whether or not garbage collection processing is currently required.
- FIG. 2 is a configuration diagram showing a flash memory according to the first embodiment of the present invention and circuits arranged outside the flash memory.
- the flash memory 20 includes a memory cell array 21, a ratio storage unit 22, a comparison unit 23, a time management unit 24, and a control unit 25.
- the memory cell array 21 includes a plurality of user areas ux and a plurality of flag areas fy as shown in FIG.
- the flag area i y has two bits of information for each user area u x. When the flag area f y is “0 0”, it indicates that the data of the user area ux corresponding to the flag area f y has been deleted. If the flag area ⁇ y is “01”, it indicates that the data of the user area u X corresponding to the flag area f y is valid.
- the flag area f y When the flag area f y is “1 1”, it indicates that the data of the user area u X corresponding to the flag area f y is invalid. In the memory cell array 21 of the flash memory 20 before use, data has not been written to the entire area of the user area uX. Further, a value “0 0” indicating that data has been erased is written in the entire area of the flag area f y of the memory cell array 21.
- the ratio storage unit 22 stores a predetermined ratio in advance. For example, "80%" is stored.
- the comparison unit 23 determines the state of the flag area fy of the memory cell array 21, calculates the ratio at which the user area ux is invalid, and then calculates the ratio stored in the ratio storage unit 22. Compare with
- the time management unit 24 sends a signal to the control unit 25 at certain time intervals, for example, at intervals of 60 seconds.
- the control unit 25 controls each unit of the flash memory 20, and transmits and receives information to and from the outside.
- the control unit 25 is connected to the CPU 50 by an interrupt signal line 101 and a control signal line 102. Furthermore, it is connected to the data bus 60 and the address bus 70.
- the CPU 50 is connected to a data bus 60 and an address bus 70, and the data path is connected to an address bus 70 via a RAM (Random Access Memory) 80.
- the CPU 50 reads and writes data in the flash memory 20 and the RAM 80 using the data bus 60 and the address path 70, and executes a program written in the RAM 80.
- the function of the state notification information generation unit 12 in FIG. 1 is included in the comparison unit 23, and the function of the output unit 13 is included in the control unit 25.
- FIG. 3 is a timing chart when writing data to the flash memory.
- FIG. 3 shows the state of signals on an address bus 70, a control signal line 102, an interrupt signal line 101, and a data bus 60 in a data write process.
- the CPU 50 When writing the data written in the RAM 80 to the flash memory 20, the CPU 50 sets the signal level of the control signal line 102 to “H” (high level) and simultaneously writes the data via the data bus 60. The command is sent to the control unit 25. After that, the control signal line 102 is returned to "L” (low level). Further, the CPU 50 sends the data read from the RAM 80 via the data bus 60 to the control unit 25. Further, the CPU 50 sends the write destination address to the control unit 25 via the address bus 70.
- the control unit 25 of the flash memory 20 receives a data write command from the data bus 60 when the control signal line 102 becomes "H" as shown in FIG. Next, data is received from the data path 60, an address is received from the address bus 70, and the data is written to the user area uX of the memory cell array 21 specified by the address. No. Further, the control unit 25 writes a value “01” indicating that the data is valid to the flag area fy corresponding to the user area uX.
- Figure 4 is an evening chart when invalidating (or deleting) flash memory data.
- the figure shows the state of the signals on the address bus 70, the control signal line 102, the interrupt signal line 101, and the data bus 60 at the time of invalidating (or deleting) data.
- the CPU 50 sets the control signal line 102 to "H” and simultaneously transfers the data via the data bus 60.
- the instruction to invalidate is sent to the control unit 25 of the flash memory 20. After that, the control signal line 102 is returned to "L”. Further, the CPU 50 sends the address of the data to be invalidated to the control unit 25 via the address bus 70.
- the control unit 25 of the flash memory 20 receives an invalidation (or deletion) instruction from the data bus 60 when the control signal line 102 becomes "H" as shown in FIG. Next, a value “1 1” indicating that data is invalid is written to the flag area f y corresponding to the user area ux of the memory cell array 21 specified by the address received from the address bus 70. In the case of data deletion, the data in the user area ux of the memory cell array 21 specified by the received address is deleted, and the flag area corresponding to the deleted user area uX and the data in fy are deleted. Write the value "0 0" indicating that the
- the time management unit 24 sends a signal to the control unit 25 at a certain time interval, for example, at an interval of 60 seconds.
- the control unit 25 that has received the signal from the time management unit 24 reads the data in the flag area fy, and sends the read data to the comparison unit 23.
- the comparing section 23 Upon receiving the data of the flag area fy, the comparing section 23 counts the number of data indicating that the data is invalid, and calculates the ratio of invalid data in the user area uX. Further, the comparison unit 23 compares the ratio stored in the ratio storage unit 22 in advance with, for example, “80%”. As a result of the comparison, the ratio at which the data in the user area ux is invalid is smaller than the ratio stored in the ratio storage unit 22 in advance. If it is also large, a signal is sent to the control unit 25.
- the control unit 25 that has received the signal from the comparison unit 23 transmits the interrupt signal to the CPU 50 using the interrupt signal line 101.
- FIG. 5 is a timing chart when an interrupt signal is output to the outside.
- the figure shows the state of signals on the address bus 70, the control signal line 102, the interrupt signal line 101, and the data bus 60 when outputting an interrupt signal.
- This interrupt signal is a signal that notifies the outside that the flash memory 20 needs garbage collection processing.
- the CPU 50 Upon receiving the interrupt signal, the CPU 50 executes a garbage collection program stored in the RAM 80. As a result, unnecessary data in the flash memory 20 is erased, and garbage collection for increasing free space is executed.
- FIG. 6 is a timing chart when the ratio is rewritten.
- the figure shows the state of signals on the address bus 70, the control signal line 102, the interrupt signal line 101, and the data path 60 in the process of rewriting the ratio.
- the CPU 50 When rewriting the ratio stored in the ratio storage unit 22 of the flash memory 20, the CPU 50 first sets the control signal line 102 to “H” as shown in FIG. A ratio storing instruction is transmitted to the control unit 25 of the flash memory 20 via the bus 60. After that, the control signal line 102 is returned to "L”. Next, the data of the rewriting ratio stored in the RAM 80, for example, is transmitted to the control unit 25 via the data path 60.
- control unit 25 When the control signal line 102 becomes “H”, the control unit 25 receives the ratio storing instruction from the data bus 60, and then receives the data of the rewriting ratio from the data path 60. The control unit 25 sends the received data of the rewriting ratio to the ratio storage unit 22, and the ratio storage unit 22 stores the received ratio data.
- FIG. 7 is a flowchart showing a processing flow when rewriting data in the flash memory.
- the CPU 50 determines whether the data processing to be executed is data writing processing or data invalidation processing. The process proceeds to step S11 in the case of the writing process of the night, and proceeds to step S12 in the case of the invalidation process of the night.
- step S10 it is determined that the data write process is to be performed, so the data write process is performed.
- step S10 it is determined that data invalidation processing is to be performed, so data invalidation processing is performed.
- step S11 or step S12 ends, the CPU 50 ends the processing for rewriting the data in the flash memory 20.
- FIG. 8 is a flowchart showing a flow of processing at the time of a write operation.
- control unit 25 of the flash memory 20 writes data to the specified address of the user area ux of the memory cell array 21 at the timing shown in FIG.
- control unit 25 sets the value “01” indicating that the data is valid to the flag area fy corresponding to the user area uX in which the data is written. Write.
- FIG. 9 is a flowchart showing the invalidation processing.
- FIG. 10 is a flowchart showing the flow of a process for erasing data.
- control unit 25 of the flash memory 20 erases the data at the specified address in the user area uX of the memory cell array 21 at the timing shown in FIG.
- the control unit 25 writes “00”, a value indicating that data has been erased, to the flag area f y corresponding to the erased user area u X, and ends the data erasing process.
- FIG. 11 is a flowchart showing the flow of processing in the flash memory when an interrupt signal is output.
- the J control unit 25 receives a signal output at a predetermined time interval from the time management unit 24, and determines whether a predetermined time (for example, 60 seconds) has elapsed. Here, if it is determined that the predetermined time has elapsed, the process proceeds to step S51. When it is determined that the predetermined time has not elapsed, that is, when the signal from the time management unit 24 is not received, step S50 is repeated.
- a predetermined time for example, 60 seconds
- the control unit 25 causes the comparing unit 23 to calculate the ratio of the data “11” in the flag area f y indicating that the data in the corresponding user area ux is invalid.
- control unit 25 takes out a predetermined ratio stored in the ratio storage unit 22 in advance and sends it to the comparison unit 23, where it is compared with the ratio calculated in the process of step S51.
- a predetermined ratio stored in advance for example, 80%
- the process proceeds to step S53, and if not, the process returns to step S50.
- the control unit 25 outputs an interrupt signal to the outside and requests garbage collection processing because the ratio of invalidity is large. Then, repeat the processing from step S50. Return.
- FIG. 12 is a flowchart showing the flow of the garbage collection process. S60: Determines whether an interrupt signal has been received
- the CPU 50 determines whether or not an interrupt signal requesting execution of the garbage collection process has been received from the control unit 25 of the flash memory 20. Proceed to 1 and if not received, repeat step S60.
- the CPU 50 performs a garbage collection process on the flash memory 20.
- the garbage collection process is a process of erasing invalid data in the user area uX and combining valid areas into a continuous area, thereby increasing the usable area.
- the program for rewriting the data in the flash memory 20 executed by the CPU 50 and the garbage collection program are independent programs. It can be executed as Further, according to the flash memory 20 of the first embodiment, the timing for executing the garbage collection program can be notified to the outside as an interrupt signal.
- FIG. 13 is a configuration diagram showing a flash memory according to the second embodiment of the present invention and circuits arranged outside the flash memory.
- the flash memory 30 includes a memory cell array 31, a ratio calculator 32, and a controller 33.
- the memory cell array 31 includes a plurality of user areas UX and corresponding flag areas fy.
- the ratio calculation unit 32 determines the state of the flag area fy of the memory cell array 31, calculates a ratio at which the user area ux is invalid, and sends the calculated ratio to the control unit 33.
- the control unit 33 controls each unit of the flash memory 30 and transmits and receives information to and from the outside. I do.
- the control unit 33 is connected to the CPU 50 by a control signal line 102. In addition, it is connected to the overnight bus 60 and the address bus 70. Further, the control unit 33 receives the ratio calculated by the ratio calculation unit 32, and outputs this to the outside immediately after the data write operation or the invalidation process.
- the configuration of the external circuit of the flash memory 30 is the same as that of the first embodiment, so the same reference numerals are used and the description is omitted.
- the function of the state notification information generation unit 12 in FIG. 1 is included in the ratio calculation unit 32, and the function of the output unit 13 is included in the control unit 33.
- the flash memory 30 according to the second embodiment of the present invention differs from the flash memory 20 according to the first embodiment in that the ratio itself calculated by the ratio calculator 32 is externally controlled by the controller 33. The output point is different. Another difference is that the time management unit 24 is omitted, and the data is output to the outside immediately after the data writing operation or the invalidation processing.
- FIG. 14 is a timing chart when the ratio is output after the writing process.
- the figure shows the state of the signals on the address bus 70, the control signal line 102, and the data bus 60 when the ratio is output after the write processing.
- the control unit 33 of the flash memory 30 receives a write command from the data bus 60 when the control signal 102 becomes "H" as shown in FIG. Next, the data received via the data bus 60 is written to the user area tl x of the memory cell array 31 specified by the address received from the address bus 70. Further, a value “01” indicating that the data is valid is written to the corresponding flag area f y. Then, the ratio calculation unit 32 determines the state of the flag area f y to calculate a ratio at which the user area u X is invalid. The control unit 33 receives the ratio calculated by the ratio calculation unit 32, outputs this to the data bus 60, and notifies the outside.
- FIG. 15 is a timing chart when the ratio is output after the invalidation processing.
- the figure shows the state of the signals on the address bus 70, the control signal line 102, and the data bus 60 when the ratio is output after the invalidation processing.
- the control section 33 of the flash memory 30 has a control signal line 102 as shown in FIG.
- an invalidation instruction is received from the data bus 60.
- the value "1 1" indicating that the data is invalid is stored in the flag area fy corresponding to the user area u X of the memory cell array 31 specified by the address received from the address bus 70.
- the ratio calculation unit 32 determines the state of the flag area fy and calculates a ratio at which the user area ux is invalid.
- the control unit 33 receives the ratio calculated by the ratio calculation unit 32 and outputs it to the data bus 60 to notify the outside.
- FIG. 16 is a flowchart showing the flow of processing in the configuration of the second embodiment.
- the CPU 50 determines whether the data processing to be executed is a data write processing or a data invalidation processing. In the case of data write processing, the flow proceeds to step S71, and in the case of data invalidation processing, the flow proceeds to step S72.
- step S70 it is determined that data write processing is to be performed, so data write processing is performed.
- step S70 it is determined that data invalidation processing is to be performed, so data invalidation processing is performed.
- the CPU 50 reads the ratio calculated and output by the flash memory 30 immediately after the writing or invalidating processing via the data bus 60.
- the CPU 50 determines whether or not the calculated ratio is larger than a predetermined ratio (for example, 80%) stored in the RAM 80. If the calculated ratio is larger, the process proceeds to step S75. If it is, the process ends.
- a predetermined ratio for example, 80%
- the CPU 50 determines that garbage collection processing is necessary and performs garbage collection processing.
- the flash memory 20 outputs the ratio immediately after data writing or data invalidation processing, so that the interrupt signal line 101 becomes unnecessary.
- the configuration of the third embodiment is the same as the configuration diagram of the second embodiment shown in FIG.
- the third embodiment is different from the second embodiment in that the CPU 50 transmits a ratio output command requesting a ratio to the flash memory 20.
- FIG. 17 is a timing chart when the ratio is output according to the ratio output command.
- the figure shows the state of the signals on the address bus 70, the control signal line 102, and the data bus 60 at that time.
- the control unit 33 of the flash memory 30 receives the ratio output command from the data bus 60 when the control signal line 102 becomes "H" as shown in FIG. In response to this, the ratio calculation unit 32 determines the state of the flag area i y and calculates the ratio at which the user area u x is invalid. The control unit 33 receives the ratio calculated by the ratio calculation unit 32, outputs this to the data bus 60, and notifies the external device.
- the ratio is obtained when the ratio output command is transmitted to the flash memory 20, so that the ratio can be obtained at an arbitrary timing.
- the ratio at which the user area ux is invalid is calculated at regular time intervals, and the calculated ratio is compared with the predetermined ratio stored in advance in the flash memory 20. In comparison, when the calculated ratio is large, an interrupt signal requesting garbage collection processing is output.
- the calculated ratio itself is output immediately after the write operation or the invalidation processing.
- the present invention is not limited to this, and the calculated ratio itself may be output at regular time intervals, or may be stored in advance with the calculated ratio immediately after the write operation or the invalidation process. If the calculated ratio is higher than the specified ratio, an interrupt signal requesting garbage collection processing Signal may be output.
- the ratio at which the user area ux is invalid is output in response to a ratio output command from the outside.
- an interrupt signal requesting a garbage collection process may be output.
- the value of the flag area f y is described as “0 0” in the erased state, “01” in the valid state, and “1 1” in the invalid state, but is not limited to this.
- the status notification information for notifying the information corresponding to the status of the user area to the outside is generated and the status notification information is output to the outside, so outside the flash memory, the You can easily know the status and determine whether garbage collection is currently required.
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Priority Applications (4)
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CNA038240629A CN1689116A (zh) | 2003-02-28 | 2003-02-28 | 闪存以及存储器控制方法 |
JP2004568776A JP4017178B2 (ja) | 2003-02-28 | 2003-02-28 | フラッシュメモリ及びメモリ制御方法 |
PCT/JP2003/002404 WO2004077447A1 (ja) | 2003-02-28 | 2003-02-28 | フラッシュメモリ及びメモリ制御方法 |
US11/083,016 US7487286B2 (en) | 2003-02-28 | 2005-03-18 | Flash memory and method for controlling the memory |
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PCT/JP2003/002404 WO2004077447A1 (ja) | 2003-02-28 | 2003-02-28 | フラッシュメモリ及びメモリ制御方法 |
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US11/083,016 Continuation US7487286B2 (en) | 2003-02-28 | 2005-03-18 | Flash memory and method for controlling the memory |
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JP2009503744A (ja) * | 2005-08-03 | 2009-01-29 | サンディスク コーポレイション | 予定再生操作を伴う不揮発性メモリ |
WO2009118917A1 (ja) * | 2008-03-26 | 2009-10-01 | Suzuki Masumi | フラッシュメモリを用いた記憶装置 |
JP2011159044A (ja) * | 2010-01-29 | 2011-08-18 | Toshiba Corp | 不揮発性メモリのコントローラ及び不揮発性メモリの制御方法 |
JP4985781B2 (ja) * | 2007-11-05 | 2012-07-25 | 富士通株式会社 | 半導体記憶装置およびその制御方法 |
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US7984084B2 (en) * | 2005-08-03 | 2011-07-19 | SanDisk Technologies, Inc. | Non-volatile memory with scheduled reclaim operations |
US20070058923A1 (en) * | 2005-09-09 | 2007-03-15 | Buhler Kirk A | Use of flash based memory to store and play feature length licensed movie or TV productions |
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Also Published As
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JPWO2004077447A1 (ja) | 2006-06-08 |
JP4017178B2 (ja) | 2007-12-05 |
US20050166005A1 (en) | 2005-07-28 |
CN1689116A (zh) | 2005-10-26 |
US7487286B2 (en) | 2009-02-03 |
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