WO2004077304A1 - データ転送装置 - Google Patents
データ転送装置 Download PDFInfo
- Publication number
- WO2004077304A1 WO2004077304A1 PCT/JP2003/002270 JP0302270W WO2004077304A1 WO 2004077304 A1 WO2004077304 A1 WO 2004077304A1 JP 0302270 W JP0302270 W JP 0302270W WO 2004077304 A1 WO2004077304 A1 WO 2004077304A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- transfer
- buffer
- data
- channel
- address
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Definitions
- the present invention generally relates to a data transfer device, and more particularly, to a data transfer device for performing DMA transfer of data in a dual path system.
- Direct memory access (DMA) transfer which performs direct data transfer, is an indispensable technology for achieving high system performance.
- DMA C DMAControlUer
- CPU DirectMemoryAccess
- DMA C directly transfers data between slave devices without going through the CPU.
- the address is used to specify each slave device and the position in each slave device (for example, each address in a memory device).
- Figure 1 shows the allocation of slave devices in the address space.
- DMA C issues a Read request to the slave device, and reads information from a specific position in the slave device specified by the address. After that, the DMAC issues a Write request and transfers the read information to another slave device. In this way, the DMA C realizes data transfer between slave devices by issuing a request for Read and Wright.
- Figure 2 shows the data transfer operation of the double buffer system in a dual-pass system. It is a figure for explaining a work.
- the dual bus system of FIG. 2 includes a DMAC 10, a path 11, a bus 12, a RAM 13, a ROM 14, a video display 15, and a UART (Universal Asynchronous Receiver Transmitter) 16.
- DMA CIO is a master device
- RAMI 3, ROM 14, video display 15, and UART 16 are slave devices.
- the RAMI 3 and the ROM 14 are connected to the DMAC 10 via the bus 11, and the video display 15 and the UART 16 are connected to the DMAC 10 via the bus 12.
- the DMA C 10 includes two buffers (Bufferl) 21 and a buffer (Buffer2) 22.
- Bufferl buffer
- Buffer2 buffer
- FIG. 3 is a timing chart showing a DMA data transfer operation from the RAMI 3 to the video display 15.
- DMAC 10 first sends a Read request to RAMI 3, and stores data sent from RAMI 3 as a result of the Read request in buffer 21. This Read operation is shown in FIG. 3 as RAM-> buffei. When this Read operation is completed, the DMAC 10 writes the information stored in the buffer 21 to the video display 15. This Write operation is shown as bufferl-> video in FIG.
- another buffer (buffei'2) 22 can be used simultaneously with the buffer 21. That is, in parallel with writing from the buffer 21 to the video display 15, the next data is read from the RAMI 3 and stored in the buffer 22 (RAM-> buffer2). The data stored in the buffer 22 is written to the video display 15 in parallel with reading the data from the RAMI 3 and storing the data in the buffer 21 (bufifer2-> video).
- the double buffer system described above has twice as much information as the single buffer system. Must be stored, which consumes a lot of chip area. In general, there are not many slave devices in the system that require high-level transfer performance that can be realized for the first time by the double buffer method. Therefore, although the double buffer method has the disadvantage of requiring a large amount of chip area, there are limited cases where the merit of high-speed data transfer can be enjoyed.
- an object of the present invention is to provide a data transfer device that normally operates as a single buffer, operates as a double buffer system as needed, and can realize high-speed data transfer.
- Patent Document 1
- Patent Document 2
- a data transfer device comprises: a first channel unit for maintaining a first buffer in a first operation mode and executing a first data transfer; and a second buffer unit in the first operation mode. And a second channel unit for performing a second data transfer different from the first data transfer by relaying the first data transfer.
- the second operation mode at least the first buffer and the second buffer are connected to each other.
- the data read from the transfer source and the data write to the transfer destination are sequentially selected by transferring the data to be read from the transfer source to the transfer destination via the sequentially selected buffers. It is characterized by being configured to be executed in parallel.
- each channel when high-speed data transfer is not required, each channel operates as a separate channel in the first operation mode to realize separate data transfer. Then, when high-speed data transfer becomes necessary, the data read operation and the data write operation are executed in parallel in the second operation mode, thereby realizing double buffer data transfer. Therefore, when there is no need for high-speed data transfer, efficient data transfer is performed using multiple single-buffer channels.
- a single channel of the double-buffer method is implemented to execute high-speed data transfer. In this way, it is possible to enjoy the advantage of the high-speed data transfer of the double buffer system while reducing the disadvantages of the double buffer system.
- FIG. 1 is an address map showing assignment of slave devices in an address space.
- FIG. 2 is a diagram for explaining the data transfer operation of the double buffer system in the dual bus system.
- FIG. 3 is a timing chart showing the DMA data transfer operation from the RAM to the video display.
- FIG. 4 is a diagram for explaining a DMA controller (data transfer device) according to the present invention.
- FIG. 5 is a timing chart showing a double-buffer data transfer operation from the RAM to the video display.
- FIG. 6 is a diagram for explaining an operation in which the first channel executes DMA data transfer from the RAM to the UART and the second channel executes DMA data transfer from the RAM to the video display.
- FIG. 7 is a timing chart showing a data transfer operation using the two channels shown in FIG.
- FIG. 8 is a diagram showing an embodiment of a configuration in which two channels operate as one channel to realize double-buffer data transfer.
- FIG. 9 is a timing chart showing the data transfer operation of FIG.
- FIG. 10 is a diagram showing another embodiment of a configuration in which two channels operate as one channel to realize double buffer data transfer.
- FIG. 11 is a timing chart showing the data transfer operation of FIG.
- FIG. 12 is a diagram for explaining another embodiment of the high-speed data transfer according to the present invention.
- FIG. 13 is a timing chart showing a double-buffer data transfer operation from the RAM to the video display.
- FIG. 4 is a diagram for explaining the DMA controller (data transfer device) according to this effort.
- the DMA controller (DMAC) 30 is used in a Duanore bus system as shown in FIG. 4 includes a DMAC 30, a bus 11, a bus 12, a RAMI 3, a ROM 14, a video display 15, and a UART 16.
- the RAMI 3 and the ROM 14 are connected to the DMAC 30 via the bus 11, and the video display 15 and the UART 16 are connected to the DMAC 30 via the bus 12.
- a plurality of channels (channel units) 31-1 to 31-N are mounted on the DMAC 30, and one buffer is provided for each channel.
- channel 31-1 has a buffer 32-1 and channel 31-2 has a buffer 32-2.
- Each channel of the DMAC is provided with two registers S and D for setting addresses.
- Register S stores the address that indicates the position in the slave device that is the transfer source
- register D stores the address that indicates the position in the slave device that is the transfer destination.
- both the channel 31-1 and the channel 31-2 execute the DMA data transfer from the RAMI 3 to the video display 15.
- the channel 31-1 and the channel 31-2 virtually operate as one channel, and execute the double buffer data transfer using the two buffers 32-1 and 32-2.
- FIG. 5 is a timing chart showing a double-buffer data transfer operation from the RAM 13 to the video display 15.
- a read request is sent to RAMI 3 on channel 31 of the DMAC 30, and data sent from RAMI 3 as a result of the read request is buffered.
- the R ea d operation Ru shown as RAM-> bufferl 5.
- the channel 31-1 sends an odd read completion signal to channel 31-2, and instructs channel 31-2 to start data transfer (arrow 1 in Fig. 5). And arrow 3).
- channel 31-1 starts the operation of writing the information stored in buffer 32-1 to video display 15 (arrow 2 in FIG. 5). This W rite operation is shown as bufferl-> video in FIG.
- Channels 31-2 detect the assertion of the odd read completion signal and send a Read request to RAM I3.
- the next data is read from RAM I 3 and stored in buffer 32-2 (RAM-> buffer2). This operation is performed in parallel with the operation (buflferl-> video) in which the channel 31_1 writes the information stored in the buffer 32-1 to the video display 15.
- channel 31-2 sends an even read complete signal, instructing channel 31-1 to start data transfer (arrow in Figure 5). 4 and 7).
- Channel 3 1-1 issues the next Read request to RAM I3 and starts the read operation upon completion of the write (arrow 6) and assertion of the even-number read completion signal (arrow 7). I do.
- channel 31-2 is stored in buffer 32-2.
- the written data is written to the video display 15 (buffer2-> video).
- the two channels use their own buffers alternately to operate virtually as one channel and perform double-buffered data transfer. Thereby, high transfer performance can be realized as needed.
- channels 3 1-1 perform DMA data transfer from RAM I 3 to UART 16 and channels 3 1-2 perform DMA data transfer from RAM I 3 to video display 15
- FIG. 7 is a diagram for explaining an operation performed by the user.
- FIG. 7 is a timing chart C showing the data transfer operation using the two channels shown in FIG.
- the channel 31_1 of the DMAC 30 issues a Read request to the RAM I3.
- the information obtained as a result of the Read request is stored in the buffer 32-1 of channel 31-1 (RAM-> CH1). After that, channel 31-1 issues a W rite request to UART 16 and writes the contents of buffer 32-1 to UART 16 (CH1-> UART). At the same time that channel 31-1 performs a write operation to UART16, channel 31-2 issues a Read request to RAM I3 and stores the read information in buffer 32-2. (RAM-> CH2). After that, the channel 31-2 writes the contents of the buffer 32-2 to the video display 15 (CH2-> Video).
- each channel when high-speed data transfer is not required, each channel operates as a separate channel to achieve separate data transfer. Then, when high-speed data transfer becomes necessary, as described above, the two channels virtually operate as one channel to execute double-buffer data transfer. Therefore, when high-speed data transfer is not required, efficient data transfer is realized as a single-buffer multiple channel. When high-speed data transfer is required, a single double-buffer channel is used. To perform high-speed data transfer. In this way, while reducing the disadvantages of the double-buffer method, the advantages of the high-speed data transfer of the double-buffer method can be enjoyed.
- FIG. 8 is a diagram showing an embodiment of a configuration in which two channels operate as one channel to realize double-buffer data transfer.
- DMA C30 has multiple channels 31-1 through 31-N One buffer is provided for each channel.
- Each channel is provided with a source register 41, a destination register 42, an address increment module 43, and an address increment module 44.
- the transfer source register 41 stores the address of the transfer source of the data transfer performed by the channel
- the transfer destination register 42 stores the address of the transfer destination of the data transfer performed by the channel.
- the dress increment module 43 updates the contents of the original register 41 by +2.
- the address increment module 44 updates the contents of the transfer destination register 42 by +2.
- DMA C data is transferred while incrementing the transfer source address and the transfer destination address. Normally, the end address is incremented (+1) by the transfer data size read or written in one buffer transfer operation. In contrast, in the embodiment of FIG. 8, each of the two channels increments (+2) the address by twice the transfer size.
- a double buffer operation can be realized with little modification of the address increment module without changing the configuration of the controller that controls the buffer.
- the address increment module can also execute +1 address increment in order to support single-buffer data transfer, and is configured to be able to switch between +1 increment and +2 increment. You.
- FIG. 9 is a timing chart showing the data transfer operation of FIG.
- the contents of the transfer source register 41 of channel 31-1 are shown as Srcl, and the contents of the transfer destination register 42 of channel 31-1 are shown as Destl.
- the contents of the source registers 41 on channels 31-2 are shown as Src2, and the contents of the destination registers 42 on channels 31-2 are shown as Dest2.
- channel 3 1-1 executes the Read operation for the address (0) of Srcl (RAM-> Bufferl).
- 2 is added to the value of Srcl, and Srcl is updated with the addition result (2).
- Channels 3 1-2 perform a Read operation on address (1) of Src2 (RAM-> Buffer2), and respond to the completion (arrow 2), add 2 to the value of Src2, and add the result Update Src2 in (3).
- channel 31-1 performs a write operation on the address (1000) of Destl (Bufferl-> Video).
- Add 2 to the value of Destl and update Destl with the addition result (1002).
- 2 is added to the value of Dest2, and Dest2 is updated with the addition result (1003).
- FIG. 10 is a diagram showing another embodiment of a configuration in which two channels operate as one channel to realize a dubnole buffer type data transfer. At i 0,
- the address increment module 43 updates the contents of the transfer source register 41 by +1 and updates the contents of the transfer destination register 42 by +1. That is, the address is incremented (+1) by the size of the transfer data read or written in one buffer transfer operation.
- the channels 31-1 and 31-2 are connected to the buffer 32-1 and the buffer 32-2.
- a double-buffer data transfer is realized by using.
- FIG. 11 is a timing chart showing the data transfer operation of FIG.
- channel 31-1 executes Read operation for Srcl address (0) (RAM-> Buferl). In response to the completion of this Read operation (arrow 1), 1 is added to the value of Srcl, and Srcl is updated with the addition result (1).
- channel 31-2 executes a Read operation for address (1) of Srcl (RAM-> Buffer2).
- channel 31-1 adds 1 to the value of Srcl and updates Srcl with the result of addition (2). This update may be performed in response to an even read completion signal from channel 31-2 to channel 31-1.
- channel 31-1 performs a write operation on the address (1000) of Destl (Bufferl-> Video).
- FIG. 12 is a diagram for explaining another embodiment of the high-speed data transfer according to the present invention.
- a DMA controller (DMAC) 50 is used in a dual bus system as shown in FIG.
- the bus system of FIG. 12 includes a DMA C 50, a bus 11, a bus 12, a RAMI 3, a video display 15, a UART 16, and a CPU 60.
- RAMI 3 is connected to DMAC 50 via bus 11, and video display 15 and UART 16 are connected to DMAC 50 via path 12.
- the DMAC 50 is provided with a plurality of channels 51_1 to 511-1N, and one buffer number queue is provided for each channel.
- channel 51-1 is provided with a buffer number queue 52-1
- channel 51-2 is provided with a buffer number queue 52-2.
- buffers 53-1 to 53-1N are provided.
- valid flags 54-1 to 54-N are provided, and the corresponding knockers 53-1 to 53-N indicate whether or not the available power is available.
- FIG. 13 is a timing chart showing a high-speed data transfer operation from the RAM 13 to the video display 15.
- channel 51-1 checks the valid flags 54-1 to 54-N to find an empty buffer, and stores the buffer number (Bufferl) in the buffer number queue.
- 1 5 2 Store in 1.
- the data read from the RAM I 3 is stored in the buffer (the buffer with the last number in the queue) (RAM-> Bufferl).
- check the channel 5 1—1 force valid flags 5 4 _ 1 to 5 4—N to find an empty buffer, and store the buffer number (Buffer 2) in the buffer number queue 52 1 I do.
- the next data read from RAM I3 is stored in the buffer (the buffer with the last number in the queue) (RAM-> Buffer2).
- the channel 5 1-1 When a write request comes from the video display 15, the channel 5 1-1 performs writing to the video display 15. At this time, data is sent to the video display 15 from the buffer indicated by the number (head number of the queue) output from the buffer number queue 5 2-1 (Bufferl-> Video). As shown in FIG. 13, the channel 51-1 can execute the data reading from the RAM I3 and the data writing to the video display 15 in parallel. In the example of FIG. 13, the channel 51-1 uses Buffer1, Buffer2, and Buffers in that order, then uses Buffer1 again, then uses Buffer2, and then uses Buffer1 again. In the data transfer according to the present embodiment, a valid flag is checked and a buffer that can be used at any time is specified, so that the buffer to be used changes according to the situation.
- Each channel may acquire its own buffer and execute various data transfer operations.
- a plurality of buffers are comprehensively managed, and each channel acquires and uses the buffers as needed.
- buffer control is more complicated than the methods in Figs. 8 and 10, but if two buffers are available, the same effect as double buffer data transfer can be obtained. it can.
- the configuration of this embodiment has a problem that if a certain channel secures all the buffers, the Read transfer of another channel cannot be performed. In general, there are many restrictions that the operation from the transfer request to the data reception must be performed within a predetermined time.To solve the above problem, control is performed so that one buffer corresponds to each channel after all. Is an easy solution. In this case, the operation is essentially the same as the operation in FIG. 4 and FIG.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN03822125.XA CN1682202A (zh) | 2003-02-27 | 2003-02-27 | 数据传送装置 |
JP2004568756A JPWO2004077304A1 (ja) | 2003-02-27 | 2003-02-27 | データ転送装置 |
PCT/JP2003/002270 WO2004077304A1 (ja) | 2003-02-27 | 2003-02-27 | データ転送装置 |
US11/064,097 US20050144338A1 (en) | 2003-02-27 | 2005-02-24 | Data transfer apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/002270 WO2004077304A1 (ja) | 2003-02-27 | 2003-02-27 | データ転送装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/064,097 Continuation US20050144338A1 (en) | 2003-02-27 | 2005-02-24 | Data transfer apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004077304A1 true WO2004077304A1 (ja) | 2004-09-10 |
Family
ID=32923110
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/002270 WO2004077304A1 (ja) | 2003-02-27 | 2003-02-27 | データ転送装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20050144338A1 (ja) |
JP (1) | JPWO2004077304A1 (ja) |
CN (1) | CN1682202A (ja) |
WO (1) | WO2004077304A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100449519C (zh) * | 2005-03-23 | 2009-01-07 | 精工爱普生株式会社 | 数据传输控制装置及电子设备 |
JP2010039140A (ja) * | 2008-08-04 | 2010-02-18 | Toshiba Corp | 携帯端末 |
US11556104B2 (en) * | 2011-09-21 | 2023-01-17 | Hitachi Astemo, Ltd. | Electronic control unit for vehicle and method of executing program |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102006004191B4 (de) * | 2006-01-27 | 2007-12-20 | Airbus Deutschland Gmbh | Deterministisches Kommunikations-System |
US8843675B2 (en) * | 2007-03-15 | 2014-09-23 | Broadcom Corporation | Pipelined buffer interconnect |
CN101441610B (zh) * | 2007-11-21 | 2010-09-01 | 中兴通讯股份有限公司 | 一种实现数据并串转换无缝输出的***及方法 |
CN103593148B (zh) * | 2013-11-08 | 2017-10-27 | 大唐移动通信设备有限公司 | 一种cdf侧离线话单数据快速存取的方法及装置 |
WO2021124917A1 (ja) * | 2019-12-18 | 2021-06-24 | ソニーグループ株式会社 | 情報処理システム、情報処理方法、及び、情報処理装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05250306A (ja) * | 1992-03-05 | 1993-09-28 | Fujitsu Ltd | Dmaコントローラ |
JPH1063607A (ja) * | 1996-08-14 | 1998-03-06 | Oki Electric Ind Co Ltd | Dmaコントローラ |
JPH10307787A (ja) * | 1997-05-09 | 1998-11-17 | Nec Corp | バッファメモリ装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6067300A (en) * | 1998-06-11 | 2000-05-23 | Cabletron Systems, Inc. | Method and apparatus for optimizing the transfer of data packets between local area networks |
JP3415567B2 (ja) * | 2000-06-21 | 2003-06-09 | エヌイーシーマイクロシステム株式会社 | Usb転送制御方法およびusbコントローラ |
US6985977B2 (en) * | 2002-08-30 | 2006-01-10 | National Instruments Corporation | System and method for transferring data over a communication medium using double-buffering |
-
2003
- 2003-02-27 WO PCT/JP2003/002270 patent/WO2004077304A1/ja active Application Filing
- 2003-02-27 CN CN03822125.XA patent/CN1682202A/zh active Pending
- 2003-02-27 JP JP2004568756A patent/JPWO2004077304A1/ja not_active Withdrawn
-
2005
- 2005-02-24 US US11/064,097 patent/US20050144338A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05250306A (ja) * | 1992-03-05 | 1993-09-28 | Fujitsu Ltd | Dmaコントローラ |
JPH1063607A (ja) * | 1996-08-14 | 1998-03-06 | Oki Electric Ind Co Ltd | Dmaコントローラ |
JPH10307787A (ja) * | 1997-05-09 | 1998-11-17 | Nec Corp | バッファメモリ装置 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100449519C (zh) * | 2005-03-23 | 2009-01-07 | 精工爱普生株式会社 | 数据传输控制装置及电子设备 |
JP2010039140A (ja) * | 2008-08-04 | 2010-02-18 | Toshiba Corp | 携帯端末 |
US11556104B2 (en) * | 2011-09-21 | 2023-01-17 | Hitachi Astemo, Ltd. | Electronic control unit for vehicle and method of executing program |
Also Published As
Publication number | Publication date |
---|---|
JPWO2004077304A1 (ja) | 2006-06-08 |
CN1682202A (zh) | 2005-10-12 |
US20050144338A1 (en) | 2005-06-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6874039B2 (en) | Method and apparatus for distributed direct memory access for systems on chip | |
US6247084B1 (en) | Integrated circuit with unified memory system and dual bus architecture | |
US8719476B2 (en) | Communication system, master device and slave device, and communication method, configured to handle plural concurrent requests | |
US20040107265A1 (en) | Shared memory data transfer apparatus | |
US7016984B2 (en) | System controller using plural CPU's | |
JPH0792654B2 (ja) | ビデオ・データ・フレーム伝送方法および装置 | |
US6675251B1 (en) | Bridge device for connecting multiple devices to one slot | |
KR20100106262A (ko) | 저장 컨트롤러 및 저장 시스템 | |
KR20060122934A (ko) | 복수의 어드레스 2 채널 버스 구조 | |
US20050144338A1 (en) | Data transfer apparatus | |
CN114785748B (zh) | 用于图像传输的dma控制***与方法 | |
US10127172B2 (en) | Single SDIO interface with multiple SDIO units | |
JPH06266615A (ja) | 順次データ転送型メモリ及び順次データ転送型メモリを用いたコンピュータシステム | |
US9830280B2 (en) | Multiple access single SDIO interface with multiple SDIO units | |
US6748505B1 (en) | Efficient system bus architecture for memory and register transfers | |
JP2001134752A (ja) | グラフィックプロセッサおよびグラフィックプロセッサにおけるデータ処理方法 | |
US9811485B2 (en) | Single relay SDIO interface with multiple SDIO units | |
US8996772B1 (en) | Host communication device and method with data transfer scheduler | |
US8151015B2 (en) | Systems and methods for effecting DMA data transfers | |
US8296481B2 (en) | Device and method for improving transfer efficiency of odd number of data blocks | |
KR100704218B1 (ko) | 데이터 전송 장치 | |
US20040162924A1 (en) | Apparatus and method for transmitting data by means of direct memory access medium | |
JP4229242B2 (ja) | ダイレクトメモリアクセスコントローラ | |
JP2005235216A (ja) | ダイレクト・メモリ・アクセス制御 | |
CN118034638A (zh) | 重排序缓冲器、***、组件、设备及传输方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): CN JP KR US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2004568756 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 11064097 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020057004468 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2003822125X Country of ref document: CN |
|
WWP | Wipo information: published in national office |
Ref document number: 1020057004468 Country of ref document: KR |