WO2003063436A1 - Etage de sortie d'emetteur pour bus a deux fils - Google Patents

Etage de sortie d'emetteur pour bus a deux fils Download PDF

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Publication number
WO2003063436A1
WO2003063436A1 PCT/IB2002/005744 IB0205744W WO03063436A1 WO 2003063436 A1 WO2003063436 A1 WO 2003063436A1 IB 0205744 W IB0205744 W IB 0205744W WO 03063436 A1 WO03063436 A1 WO 03063436A1
Authority
WO
WIPO (PCT)
Prior art keywords
bus
voltage source
current
output stage
wire
Prior art date
Application number
PCT/IB2002/005744
Other languages
English (en)
Inventor
Bernd Elend
Original Assignee
Philips Intellectual Property & Standards Gmbh
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Intellectual Property & Standards Gmbh, Koninklijke Philips Electronics N.V. filed Critical Philips Intellectual Property & Standards Gmbh
Priority to US10/502,360 priority Critical patent/US20050104633A1/en
Priority to EP02806570A priority patent/EP1472840B1/fr
Priority to DE60226646T priority patent/DE60226646D1/de
Priority to JP2003563170A priority patent/JP2005516479A/ja
Publication of WO2003063436A1 publication Critical patent/WO2003063436A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H04L25/0274—Arrangements for ensuring balanced coupling

Definitions

  • the invention relates to a transmitter output stage for a two-wire bus.
  • common mode chokes In two- wire bus systems, e.g. the CAN bus, use is made of so-called common mode chokes. These are provided separately from the transmitter output stages and the purpose they serve is to reduce the electromagnetic radiation from the bus system. This is achieved by virtue of the fact that the common mode chokes impose currents of equal size but opposite sign on the two wires of the bus system.
  • the common mode chokes represent an additional cost for a bus system of this kind because they have to be provided as separate pieces of circuitry.
  • a transmitter output stage for a two-wire bus which output stage imposes equal but opposed currents on the two wires (7, 8) of the bus and has a first voltage source (5) for supplying voltage, a second voltage or current source (6) for controlling the equal but opposed currents and for generating data bits on the bus wires (7, 8), and two first transistors (1, 2) whose bases are driven by the second voltage source (6) and which both generate equal collector currents of which one (Ii) is fed to the first bus wire (7) and a second (I ⁇ ) is fed to an input of a current mirror circuit (3, 4) that, at the output end, imposes on the second bus wire (8) a current (I ) of equal value but opposite sign to the current (Ii) fed to the first bus wire (7).
  • a transmitter output stage of this kind has a first voltage source that is used to supply current or voltage to the output stage.
  • a second voltage source or current source By means of a second voltage source or current source, a drive is provided for the bases of two first transistors that are so designed that they generate equal collector currents.
  • a first one of these collector currents is fed to a first wire of the two- wire bus.
  • the current of equal size generated by the second transistor is fed to a current mirror circuit and the latter produces, at the output end, a current of equal value but opposite sign that is fed to the second wire of the two-wire bus. What is achieved in this way is that currents of the same magnitude but different sign are fed to the two bus wires in the desired manner, thus minimizing the electromagnetic radiation from the two wires of the bus system.
  • the transmitter output stage under the control of the second voltage source, at all times ensures that equal but opposite currents are fed to the two wires of the bus system. This is true both when the transmitter output stage is operating off-load, i.e. when no data is being fed to the data bus, and when it is in the active mode, namely when data is being fed on.
  • These two modes provision may also be made for more than two modes) may be selected by selecting the value of the voltage that is supplied by the second voltage source.
  • two PNP transistors may be provided as the two first transistors that supply equal currents, as is provided for in an embodiment of the invention that is claimed in claim 2.
  • the current mirror that supplies a current of equal magnitude but opposite sign as compared with the current fed to the first bus wire is advantageously constructed from two NPN transistors.
  • the second voltage source that controls the size of the currents that are fed to the two wires of the two- wire bus may supply a plurality of voltages of different values that initiate, for example, a quiescent state for the data bus and one or more active states on the data bus.
  • the data bus may, for example, be a CAN bus for which, because it is used in vehicles, it is particularly important for the electromagnetic radiation to be minimized.
  • FIG. 1 shows, in the form of a circuit diagram, a transmitter output stage according to the invention having a first voltage source 5 that supplies the circuit of the transmitter output stage with voltage. Also provided is a second voltage source 6 that drives the bases of a first PNP transistor 1 and a second PNP transistor 2. The emitters of these two PNP transistors 1 and 2 are connected to the positive pole of the first voltage source 5.
  • the two PNP transistors 1 and 2 are so designed that they generate collector currents of equal value.
  • the collector current of the PNP transistor 2, which is identified in the Figure as Ii, is fed to a first bus wire 7 of a two-wire bus system that is not otherwise represented in the Figure.
  • the aim is to feed a current of equal value but opposite sign to a second bus wire 8 of the two-wire bus.
  • a current of equal value but opposite sign is fed to a second bus wire 8 of the two-wire bus.
  • This current I ⁇ is fed to a current mirror circuit that is constructed from two NPN transistors 3 and 4.
  • the emitters of the two NPN transistors 3 and 4 are connected to the negative pole of the first voltage source 5.
  • the input transistor 3 of the current mirror circuit is connected as a diode, i.e. its base and collector are connected together.
  • the current I ⁇ from the first PNP transistor 1 is fed to the collector of the input transistor 3 of the current mirror circuit.
  • the output transistor 4 of the current mirror circuit generates on its collector a current of equal value but opposite sign.
  • This current is identified in the Figure as I 2 .
  • current I is precisely the desired current that, compared with the current I ⁇ , is of equal magnitude but opposite sign.
  • This current is fed to the second bus wire 8.
  • the voltage source 6 may be controlled, i.e. it may deliver a plurality of different voltage values that may, for example, be used to produce various states on the data bus, or rather on its bus wires 7 and 8.
  • the transistors at the bus end i.e. the transistors 2 and 4 may be replicated, that is to say that more than one such transistor may be provided connected in parallel, in order to obtain a larger output current.
  • a current source may be provided that feeds a current to the bases of the transistors and whose other pole is connected to the input of the current mirror circuit.
  • the transistors 1 to 4 may also take the form of field-effect transistors.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

L'invention concerne un étage de sortie d'émetteur pour un bus à deux fils. Cet étage de sortie applique des courants égaux mais opposés sur les deux fils (7, 8) du bus. L'étage de sortie selon l'invention comprend: une première source de tension (5) destinée à acheminer une tension; une deuxième source de tension (6) destinée à réguler lesdits courants égaux mais opposés, et à produire des bits d'information sur les fils du bus (7, 8); et deux transistors PNP (1, 2) dont les bases sont entraînées par la deuxième source de tension (6), et qui produisent tous les deux des courants de collecteur égaux, un de ces courants (I1) étant acheminé vers le premier fil du bus (7), l'autre courant (IT1) étant acheminé vers une entrée d'un circuit miroir de courant (3, 4) qui, au niveau de son extrémité de sortie, applique sur le deuxième fil du bus (8) un courant de taille égale mais de signe opposé au courant (I1) acheminé vers le premier fil du bus (7).
PCT/IB2002/005744 2002-01-23 2002-12-18 Etage de sortie d'emetteur pour bus a deux fils WO2003063436A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US10/502,360 US20050104633A1 (en) 2002-01-23 2002-12-18 Transmitter output stage for a two-wire bus
EP02806570A EP1472840B1 (fr) 2002-01-23 2002-12-18 Etage de sortie d'emetteur pour bus a deux fils
DE60226646T DE60226646D1 (de) 2002-01-23 2002-12-18 Sendeausgangsstufe für einen zweidrahtbus
JP2003563170A JP2005516479A (ja) 2002-01-23 2002-12-18 ２線式バス用送信器出力段

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10202336.0 2002-01-23
DE10202336A DE10202336A1 (de) 2002-01-23 2002-01-23 Transmitterendstufe für einen Zweidrahtbus

Publications (1)

Publication Number Publication Date
WO2003063436A1 true WO2003063436A1 (fr) 2003-07-31

Family

ID=7712780

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2002/005744 WO2003063436A1 (fr) 2002-01-23 2002-12-18 Etage de sortie d'emetteur pour bus a deux fils

Country Status (7)

Country Link
US (1) US20050104633A1 (fr)
EP (1) EP1472840B1 (fr)
JP (1) JP2005516479A (fr)
CN (1) CN100454916C (fr)
AT (1) ATE395771T1 (fr)
DE (2) DE10202336A1 (fr)
WO (1) WO2003063436A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7827418B2 (en) * 2005-01-25 2010-11-02 Linear Technology Corporation Controlling power distribution among multiple wires in communication cable
TWI514826B (zh) * 2008-11-14 2015-12-21 Univ Nat Sun Yat Sen 用於車載網路通訊系統之接收裝置
TWI427973B (zh) * 2010-04-13 2014-02-21 Univ Nat Changhua Education ＦｌｅｘＲａｙ發射器
DE102013219141A1 (de) * 2013-09-24 2015-03-26 Robert Bosch Gmbh Interlock-Schaltkreis zur Absicherung eines elektrischen Bordnetzes
CN103837732B (zh) * 2014-03-21 2017-07-18 上海富欣智能交通控制有限公司 无源电流检测电路

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4614882A (en) * 1983-11-22 1986-09-30 Digital Equipment Corporation Bus transceiver including compensation circuit for variations in electrical characteristics of components
US6154061A (en) * 1998-05-06 2000-11-28 U.S. Philips Corporation CAN bus driver with symmetrical differential output signals

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4649301A (en) * 1985-01-07 1987-03-10 Thomson Components-Mostek Corp. Multiple-input sense amplifier with two CMOS differential stages driving a high-gain stage
WO1992007425A1 (fr) * 1990-10-23 1992-04-30 Seiko Epson Corporation Circuit oscillant commande en tension et boucle a verrouillage de phase
US5331295A (en) * 1993-02-03 1994-07-19 National Semiconductor Corporation Voltage controlled oscillator with efficient process compensation
US5479137A (en) * 1993-12-14 1995-12-26 Samsung Electronics Co., Ltd. Controlled oscillator, as for synchyronous video detector
CN1206518A (zh) * 1995-11-10 1999-01-27 艾利森电话股份有限公司 通用的接收装置
US5854574A (en) * 1996-04-26 1998-12-29 Analog Devices, Inc. Reference buffer with multiple gain stages for large, controlled effective transconductance
JP3022410B2 (ja) * 1997-06-17 2000-03-21 日本電気株式会社 インタフェース回路およびその判定レベル設定方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4614882A (en) * 1983-11-22 1986-09-30 Digital Equipment Corporation Bus transceiver including compensation circuit for variations in electrical characteristics of components
US6154061A (en) * 1998-05-06 2000-11-28 U.S. Philips Corporation CAN bus driver with symmetrical differential output signals

Also Published As

Publication number Publication date
EP1472840A1 (fr) 2004-11-03
DE60226646D1 (de) 2008-06-26
JP2005516479A (ja) 2005-06-02
EP1472840B1 (fr) 2008-05-14
DE10202336A1 (de) 2003-07-24
US20050104633A1 (en) 2005-05-19
CN1615620A (zh) 2005-05-11
ATE395771T1 (de) 2008-05-15
CN100454916C (zh) 2009-01-21

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