WO2003003473A1 - Cellule memoire a semi-conducteurs non volatile, memoire a semi-conducteurs et procede pour produire une memoire a semi-conducteurs non volatile - Google Patents

Cellule memoire a semi-conducteurs non volatile, memoire a semi-conducteurs et procede pour produire une memoire a semi-conducteurs non volatile Download PDF

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Publication number
WO2003003473A1
WO2003003473A1 PCT/JP2001/005544 JP0105544W WO03003473A1 WO 2003003473 A1 WO2003003473 A1 WO 2003003473A1 JP 0105544 W JP0105544 W JP 0105544W WO 03003473 A1 WO03003473 A1 WO 03003473A1
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WIPO (PCT)
Prior art keywords
insulating film
semiconductor memory
memory device
gate
substrate
Prior art date
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PCT/JP2001/005544
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English (en)
Japanese (ja)
Inventor
Renichi Yamada
Tomoko Sekiguchi
Yuki Mori
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Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP2001/005544 priority Critical patent/WO2003003473A1/fr
Priority to JP2003509547A priority patent/JPWO2003003473A1/ja
Publication of WO2003003473A1 publication Critical patent/WO2003003473A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a nonvolatile semiconductor memory device and a semiconductor memory device.
  • nonvolatile semiconductor memory devices are mainly flash memories having a floating gate between a substrate and a control gate.
  • Flash memory requires a floating gate, which complicates the structure and makes it difficult to reduce production costs.
  • the complexity of this structure is also disadvantageous in terms of obtaining high production yields.
  • low power consumption and low drive voltage are required for the application of nonvolatile semiconductor memory devices to portable equipment in recent years.
  • the flash memory has a disadvantage that a high voltage of about 2 OV is required for rewriting since the flash memory has a structure in which two layers of gate insulating films are stacked above and below the floating gate.
  • MONOS metal-oxide-nitride-oxide-semiconductor
  • a nonvolatile semiconductor memory device having a metal-oxide-semiconductor (hereinafter, referred to as “MOS”) structure has been proposed in contrast to the above-mentioned two nonvolatile semiconductor memory devices.
  • MOS metal-oxide-semiconductor
  • Such examples can be found in, for example, Japan, Patent Publication, Japanese Patent Application Laid-Open Nos. H11-134870 and H5-112765.
  • nonvolatile storage is realized by capturing charges in an oxide.
  • the storage element can be manufactured in the same process as the peripheral circuit. Therefore, it can be manufactured at a lower cost as compared with the above-mentioned 2 nonvolatile semiconductor memory device.
  • the threshold voltage becomes lower than necessary in a state where the absolute value of the threshold voltage is lower (hereinafter referred to as “low V th state”). And read failure.
  • the present invention provides a MOS type nonvolatile semiconductor memory element in which the influence of threshold voltage variation is reduced, and a nonvolatile semiconductor memory device using the same.
  • the present invention provides a method for controlling traps (t ra p) in an oxide film, which is a cause of threshold voltage variation in the first place.
  • the present invention provides a method for easily manufacturing an enhancement transistor as a technique for eliminating the influence of threshold voltage variation of a nonvolatile semiconductor memory device.
  • MOS type non-volatile semiconductor storage element capable of performing a stable storage operation
  • a substrate a source region and a drain region provided on a surface portion of the substrate, a channel region provided on a surface portion of the substrate between the source region and the drain region, and the channel region.
  • a gate electrode formed on the insulating film, wherein the insulating film constitutes a charge storage portion, and a trap level of the insulating film is:
  • This is a nonvolatile semiconductor memory element formed by requiring trap level forming means in addition to the forming means. Further, if the invention of the present application is referred from another viewpoint, the following can be said.
  • a second aspect of the present invention provides a semiconductor device comprising: a substrate; a source region and a drain region provided on a surface portion of the substrate; a channel region provided on a surface portion of the substrate between the source region and the drain region; At least a gate electrode formed above the insulating film, the insulating film forming a charge storage portion, and a trap level of the insulating film.
  • a nonvolatile semiconductor memory element that is larger than at least the number of trap levels formed in a thermal oxide film as a usual insulating film.
  • the trap level of the insulating film formed over the channel region of the transistor in the memory portion is changed by the insulating film formed over the channel region of the transistor in the peripheral circuit portion of the semiconductor memory device. It is larger than the number of trap levels.
  • FIG. 15 shows the basic configuration of the semiconductor memory device of the present invention.
  • Reference numeral 50 is a substrate, 51 and 52 are a source and a drain, 53 is an insulating film, 54 is a trap, 55 is a gate electrode, and 56 is a carrier captured at a trap level. Is shown.
  • the basic operation of the above-described nonvolatile semiconductor memory device is as follows. That is, by trapping carriers of the same conductivity type as the substrate of the field-effect transistor at the trap (capture) level of carriers formed in the gate insulating film of the MOS field-effect transistor, At the interface between the substrate of the field effect transistor and the gate insulating film, a carrier of a conductivity type opposite to that of the trapped carrier is induced.
  • the threshold voltage of the field-effect transistor decreases. Conversely, by trapping the carrier of the opposite conductivity type with the substrate of the field-effect transistor, the carrier trapped on the interface between the substrate of the field-effect transistor and the gate insulating film. A carrier of the same conductivity type is induced. Therefore, the threshold voltage of the field-effect transistor increases. In this way, multiple threshold voltages can be achieved depending on the presence or absence of carriers to be captured. Therefore, by utilizing the difference in current driving force at a desired gate voltage, Information can be stored. Further, by applying a bias to the gate electrode of the field-effect transistor, carriers trapped in the gate insulating film can be released from the trap level and erased. Thus, it is possible to realize a semiconductor memory element capable of electrically writing and erasing information.
  • the insulating film is a silicon oxide film, a silicon nitride film, or a composite film thereof.
  • desired carriers can be captured in a so-called gate insulating film, and a so-called nonvolatile memory element can be operated sufficiently stably. That is, a desired carrier is captured by the trap level, and desired information is stored.
  • the present invention is a nonvolatile memory element, it does not require a so-called floating gate. Note that the basic operation such as reading of information is the same as that of the conventional nonvolatile semiconductor memory element, and therefore detailed description is omitted.
  • the trap level forming means added to the insulating film forming means the following method can be used.
  • a voltage at which a tunnel current is generated that is, an electrical stress is applied to a gate electrode of the memory device, and a trap level is actively formed. I do.
  • electrical stress which corresponds to the amount of injected charges at which the trap density generated in the insulating film is saturated.
  • This voltage application is preferably performed when the gate electrode has a negative potential.
  • the insulating film is formed in a plurality of times.
  • trap levels are introduced between these layers. Is entered.
  • more trap levels can be introduced into the gate insulating film than in a single step of forming the insulating film.
  • a plurality of different manufacturing methods can be used for forming the insulating film in the plurality of steps. For example, by forming a thermal oxide film and forming an oxide film thereon by the CVD method, more trap levels can be introduced than in forming an insulating film in one step.
  • This method can more effectively introduce a trap level at a desired position. Further, according to the embodiment of the present invention, it is possible to control the position of the trap level to be formed, that is, the distance from the substrate interface. Even for the same amount of charge, the amount of change in the threshold voltage varies depending on the trapped position. Therefore, it is preferable to control the position of the trap level to be formed according to the required characteristics.
  • a typical example of the nonvolatile semiconductor memory device of the present invention is an example in which the nonvolatile semiconductor memory device includes at least a memory transistor section and an enhancement transistor section.
  • the first feature of the nonvolatile semiconductor memory device according to the present invention is the two-level gate oxide film. That is, the thickness of the gate oxide film is changed from the position corresponding to the source region to the position corresponding to the drain region.
  • a second typical example of the nonvolatile semiconductor memory device of the present invention is a form in which at least each source and drain of the memory transistor portion and the enhancement transistor portion are commonly configured.
  • the enhancement transistor is a transistor having a threshold voltage between the low V th and the high V th state of the memory transistor in the memory cell, and the threshold voltage is stable against rewriting of the memory cell. .
  • the enhancement transistor is connected to the source (or drain) of the memory transistor. By connecting the drain (or source) of the transistor, it plays a role in preventing read failure due to Vth variation in the low Vth state of the memory transistor. In order to realize such a state in the MOS nonvolatile memory, it is necessary to realize two kinds of film thicknesses in which the gate oxide film thickness changes from the source to the drain as shown in FIG. In FIG. In FIG. In FIG.
  • 1, 1 is a gate electrode, 2 is a semiconductor substrate, 3 is a source, 4 is a drain, 5 and 6 are two types of gate oxide films, 5 is a thin film portion, 6 is a thick film portion, 7 Is an interlayer insulator.
  • the source and the drain may be exchanged.
  • the structure in FIG. 1 has two types of gate oxide films, and as shown in the equivalent circuit in FIG. 2, a structure in which two types of transistors having different threshold voltages are joined by a source and a drain is realized.
  • the enhancement transistor can be realized by separating the gate electrode into two as shown in FIG.
  • 2 is a semiconductor substrate
  • 3 and 4 are a source and a drain
  • 5 is a gate oxide film
  • 8 is a gate electrode of a memory transistor
  • 9 is a gate electrode of an enhancement transistor
  • 7 is an interlayer. It is an insulating film.
  • Fig. 4 shows an equivalent circuit of the structure in Fig. 3.
  • a bias necessary for rewriting operation is applied to the gate electrode 8 of the memory transistor to the MOS nonvolatile memory, and only a bias that does not cause a rewriting operation is applied to the gate electrode 9 of the enhancement transistor. By applying the voltage, a desired operation can be realized.
  • the process can be simplified by forming the gate of the peripheral circuit at the same time as forming the gate oxide film. You.
  • the charge trap density in the oxide film immediately after formation is often insufficient for realizing a MOS nonvolatile memory, and even if the density is sufficient, the trap density between memory cells varies. And it is difficult to control the threshold voltage.
  • it is effective to apply an electric stress to the gate oxide film of the memory transistor in advance to make the trap density constant.
  • Q crit the charge trap density in the oxide film is saturated at a certain value (Q crit). The value does not depend on the initial charge trap density.
  • a uniform and stable charge trap can be realized by applying an electrical stress corresponding to the amount of injected charge Qcrit to the gate oxide film of the memory cell transistor in advance.
  • traps are often generated at the oxide film interface, and the trap is likely to be generated. Therefore, if an oxide film is formed in plural times to form an interface in the film, the trap generation position can be controlled.
  • nonvolatile semiconductor memory device Various forms of the nonvolatile semiconductor memory device described above are arranged and listed below.
  • a second conductive type drain region selectively formed on a semiconductor substrate surface on a first conductive type semiconductor substrate, and a predetermined distance from the drain region
  • a source region of the second conductivity type selectively formed on the surface of the semiconductor substrate across the semiconductor substrate, the semiconductor region at least partially overlapping an end of the drain region, and the end of the source region.
  • a storage element including an insulating film having two different thicknesses formed over a substrate and a gate electrode formed over the insulating film is provided. This is a semiconductor memory device that stores information in a state.
  • the nonvolatile semiconductor memory device of the first embodiment described above is arranged in n pieces.
  • m pieces of semiconductor memory rows in which a source is connected to a source line and a drain is connected to a bit line are arranged, and n pieces are arranged.
  • the gates of the m semiconductor devices are connected to the lead lines of the semiconductor device, and at this time, only one semiconductor storage device belonging to a different row of the semiconductor storage devices is connected to one word line.
  • Semiconductor storage device is composed of two cells of the first embodiment of the above-mentioned nonvolatile semiconductor memory device, and is composed of n semiconductor memory cells having a structure in which the sources are connected to each other.
  • the source and gate of the m semiconductor memory cells are connected to the source line and the word line, respectively, by connecting m source lines and 2 ⁇ n read lines connected to the m rows of the semiconductor memory devices connected to the lines.
  • this is a NOR type semiconductor memory device in which only one semiconductor memory device belonging to a different semiconductor memory device column is connected to one source line and one gate line.
  • a second conductive type drain region selectively formed on a surface of the semiconductor substrate on a first conductive type semiconductive substrate;
  • a source region of the second conductivity type selectively formed on the surface of the semiconductor substrate at a distance of at least a distance from the end of the source region;
  • a memory transistor portion and an enhancement transistor portion each including an insulating film having two different thicknesses formed on the semiconductor substrate and a gate electrode formed on the insulating film are provided.
  • the semiconductor memory device has a common source and drain.
  • the insulating film of this type of memory transistor is deposited by CVD. It is useful to apply the above-described method of performing thermal oxidation after forming an oxide film. Further, it is also useful to form the insulating film of the memory transistor by performing thermal oxidation a plurality of times. Further, in such a semiconductor memory device, it is particularly useful to form a trap in the insulating film of the memory transistor by applying an electric stress to the gate electrode.
  • a typical NOR type memory array to which the nonvolatile semiconductor memory device shown so far is applied will be exemplified.
  • the nonvolatile semiconductor memory device is composed of two nonvolatile semiconductor memory devices according to the second embodiment, and has a structure in which n sources of the semiconductor memory device are connected to each other, and 2 ⁇ n drains are all connected to the bit lines.
  • An array of m semiconductor memory devices is arranged, and n source lines, 2 ⁇ n lead lines, and 2 n memory lines are connected to the m sources of the semiconductor memory device cells and the enhancement transistor transistors.
  • the gate of the transistor and the gate of the transistor are connected to a source line, a word line, and a memory line, respectively, and one source line, a lead line, and a memory line belong to different semiconductor storage device columns. Only a NOR type semiconductor memory device to which only one is connected.
  • the gate insulating film of the MOS transistor used in the nonvolatile semiconductor element application circuit or the peripheral circuit of the nonvolatile semiconductor device is formed by the same process as the formation of the thin film portion of the memory cell insulating film. It can be manufactured. And this measure is extremely useful in practice.
  • FIG. 1 is a schematic sectional view of a cell of a MOS type nonvolatile memory having two types of gate oxide films.
  • FIG. 2 is a cell equivalent circuit diagram of the MOS nonvolatile memory shown in FIG.
  • FIG. 3 is a schematic cross-sectional view of a cell of a MOS nonvolatile memory having a memory transistor and an enhancement transistor.
  • FIG. 4 is a cell equivalent circuit of the MOS nonvolatile memory shown in FIG.
  • FIG. 5 is an AND type memory array circuit diagram using the MOS type nonvolatile memory cells shown in FIGS. 1 and 2.
  • FIG. 6 is a schematic cross-sectional view of the element shown in the order of steps for manufacturing the memory array shown in FIG.
  • FIG. 7 is a schematic plan view of an element shown in the order of steps for manufacturing the memory array shown in FIG.
  • FIG. 8 is a circuit diagram of a NOR memory array using the MOS nonvolatile memory cells shown in FIGS. 1 and 2.
  • FIG. 9 is a schematic cross-sectional view of an element shown in the order of steps for manufacturing the memory array shown in FIG.
  • FIG. 10 is a schematic plan view of an element shown in the order of steps for manufacturing the memory array shown in FIG.
  • FIG. 11 is a circuit diagram of a NOR type memory array using the MOS type nonvolatile memory cells shown in FIGS. 3 and 4.
  • FIG. 12 is a schematic cross-sectional view of an element shown in the order of steps for manufacturing the memory array shown in FIG.
  • FIG. 13 is a schematic plan view of an element shown in the order of steps for manufacturing the memory array shown in FIG.
  • FIG. 14 is a diagram showing the dependence of the trap density generated in the oxide film on the amount of injected charge when a high bias stress is applied to the MOS capacitor.
  • FIG. 15 is a sectional view of a main part of the nonvolatile semiconductor memory element of the present invention.
  • FIG. 5 shows a circuit diagram when the memory cells shown in FIGS. 1 and 2 are arranged in an AND memory array.
  • a process as shown in FIGS. 6 and 7 can be considered.
  • FIG. 6 is a schematic sectional view showing the progress of the process in the order of a to i.
  • FIG. 7 shows a schematic plan view of a part of the process shown in FIG.
  • a part 10 of a gate electrode is formed (FIG. 6B). Again, an oxide film is grown on the substrate to form a gate oxide film portion 6 (FIG. 6, c).
  • the source and drain 12 are formed using the gate electrode as a mask region (FIG. 6E).
  • a sidewall 13 is formed beside the gate electrode (f in FIG. 6), and a trench 14 for element isolation is formed using this as a mask (g in FIG. 6).
  • An insulator 15 serving as both an element isolation and an interlayer insulator is buried in the groove 14 (h in FIG. 6).
  • FIG. 7a and FIG. 7 when viewed from above in steps g and h in FIG. 6, respectively.
  • a lead line 16 which is in electrical contact with the gate electrode is formed (i in FIG. 6), and is processed into a stripe shape in a direction perpendicular to the element isolation groove (c in FIG. 7). If the processing depth is set within the gate oxide film 5 formed first, the AND type memory array shown in FIG. 5 can be realized.
  • a trap having a density required for a MOS nonvolatile memory can be formed. Also, when forming the gate oxide film 5, by forming the oxide film a plurality of times and forming an interface in the oxide film, a trap-rich portion can be formed in the oxide film. Further Needless to say, as described above, a plurality of different insulating film manufacturing methods may be combined. That is, a silicon oxide film is manufactured using a CVD method and a thermal oxidation method.
  • the above-described high bias stress generally uses the following method. As described with reference to FIG. 14, charge injection corresponding to the injected charge amount at which the trap density is saturated in the film is performed. The optimum value differs depending on the type and quality of the insulating film, but generally, the current silicon oxide film is injected with a charge of 1 C, cm 2 from 10 OmCZcm 2 . Therefore, 1 mAZcm 2 than 1 0 OmA / cm 2 of current density, and the current injection, it is preferable to apply a stress. Although charge injection is possible at 1 mA / cm 2 or less, it takes too much time to obtain the desired value, which is not practical.
  • the film is more likely to cause dielectric breakdown, which is not practical.
  • the range of 51 ⁇ 1001 ⁇ 201 ⁇ 10 is preferable.
  • charge injection is possible at 5 MV cm or less, it takes too much time to obtain a desired value, which is not practical.
  • the film is more likely to cause dielectric breakdown, which is also impractical.
  • the oxidation process can be reduced by removing the oxide after performing the oxidation of step 5 and removing the oxide film to have the same thickness as the oxide film formed by the second oxidation.
  • FIG. 8 shows a circuit diagram when the memory cells shown in FIGS. 1 and 2 are arranged in a NOR type memory array.
  • a process as shown in FIGS. 9 and 10 can be considered.
  • Fig. 9 In the schematic plan view, the progress of the process is shown in the order of a to g.
  • FIG. 10 shows a schematic plan view of a part of the steps shown in FIG.
  • a stripe-shaped element isolation groove is formed in a semiconductor substrate, and an insulator 15 is buried in the groove.
  • a gate oxide thin film portion 5 is formed on the surface of the semiconductor substrate (a in FIG. 9).
  • the plan view at this time is shown in FIG.
  • a portion 10 of the gate electrode is formed (FIG. 9b), and an oxide film is formed again on the semiconductor substrate to form a gate oxide thick film portion 6 (FIG. 9c).
  • the remaining 11 is formed (d in FIG. 9).
  • the source and drain 12 are formed by ion implantation (FIG. 9, e).
  • the gate electrode is covered with silicon nitride 17 (f in FIG. 9).
  • the plan view at this time is shown in FIG.
  • the source of the memory cell is short-circuited at the source line 18, the plug 19 is set up at the drain (c in FIG. 10), and this plug 19 is short-circuited at the bit line 20 (g in FIG. 9). ).
  • the plan view at this time is shown in FIG. 10d.
  • a trap having a density required for the MOS type nonvolatile memory can be formed.
  • the gate oxide film 5 by forming the oxide film a plurality of times and forming an interface in the oxide film, a portion with many traps can be formed in the oxide film.
  • a plurality of different methods of manufacturing the insulating film may be combined as described above. That is, a silicon oxide film is manufactured using the CVD method and the thermal oxidation method.
  • the thickness of the gate oxide film of the MOS FET in the circuit on the same device other than the memory cell is the same as the oxide film of layer 5 or layer 6.
  • the oxidation step can be reduced by oxidizing the layer 5 and then removing it to make it the same as the oxide film thickness formed by the second oxidation.
  • FIG. 11 the memory cells shown in FIG. 3 and FIG. FIG. 2 shows a circuit diagram in the case of arrangement in an array.
  • the processes shown in FIGS. 12 and 13 can be considered.
  • FIG. 12 is a schematic sectional view showing the progress of the process in the order of a to f.
  • FIG. 13 shows a schematic plan view of a part of the steps shown in FIG.
  • a stripe-shaped element isolation groove is formed in a semiconductor substrate, an insulator 15 is buried in the groove, and then a gate oxide film 5 is formed on the surface of the semiconductor substrate (a in FIG. 12).
  • the plan view at this time is shown in Fig. 13a.
  • the gate 8 of the memory transistor and the gate 9 of the enhancement transistor are formed (FIG. 12b), and the source and drain 12 are formed by ion implantation using this gate electrode as a mask region (first step). 2 Figure 1 c).
  • the gate electrode 9 of the enhancement transistor and the gate electrode 8 of the memory transistor are covered with silicon nitride 17 (d in FIG. 12 and b in FIG. 13), and the source of the memory cell is connected to the source line 1.
  • Short-circuit at 8 and set up a plug 19 at the drain (c in FIG. 13), and short-circuit this plug 19 with a bit line 20 (e in FIG. 12).
  • the plan view at this time is shown in Fig. 13d.
  • a trap having a density required for the MOS type volatile memory can be formed. Also, by forming the oxide film a plurality of times when forming the gate oxide film 5 and forming an interface in the oxide film, a portion with many traps can be formed in the oxide film. Further, it goes without saying that a plurality of different methods of manufacturing the insulating film may be combined as described above. That is, a silicon oxide film is manufactured using the CVD method and the thermal oxidation method.
  • the oxidation process is performed by making the thickness of the gate oxide film of the MOS FET in the circuit on the same device other than the memory cell the same as that of the oxide film 5. Can be reduced.
  • a non-volatile memory having a simple structure can be realized with a smaller number of masks. With a small number of masks, memories can be manufactured at low cost. In addition, because of its simple structure, the cause of failures is smaller than that of conventional non-volatile memory, and development time can be shortened and high yield can be achieved.
  • the present invention can provide a nonvolatile semiconductor memory element and a semiconductor device with stable operation.

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Abstract

La présente invention concerne une cellule mémoire à semi-conducteurs non volatile comprenant un substrat, une région de source, une région de drain, pourvue à la surface du substrat, une région de canal, pourvue à la surface du substrat, entre la région de source et la région de drain, un film isolant, conçu pour recouvrir la région de canal, ainsi qu'une électrode de grille, pourvue au-dessus du film isolant. Ce film isolant constitue une section de stockage de charge dont le niveau de piégeage est réglé par utilisation d'un système de réglage de niveau de piégeage et d'un système de formation de film isolant. De plus, on peut supprimer la variation des caractéristiques d'une mémoire non volatile qui retient la mémoire par piégeage d'une charge dans un isolateur de grille en utilisant un transistor à enrichissement. Cette invention permet de produire une mémoire non volatile à faible coût et avec un haut rendement.
PCT/JP2001/005544 2001-06-28 2001-06-28 Cellule memoire a semi-conducteurs non volatile, memoire a semi-conducteurs et procede pour produire une memoire a semi-conducteurs non volatile WO2003003473A1 (fr)

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PCT/JP2001/005544 WO2003003473A1 (fr) 2001-06-28 2001-06-28 Cellule memoire a semi-conducteurs non volatile, memoire a semi-conducteurs et procede pour produire une memoire a semi-conducteurs non volatile
JP2003509547A JPWO2003003473A1 (ja) 2001-06-28 2001-06-28 不揮発性半導体記憶素子及び半導体記憶装置

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PCT/JP2001/005544 WO2003003473A1 (fr) 2001-06-28 2001-06-28 Cellule memoire a semi-conducteurs non volatile, memoire a semi-conducteurs et procede pour produire une memoire a semi-conducteurs non volatile

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WO2003003473A1 true WO2003003473A1 (fr) 2003-01-09

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EP2264756A1 (fr) * 2008-03-31 2010-12-22 Fujitsu Semiconductor Limited Dispositif à semi-conducteurs
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

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US6998317B2 (en) 2003-12-18 2006-02-14 Sharp Laboratories Of America, Inc. Method of making a non-volatile memory using a plasma oxidized high-k charge-trapping layer
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
EP2264756A1 (fr) * 2008-03-31 2010-12-22 Fujitsu Semiconductor Limited Dispositif à semi-conducteurs
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