WO2002065475A3 - Ligne conductrice auto-alignee pour circuits integres possedant une memoire magnetique a point de croisement - Google Patents

Ligne conductrice auto-alignee pour circuits integres possedant une memoire magnetique a point de croisement Download PDF

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Publication number
WO2002065475A3
WO2002065475A3 PCT/US2002/001918 US0201918W WO02065475A3 WO 2002065475 A3 WO2002065475 A3 WO 2002065475A3 US 0201918 W US0201918 W US 0201918W WO 02065475 A3 WO02065475 A3 WO 02065475A3
Authority
WO
WIPO (PCT)
Prior art keywords
cross
self
magnetic memory
integrated circuits
conductive line
Prior art date
Application number
PCT/US2002/001918
Other languages
English (en)
Other versions
WO2002065475A2 (fr
WO2002065475A8 (fr
Inventor
Xian Ning
Original Assignee
Infineon Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Corp filed Critical Infineon Technologies Corp
Priority to KR1020037009835A priority Critical patent/KR100566146B1/ko
Priority to JP2002565312A priority patent/JP2005504430A/ja
Priority to EP02718865A priority patent/EP1354348A2/fr
Publication of WO2002065475A2 publication Critical patent/WO2002065475A2/fr
Publication of WO2002065475A3 publication Critical patent/WO2002065475A3/fr
Publication of WO2002065475A8 publication Critical patent/WO2002065475A8/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

L'invention concerne un procédé servant à fabriquer un composant de mémoire magnétique. Dans un mode de réalisation, on crée une première pluralité de lignes conductrices au-dessus d'un substrat de semi-conducteur. On crée une pluralité de lignes en matériau magnétique au-dessus des lignes correspondantes de la première pluralité de lignes conductrices et on crée une deuxième pluralité de lignes conductrices au-dessus du substrat de semi-conducteur. La deuxième pluralité de lignes conductrices croise les premières lignes conductrices et les lignes en matériau magnétique. On peut utiliser ces deuxièmes lignes en tant que masque pendant qu'on exécute la configuration des lignes en matériau magnétique.
PCT/US2002/001918 2001-01-24 2002-01-24 Ligne conductrice auto-alignee pour circuits integres possedant une memoire magnetique a point de croisement WO2002065475A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020037009835A KR100566146B1 (ko) 2001-01-24 2002-01-24 교차점 자기메모리 집적회로용 자기정렬된 도전라인
JP2002565312A JP2005504430A (ja) 2001-01-24 2002-01-24 交点磁気記憶集積回路用の自己整合電導線
EP02718865A EP1354348A2 (fr) 2001-01-24 2002-01-24 Ligne conductrice auto-alignee pour circuits integres possedant une memoire magnetique a point de croisement

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US26399001P 2001-01-24 2001-01-24
US60/263,990 2001-01-24
US09/923,266 US6692898B2 (en) 2001-01-24 2001-08-03 Self-aligned conductive line for cross-point magnetic memory integrated circuits
US09/923,266 2001-08-03

Publications (3)

Publication Number Publication Date
WO2002065475A2 WO2002065475A2 (fr) 2002-08-22
WO2002065475A3 true WO2002065475A3 (fr) 2003-04-03
WO2002065475A8 WO2002065475A8 (fr) 2003-11-20

Family

ID=26950187

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/001918 WO2002065475A2 (fr) 2001-01-24 2002-01-24 Ligne conductrice auto-alignee pour circuits integres possedant une memoire magnetique a point de croisement

Country Status (7)

Country Link
US (1) US6692898B2 (fr)
EP (1) EP1354348A2 (fr)
JP (1) JP2005504430A (fr)
KR (1) KR100566146B1 (fr)
CN (1) CN1322578C (fr)
TW (1) TW560037B (fr)
WO (1) WO2002065475A2 (fr)

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US6692898B2 (en) * 2001-01-24 2004-02-17 Infineon Technologies Ag Self-aligned conductive line for cross-point magnetic memory integrated circuits
US6635496B2 (en) * 2001-10-12 2003-10-21 Infineon Technologies, Ag Plate-through hard mask for MRAM devices
US7101770B2 (en) * 2002-01-30 2006-09-05 Micron Technology, Inc. Capacitive techniques to reduce noise in high speed interconnections
US7235457B2 (en) * 2002-03-13 2007-06-26 Micron Technology, Inc. High permeability layered films to reduce noise in high speed interconnects
US6846738B2 (en) * 2002-03-13 2005-01-25 Micron Technology, Inc. High permeability composite films to reduce noise in high speed interconnects
US6900116B2 (en) 2002-03-13 2005-05-31 Micron Technology Inc. High permeability thin films and patterned thin films to reduce noise in high speed interconnections
US7160577B2 (en) * 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
US20040084400A1 (en) * 2002-10-30 2004-05-06 Gregory Costrini Patterning metal stack layers of magnetic switching device, utilizing a bilayer metal hardmask
US7183120B2 (en) * 2002-10-31 2007-02-27 Honeywell International Inc. Etch-stop material for improved manufacture of magnetic devices
US6838354B2 (en) * 2002-12-20 2005-01-04 Freescale Semiconductor, Inc. Method for forming a passivation layer for air gap formation
JP2004259306A (ja) * 2003-02-24 2004-09-16 Hitachi Ltd 磁気記録媒体および磁気記録媒体の製造方法
US6970053B2 (en) * 2003-05-22 2005-11-29 Micron Technology, Inc. Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection
JP4880894B2 (ja) * 2004-11-17 2012-02-22 シャープ株式会社 半導体記憶装置の構造及びその製造方法
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US8233248B1 (en) 2009-09-16 2012-07-31 Western Digital (Fremont), Llc Method and system for providing a magnetic recording transducer using a line hard mask
US8790524B1 (en) 2010-09-13 2014-07-29 Western Digital (Fremont), Llc Method and system for providing a magnetic recording transducer using a line hard mask and a wet-etchable mask
US8486743B2 (en) 2011-03-23 2013-07-16 Micron Technology, Inc. Methods of forming memory cells
US8871102B2 (en) 2011-05-25 2014-10-28 Western Digital (Fremont), Llc Method and system for fabricating a narrow line structure in a magnetic recording head
US8994489B2 (en) 2011-10-19 2015-03-31 Micron Technology, Inc. Fuses, and methods of forming and using fuses
US8546231B2 (en) 2011-11-17 2013-10-01 Micron Technology, Inc. Memory arrays and methods of forming memory cells
US8723155B2 (en) 2011-11-17 2014-05-13 Micron Technology, Inc. Memory cells and integrated devices
US9252188B2 (en) 2011-11-17 2016-02-02 Micron Technology, Inc. Methods of forming memory cells
US8607438B1 (en) 2011-12-01 2013-12-17 Western Digital (Fremont), Llc Method for fabricating a read sensor for a read transducer
US8623468B2 (en) * 2012-01-05 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of fabricating metal hard masks
US8765555B2 (en) 2012-04-30 2014-07-01 Micron Technology, Inc. Phase change memory cells and methods of forming phase change memory cells
US9136467B2 (en) 2012-04-30 2015-09-15 Micron Technology, Inc. Phase change memory cells and methods of forming phase change memory cells
US9553262B2 (en) 2013-02-07 2017-01-24 Micron Technology, Inc. Arrays of memory cells and methods of forming an array of memory cells
US9034564B1 (en) 2013-07-26 2015-05-19 Western Digital (Fremont), Llc Reader fabrication method employing developable bottom anti-reflective coating
US9007719B1 (en) 2013-10-23 2015-04-14 Western Digital (Fremont), Llc Systems and methods for using double mask techniques to achieve very small features
US9881971B2 (en) 2014-04-01 2018-01-30 Micron Technology, Inc. Memory arrays
US9362494B2 (en) 2014-06-02 2016-06-07 Micron Technology, Inc. Array of cross point memory cells and methods of forming an array of cross point memory cells
US9343506B2 (en) 2014-06-04 2016-05-17 Micron Technology, Inc. Memory arrays with polygonal memory cells having specific sidewall orientations
US9705077B2 (en) 2015-08-31 2017-07-11 International Business Machines Corporation Spin torque MRAM fabrication using negative tone lithography and ion beam etching
TWI579970B (zh) * 2015-12-22 2017-04-21 華邦電子股份有限公司 半導體裝置及其製造方法
US11488863B2 (en) 2019-07-15 2022-11-01 International Business Machines Corporation Self-aligned contact scheme for pillar-based memory elements

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Also Published As

Publication number Publication date
JP2005504430A (ja) 2005-02-10
EP1354348A2 (fr) 2003-10-22
CN1488168A (zh) 2004-04-07
KR20030082573A (ko) 2003-10-22
CN1322578C (zh) 2007-06-20
WO2002065475A2 (fr) 2002-08-22
US20020098281A1 (en) 2002-07-25
WO2002065475A8 (fr) 2003-11-20
US6692898B2 (en) 2004-02-17
KR100566146B1 (ko) 2006-03-30
TW560037B (en) 2003-11-01

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