WO2002043157A1 - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
WO2002043157A1
WO2002043157A1 PCT/JP2001/007810 JP0107810W WO0243157A1 WO 2002043157 A1 WO2002043157 A1 WO 2002043157A1 JP 0107810 W JP0107810 W JP 0107810W WO 0243157 A1 WO0243157 A1 WO 0243157A1
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Prior art keywords
layer
region
semiconductor layer
semiconductor device
semiconductor
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PCT/JP2001/007810
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French (fr)
Japanese (ja)
Inventor
Makoto Kitabatake
Toshiya Yokogawa
Osamu Kusumoto
Masao Uchida
Kunimasa Takahashi
Kenya Yamashita
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Matsushita Electric Industrial Co.,Ltd.
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Application filed by Matsushita Electric Industrial Co.,Ltd. filed Critical Matsushita Electric Industrial Co.,Ltd.
Priority to EP01963539A priority Critical patent/EP1315212A4/en
Priority to JP2002544789A priority patent/JP3773489B2/en
Priority to US10/204,097 priority patent/US6580125B2/en
Publication of WO2002043157A1 publication Critical patent/WO2002043157A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H01L29/365—Planar doping, e.g. atomic-plane doping, delta-doping

Definitions

  • the present invention relates to a semiconductor device functioning as a high-breakdown-voltage semiconductor power element arranged in a room or the like, and more particularly to a measure for improving current driving capability and breakdown voltage.
  • an insulated gate electrode and a source electrode are provided on an upper surface side of a semiconductor substrate, and a drain electrode is provided on a lower surface side. It is known that a large current is supplied to the power supply.
  • FIG. 1 is a cross-sectional view of a disclosed semiconductor power device called a DMOS device.
  • the semiconductor power device is formed on a SiC substrate 111 (6H—SiC substrate) containing a high concentration of n-type impurities and a SiC substrate 111.
  • N-SiC layer 112 drift region
  • a source electrode 119 provided on the epitaxial layer to surround the gate electrode 118
  • a drain electrode provided on the lower surface of the SiC substrate 111
  • the layer 113 and the region of the epitaxial layer located below the end of the source electrode 119 are doped with high-concentration n-type impurities. And an n + S i C layer 1 14 that is.
  • the n + SiC layer 114 Functions as a source region, and a region near the boundary with the gate insulating film 1 16 of the 3: 1 layer 113 functions as a channel region, and the SiC substrates 1 1 1 and n—
  • the SiC layer 112 functions as a drain region.
  • the n-SiC layer 112 is generally called a drift region because the carrier moves by drift diffusion.
  • this semiconductor device is formed by forming the pattern of the gate electrode 118 and the source electrode 119 over a wide range of the SiC substrate 111. It is configured so that a large current can flow vertically through a wide area. In particular, since SiC has a large band gap, this semiconductor power element can exhibit higher withstand voltage characteristics than a semiconductor power element using an Si substrate.
  • IGBT is a power device that allows current to flow in the vertical direction.
  • the basic structure of the IGBT is almost the same as the basic structure of the DMOS device, except that the drift region and the semiconductor substrate are of opposite conductivity types.
  • a DMOS device for example, an n-type epitaxial layer is grown on an n-type substrate.
  • an IGBT for example, an n-type epitaxial layer is grown on a p-type substrate.
  • SiC substrate 111 shown in FIG. 4 uses a p-type substrate instead of an n-type substrate, an IGBT is formed. Solution issues
  • a wide depletion layer 115 is formed in the n-SiC layer 112 (drift region) as shown by the broken line in Fig. 4. .
  • the width of the depletion layer 115 becomes narrower on the surface portion of the 11-3; 1 ⁇ layer 112 below the gate electrode 118.
  • the drift layer The electric field applied to the depletion layer 115 at the surface of the 1 ⁇ layer 112 increases, and dielectric breakdown easily occurs at this portion.
  • An object of the present invention is to provide a semiconductor device which functions as a semiconductor power element having a large current driving force and a high withstand voltage by relaxing a trade-off between a low resistance and a high withstand voltage. .
  • a semiconductor device includes a semiconductor substrate, a compound semiconductor layer provided on a main surface of the semiconductor substrate, a gate insulating film provided on the compound semiconductor layer, and a gate insulating film provided on the gate insulating film.
  • a gate electrode provided, a source electrode provided on the compound semiconductor layer beside the gate electrode, a drain electrode provided on a surface of the semiconductor substrate facing the main surface, A source region including a first conductivity type impurity extending from below a part of the source electrode to below an end of the gate electrode in the compound semiconductor layer; and a source region in the compound semiconductor layer below the gate electrode.
  • An active region provided and functioning as a carrier transit region containing a first conductivity type impurity; a drift region provided below the gate electrode in the compound semiconductor layer and containing the first conductivity type impurity; A reverse doping region provided between the drift region and the source region in the compound semiconductor layer and including a second conductivity type impurity, wherein the active region includes at least one first semiconductor At least one layer containing a carrier impurity at a higher concentration than the first semiconductor layer and having a thickness smaller than that of the first semiconductor layer and capable of leaching the carrier into the first semiconductor layer by a quantum effect. And two second semiconductor layers.
  • the active region a quantum level occurs in the second semiconductor layer due to the quantum effect, and the carrier wave function localized in the second semiconductor layer expands to some extent.
  • the carriers are distributed not only in the second semiconductor layer but also in the first semiconductor layer. That is, carriers spread from the second semiconductor layer to the first semiconductor layer due to the quantum effect.
  • the potential of the active region is increased, carriers are constantly supplied to the first and second semiconductor layers. Since carriers flow through the first semiconductor layer having a low impurity concentration, high channel mobility can be obtained by reducing impurity ion scattering.
  • the off state the entire active region is depleted, and the carrier does not exist in the active region.
  • the withstand voltage is defined by the first semiconductor layer having a low impurity concentration, and the high withstand voltage in the entire active region is increased. Will be obtained. Therefore, in a semiconductor device configured to flow a large current between the source and the drain using the active region of the first conductivity type, it is possible to simultaneously achieve high channel mobility and high withstand voltage. .
  • the semiconductor substrate is of the first conductivity type, the above-described effects can be obtained in a semiconductor device functioning as ACCUFET.
  • the semiconductor substrate is of the second conductivity type, the above-described operation and effect can be obtained in a semiconductor device that functions as an IGBT.
  • the active region is provided by laminating a plurality of the first semiconductor layers and the plurality of the second semiconductor layers, the above-described effects can be surely exerted.
  • the second semiconductor layer is a silicon carbide layer, and the thickness of the second semiconductor layer is at least one monolayer and less than 20 nm.
  • the first semiconductor layer is a silicon carbide layer, and the thickness of the first semiconductor layer is not less than 100 ⁇ m and not more than 100 nm.
  • a depletion layer in the lateral direction is provided by further comprising at least one high-concentration doping layer provided across the drift region and containing a first-conductivity-type impurity at a higher concentration than the drift region.
  • the source electrode is provided on a wall surface of the opening, and each of the source region and the reverse doping region is provided.
  • the source electrode can be provided avoiding the area with many defects and the area with a rough surface. Characteristics are obtained.
  • the method of manufacturing a semiconductor device includes a step (a) of forming a compound semiconductor layer of the first conductivity type on the main surface of the semiconductor substrate; (B) forming a reverse doped region by introducing a substance; and forming at least one first semiconductor layer on the compound semiconductor layer and the reverse doped region; At least one second semiconductor containing a carrier impurity at a higher concentration than the body layer and having a thickness smaller than that of the first semiconductor layer and capable of exuding the carrier into the first semiconductor layer by a quantum effect; (C) forming an active region having a layer, and forming a source region by introducing a first conductivity type impurity into at least a region of the active region located above the reverse doped region (d).
  • the source electrode and the reverse-doped region can be brought into contact with each other without injecting impurities of the same conductivity type as the reverse-doped region into the source region in step (e).
  • a semiconductor device functioning as a semiconductor device is formed.
  • the compound semiconductor layer is preferably formed by an epitaxial growth method involving in-situ doping of the first conductivity type impurity.
  • a SiC layer is formed as the compound semiconductor layer and the active region, thereby functioning as a power element using the SiC layer having a wide band gap and high withstand voltage. Is formed.
  • the activation rate of the ion-implanted impurities is low in the SiC layer, so that a defect is likely to occur in the region formed by the ion implantation, but the defect is formed by forming the source electrode in the opening. It is possible to avoid generation of a region including a large amount.
  • FIG. 1 is a sectional view of a DMOS device according to the first embodiment of the present invention.
  • FIG. 2 is a top view showing a cell arrangement of the DMOS device according to the first embodiment of the present invention.
  • FIG. 3 is a cross-sectional view showing an enlarged state of a depletion layer when the cell is off in the DMOS device according to the first embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of a DMOS device disclosed in a conventional document.
  • FIG. 5 is a cross-sectional view showing an enlarged state of a depletion layer when the DMOS device using the conventional SiC substrate shown in FIG. 4 is turned off.
  • FIG. 6 is a cross-sectional view of a DMOS device according to the second embodiment of the present invention.
  • FIGS. 7A to 7D are cross-sectional views showing the first half of the manufacturing process of the DMOS device according to the second embodiment of the present invention.
  • FIGS. 8A to 8D are cross-sectional views illustrating the latter half of the manufacturing process of the DMOS device according to the second embodiment of the present invention.
  • FIGS. 9 (a) and 9 (b) are cross-sectional views respectively showing the difference in current component between the DMOS device and the IGBT.
  • FIG. 10 is a top view showing a cell arrangement of a DMOS device according to a modification of the second embodiment of the present invention.
  • FIG. 11 is a diagram showing current (I) -voltage (V) characteristics of the DMOS device according to the second embodiment of the present invention. Best Embodiment
  • FIG. 1 is a sectional view showing a structure of a DMOS device alone according to the first embodiment of the present invention.
  • FIG. 2 is a top view of the DMOS device of the present embodiment.
  • the SiC substrate 2 (6H-) in which the main surface containing the high-concentration n-type impurity is the (001) off surface is used.
  • a gate insulating film 6 provided on the epitaxial layer and a gate electrode 7a thereon, and a source electrode 7b provided on the epitaxial layer so as to surround the gate electrode 7a.
  • a high concentration n-type impurity is doped into the p-SiC layer 4 and the region of the epitaxial layer located below the end of the source electrode 7b and below the end of the gate electrode 7a. And an n + S i C layer 5 formed as described above.
  • the first feature of the present embodiment is that the ⁇ + dove layer 10 (active region) is formed in a region of the surface of the epitaxial layer other than the portion where the ⁇ + SiC layer 5 is formed. Is provided.
  • the DMOS device of the present embodiment functions as a so-called AC CUFET (Accumulation Mode FET).
  • the multiple (5-doped layer 10) has a high concentration (for example, 1 ⁇ 10 18 atoms ⁇ cm 3 ) of nitrogen having a thickness of about 10 nm.
  • the lowermost layer is constituted by an AND layer 10b, that is, the total thickness is about 350 nm.
  • the n + S i C layer 5 functions as a source region
  • the multiplex (the five-doped layer 10 functions as a channel region
  • the 31 ⁇ substrate 2 and 1 — S i C layer 3 Function as a drain region.
  • a quantum level is generated in the n-type doped layer 10 a by the quantum effect, and the wave function of the electrons localized in the n-type doped layer 10 a is expanded to some extent. Become a member. As a result, the distribution state is such that electrons exist not only in the n-type doped layer 10a but also in the and-doped layer 10b.
  • this semiconductor power element When this semiconductor power element is turned on, a voltage of about 5 V is applied to the gate electrode 7a, the source electrode 7b is grounded, and a voltage of about 600 V is applied to the drain electrode 7c. At this time, the potential of the multi-layer (5 doped layer 10) is increased, and the quantum effect spreads the electron wave function from the n-type doped layer 10a to the AND layer 10b. Electrons are constantly supplied to the 10 a and the amplifying layer 10 b. Since the electrons flow through the undoped layer 10 b having a low impurity concentration, a high channel mobility can be obtained by reducing impurity ion scattering. When a current flows, the drain voltage drops to several volts.
  • the entire active region (the region corresponding to the multiply-doped layer 10 in the present embodiment) except the source / drain regions has a substantially uniform impurity concentration.
  • increasing the impurity concentration increases the amount of supplied electrons.
  • the impurity concentration of the active region except the source 'drain region is made from approximately 1 X 1 0 16 cm one 3 1 X 1 0 17 cm one 3.
  • the doped layer has a high impurity concentration but a very thin layer thickness, so that the undoped layer has a large thickness and a low impurity concentration. This suppresses the decrease in breakdown voltage.
  • the drain voltage drops to several volts.
  • a current flows in a wide range through the entire multiple ⁇ -doped layer 10 below the gate electrode 7a, and a particularly high current value is obtained.
  • the entire multi-layer (the five-doped layer 10 is depleted, and no electrons are present in the multi-layer (the five-doped layer 10).
  • the withstand voltage is defined by the low AND layer 10b, and a high withstand voltage value can be obtained in the entire multiple (5 doped layer 10).
  • a high channel mobility and a high withstand voltage are simultaneously realized in the ACCUFET configured to allow a large current to flow between the source and drain regions using the multiplexed (5-doped layer 10). It becomes possible to do.
  • the multi-layer (the gate insulating film 6 ⁇ the gate insulating film—the multi-layer (in the vicinity of the interface between the five-doped layers)
  • the multi-layer it is possible to improve the channel mobility by reducing the charges trapped in the semiconductor device, improve the channel mobility by reducing the impurity ion scattering, and improve the breakdown voltage.
  • ACCUFET is characterized by a large saturation current value and a small on-resistance.
  • One of the major reasons that ACC FET has not yet been put to practical use is that it has a poor breakdown voltage in the off state.
  • the off-state is achieved while further improving the current driving force by using the laminated structure of the five-doped layer and the In this embodiment, a high concentration doped layer ( ⁇ 5 doped layer) and a low concentration doped layer (AND layer) are alternately stacked.
  • the doped layer 10 may have only one high-concentration doped layer and one low-concentration doped layer.
  • One low-concentration doping layer (undoped layer) may be disposed above and below the one high-concentration doping layer, respectively.
  • the number of layers and the number of lightly doped layers may be different.
  • the part is preferably an undoped layer.
  • the second feature of the present embodiment is that the n-SiC layer 3 contains two high-concentration (eg, IX 10 18 atoms ⁇ cm 3 ) nitrogen layers having a thickness of about 100 nm.
  • the point is that the doped layers 8a and 8b are provided. And these two highly doped layers 8 The interval between a and 8b is about 500 nm.
  • FIG. 5 is a cross-sectional view showing an enlarged state of a depletion layer at the time of off in the DMSO device using the conventional SiC substrate shown in FIG.
  • the gate electrode 118 for example, 0 V
  • the source electrode 119 is grounded
  • a voltage of about 600 V is applied to the drain electrode 117.
  • the depletion layer 109 expands in the vertical and horizontal directions in the n-SiC layer 112.
  • the spread of the depletion layer in the horizontal direction indicated by the arrow X in the figure is smaller than that in the vertical direction (thickness direction) indicated by the arrow y in the figure.
  • the interval between the equipotential surfaces 109a in the horizontal direction is narrower than the interval between the equipotential surfaces 109a in the vertical direction.
  • the electric field in the depletion layer 109 becomes largest near the edge of the lower end face of the gate electrode 118, and dielectric breakdown (breakdown) tends to occur in this portion.
  • FIG. 3 shows a DM of this embodiment in which a heavily doped layer is provided in the n-SiC layer 112.
  • FIG. 4 is a cross-sectional view showing an enlarged state of a depletion layer in a single cell of the 0S device when the cell is off.
  • an off voltage is applied to the gate electrode 7a (for example, 0 V) and the source electrode 7b is grounded and a voltage of about 600 V is applied to the drain electrode 7c, n ⁇ S
  • the depletion layer 9 spreads in the vertical and horizontal directions.
  • the heavily doped layer functions like an electrode inserted in the drift region (here, n-SiC layer 3). Therefore, when the depletion layer 9 spreads in the vertical direction (thickness direction) indicated by the arrow y in the figure and comes into contact with the high-concentration doped layers 8a and 8b, the further downward depletion of the depletion layer 9 increases. Since the depletion layer 9 is once suppressed by 8a and 8b, the expansion of the depletion layer 9 in the horizontal direction indicated by the arrow X in the figure is larger than that in the vertical direction.
  • the interval between the equipotential surfaces 9a in the horizontal direction is wider than the interval between the equipotential surfaces 9a in the vertical direction.
  • the concentration of the electric field near the edge of the lower end face of the gate electrode 7a is almost eliminated.
  • the equipotential lines 9a in the depletion layer 9 are formed almost parallel to the high-concentration doped layers 8a and 8b, the vertical electric field in the depletion layer 9 is wide without being locally concentrated. Occurs uniformly in the range. Therefore, dielectric breakdown (breakdown) is unlikely to occur. Therefore, the DMOS device of the present invention has a higher withstand voltage (at least about 600 V) than the conventional DMOS device shown in FIG.
  • the multiple (5 doped layers 10 and the high concentration doped layers 8 a and 8 b are provided, but by providing only one of them, the DMOS device The withstand voltage value can be increased.
  • a multiplexed (5-doped layer 10)
  • it functions as ACCUFET, so that a characteristic with a high saturation current value can be obtained.
  • the high concentration dove layer is not limited to only one layer as in the present embodiment, but may be only one layer or two or more layers. In general, it can be said that the larger the number of high-concentration doped layers, the higher the breakdown voltage of the DMOS device.
  • an n + type SiC substrate 2 whose main surface has an orientation deviated from the (00001) plane (C plane) by several degrees is prepared.
  • the diameter of the SiC substrate 2 is 25 mm.
  • silane gas with a flow rate of 3 (ml / min.) Introduce within.
  • the source gas is diluted with a hydrogen gas at a flow rate of 50 (m 1 / min.).
  • a low-concentration (about 1 ⁇ 10 16 atoms ⁇ cm— 3 ) nitrogen is formed on the main surface of the SiC substrate 2.
  • An nSiC layer 3 having a thickness of about 10 ⁇ m and made of an n-type SiC single crystal containing that time , N- to S i C layer 3 in the middle of second force plants, the impurity concentration of, for example 1 x 1 0 18 atoms - cm one 3 about two high concentration de one flop layer 8 a, to form a 8 b.
  • a doping gas is used.
  • a pulse valve is provided between the high-pressure cylinder and the doping gas supply pipe.
  • a multi-doped layer 10 is formed by the following procedure.
  • the n-type doped layer 10a is formed by simultaneously opening and closing the pulse valve and introducing the doping gas (nitrogen) while supplying the source gas and the diluent gas, and closing the pulse valve.
  • the formation of the AND layer 10b by supplying only the source gas and the diluent gas without supplying the doping gas is repeated five times each.
  • an AND layer 10b having a thickness of 5 O nm is formed on the uppermost layer.
  • a multi-doped layer 10 having a thickness of about 350 nm is formed.
  • the thickness of the undoped layer 10b occupying the uppermost layer of the multiple doped layer 10 may be about 50 nm thicker than the other doped layers 10b.
  • the threshold voltage of the DMOS device is increased. Therefore, the channel mobility and the threshold voltage due to the adverse effect of the interface state at the interface between the gate insulating film and the multi-doped layer are adjusted to desired conditions.
  • the thickness of the uppermost AND layer 10b can be determined.
  • n + S i C layer 5 of 0 ⁇ m is formed, and a p-type impurity is ion-implanted into a portion below the source electrode 7 b to form an upper portion 4 a of the p—S i C layer 4.
  • the source electrode 7b is brought into direct contact with the p-SiC layer 4 to control the potential of the reversely doped region and to reduce the DMO S when a reverse current flows. It is necessary to prevent the destruction of the device.In terms of the latter, usually, the load of a DMOS device is often an inductive load (a load containing a large amount of an L component such as a motor coil).
  • a reverse voltage is applied between the source and drain by electromagnetic induction. That is, for a moment, the drain potential is lower than the source potential, so that a voltage is applied in the forward direction to the PN diode composed of the p-SiC layer 4 and the n-SiC layer 3, and a large current ⁇ Flow between the drains If there is the same n-type surface layer as the active region between the source electrode 7b and the p-SiC layer 4, the n-type surface layer and p-Si Since a reverse bias is applied to the surface PN junction between the C layer and the surface PN junction, the surface PN junction becomes a resistor and generates heat, which may cause the device to be destroyed.
  • the surface PN junction is prevented from forming.
  • a gate insulating film 6 made of a silicon oxide film or the like is formed on the substrate.
  • a source electrode 7b and a drain electrode 7c made of a Ni alloy film formed by a vacuum evaporation method are formed. Further, annealing is performed at 100 ° C. for 3 minutes to obtain an ohmic contact between the source / drain electrodes 7 a and 7 b and the underlying layer. Then, a gate electrode 7a made of a Ni film and having a gate length of about 5 ⁇ m is formed.
  • the gate voltage dependence of the current-voltage characteristics (the relationship between the drain current and the drain voltage) of the DMOS device (AC CUFE T) formed by the above process was compared with the conventional DMOS device. It was found that the saturation current was further increased. In addition, a stable drain current is obtained without blurring one Kudaun in the drain voltage 40 0 V or more, the dielectric breakdown voltage in the off state is a 6 0 0 V or higher, as low as even on resistance 1 ⁇ . Cm 2 The value has been realized.
  • the thickness of the doping layer does not need to be unnecessarily thick as long as the wave function of electrons from the doped layer to the undoped layer is effectively leached.
  • the thickness of the n-type doped layer 10a is 20 monolayers or more when the SiC layer is used. It has been found that a value of less than nm is preferable.
  • the thickness of the undoped layer 10b may be about 10 nm, as long as the wave function of electrons from the upper and lower doped layers in contact with the undoped layer extends over the range. The thickness is preferably about 100 nm or less.
  • a compound semiconductor layer other than the SiC layer may be used.
  • the thickness of the highly doped layer (5-doped layer) depends on the material. The appropriate thickness is determined according to the conditions. For example, when a GaAs layer is used, one monolayer and one doping layer can be provided. In general, as long as the carrier supply capacity can be maintained properly, it can be said that the thinner the high-concentration doped layer ((5 doped layer), the better) in order to improve the breakdown voltage with the same thickness. .
  • the uppermost layer of the layer 10 is preferably an undoped layer, and its thickness must be at least not less than a thickness that changes into an oxide film. For example, to form a thermal oxide film having a thickness of 40 nm, an AND layer having a thickness of at least 20 nm is required.
  • the following second embodiment can be performed by the same manufacturing method as the present embodiment. It is possible to prototype IGBT (see Fig. 9 (b)) as described in the form. In this case, instead of nickel, the drain electrode 7c may be replaced with nickel by a metal film (for example, an aluminum film, a laminated film of an aluminum film and a nickel film or a titanium film, Alloy film made of an alloy of aluminum and nickel or titanium). I GB T obtained by this manufacturing method The on-resistance of was further lowered 0. 7 mQ 'cm 2. Modification 1 regarding one plane shape
  • the planar shape of the AC CUFET cell of the present invention is not necessarily limited to a square, and various shapes may be used. Can be taken.
  • the planar shape of the AC CUFET (or IGBT) cell can be made hexagonal. Since the SiC crystal is hexagonal, by forming an ACCUFET (or IGBT) having a hexagonal planar shape with six sides parallel to the direction of its crystal axis (A axis), the carrier The mobility can be improved.
  • the source electrode 7b is brought into direct contact with the p-SiC layer 4, which is a reverse-doped region, the multiple 6-doped layer provided on the P-SiC layer 4 is formed.
  • P-type impurities are ion-implanted into the layer 10 or a part of the n + SiC layer 5 to form the upper part 4a of the pSiC layer 4.
  • a source electrode 7b that comes into contact with the p-SiC layer 4 is provided.
  • n-type doped layer 10a or n + SiC layer 5 a highly doped n-type layer (n-type doped layer 10a or n + SiC layer 5) is obtained.
  • Type impurities must be implanted. Aluminum or boron is used as the p-type impurity in the SiC layer, but the activation rate of these impurities after ion implantation is from several percent to several ten percent, so an extremely high implantation dose is required. Becomes However, in the SiC layer where it is difficult to recover implantation defects, the ion-implanted region containing such a high-dose impurity becomes a high-resistance region, so that a large resistance loss occurs when a current flows through this region.
  • FIG. 6 is a cross-sectional view of the DMOS device according to the present embodiment. Also in the present embodiment, the planar shape of the DMOS device is as shown in FIG. Shown in the figure
  • the DMOS device according to the present embodiment includes the S i C substrate 2 (6H-S i C substrate) in which the main surface containing the high-concentration n-type impurity is the (001) off surface, n—SiC layer 3 (drift region) containing low-concentration n-type impurities provided in an epitaxial layer formed on iC substrate 2, and a gate provided on the epitaxial layer An insulating film 6 and a gate electrode 7a thereon, a source electrode 7b provided on the epitaxial layer so as to surround the gate electrode 7a, and a source electrode 7b provided on the lower surface of the SiC substrate 2.
  • S i C substrate 2 (6H-S i C substrate) in which the main surface containing the high-concentration n-type impurity is the (001
  • the feature of the DMOS device of the present embodiment is different from the DMOS device of the first embodiment in that an opening is formed in a part of the multiplex ⁇ 5 doping layer 10 and the n + SiC layer 5. This is that a part of the p-SiC layer 4 is exposed at the bottom of the opening, and the source electrode 7b is in contact with the exposed part of the p-SiC layer 4.
  • the multi-layer (5 doped layer 10 (active region) is provided in the region of the surface portion of the epitaxial layer other than the portion where the n + S i C layer 5 is formed.
  • the point that the MOS device functions as an ACCUFET (Accumulation Mode FET) is the same as the DMOS device of the first embodiment, and the structure of the multiplexed 6-doped layer 10 is the same as that of the first embodiment.
  • the multi-doped layer 10 of the present embodiment has an undoped layer 10 b (low Concentration doped layer) (impurity concentration is about 5 ⁇ 10 15 cm 3 ) and 11-type doped layer with thickness of about 11011111 10 & (high concentration doped layer) (impurity concentration is about 1 ⁇ 10 18 cm 3 ) alternately, and then an undoped layer 10 b with a thickness of 40 nm is provided on the uppermost layer, for a total thickness of about 240 nm.
  • an undoped layer 10 b low Concentration doped layer
  • impurity concentration is about 5 ⁇ 10 15 cm 3
  • 11-type doped layer with thickness of about 11011111 10 & high concentration doped layer
  • impurity concentration is about 1 ⁇ 10 18 cm 3
  • the n + SiC layer 5 functions as a source region
  • the multiple d-doped layer 10 functions as a channel region
  • the 310 substrates 2 and 11—SiC layers 3 Functions as a drain region.
  • an n + -type SiC substrate 2 whose main surface has an orientation shifted from the (001) plane (C plane) by several degrees is prepared.
  • the diameter of the SiC substrate 2 is 50 mm, and the concentration of the n-type impurity is 1 ⁇ 10 18 cm— 3 .
  • the SiC substrate 2 is set in the chamber of the CVD apparatus, and the pressure in the chamber is reduced to a degree of vacuum of about 10 to 6 Pa (10 to 8 Torr).
  • hydrogen gas at a flow rate of 2 (1 / min.) And argon gas at a flow rate of 1 (1 / min.) are supplied as dilution gases into the chamber, and the pressure in the chamber is reduced to 0.093.
  • the substrate temperature is controlled to about 160 ° C. as MPa.
  • a propane gas with a flow rate of 2 (m1 / min.) And a silane gas with a flow rate of 3 (m1 / min.) Introduce within one.
  • the source gas is diluted with a hydrogen gas at a flow rate of 50 (ml / min.).
  • a pulse valve for supplying a driving gas and in-situ doping with nitrogen By opening a pulse valve for supplying a driving gas and in-situ doping with nitrogen, a low concentration (110 16 atoms ⁇ cm— 3 11-3; 1 ⁇ layer 3 composed of n-type S i C single crystal containing nitrogen (about 1). '
  • the doping is performed so that a hydrogen gas containing about 10% of nitrogen can be supplied as a doping gas.
  • the gas is stored in a high-pressure cylinder, and a pulse valve is provided between the high-pressure cylinder and the doping gas supply pipe.
  • n- S i after forming an implantation mask consisting of S i 0 2 on the C layer 3 (not shown), S i C substrate 2 5 0 0
  • ions of aluminum (A 1) which is a p-type impurity
  • a 1 ions of aluminum
  • the non-implanted area on the surface is removed by reactive ion etching (RIE), and then in an argon gas atmosphere, at a temperature of 170 ° C.
  • annealing for activation is performed to form a P-SiC layer 4 which is a reverse doped region.
  • annealing for activation is performed after RIE, but RIE may be performed after annealing for activation.
  • RIE reactive ion etching
  • a multiplexed lead layer 10 is formed by the following procedure.
  • the pulse valve is closed without changing the conditions such as the supply amount of the source gas and the dilution gas and the temperature when the n-SiC layer 3 is formed.
  • the pulse valve is opened and the gas (doping gas) containing aluminum, which is a p-type impurity, is supplied in a pulsed manner without changing the conditions such as the supply amount of diluent gas, source gas, and temperature in the chamber.
  • an n-type doped layer 10a (highly doped layer) with a thickness of about 10 nm (impurity concentration of about 1 ⁇ 10 1 B cm 3 ) is formed on the AND layer 10b.
  • the n-type doped layer 10a is formed by simultaneously opening and closing the pulse valve and introducing the doping gas (nitrogen) while supplying the source gas and the diluent gas, and closing the pulse valve.
  • the formation of the AND layer 10b by supplying only the source gas and the dilution gas without supplying the doping gas is repeated four times each.
  • an AND layer 10b having a thickness of 4 O nm is formed on the uppermost layer.
  • a multiple 5-doped layer 10 having a thickness of about 24 O nm is formed.
  • the thickness of the undoped layer 10b occupying the uppermost layer of the multiple undoped layer 10 may be made about 50 nm thicker than the other undoped layers 10b. Since the threshold voltage of the DMOS device is increased, the channel mobility and the threshold voltage due to the adverse effect of the interface state at the interface between the gate insulating film and the multi-doped layer should be adjusted to the desired conditions. The thickness of the upper undoped layer 10b can be determined.
  • an implantation mask made of SiO 2 shown in FIG. After forming
  • a high concentration of n-type impurity which is an n-type impurity, is introduced into the multiple doped layers 10 from above the implantation mask.
  • the ion implantation of nitrogen (N) is performed so that the implantation depth becomes 300 nm.
  • annealing for activation is performed at 160 ° C. in a SiC petri dish to form an n + SiC layer 5 serving as a source region.
  • n + SiC layer 5 penetrates the multi-doped layer 10 and its lower end is in contact with the pSiC layer 4. Since the n + S i C layer 5 as the source region preferably contacts all the semiconductor layers of the multiple ⁇ -doped layer 10, the depth of the n + S i C layer 5 is It is preferable that the thickness is larger than the thickness.
  • a part of the n + Sic layer 5 (source region) is removed to expose the surface of the p-SiC layer 4.
  • an aluminum thin film is deposited on the substrate by vapor deposition, and the aluminum thin film is patterned by photolithography and dry etching to form an etching mask (not shown).
  • the depth of the opening 20 needs to be at least deeper than the depth of the n + SiC layer 5 (source region).
  • the etch rate is 67 nm / min.
  • the etch rate is almost the same as when etching layer 4, and can be regarded as almost constant. Therefore, the depth of the opening 20 can be controlled by the etching time.
  • a thermal oxide film to be the gate insulating film 6 was formed on the substrate.
  • the surface area of each layer on the SiC substrate 2 is thermally oxidized at 110 ° C for 3 hours in a steam atmosphere bubbled with oxygen at a flow rate of 2.5 (1 / min.).
  • a thermal oxide film having a thickness of about 40 nm is formed on the surface of the substrate.
  • an opening is formed on the thermal oxide film serving as the gate insulating film 6.
  • a region of the thermal oxide film located in the opening portion 20 of the resist mask is removed by buffered hydrofluoric acid.
  • the surface of each of the p-SiC layer 4 and the n + SiC layer 5 is exposed in the opening 20 and the periphery thereof.
  • a source electrode 7b is formed on the surface of each of the exposed p-SiC layer 4 and n + SiC layer 5 by a lift-off method.
  • the source electrode 7b is formed by the lift-off method in the following procedure.
  • a nickel film with a thickness of about 200 nm is deposited on the substrate by electron beam evaporation, and the entire substrate is immersed in an organic solvent to form the p-SiC layer of the nickel film. Except for the part in contact with each part of 4 and n + SiC layer 5, the other part is peeled off from the substrate.
  • a Ni alloy film having a thickness of about 200 nm is deposited on the rear surface of the SiC substrate 2 by a vacuum evaporation method, thereby forming a drain electrode 7c made of: Further, annealing is performed in N 2 gas at 100 ° C. for 3 minutes at a temperature of 100 ° C. in order to obtain an ohmic contact between the source and drain electrodes 7 b and 7 c and the underlying layer.
  • an aluminum film (not shown) having a thickness of about 200 nm is formed on the substrate by electron beam evaporation, and then photolithography and drying are performed.
  • the aluminum film is patterned to form a gate electrode 7a having a gate length of about 10 / zm.
  • FIG. 11 is a diagram showing a current (I) -voltage (V) characteristic of the DMOS device (AC CUFET) of the present embodiment. As shown in the figure, the saturation current is further increased compared to the conventional DMOS device.
  • the DMOS device of the present embodiment basically the same operational effects as the DMOS device of the first embodiment can be exerted.
  • the source electrode 7b is formed above the opening 20 formed in the n + SiC layer 5, it can be used for high dose ion implantation. Therefore, it is in contact with the P—SiC layer 4 without generating a region whose surface is roughened or a region where many defects exist due to high dose ion implantation. As a result, there is an advantage that the resistance under the source electrode 7b when the reverse current flows through the multiplexed (5-doped layer 10) is low, and the resistance loss due to the reverse current is lower than in the first embodiment.
  • the drain electrode 7c may be replaced with nickel by a metal film (for example, an aluminum film, a laminated film of an aluminum film and a nickel film or a titanium film, Alloy film made of an alloy of aluminum and nickel or titanium).
  • a metal film for example, an aluminum film, a laminated film of an aluminum film and a nickel film or a titanium film, Alloy film made of an alloy of aluminum and nickel or titanium.
  • FIG. 9 (a) and 9 (b) are cross-sectional views showing the currents flowing through the DMOS device and the IGBT in order.
  • the SiC substrate 2 and the drift region (n—SiC layer 3) are both n-type layers, the DMOS device When is turned on, only electron current flows.
  • the SiC substrate 2 is a p-type layer and the drift region (n—SiC layer 3) is an n-type layer.
  • the IGBT of the present embodiment can be said to be a structure suitable for a high withstand voltage type device having a withstand voltage design value of about several kV.
  • planar shape of the AC CUFET cell of the present invention is not necessarily limited to a square. It can take various shapes.
  • FIG. 10 is a plan view of a modification of the present embodiment in which the planar shape of the AC CUF ET (or I GB T) cell is hexagonal. Each cell is arranged at equal intervals, and a honeycomb-shaped gate electrode ⁇ ⁇ ⁇ a is provided.
  • ACCUFETs or IGBTs
  • ACCUFETs are less susceptible to dielectric breakdown when depletion layers extending from adjacent cells are connected to each other.
  • the distance between adjacent vertices in the diagonal direction is larger than the distance between sides of adjacent cells. That is, even if the depletion layer is connected between the sides of adjacent cells, a region that is not connected between the adjacent vertices may remain. As a result, dielectric breakdown is likely to occur.
  • the planar shape of the AC CUFET (or IGBT) cell of the present invention is not necessarily limited to a square or a hexagon, and may take various shapes.
  • the gate electrode 7a can be formed first.
  • an aluminum film in this example, coincident with the gate electrode
  • n-type impurities is performed. Thereafter, an opening is formed to reach the p-SiC layer 4 through the n + SiC layer 5, and a source electrode 7b is formed.
  • the source region (n + SiC layer 5) can be formed in a self-aligned manner with the gate electrode 7a, so that the semiconductor device functioning as a fine AC CUFET or IGBT. Is obtained.
  • a portion functioning as a channel region below a gate electrode is formed by a first semiconductor layer and a first semiconductor.
  • the first semiconductor layer contains a carrier impurity at a higher concentration than the first semiconductor layer, is thinner than the first semiconductor layer, and is capable of exuding carriers into the first semiconductor layer by a quantum effect.
  • Carriers are supplied from the first semiconductor layer including the high-concentration impurity layer, and the carrier travels through the second semiconductor layer, which is low in impurities and has good crystallinity. It can be realized.
  • the semiconductor device of the present invention is used for devices such as an AC CUFET, a vertical MOS FET, a DMOS device, and an IGBT mounted on an electronic device, particularly, a device that handles a high-frequency signal and a power device. .

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Abstract

A DMOS device (or IGBT) comprises a SiC substrate (2), an n-SiC layer (3) (drift region) provided in an epitaxial layer, a gate insulation film (6) and a gate electrode (7a), a source electrode (7b) so provided as to surround the gate electrode (7a), a drain electrode (7c) provided on the lower surface of the SiC substrate (2), a p-SiC layer (4), and an n+ SiC layer 3 formed over a range from the lower part of the end of the source electrode (7b) to the lower part of the end of the gate electrode (7a). A region except the part of the surface part of the epitaxial layer where an n+ SiC layer 5 is formed has a laminate of an n-type doped layer (10a) containing a high concentration of nitrogen and an undoped layer (10b). A decrease in on-resistance and an improvement in withstand voltage on the off-time can be attained by utilizing a quantum effect.

Description

曰月糸田 » 半導体装置およびその製造方法 技術分野  Satsuki Itoda »Semiconductor device and manufacturing method
本発明は、 ィンバ一夕等に配置される高耐圧半導体パワー素子として機能する 半導体装置に係り、 特に、 電流駆動能力と耐圧との向上対策に関するものである  The present invention relates to a semiconductor device functioning as a high-breakdown-voltage semiconductor power element arranged in a room or the like, and more particularly to a measure for improving current driving capability and breakdown voltage.
背景技術 Background art
従来より、 インバー夕等に配置される半導体パワー素子として、 半導体基板の 上面側に絶縁ゲート電極及びソース電極を設け、 下面側にドレイン電極を設けて 、 半導体基板の広い面積を利用して上下方向に大電流を流すようにしたものが知 られている。  Conventionally, as a semiconductor power element arranged in an inverter or the like, an insulated gate electrode and a source electrode are provided on an upper surface side of a semiconductor substrate, and a drain electrode is provided on a lower surface side. It is known that a large current is supplied to the power supply.
図 4は、 文献 (Silicon Carbide; A Review of Fundamental Questions and A pplications to Current Device Technology, edited by W. J. Choyke,H.Matsuna mi, and G.Pensl, Akademie Verlag 1997 Vol.11 pp.369-388 ) に開示されてい る DM0 Sデバイスと呼ばれる半導体パワー素子の断面図である。  Figure 4 is shown in the literature (Silicon Carbide; A Review of Fundamental Questions and Applications to Current Device Technology, edited by WJ Choyke, H. Matsunami, and G. Pensl, Akademie Verlag 1997 Vol.11 pp.369-388). FIG. 1 is a cross-sectional view of a disclosed semiconductor power device called a DMOS device.
同図に示すように、 半導体パワー素子は、 高濃度の n型不純物を含む S i C基 板 1 1 1 ( 6 H— S i C基板） と、 S i C基板 1 1 1の上に形成されたェピタキ シャル層内に設けられた低濃度の n型不純物を含む n— S i C層 1 1 2 (ドリフ ト領域） と、 ェピタキシャル層の上に設けられたゲート絶縁膜 1 1 6及びその上 のゲート電極 1 1 8と、 ェピタキシャル層の上でゲート電極 1 1 8を囲むように 設けられたソース電極 1 1 9と、 S i C基板 1 1 1の下面に設けられたドレイン 電極 1 1 7と、 ェピタキシャル層のうちソース電極 1 1 9の下方に位置する領域 からゲート電極 1 1 8の端部下方に位置する領域に p型不純物をドープして形成 された ー 3 ;1〇層 1 1 3と、 ェピタキシャル層のうちソ一ス電極 1 1 9の端部 下方に位置する領域に高濃度の n型不純物をドープして形成された n+ S i C層 1 14とを備えている。 この半導体パワー素子において、 n+ S i C層 1 1 4が ソース領域として機能し、 — 3 :1〇層 1 1 3のぅちゲ一ト絶縁膜 1 1 6との境 界付近の領域がチャネル領域として機能し、 S i C基板 1 1 1及び n— S i C層 1 1 2がドレイン領域として機能する。 ただし、 n— S i C層 1 1 2は、 キヤリ ァがドリフ ト拡散により移動することから、 一般にはドリフ ト領域と呼ばれてい る。 半導体パワー素子をオンする時には、 ゲ一ト電極 1 1 8に 5 V程度の電圧を 印加して、 ソース電極 1 1 9を接地し、 ドレイン電極 1 1 7に数 Vの電圧を印加 する。 このとき、 通常の MO S F E Tと同様の動作によって、 n— S i C層 1 1 2のうちゲート電極 1 1 8の下方に位置する領域から p— S i C層 1 1 3を経て n+ S i C層 1 14に電流が流れる。 As shown in the figure, the semiconductor power device is formed on a SiC substrate 111 (6H—SiC substrate) containing a high concentration of n-type impurities and a SiC substrate 111. N-SiC layer 112 (drift region) containing a low-concentration n-type impurity provided in the formed epitaxial layer, gate insulating film 116 provided on the epitaxial layer, and A gate electrode 118 on top of it, a source electrode 119 provided on the epitaxial layer to surround the gate electrode 118, and a drain electrode provided on the lower surface of the SiC substrate 111 And a region formed by doping a p-type impurity from a region located below the source electrode 119 to a region located below the end of the gate electrode 118 in the epitaxial layer. 〇 The layer 113 and the region of the epitaxial layer located below the end of the source electrode 119 are doped with high-concentration n-type impurities. And an n + S i C layer 1 14 that is. In this semiconductor power device, the n + SiC layer 114 Functions as a source region, and a region near the boundary with the gate insulating film 1 16 of the 3: 1 layer 113 functions as a channel region, and the SiC substrates 1 1 1 and n— The SiC layer 112 functions as a drain region. However, the n-SiC layer 112 is generally called a drift region because the carrier moves by drift diffusion. When the semiconductor power element is turned on, a voltage of about 5 V is applied to the gate electrode 118, the source electrode 119 is grounded, and a voltage of several V is applied to the drain electrode 117. At this time, by the same operation as that of a normal MOS FET, n + Si from the region located below the gate electrode 118 in the n-SiC layer 112 through the p-SiC layer 113 A current flows through the C layer 114.
すなわち、 この半導体パヮ一素子 （DMO Sデバイス） は、 ゲート電極 1 1 8 及びソース電極 1 1 9のパターンを S i C基板 1 1 1の広い範囲に亘つて形成し ておく ことで、 基板の広い領域を通って縦方向に大電流を流すことができるよう に構成されている。 また、 特に、 S i Cはバンドギヤヅプが大きいので、 この半 導体パワー素子は、 S i基板を用いた半導体パワー素子に比べると高い耐圧特性 を発揮することができる。  In other words, this semiconductor device (DMOS device) is formed by forming the pattern of the gate electrode 118 and the source electrode 119 over a wide range of the SiC substrate 111. It is configured so that a large current can flow vertically through a wide area. In particular, since SiC has a large band gap, this semiconductor power element can exhibit higher withstand voltage characteristics than a semiconductor power element using an Si substrate.
また、 縦方向に電流を流すパワーデバイスとして I GB Tがある。 I GB Tの 基本構造は、 DMO Sデバイスの基本構造とほぼ同じであるが、 ドリ フ ト領域と 半導体基板とが互いに逆導電型である点だけが異なる。 D MO Sデバイスにおい ては、 例えば n型基板上に n型ェピタキシャル層を成長させるが、 I GB Tの場 合、 例えば p型基板上に n型ェピタキシャル層を成長させる。 例えば、 図 4に示 す S i C基板 1 1 1を n型でなく p型基板を用いると I GB Tが形成される。 解決課題  IGBT is a power device that allows current to flow in the vertical direction. The basic structure of the IGBT is almost the same as the basic structure of the DMOS device, except that the drift region and the semiconductor substrate are of opposite conductivity types. In a DMOS device, for example, an n-type epitaxial layer is grown on an n-type substrate. In the case of an IGBT, for example, an n-type epitaxial layer is grown on a p-type substrate. For example, if the SiC substrate 111 shown in FIG. 4 uses a p-type substrate instead of an n-type substrate, an IGBT is formed. Solution issues
ところが、 上記従来の DMO Sデバイス、 I GB Tなどの半導体パワー素子に おいては、 以下のような不具合があった。  However, the following problems have been encountered in the above-described conventional semiconductor power devices such as DMOS devices and IGBTs.
DMO Sデバイスまたは I GB Tに逆バイァスが印加されると、 図 4の破線で 示すように、 n— S i C層 1 1 2 (ドリフ ト領域） において広い空乏層 1 1 5が 形成される。 このとき、 11— 3 ;1〇層 1 1 2のぅちゲート電極 1 1 8の下方に位 置する表面部においては、 空乏層 1 1 5の幅が狭くなる。 その結果、 ドリ フ ト層 でぁる 11ー3 ;1〇層 1 1 2の表面部において空乏層 1 1 5に印加される電界が大 きくなり、 この部分で絶縁破壊を起こし易くなる。 When a reverse bias is applied to the DMOS device or IGBT, a wide depletion layer 115 is formed in the n-SiC layer 112 (drift region) as shown by the broken line in Fig. 4. . At this time, the width of the depletion layer 115 becomes narrower on the surface portion of the 11-3; 1〇 layer 112 below the gate electrode 118. As a result, the drift layer The electric field applied to the depletion layer 115 at the surface of the 1〇 layer 112 increases, and dielectric breakdown easily occurs at this portion.
また、 上記従来の D M O Sまたは I G B Tにおいて、 耐圧性を向上させるには p— S i C層 1 1 3の不純物濃度を高くする必要があるが、 その場合にはチヤネ ル抵抗が増大するので電流駆動力が低減する。 すなわち、 低抵抗化と高耐圧化と はト レ一ドオフの関係があり、 半導体パワーデバイスの性能の向上に限界があつ た。 発明の開示  Also, in the above-mentioned conventional DMOS or IGBT, it is necessary to increase the impurity concentration of the p-SiC layer 113 in order to improve the withstand voltage. In that case, however, the channel resistance increases, so that the current drive is performed. The force is reduced. In other words, there is a trade-off between low resistance and high breakdown voltage, and there is a limit to improving the performance of semiconductor power devices. Disclosure of the invention
本発明の目的は、 低抵抗化と高耐圧化とのトレ一ドオフを緩和することにより 、 電流駆動力の大きい、 かつ、 耐圧の大きい半導体パワー素子として機能する半 導体装置を提供することにある。  An object of the present invention is to provide a semiconductor device which functions as a semiconductor power element having a large current driving force and a high withstand voltage by relaxing a trade-off between a low resistance and a high withstand voltage. .
本発明の半導体装置は、 半導体基板と、 上記半導体基板の主面上に設けられた 化合物半導体層と、 上記化合物半導体層の上に設けられたゲート絶縁膜と、 上記 ゲート絶縁膜の上に設けられたゲート電極と、 上記化合物半導体層の上で上記ゲ ート電極の側方に設けられたソース電極と、 上記半導体基板の上記主面に対向す る面に設けられたドレイン電極と、 上記化合物半導体層内で上記ソース電極の一 部の下方から上記ゲート電極の端部下方に亘つて設けられ第 1導電型不純物を含 むソース領域と、 上記化合物半導体層内で上記ゲート電極の下方に設けられ第 1 導電型不純物を含むキヤリァ走行領域として機能する活性領域と、 上記化合物半 導体層内で上記ゲート電極の下方に設けられ、 第 1導電型不純物を含むド リ フ ト 領域と、 上記化合物半導体層内で上記ドリフ ト領域と上記ソース領域との間に設 けられ、 第 2導電型不純物を含む逆ドープ領域とを備え、 上記活性領域は、 少な くとも 1つの第 1の半導体層と、 上記第 1の半導体層よりも高濃度のキヤリァ用 不純物を含み上記第 1の半導体層よりも膜厚が薄く量子効果による第 1の半導体 層へのキヤリァの浸みだしが可能な少なくとも 1つの第 2の半導体層とを有して いる。  A semiconductor device according to the present invention includes a semiconductor substrate, a compound semiconductor layer provided on a main surface of the semiconductor substrate, a gate insulating film provided on the compound semiconductor layer, and a gate insulating film provided on the gate insulating film. A gate electrode provided, a source electrode provided on the compound semiconductor layer beside the gate electrode, a drain electrode provided on a surface of the semiconductor substrate facing the main surface, A source region including a first conductivity type impurity extending from below a part of the source electrode to below an end of the gate electrode in the compound semiconductor layer; and a source region in the compound semiconductor layer below the gate electrode. An active region provided and functioning as a carrier transit region containing a first conductivity type impurity; a drift region provided below the gate electrode in the compound semiconductor layer and containing the first conductivity type impurity; A reverse doping region provided between the drift region and the source region in the compound semiconductor layer and including a second conductivity type impurity, wherein the active region includes at least one first semiconductor At least one layer containing a carrier impurity at a higher concentration than the first semiconductor layer and having a thickness smaller than that of the first semiconductor layer and capable of leaching the carrier into the first semiconductor layer by a quantum effect. And two second semiconductor layers.
これにより、 活性領域においては、 量子効果によって第 2の半導体層に量子準 位が生じ、 第 2の半導体層中の局在するキヤリァの波動関数はある程度の広がり を持つようになる。 その結果、 キャリアが第 2の半導体層だけでなく第 1の半導 体層にも存在するような分布状態となる。 すなわち量子効果によって第 2の半導 体層から第 1の半導体層にキャリアが広がった状態になる。 この状態で、 活性領 域のポテンシャルが高められると、 第 1， 第 2の半導体層に絶えずキャリアが供 給される。 そして、 キャリアが不純物濃度の低い第 1の半導体層を流れるので、 不純物イオン散乱の低減により、 高いチャネル移動度が得られる。 一方、 オフ状 態では活性領域全体が空乏化され、 活性領域にはキヤリァが存在しなくなるので 、 不純物濃度の低い第 1の半導体層によって耐圧が規定され、 活性領域全体にお いて高い耐圧値が得られることになる。 よって、 第 1導電型の活性領域を利用し てソース · ドレイン間に大電流を流すように構成された半導体装置において、 高 いチャネル移動度と、 高い耐圧とを同時に実現することが可能になる。 As a result, in the active region, a quantum level occurs in the second semiconductor layer due to the quantum effect, and the carrier wave function localized in the second semiconductor layer expands to some extent. To have As a result, the carriers are distributed not only in the second semiconductor layer but also in the first semiconductor layer. That is, carriers spread from the second semiconductor layer to the first semiconductor layer due to the quantum effect. In this state, when the potential of the active region is increased, carriers are constantly supplied to the first and second semiconductor layers. Since carriers flow through the first semiconductor layer having a low impurity concentration, high channel mobility can be obtained by reducing impurity ion scattering. On the other hand, in the off state, the entire active region is depleted, and the carrier does not exist in the active region. Therefore, the withstand voltage is defined by the first semiconductor layer having a low impurity concentration, and the high withstand voltage in the entire active region is increased. Will be obtained. Therefore, in a semiconductor device configured to flow a large current between the source and the drain using the active region of the first conductivity type, it is possible to simultaneously achieve high channel mobility and high withstand voltage. .
上記半導体基板が第 1導電型であることにより、 A C C U F E Tとして機能す る半導体装置において、 上述の作用効果が得られる。  Since the semiconductor substrate is of the first conductivity type, the above-described effects can be obtained in a semiconductor device functioning as ACCUFET.
上記半導体基板が第 2導電型であることにより、 I G B Tとして機能する半導 体装置において、 上述の作用効果が得られる。  Since the semiconductor substrate is of the second conductivity type, the above-described operation and effect can be obtained in a semiconductor device that functions as an IGBT.
上記活性領域が、 上記第 1の半導体層と第 2の半導体層とを各々複数個積層し て設けられていることにより、 上述の効果を確実に発揮することができる。  Since the active region is provided by laminating a plurality of the first semiconductor layers and the plurality of the second semiconductor layers, the above-described effects can be surely exerted.
上記第 2の半導体層が炭化珪素層であり、 上記第 2の半導体層の厚みが 1モノ レィャ一以上で 2 0 n m未満であることが好ましい。  Preferably, the second semiconductor layer is a silicon carbide layer, and the thickness of the second semiconductor layer is at least one monolayer and less than 20 nm.
上記第 1の半導体層が炭化珪素層であり、 上記第 1の半導体層の厚みが 1 0 η m以上で 1 0 0 n m以下であることが好ましい。  Preferably, the first semiconductor layer is a silicon carbide layer, and the thickness of the first semiconductor layer is not less than 100 ηm and not more than 100 nm.
上記ドリフ ト領域を横切って設けられ、 上記ドリフ ト領域よりも高濃度の第 1 導電型不純物を含む少なくとも 1つの高濃度ド一プ層をさらに備えていることに より、 横方向への空乏層の広がりを確保して、 より耐圧の高い半導体装置を得る ことができる。  A depletion layer in the lateral direction is provided by further comprising at least one high-concentration doping layer provided across the drift region and containing a first-conductivity-type impurity at a higher concentration than the drift region. As a result, a semiconductor device having a higher withstand voltage can be obtained.
上記ソース領域を貫通して上記逆ド一プ領域に達する開口部をさらに備え、 上 記ソース電極は、 上記開口部の壁面上に設けられて、 上記ソース領域および上記 逆ド一プ領域の各一部に直接接触していることにより、 欠陥の多い領域や表面の 荒れた領域を回避してソース電極を設けることができるので、 高い耐圧値などの 特性が得られる。 An opening that penetrates through the source region and reaches the reverse doping region; wherein the source electrode is provided on a wall surface of the opening, and each of the source region and the reverse doping region is provided. By directly contacting the part, the source electrode can be provided avoiding the area with many defects and the area with a rough surface. Characteristics are obtained.
本発明の半導体装置の製造方法は、 半導体基板の主面上に、 第 1導電型の化合 物半導体層を形成する工程 （a ) と、 上記化合物半導体層の一部に第 2導電型不 純物を導入して逆ドープ領域を形成する工程 （b ) と、 上記化合物半導体層及び 上記逆ド一プ領域の上に、 少なく とも 1.つの第 1の半導体層と、 上記第 1の半導 体層よりも高濃度のキヤリァ用不純物を含み上記第 1の半導体層よりも膜厚が薄 く量子効果による第 1の半導体層へのキヤリァの浸みだしが可能な少なく とも 1 つの第 2の半導体層とを有する活性領域を形成する工程 （ c ) と、 上記活性領域 のうち少なくとも逆ド一プ領域の上方に位置する領域に第 1導電型不純物を導入 してソース領域を形成する工程 （d ) と、 上記活性領域のうち上記逆ド一プ領域 の上に位置する部分を除去して、 逆ド一プ領域に達する開口部を形成する工程 （ e ) と、 上記活性化領域の上にゲート絶縁膜を形成する工程 （f ) と、 上記開口 部内に露出するソース領域および上記逆ド一プ領域の両方に接触するソース電極 を設ける工程 （g ) と、 上記ゲート絶縁膜上にゲート電極を形成する工程 （h ) とを含んでいる。  The method of manufacturing a semiconductor device according to the present invention includes a step (a) of forming a compound semiconductor layer of the first conductivity type on the main surface of the semiconductor substrate; (B) forming a reverse doped region by introducing a substance; and forming at least one first semiconductor layer on the compound semiconductor layer and the reverse doped region; At least one second semiconductor containing a carrier impurity at a higher concentration than the body layer and having a thickness smaller than that of the first semiconductor layer and capable of exuding the carrier into the first semiconductor layer by a quantum effect; (C) forming an active region having a layer, and forming a source region by introducing a first conductivity type impurity into at least a region of the active region located above the reverse doped region (d). ) And a portion of the active region located above the reverse doping region Removing the portion to form an opening reaching the reverse doped region (e), forming a gate insulating film on the activation region (f), and exposing a source exposed in the opening. A step (g) of providing a source electrode in contact with both the region and the reverse doped region; and (h) a step of forming a gate electrode on the gate insulating film.
この方法により、 工程 （e ) でソース領域に逆ド一プと同じ導電型の不純物を 注入しなくても、 ソース電極と逆ドーブ領域とを接触させることができるので、 高性能の A C C U F E T又は I G B Tとして機能する半導体装置が形成される。 上記工程 （a ) では、 第 1導電型不純物の in- situ ド一プを伴うェピ夕キシャ ル成長法により、 上記化合物半導体層を形成することが好ましい。  According to this method, the source electrode and the reverse-doped region can be brought into contact with each other without injecting impurities of the same conductivity type as the reverse-doped region into the source region in step (e). A semiconductor device functioning as a semiconductor device is formed. In the step (a), the compound semiconductor layer is preferably formed by an epitaxial growth method involving in-situ doping of the first conductivity type impurity.
上記工程 （a ) 及び （ c ) では、 上記化合物半導体層及び上記活性領域として 、 S i C層を形成することにより、 バンドギャップが広く耐圧性の高い S i C層 を利用したパワー素子として機能する半導体装置が形成される。 その場合、 S i C層内ではイオン注入された不純物の活性化率が低いので、 イオン注入によって 形成された領域では欠陥が発生しやすいが、 開口部にソース電極を形成すること により、 欠陥を多く含む領域の発生を回避することができる。 図面の簡単な説明  In the above steps (a) and (c), a SiC layer is formed as the compound semiconductor layer and the active region, thereby functioning as a power element using the SiC layer having a wide band gap and high withstand voltage. Is formed. In this case, the activation rate of the ion-implanted impurities is low in the SiC layer, so that a defect is likely to occur in the region formed by the ion implantation, but the defect is formed by forming the source electrode in the opening. It is possible to avoid generation of a region including a large amount. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明の第 1の実施形態における D M O Sデバイスの断面図である。 図 2は、 本発明の第 1の実施形態における DMO Sデバイスのセル配置を示す 上面図である。 FIG. 1 is a sectional view of a DMOS device according to the first embodiment of the present invention. FIG. 2 is a top view showing a cell arrangement of the DMOS device according to the first embodiment of the present invention.
図 3は、 本発明の第 1の実施形態の D MO Sデバイスのセル単体におけるオフ 時の空乏層の拡大状態を示す断面図である。  FIG. 3 is a cross-sectional view showing an enlarged state of a depletion layer when the cell is off in the DMOS device according to the first embodiment of the present invention.
図 4は、 従来の文献に開示されている DMO Sデバイスの断面図である。  FIG. 4 is a cross-sectional view of a DMOS device disclosed in a conventional document.
図 5は、 図 4に示す従来の S i C基板を用いた DMO Sデバイスにおけるオフ 時の空乏層の拡大状態を示す断面図である。  FIG. 5 is a cross-sectional view showing an enlarged state of a depletion layer when the DMOS device using the conventional SiC substrate shown in FIG. 4 is turned off.
図 6は、 本発明の第 2の実施形態における DMO Sデバイスの断面図である。 図 7 (a) 〜 （d) は、 本発明の第 2の実施形態における DMO Sデバイスの 製造工程のうちの前半部分を示す断面図である。  FIG. 6 is a cross-sectional view of a DMOS device according to the second embodiment of the present invention. FIGS. 7A to 7D are cross-sectional views showing the first half of the manufacturing process of the DMOS device according to the second embodiment of the present invention.
図 8 (a) 〜 （d) は、 本発明の第 2の実施形態における DMO Sデバイスの 製造工程のうちの後半部分を示す断面図である。  FIGS. 8A to 8D are cross-sectional views illustrating the latter half of the manufacturing process of the DMOS device according to the second embodiment of the present invention.
図 9 (a) , (b) は、 それぞれ順に DMO Sデバイスと I GB Tとの電流成 分の違いを示す断面図である。  FIGS. 9 (a) and 9 (b) are cross-sectional views respectively showing the difference in current component between the DMOS device and the IGBT.
図 1 0は、 本発明の第 2の実施形態の変形例における DMO Sデバイスのセル 配置を示す上面図である。  FIG. 10 is a top view showing a cell arrangement of a DMOS device according to a modification of the second embodiment of the present invention.
図 1 1は、 本発明の第 2の実施形態の DMO Sデバイスの電流 （ I ) —電圧 （ V) 特性を示す図である。 最良の実施形態  FIG. 11 is a diagram showing current (I) -voltage (V) characteristics of the DMOS device according to the second embodiment of the present invention. Best Embodiment
一第 1の実施の形態—  First Embodiment—
図 1は、 本発明の第 1の実施形態における DMO Sデバイス単体の構造を示す 断面図である。 図 2は、 本実施形態の D MO Sデバイスの上面図である。 図 1， 図 2に示すように、 本実施形態の DMO Sデバイスは、 高濃度の n型不純物を含 む主面が （ 0 0 0 1) オフ面である S i C基板 2 ( 6 H- S i C基板） と、 S i C基板 2の上に形成されたェビ夕キシャル層内に設けられた低濃度の n型不純物 を含む n— S i C層 3 (ドリフ ト領域） と、 ェピタキシャル層の上に設けられた ゲート絶縁膜 6及びその上のゲ一ト電極 7 aと、 ェピタキシャル層の上でゲ一ト 電極 7 aを囲むように設けられたソース電極 7 bと、 S i C基板 2の下面に設け られたドレイン電極 7 cと、 ェピタキシャル層のうちソース電極 7 bの下方に位 置する領域からゲ一ト電極 7 aの端部下方に位置する領域に p型不純物をド一プ して形成された p— S i C層 4と、 ェピタキシャル層のうちソース電極 7 bの端 部下方からゲ一ト電極 7 aの端部下方に位置する領域に高濃度の n型不純物を ド —プして形成された n+ S i C層 5とを備えている。 FIG. 1 is a sectional view showing a structure of a DMOS device alone according to the first embodiment of the present invention. FIG. 2 is a top view of the DMOS device of the present embodiment. As shown in FIGS. 1 and 2, in the DMOS device of the present embodiment, the SiC substrate 2 (6H-) in which the main surface containing the high-concentration n-type impurity is the (001) off surface is used. An S—C substrate) and an n—S i C layer 3 (drift region) containing a low-concentration n-type impurity provided in an epitaxial layer formed on the S i C substrate 2; A gate insulating film 6 provided on the epitaxial layer and a gate electrode 7a thereon, and a source electrode 7b provided on the epitaxial layer so as to surround the gate electrode 7a. Provided on the underside of the SiC substrate 2 Formed by doping a p-type impurity from the region located below the source electrode 7b of the epitaxial layer to the region located below the end of the gate electrode 7a. A high concentration n-type impurity is doped into the p-SiC layer 4 and the region of the epitaxial layer located below the end of the source electrode 7b and below the end of the gate electrode 7a. And an n + S i C layer 5 formed as described above.
ここで、 本実施形態の第 1の特徴は、 ェピ夕キシャル層の表面部のうち η+ S i C層 5が形成されている部分を除く領域に多重 ά ドーブ層 1 0 (活性領域） が 設けられている点である。 そして、 これにより、 本実施形態の DMO Sデバイス は、 いわゆる AC CUF E T (Accumulation Mode F E T) として機能する。 一方、 図 1の下方に拡大して示すように、 多重 (5 ドープ層 1 0は、 高濃度 （例 えば 1 X 1 018 atoms · cm 3) の窒素を含む厚みが約 1 0 nmの n型ドープ層 1 0 aの 5層と、 アン ド一プの S i C単結晶からなる厚さ約 5 O nmのアンド一 プ層 1 0 bの 6層とを交互に積層し、 最上層と最下層とをアンド一プ層 1 0 bに して構成されている。 つまり、 トータル厚みが約 3 5 0 nmである。 Here, the first feature of the present embodiment is that the ά + dove layer 10 (active region) is formed in a region of the surface of the epitaxial layer other than the portion where the η + SiC layer 5 is formed. Is provided. Thus, the DMOS device of the present embodiment functions as a so-called AC CUFET (Accumulation Mode FET). On the other hand, as shown in an enlarged manner at the bottom of FIG. 1, the multiple (5-doped layer 10) has a high concentration (for example, 1 × 10 18 atoms · cm 3 ) of nitrogen having a thickness of about 10 nm. The five layers of the doped layer 10a and the six layers of the AND layer 10b of about 5 O nm in thickness, which are made of single-crystal SiC single crystal, are alternately laminated, and the uppermost layer is formed. The lowermost layer is constituted by an AND layer 10b, that is, the total thickness is about 350 nm.
そして、 この半導体パワー素子において、 n+ S i C層 5がソース領域として 機能し、 多重 (5 ド一プ層 1 0がチャネル領域として機能し、 31〇基板2及び1 — S i C層 3がドレイン領域として機能する。 In this semiconductor power device, the n + S i C layer 5 functions as a source region, and the multiplex (the five-doped layer 10 functions as a channel region, and the 31〇 substrate 2 and 1 — S i C layer 3 Function as a drain region.
多重 5 ド一プ層 1 0においては、 量子効果によって n型ド一プ層 1 0 aに量子 準位が生じ、 n型ドープ層 1 0 a中の局在する電子の波動関数はある程度の広が りを持つようになる。 その結果、 電子が n型ド一プ層 1 0 aだけでなくアン ド一 プ層 1 0 bにも存在するような分布状態となる。  In the multi-layer 5 doped layer 10, a quantum level is generated in the n-type doped layer 10 a by the quantum effect, and the wave function of the electrons localized in the n-type doped layer 10 a is expanded to some extent. Become a member. As a result, the distribution state is such that electrons exist not only in the n-type doped layer 10a but also in the and-doped layer 10b.
この半導体パワー素子をオンする時には、 ゲート電極 7 aに 5 V程度の電圧を 印加して、 ソース電極 7 bを接地し、 ドレイン電極 7 cに 6 0 0 V程度の電圧を 印加する。 そのとき、 多重 (5 ド一プ層 1 0のポテンシャルが高められ、 量子効果 によって n型ドープ層 1 0 aからアンド一プ層 1 0 bに電子の波動関数が広がり 、 n型ド一プ層 1 0 a , アンド一プ層 1 0 bに絶えず電子が供給される。 そして 、 電子が不純物濃度の低いアンドープ層 1 0 bを流れるので、 不純物イオン散乱 の低減により、 高いチャネル移動度が得られる。 なお、 電流が流れると、 ドレイ ン電圧は数 Vにまで低下する。 特に、 S i c基板上にゲート酸化膜として熱酸化膜を形成する場合には、 シリ コン酸化膜中に炭素等の不純物が残留するので、 ゲート酸化膜と S i Cチャネル 領域 （活性領域） との界面付近に界面準位が多く存在している。 そのために、 従 来の S i C基板を利用した反転型 MO S F E Tにおいては、 活性領域内でゲート 酸化膜に近い領域を走行するキャリアの移動度は低い。 したがって、 従来の反転 型 MO S FE Tの場合は、 活性領域中の界面準位の多い領域， いわば劣悪な界面 に近い領域に、 キャリアが流れるチャネルが形成されるので、 FE Tの電流量は 少ない。 When this semiconductor power element is turned on, a voltage of about 5 V is applied to the gate electrode 7a, the source electrode 7b is grounded, and a voltage of about 600 V is applied to the drain electrode 7c. At this time, the potential of the multi-layer (5 doped layer 10) is increased, and the quantum effect spreads the electron wave function from the n-type doped layer 10a to the AND layer 10b. Electrons are constantly supplied to the 10 a and the amplifying layer 10 b. Since the electrons flow through the undoped layer 10 b having a low impurity concentration, a high channel mobility can be obtained by reducing impurity ion scattering. When a current flows, the drain voltage drops to several volts. In particular, when a thermal oxide film is formed as a gate oxide film on a sic substrate, impurities such as carbon remain in the silicon oxide film, so that the gate oxide film and the SiC channel region (active region) There are many interface states near the interface. For this reason, in the case of a conventional inverted MOS FET using a SiC substrate, the mobility of carriers traveling in a region near the gate oxide film in the active region is low. Therefore, in the case of the conventional inversion type MOS FET, a channel through which carriers flow is formed in a region having many interface states in the active region, that is, a region close to a bad interface, so that the current amount of the FET is small. Few.
ところが、 本実施形態の MO S F E Tにおける活性領域の場合、 界面から離れ たアンド一プ層 1 0 bを電子が走るので劣悪な界面の影響を受けにく く、 電子の 移動度を高くすることができ、 F E Tの電流量を大きくすることができる。  However, in the case of the active region in the MOS FET of the present embodiment, electrons run on the AND layer 10b away from the interface, so that the electron is hardly affected by the poor interface, and the mobility of electrons can be increased. It is possible to increase the current amount of the FET.
また、 通常の A C C U F E Tでは、 ソース · ドレイン領域を除く活性領域 （本 実施形態における多重 3 ドープ層 1 0に相当する領域） 全体がほぼ一様な不純物 濃度を有している。 その場合、 不純物濃度を高くするほうが電子の供給量は増大 するが、 活性領域の不純物濃度を高くすると、 電子が走行にするときに不純物に よって散乱される確率が大きくなり、 電子の移動度が低下する。 つまり、 F E T のチャネル抵抗が大きくなり、 大電流及び高速動作が確保されない。 そこで、 具 体的には、 ソース ' ドレイン領域を除く活性領域の不純物濃度は、 約 1 X 1 016 cm一3から 1 X 1 017cm一3となっている。 In a normal ACCUFET, the entire active region (the region corresponding to the multiply-doped layer 10 in the present embodiment) except the source / drain regions has a substantially uniform impurity concentration. In this case, increasing the impurity concentration increases the amount of supplied electrons. However, when the impurity concentration in the active region is increased, the probability that electrons are scattered by impurities when traveling is increased, and the mobility of electrons is increased. descend. That is, the channel resistance of the FET increases, and high current and high-speed operation cannot be secured. Therefore, the concrete, the impurity concentration of the active region except the source 'drain region is made from approximately 1 X 1 0 16 cm one 3 1 X 1 0 17 cm one 3.
さらに、 ソース ， ドレイン領域を除く活性領域の不純物濃度を高くすると、 耐 圧は低下する。 ところが、 本実施形態の A C CU F E Tによれば、 リース ' ドレ イン領域を除く活性領域において、 ドープ層は不純物濃度が高いが層厚がきわめ て薄いので、 層厚が厚く不純物濃度の低いアンドープ層によって耐圧の低下が抑 制されている。 なお、 電流が流れると、 ドレイン電圧は数 Vにまで低下する。 また、 このとき、 n— S i C層 3において、 ゲート電極 7 aの下方にある多重 δ ドープ層 1 0全体を介して広い範囲に電流が流れる状態となり、 特に高い電流 値が得られる。 この効果は、 キャリアの電導のパスを広げる効果を有し、 導通損 を下げる効果があることも確認した。 それに対し、 従来の図 4に示す DMO Sデ バイスにおいては、 電流が n— S i C層 1 1 2の中で狭い範囲に絞られるので、 それほど大きな電流値は得られない。 Further, when the impurity concentration in the active region other than the source and drain regions is increased, the withstand voltage decreases. However, according to the AC CU FET of the present embodiment, in the active region excluding the leased drain region, the doped layer has a high impurity concentration but a very thin layer thickness, so that the undoped layer has a large thickness and a low impurity concentration. This suppresses the decrease in breakdown voltage. When a current flows, the drain voltage drops to several volts. At this time, in the n-SiC layer 3, a current flows in a wide range through the entire multiple δ-doped layer 10 below the gate electrode 7a, and a particularly high current value is obtained. This effect has the effect of expanding the conduction path of carriers and has the effect of reducing conduction loss. On the other hand, in the conventional DMO S device shown in Fig. 4, the current is reduced to a narrow range in the n-SiC layer 112. A very large current value cannot be obtained.
一方、 本実施形態のデバイスにおいては、 オフ状態では、 多重 (5 ド一プ層 1 0 全体が空乏化され、 多重 (5 ド一プ層 1 0には電子が存在しなくなるので、 不純物 濃度の低いアンド一プ層 1 0 bによって耐圧が規定され、 多重 (5 ドープ層 1 0全 体において高い耐圧値が得られることになる。  On the other hand, in the device of the present embodiment, in the off state, the entire multi-layer (the five-doped layer 10 is depleted, and no electrons are present in the multi-layer (the five-doped layer 10). The withstand voltage is defined by the low AND layer 10b, and a high withstand voltage value can be obtained in the entire multiple (5 doped layer 10).
よって、 本実施形態では、 多重 (5 ドープ層 1 0を利用してソース · ドレイン領 域間に大電流を流すように構成された A C C U F E Tにおいて、 高いチャネル移 動度と、 高い耐圧とを同時に実現することが可能になる。  Therefore, in the present embodiment, a high channel mobility and a high withstand voltage are simultaneously realized in the ACCUFET configured to allow a large current to flow between the source and drain regions using the multiplexed (5-doped layer 10). It becomes possible to do.
また、 アンド一プ層 1 0 bにおける不純部濃度が低いことから、 多重 (5 ドープ 層 1 0をチャネル層として用いることにより、 ゲート絶縁膜 6ゃゲート絶縁膜— 多重 (5 ドープ層間の界面付近にトラッブされる電荷の低減によるチャネル移動度 の向上と、 不純物イオン散乱の低減によるチャネル移動度の向上と、 耐圧性の向 上とを図ることができる。  In addition, since the impurity concentration in the AND layer 10b is low, the multi-layer (the gate insulating film 6 ゃ the gate insulating film—the multi-layer (in the vicinity of the interface between the five-doped layers) Thus, it is possible to improve the channel mobility by reducing the charges trapped in the semiconductor device, improve the channel mobility by reducing the impurity ion scattering, and improve the breakdown voltage.
A C C U F E Tは、 飽和電流値が大きくオン抵抗が小さい点に特徴があるが、 まだ実用化に至っていない大きな理由の 1つとして、 オフ状態における耐圧に乏 しいという難点がある。 ところが、 本実施形態の 〇〇11 1^ £丁では、 上述のよ うに (5 ドープ層とアン ド一プ層との積層構造を利用することによって、 電流駆動 力をさらに向上させつつ、 オフ状態における高い耐圧値を確保することができる なお、 本実施形態においては、 高濃度ドープ層 （<5 ドープ層） と低濃度ド一プ 層 （アンド一プ層） とを交互に積層してなる多重 (5 ドープ層 1 0を設けたが、 1 層の高濃度ド一プ層と 1層の低濃度ド一プ層のみを有していてもよい。 また、 高 濃度ドープ層と低濃度ド一ブ層のいずれを先に形成してもよい。 1層の高濃度ド ープ層の上下にそれぞれ 1層の低濃度ドープ層 （アンドープ層） を配置されてい てもよい。 つまり、 高濃度ドープ層と低濃度ドープ層との数が異なっていてもよ い。 ゲート絶縁膜 6と接する最上部はアンドープ層であることが好ましい。  ACCUFET is characterized by a large saturation current value and a small on-resistance. One of the major reasons that ACC FET has not yet been put to practical use is that it has a poor breakdown voltage in the off state. However, as described above, in the present embodiment, the off-state is achieved while further improving the current driving force by using the laminated structure of the five-doped layer and the In this embodiment, a high concentration doped layer (<5 doped layer) and a low concentration doped layer (AND layer) are alternately stacked. (5 Although the doped layer 10 is provided, it may have only one high-concentration doped layer and one low-concentration doped layer. One low-concentration doping layer (undoped layer) may be disposed above and below the one high-concentration doping layer, respectively. The number of layers and the number of lightly doped layers may be different. The part is preferably an undoped layer.
本実施形態の第 2の特徴は、 n— S i C層 3内において、 高濃度 （例えば I X 1 0 1 8 atoms · c m 3 ) の窒素を含む厚みが約 1 0 0 n mの 2つの高濃度ドープ 層 8 a， 8 bが設けられている点である。 そして、 この 2つの高濃度ドープ層 8 a , 8 b間の間隔は、 約 5 0 0 n mである。 The second feature of the present embodiment is that the n-SiC layer 3 contains two high-concentration (eg, IX 10 18 atoms · cm 3 ) nitrogen layers having a thickness of about 100 nm. The point is that the doped layers 8a and 8b are provided. And these two highly doped layers 8 The interval between a and 8b is about 500 nm.
図 5は、 図 4に示す従来の S i C基板を用いた D M 0 Sデバイスにおけるオフ 時の空乏層の拡大状態を示す断面図である。 同図に示すように、 ゲート電極 1 1 8にオフ電圧が印加され （例えば 0 V ) 、 ソース電極 1 1 9が接地された状態で 、 ドレイン電極 1 1 7に 6 0 0 V程度の電圧が印加されると、 n— S i C層 1 1 2内で空乏層 1 0 9が縦方向及び横方向に広がる。 このとき、 図中矢印 yで示す 縦方向 （厚み方向） への空乏層の広がりに比べて、 図中矢印 Xで示す横方向への 空乏層の広がりは小さい。 つまり、 縦方向における等電位面 1 0 9 a間の間隔よ りも横方向における等電位面 1 0 9 a間の間隔が狭い。 その結果、 空乏層 1 0 9 内における電界は、 ゲート電極 1 1 8の下端面のエッジ付近でもっとも大きくな り、 この部分で絶縁破壊 （ブレークダウン） が生じやすくなる。  FIG. 5 is a cross-sectional view showing an enlarged state of a depletion layer at the time of off in the DMSO device using the conventional SiC substrate shown in FIG. As shown in the figure, when an off-voltage is applied to the gate electrode 118 (for example, 0 V) and the source electrode 119 is grounded, a voltage of about 600 V is applied to the drain electrode 117. When applied, the depletion layer 109 expands in the vertical and horizontal directions in the n-SiC layer 112. At this time, the spread of the depletion layer in the horizontal direction indicated by the arrow X in the figure is smaller than that in the vertical direction (thickness direction) indicated by the arrow y in the figure. That is, the interval between the equipotential surfaces 109a in the horizontal direction is narrower than the interval between the equipotential surfaces 109a in the vertical direction. As a result, the electric field in the depletion layer 109 becomes largest near the edge of the lower end face of the gate electrode 118, and dielectric breakdown (breakdown) tends to occur in this portion.
図 3は、 高濃度ドープ層を n— S i C層 1 1 2に設けてなる本実施形態の D M FIG. 3 shows a DM of this embodiment in which a heavily doped layer is provided in the n-SiC layer 112.
0 Sデバイスのセル単体におけるオフ時の空乏層の拡大状態を示す断面図である 。 ゲート電極 7 aにオフ電圧が印加され （例えば 0 V ) 、 ソース電極 7 bが接地 された状態で、 ドレイン電極 7 cに 6 0 0 V程度の電圧が印加されると、 n— SFIG. 4 is a cross-sectional view showing an enlarged state of a depletion layer in a single cell of the 0S device when the cell is off. When an off voltage is applied to the gate electrode 7a (for example, 0 V) and the source electrode 7b is grounded and a voltage of about 600 V is applied to the drain electrode 7c, n−S
1 C層 3内で空乏層 9が縦方向及び横方向に広がる。 このとき、 高濃度ドープ層 は、 あたかも ドリフ ト領域 （ここでは n— S i C層 3 ) 中に挿入した電極のよう に機能する。 したがって、 空乏層 9が図中矢印 yで示す縦方向 （厚み方向） に広 がって高濃度ドープ層 8 a , 8 bに接すると、 空乏層 9のさらに下方への広がり が高濃度ドニプ層 8 a， 8 bによっていったん抑制されるので、 縦方向への空乏 層 9の広がりに比べて、 図中矢印 Xで示す横方向への空乏層 9の広がりの方が大 きくなる。 つまり、 縦方向における等電位面 9 a間の間隔よりも横方向における 等電位面 9 a間の間隔が広くなる。 その結果、 空乏層 9内において、 ゲート電極 7 aの下端面のエッジ付近での電界の集中がほとんどなくなる。 また、 空乏層 9 内における等電位線 9 aは高濃度ドープ層 8 a， 8 bにほぼ平行に形成されるの で、 空乏層 9内における縦方向の電界は局所的に集中することなく広い範囲に均 一に生じる。 よって、 絶縁破壊 （ブレークダウン） が生じにく くなる。 よって、 本発明の D M O Sデバイスは、 図 4に示す従来の D M O Sデバイスに比べて、 高 い耐圧値 （少なくとも 6 0 0 V程度） を有することになる。 なお、 この効果は、 多重 5 ド一プ層 1 0の有無とは無関係に得られる。 したが つて、 本実施形態においては、 多重 (5 ド一プ層 1 0と、 高濃度ド一プ層 8 a, 8 bとを設けたが、 いずれか一方のみを設けることによって、 DMO Sデバイスの 耐圧値を高めることができる。 1 In the C layer 3, the depletion layer 9 spreads in the vertical and horizontal directions. At this time, the heavily doped layer functions like an electrode inserted in the drift region (here, n-SiC layer 3). Therefore, when the depletion layer 9 spreads in the vertical direction (thickness direction) indicated by the arrow y in the figure and comes into contact with the high-concentration doped layers 8a and 8b, the further downward depletion of the depletion layer 9 increases. Since the depletion layer 9 is once suppressed by 8a and 8b, the expansion of the depletion layer 9 in the horizontal direction indicated by the arrow X in the figure is larger than that in the vertical direction. That is, the interval between the equipotential surfaces 9a in the horizontal direction is wider than the interval between the equipotential surfaces 9a in the vertical direction. As a result, in the depletion layer 9, the concentration of the electric field near the edge of the lower end face of the gate electrode 7a is almost eliminated. Further, since the equipotential lines 9a in the depletion layer 9 are formed almost parallel to the high-concentration doped layers 8a and 8b, the vertical electric field in the depletion layer 9 is wide without being locally concentrated. Occurs uniformly in the range. Therefore, dielectric breakdown (breakdown) is unlikely to occur. Therefore, the DMOS device of the present invention has a higher withstand voltage (at least about 600 V) than the conventional DMOS device shown in FIG. This effect can be obtained irrespective of the presence or absence of the multi-doped layer 10. Therefore, in the present embodiment, the multiple (5 doped layers 10 and the high concentration doped layers 8 a and 8 b are provided, but by providing only one of them, the DMOS device The withstand voltage value can be increased.
特に、 多重 (5 ド一プ層 1 0を設けた場合には、 A C C U F E Tとして機能する ので、 飽和電流値の高い特性が得られる。  In particular, when a multiplexed (5-doped layer 10) is provided, it functions as ACCUFET, so that a characteristic with a high saturation current value can be obtained.
一方、 多重 5 ドープ層 1 0を設けずに、 高濃度ドープ層 8 a， 8 bのみを設け た場合には、 飽和電流値の向上という効果は期待できないが、 耐圧値の向上を図 ることができる。 その場合、 高濃度ドーブ層は、 本実施形態のごとく 1層のみに 限られるものではなく、 1層のみでもよく、 2層以上の多数層設けてもよい。 一 般的には、 高濃度ド一プ層の数が多いほど、 DMO Sデバイスの耐圧値が大きい といえる。  On the other hand, if only the high-concentration doped layers 8a and 8b are provided without providing the multiple 5-doped layers 10, the effect of improving the saturation current value cannot be expected, but the withstand voltage value must be improved. Can be. In this case, the high concentration dove layer is not limited to only one layer as in the present embodiment, but may be only one layer or two or more layers. In general, it can be said that the larger the number of high-concentration doped layers, the higher the breakdown voltage of the DMOS device.
次に、 本実施形態の DMO Sデバイスの製造工程について説明する。 まず、 主 面が （ 0 0 0 1) 面 （C面） から数度ずれた方位を有する n+ 型の S i C基板 2 を準備する。 S i C基板 2の直径は 2 5 mmである。 まず、 流量 5 ( 1/min.) の酸素によってバブリングされた水蒸気雰囲気中で、 S i C基板 2を 1 1 0 0 °C で 3時間ほど熱酸化し、 表面に厚みが約 40 nmの熱酸化膜を形成した後、 バッ ファード弗酸 （弗酸： フ ヅ化アンモニゥム水溶液 = 1 ： 7 ) により、 その熱酸化 膜を除去する。 そして、 CVD装置のチャンバ一内に S i C基板 2を設置し、 チ ヤンバー内を 1 0— 6P a程度 （= 1 0 -8Torr) の真空度になるまで減圧する。 次 に、 チャンバ一内に希釈ガスとして流量 2 ( 1/min.) の水素ガスと流量 1 ( 1 /min.) のアルゴンガスとを供給し、 チヤンバ一内の圧力を 0. 09 3 3 MP a として、 基板温度を約 1 6 0 0 °Cに制御する。 水素ガス及びアルゴンガスの流量 は上述の一定値に保持しながら、 原料ガスとして流量が 2 (m 1/min.) のプロ パンガスと、 流量が 3 (ml /min.) のシランガスとをチャンバ一内に導入する 。 原料ガスは流量 5 0 (m 1/min.) の水素ガスで希釈されている。 このとき、 ドーピングガス供給用のパルスバルブを開いて、 窒素を導入することにより、 S i C基板 2の主面の上に、 低濃度 ( 1 X 1 016 atoms · c m— 3程度） の窒素を含 む n型 S i C単結晶からなる厚み約 1 0〃mの n S i C層 3を形成する。 その際 、 n— S i C層 3の途中 2力所に、 不純物濃度が例えば 1 x 1 018atoms - cm 一3程度の 2つの高濃度ド一プ層 8 a, 8 bを形成する。 Next, a manufacturing process of the DMOS device of the present embodiment will be described. First, an n + type SiC substrate 2 whose main surface has an orientation deviated from the (00001) plane (C plane) by several degrees is prepared. The diameter of the SiC substrate 2 is 25 mm. First, the SiC substrate 2 was thermally oxidized at 110 ° C for about 3 hours in a steam atmosphere bubbled with oxygen at a flow rate of 5 (1 / min.), And the surface was heated to a thickness of about 40 nm. After the oxide film is formed, the thermal oxide film is removed with buffered hydrofluoric acid (hydrofluoric acid: aqueous solution of ammonium fluoride = 1: 7). Then, set up a S i C substrate 2 into the chamber in one of the CVD apparatus, the inside of the switch Yanba about 1 0- 6 P a - depressurized to a degree of vacuum (= 1 0 8 Torr). Next, hydrogen gas at a flow rate of 2 (1 / min.) And argon gas at a flow rate of 1 (1 / min.) Are supplied into the chamber as diluent gas, and the pressure in the chamber is set to 0.009 3 3MP. As a, the substrate temperature is controlled at about 160 ° C. While maintaining the flow rates of hydrogen gas and argon gas at the above-mentioned constant values, propane gas with a flow rate of 2 (m1 / min.) And silane gas with a flow rate of 3 (ml / min.) Introduce within. The source gas is diluted with a hydrogen gas at a flow rate of 50 (m 1 / min.). At this time, by opening the pulse valve for supplying the doping gas and introducing nitrogen, a low-concentration (about 1 × 10 16 atoms · cm— 3 ) nitrogen is formed on the main surface of the SiC substrate 2. An nSiC layer 3 having a thickness of about 10 μm and made of an n-type SiC single crystal containing that time , N- to S i C layer 3 in the middle of second force plants, the impurity concentration of, for example 1 x 1 0 18 atoms - cm one 3 about two high concentration de one flop layer 8 a, to form a 8 b.
ただし、 特許出願 2 00 0— 5 8 9 64号の明細書及び図面に記載されている ように、 ドーピングガスとして窒素を約 1 0 %含む水素ガスを供給可能にするた めに、 ドーピングガスを高圧ボンベに収納しておいて、 高圧ボンベとドーピング ガス供給用配管との間にパルスバルブが設けられている。  However, as described in the specification and drawings of Patent Application No. 2000-58964, in order to be able to supply a hydrogen gas containing about 10% of nitrogen as a doping gas, a doping gas is used. A pulse valve is provided between the high-pressure cylinder and the doping gas supply pipe.
次に、 n— S i C層 3の一部に選択的にアルミニウム （A 1 ) のイオン注入を 行なって、 深さが 1 0 00 nm程度の p— S i C層 4を形成する。 その後、 以下 の手順により、 多重 5 ドープ層 1 0を形成する。  Next, aluminum (A 1) ions are selectively implanted into a part of the n-SiC layer 3 to form a p-SiC layer 4 having a depth of about 1000 nm. Thereafter, a multi-doped layer 10 is formed by the following procedure.
まず、 上記 n_ S i C層 3を形成した際の原料ガスや希釈ガスの供給量， 温度 などの条件は代えずに、 パルスバルブを閉じることにより、 n— S i C層 3の上 に、 厚みが 5 0 nmのアンド一プ層 1 0 b (不純物濃度が 5 X 1 015 c m— 3程度 であることが確認されている） を形成する。 次に、 チャンバ一内への希釈ガス， 原料ガスの供給量， 温度などの条件は変えずに、 パルスバルブを開いて p型不純 物であるアルミニウムを含むガス （ドーピングガス） をパルス状に供給すること により、 アンド一プ層 1 0 bの上に、 厚み約 1 0 nmの n型ドープ層 1 0 a (高 濃度ドープ層） （不純物濃度が約 1 X 1 018 c m— 3 ) を形成する。 First, by closing the pulse valve without changing the conditions such as the supply amount of the source gas and the dilution gas and the temperature when the n_Sic layer 3 is formed, An AND layer 10b having a thickness of 50 nm is formed (it has been confirmed that the impurity concentration is about 5 × 10 15 cm— 3 ). Next, the pulse valve is opened and the gas (doping gas) containing aluminum, which is a p-type impurity, is supplied in a pulsed manner without changing the conditions such as the supply amount of diluent gas, source gas, and temperature in the chamber. As a result, an n-type doped layer 10a (highly doped layer) with a thickness of about 10 nm (impurity concentration of about 1 × 10 18 cm— 3 ) is formed on the amp layer 10b. I do.
このようにして、 原料ガス及び希釈ガスを供給しながら同時にパルスバルブを 開閉してドーピングガス （窒素） を導入することによる n型ドープ層 1 0 aの形 成と、 パルスバルブを閉じた状態にして ドーピングガスを供給しないで原料ガス 及び希釈ガスのみの供給によるアンド一プ層 1 0 bの形成とを各々 5回ずつ繰り 返す。 最後に、 最上層には、 厚みが 5 O nmのアンド一プ層 1 0 bを形成する。 これにより、 厚みが約 3 5 0 nmの多重 5 ド一プ層 1 0を形成する。  In this way, the n-type doped layer 10a is formed by simultaneously opening and closing the pulse valve and introducing the doping gas (nitrogen) while supplying the source gas and the diluent gas, and closing the pulse valve. The formation of the AND layer 10b by supplying only the source gas and the diluent gas without supplying the doping gas is repeated five times each. Finally, an AND layer 10b having a thickness of 5 O nm is formed on the uppermost layer. As a result, a multi-doped layer 10 having a thickness of about 350 nm is formed.
なお、 多重 (5 ド一プ層 1 0の最上層を占めているアンドープ層 1 0 bの厚みを 他のアンド一プ層 1 0 bよりも 5 0 nm程度厚く してもよい。 ただし、 この場合 には、 DMO Sデバイスのしきい値電圧が高くなるので、 ゲート絶縁膜—多重 5 ドープ層の界面の界面準位の悪影響によるチャネル移動度としきい値電圧とを所 望の条件に調整するように、 最上部のアンド一プ層 1 0 bの厚みを決めることが できる。 次に、 多重 ά ドープ層 1 0の一部に高濃度の窒素イオンを注入することにより 、 多重 (5 ドープ層 1 0を貫通して ρ— S i C層 4の上部に達する深さ約 4 0 0 η mの n+ S i C層 5を形成する。 また、 ソース電極 7 bの下方の一部に p型不純 物をイオン注入して、 p— S i C層 4の上部 4 aを形成する。 この工程は、 ソー ス電極 7 bを p— S i C層 4に直接接触させることにより、 逆ドープ領域のポテ ンシャルを制御するために、 かつ、 逆電流が流れたときの DMO Sデバイスの破 壊を防止するために必要である。 後者に関して説明すると、 通常、 DMO Sデバ イスの負荷は、 誘導負荷 （モーターのコイルなどいわゆる L成分を多く含む負荷 ) であることが多く、 DMO Sデバイスのゲートをオフにした瞬間は電磁誘導に よりソ—ス . ドレイン間に逆電圧がかかる。 すなわち、 一瞬の間、 ドレイ ン電位 がソース電位より低くなるので、 p— S i C層 4と n— S i C層 3からなる PN ダイオードに順方向に電圧が印加され、 大電流がソース · ドレイ ン間に流れる。 このとき、 ソース電極 7 bと p— S i C層 4との間に、 活性領域と同じ n型の表 面層があると； n型表面層と p - S i C層との間の表面 P N接合部に逆バイアス が印加されるので、 表面 P N接合部が抵抗となり発熱してデバイスを破壊にいた らしめることがある。 そこで、 ソース電極 7 bの下方の一部に p— S i C層 4の 上部 4 aを形成することにより、 表面 P N接合部が生じないようにしている。 その後、 基板上に、 シリコン酸化膜などからなるゲート絶縁膜 6を形成した後 、 真空蒸着法により形成された N i合金膜からなるソース電極 7 b及びドレイン 電極 7 cを形成する。 さらに、 ソース， ドレイン電極 7 a , 7 bと下地層とのォ —ミ ックコンタク トをとるために 1 0 0 0 °Cで 3分間ァニールを行なう。 続いて 、 ゲート絶縁膜 6の上に N iを蒸着して、 N i膜からなるゲート長約 5〃mのゲ ―ト電極 7 aを形成する。 Note that the thickness of the undoped layer 10b occupying the uppermost layer of the multiple doped layer 10 may be about 50 nm thicker than the other doped layers 10b. In such a case, the threshold voltage of the DMOS device is increased. Therefore, the channel mobility and the threshold voltage due to the adverse effect of the interface state at the interface between the gate insulating film and the multi-doped layer are adjusted to desired conditions. Thus, the thickness of the uppermost AND layer 10b can be determined. Next, by implanting a high concentration of nitrogen ions into a part of the multiply-doped layer 10, the multi-layer (about 5 depths reaching the upper part of the ρ—SiC layer 4 through the five-doped layer 10). Then, an n + S i C layer 5 of 0 η m is formed, and a p-type impurity is ion-implanted into a portion below the source electrode 7 b to form an upper portion 4 a of the p—S i C layer 4. In this step, the source electrode 7b is brought into direct contact with the p-SiC layer 4 to control the potential of the reversely doped region and to reduce the DMO S when a reverse current flows. It is necessary to prevent the destruction of the device.In terms of the latter, usually, the load of a DMOS device is often an inductive load (a load containing a large amount of an L component such as a motor coil). At the moment when the gate of the S device is turned off, a reverse voltage is applied between the source and drain by electromagnetic induction. That is, for a moment, the drain potential is lower than the source potential, so that a voltage is applied in the forward direction to the PN diode composed of the p-SiC layer 4 and the n-SiC layer 3, and a large current · Flow between the drains If there is the same n-type surface layer as the active region between the source electrode 7b and the p-SiC layer 4, the n-type surface layer and p-Si Since a reverse bias is applied to the surface PN junction between the C layer and the surface PN junction, the surface PN junction becomes a resistor and generates heat, which may cause the device to be destroyed. By forming the upper part 4a of the p-SiC layer 4 at the part, the surface PN junction is prevented from forming.After that, a gate insulating film 6 made of a silicon oxide film or the like is formed on the substrate. Thereafter, a source electrode 7b and a drain electrode 7c made of a Ni alloy film formed by a vacuum evaporation method are formed. Further, annealing is performed at 100 ° C. for 3 minutes to obtain an ohmic contact between the source / drain electrodes 7 a and 7 b and the underlying layer. Then, a gate electrode 7a made of a Ni film and having a gate length of about 5 μm is formed.
上述の工程によって形成された DMO Sデバイス （AC CUFE T) について 、 電流一電圧特性 （ドレイン電流と ドレイン電圧との関係） のゲート電圧依存性 を調べたところ、 従来の DMO Sデバイスに比べて、 飽和電流量がさらに増大し ていることがわかった。 さらに、 ドレイン電圧が 40 0 V以上においてもブレ一 クダウンなしに安定なドレイ ン電流が得られ、 オフ状態における絶縁破壊電圧は 6 0 0 V以上であり、 オン抵抗も 1 πιΩ . c m2 という低い値が実現できた。 なお、 ド一プ層の厚さは、 ドープ層からアンドーブ層への電子の波動関数の浸 み出しが効果的に行われば、 必要以上に厚くする必要はない。 実験例ゃシミュレ —シヨンデータなどを総合すると、 n型ド一プ層 1 0 a (高濃度ド一プ層） の厚 みは、 S i C層を用いる場合には、 1モノレイヤ一以上で 20 nm未満であるこ とが好ましいことがわかっている。 また、 アンドープ層 1 0 b (低濃度ドープ層 ) の厚みは、 そのアン ドープ層に接する上下のドープ層からの電子の波動関数の 浸み出しがおよぶ範囲であればいいので、 約 1 0 nm以上で約 1 00 nm以下で あることが好ましい。 The gate voltage dependence of the current-voltage characteristics (the relationship between the drain current and the drain voltage) of the DMOS device (AC CUFE T) formed by the above process was compared with the conventional DMOS device. It was found that the saturation current was further increased. In addition, a stable drain current is obtained without blurring one Kudaun in the drain voltage 40 0 V or more, the dielectric breakdown voltage in the off state is a 6 0 0 V or higher, as low as even on resistance 1 πιΩ. Cm 2 The value has been realized. The thickness of the doping layer does not need to be unnecessarily thick as long as the wave function of electrons from the doped layer to the undoped layer is effectively leached. Experimental example 1 Simulation—Synthesis data and other data are combined. The thickness of the n-type doped layer 10a (high-concentration doped layer) is 20 monolayers or more when the SiC layer is used. It has been found that a value of less than nm is preferable. The thickness of the undoped layer 10b (low-concentration doped layer) may be about 10 nm, as long as the wave function of electrons from the upper and lower doped layers in contact with the undoped layer extends over the range. The thickness is preferably about 100 nm or less.
また、 S i C層以外の化合物半導体層を用いてもよい。 例えば GaA s層， A I GaA s層， GaN層， A l GaN層， S i Ge層， S i Ge C層などの場合 には、 高濃度ドープ層 （5 ド一プ層） の厚みはその材料に応じて適正な厚みが定 められる。 例えば、 G a A s層を用いる場合には、 1モノレイヤ一の ド一プ層 を設けることができる。 一般的には、 キャリアの供給能力を適正に維持できさえ すれば、 同じ厚みで耐圧値を向上させるためには、 高濃度ド一プ層 （(5 ドープ層 ) の厚みは薄いほど好ましいといえる。  Further, a compound semiconductor layer other than the SiC layer may be used. For example, in the case of a GaAs layer, AIGaAs layer, GaN layer, AlGaN layer, SiGe layer, SiGeC layer, etc., the thickness of the highly doped layer (5-doped layer) depends on the material. The appropriate thickness is determined according to the conditions. For example, when a GaAs layer is used, one monolayer and one doping layer can be provided. In general, as long as the carrier supply capacity can be maintained properly, it can be said that the thinner the high-concentration doped layer ((5 doped layer), the better) in order to improve the breakdown voltage with the same thickness. .
一方、 多重 5 ド一プ層 1 0の最上層の一部は熱酸化によってゲート酸化膜とな る。 したがって、 ゲート酸化膜中にドナ一の窒素が大量に取りこまれると MO S 構造の閾値電圧に影響を与えたり、 ゲ.一ト酸化膜自体の耐圧低下につながるので 、 多重 <5 ド一プ層 1 0の最上層はアンドープ層であることが好ましく、 その厚さ は少なくとも酸化膜に変化する厚さ以上でなければならない。 例えば、 厚み 40 nmの熱酸化膜を形成するには、 少なく とも厚み 2 0 nm以上のアンド一プ層が 必要である。  On the other hand, part of the uppermost layer of the multi-doped layer 10 becomes a gate oxide film by thermal oxidation. Therefore, if a large amount of donor nitrogen is incorporated into the gate oxide film, it may affect the threshold voltage of the MOS structure or reduce the breakdown voltage of the gate oxide film itself. The uppermost layer of the layer 10 is preferably an undoped layer, and its thickness must be at least not less than a thickness that changes into an oxide film. For example, to form a thermal oxide film having a thickness of 40 nm, an AND layer having a thickness of at least 20 nm is required.
なお、 S i C基板 2として濃度 1 X 1 018 c m— 3前後の p型不純物を含む p + S i C基板を用いれば、 本実施形態と同様の製造方法によって、 次の第 2の実施 形態で説明するような I GB T (図 9 (b) 参照） を試作することが可能である 。 その場合、 ドレイン電極 7 cとして、 ニッケルに代えて、 p型 S i C層に対し てォ一ミヅク特性の得られる金属膜 （例えばアルミニウム膜、 アルミニウム膜と ニッケル膜またはチタン膜との積層膜、 アルミニウムとニッケルまたはチタンと の合金からなる合金膜など） を用いる。 この製造方法によって得られた I GB T のオン抵抗はさらに低く 0. 7 mQ ' c m2 であった。 一平面形状に関する変形例一 If a p + SiC substrate containing a p-type impurity having a concentration of about 1 × 10 18 cm− 3 is used as the SiC substrate 2, the following second embodiment can be performed by the same manufacturing method as the present embodiment. It is possible to prototype IGBT (see Fig. 9 (b)) as described in the form. In this case, instead of nickel, the drain electrode 7c may be replaced with nickel by a metal film (for example, an aluminum film, a laminated film of an aluminum film and a nickel film or a titanium film, Alloy film made of an alloy of aluminum and nickel or titanium). I GB T obtained by this manufacturing method The on-resistance of was further lowered 0. 7 mQ 'cm 2. Modification 1 regarding one plane shape
なお、 本実施形態では、 図 2のように正方形のセルを配置しているが、 本発明 の AC CUF E Tのセルの平面的形状は必ずしも正方形に限定されるものではな く、 各種の形状をとることができる。 例えば、 後述する第 2の実施形態の変形例 のように、 AC CUF E T (又は I GB T) のセルの平面形状を六角形にするこ とができる。 S i C結晶は六方晶であるので、 その結晶軸 （A軸） の方向に平行 な 6つの辺を有する六角形の平面形状を有する A C C U F E T (又は I GB T) を形成することにより、 キヤリアの移動度の向上を図ることができる。 一第 2の実施形態—  In this embodiment, square cells are arranged as shown in FIG. 2, but the planar shape of the AC CUFET cell of the present invention is not necessarily limited to a square, and various shapes may be used. Can be taken. For example, as in a modified example of the second embodiment described later, the planar shape of the AC CUFET (or IGBT) cell can be made hexagonal. Since the SiC crystal is hexagonal, by forming an ACCUFET (or IGBT) having a hexagonal planar shape with six sides parallel to the direction of its crystal axis (A axis), the carrier The mobility can be improved. Second Embodiment—
第 1の実施形態では、 ソース電極 7 bを逆ド一プ領域である p— S i C層 4に 直接接触させるため、 P— S i C層 4の上に設けられた多重 6 ド一プ層 1 0また は n+ S i C層 5の一部に p型不純物をイオン注入して、 p— S i C層 4の上部 4 aを形成している。 そして、 このように p— S i C層 4を表面にまで広げた後 、 p— S i C層 4に接触するソ一ス電極 7 bを設けている。 したがって、 この方 法によると、 高濃度に ド一プされた n型層 （n型ド一プ層 1 0 aや n+ S i C層 5 ) の導電型を反転させるために必要な高濃度の p型不純物をイオン注入しなけ ればならない。 S i C層の p型不純物としてはアルミニウムやボロンなどが用い られるが、 これらの不純物のイオン注入後における活性化率は、 数％から数 1 0 %であるので、 極めて高い注入ドーズ量が必要となる。 しかし、 注入欠陥を回復 するのが難しい S i C層において、 このような高ドーズ量の不純物を含むイオン 注入領域は、 高抵抗領域となるので、 この領域に電流が流れるときに大きな抵抗 損失が生じる。 また、 イオン注入によって S i C層の表面も荒れるので、 特性が さらに悪化する。 そこで、 本実施形態では、 以上のような不具合のない諸特性の 優れた DMO Sデバイスの構造及びその製造方法について説明する。  In the first embodiment, since the source electrode 7b is brought into direct contact with the p-SiC layer 4, which is a reverse-doped region, the multiple 6-doped layer provided on the P-SiC layer 4 is formed. P-type impurities are ion-implanted into the layer 10 or a part of the n + SiC layer 5 to form the upper part 4a of the pSiC layer 4. Then, after the p-SiC layer 4 is spread to the surface as described above, a source electrode 7b that comes into contact with the p-SiC layer 4 is provided. Therefore, according to this method, a high concentration of p necessary to reverse the conductivity type of a highly doped n-type layer (n-type doped layer 10a or n + SiC layer 5) is obtained. Type impurities must be implanted. Aluminum or boron is used as the p-type impurity in the SiC layer, but the activation rate of these impurities after ion implantation is from several percent to several ten percent, so an extremely high implantation dose is required. Becomes However, in the SiC layer where it is difficult to recover implantation defects, the ion-implanted region containing such a high-dose impurity becomes a high-resistance region, so that a large resistance loss occurs when a current flows through this region. Occurs. In addition, since the surface of the SiC layer is roughened by ion implantation, the characteristics are further deteriorated. Thus, in the present embodiment, a structure of a DMOS device having the above-described various characteristics and having excellent characteristics and a method of manufacturing the DMOS device will be described.
図 6は、 本実施形態における DMO Sデバイスの断面図である。 本実施形態に おいても、 DMO Sデバイスの平面形状は図 2に示すとおりである。 同図に示す ように、 本実施形態の DMO Sデバイスは、 高濃度の n型不純物を含む主面が （ 0 0 0 1) オフ面である S i C基板 2 ( 6 H- S i C基板） と、 S i C基板 2の 上に形成されたェピタキシャル層内に設けられた低濃度の n型不純物を含む n— S i C層 3 (ドリフ ト領域） と、 ェピタキシャル層の上に設けられたゲート絶縁 膜 6及びその上のゲ一ト電極 7 aと、 ェピ夕キシャル層の上でゲート電極 7 aを 囲むように設けられたソース電極 7 bと、 S i C基板 2の下面に設けられたドレ ィン電極 7 cと、 ェピタキシャル層のうちソース電極 7 bの下方に位置する領域 からゲート電極 7 aの端部下方に位置する領域に p型不純物をドープして形成さ れた p— S i C層 4と、 ェピタキシャル層のうちソース電極 7 bの端部下方から ゲート電極 7 aの端部下方に位置する領域に高濃度の n型不純物をド一プして形 成された n+ S i C層 5とを備えている。 FIG. 6 is a cross-sectional view of the DMOS device according to the present embodiment. Also in the present embodiment, the planar shape of the DMOS device is as shown in FIG. Shown in the figure As described above, the DMOS device according to the present embodiment includes the S i C substrate 2 (6H-S i C substrate) in which the main surface containing the high-concentration n-type impurity is the (001) off surface, n—SiC layer 3 (drift region) containing low-concentration n-type impurities provided in an epitaxial layer formed on iC substrate 2, and a gate provided on the epitaxial layer An insulating film 6 and a gate electrode 7a thereon, a source electrode 7b provided on the epitaxial layer so as to surround the gate electrode 7a, and a source electrode 7b provided on the lower surface of the SiC substrate 2. The drain electrode 7c and the p-type impurity formed by doping the epitaxial layer from a region located below the source electrode 7b to a region located below the end of the gate electrode 7a. — The high concentration of SiC layer 4 and the region of the epitaxial layer located below the end of source electrode 7b and below the end of gate electrode 7a an n + SiC layer 5 formed by doping n-type impurities.
ここで、 本実施形態の DMO Sデバイスの特徴は、 第 1の実施形態の DMO S デバイスとは異なり、 多重 <5 ド一プ層 1 0および n+ S i C層 5の一部に開口部 を設け、 この開口部の底面に p— S i C層 4の一部を露出させて、 ソース電極 7 bを p— S i C層 4の露出部に接触させている点である。  Here, the feature of the DMOS device of the present embodiment is different from the DMOS device of the first embodiment in that an opening is formed in a part of the multiplex <5 doping layer 10 and the n + SiC layer 5. This is that a part of the p-SiC layer 4 is exposed at the bottom of the opening, and the source electrode 7b is in contact with the exposed part of the p-SiC layer 4.
ェピタキシャル層の表面部のうち n+ S i C層 5が形成されている部分を除く 領域に多重 (5 ドープ層 1 0 (活性領域） が設けられている点、 これにより本実施 形態の D MO Sデバイスが A C C U F E T (Accumulation Mode F E T) として 機能する点は、 第 1の実施形態の DMO Sデバイスと同じである。 また、 多重 6 ド一プ層 1 0の構造も、 第 1の実施形態の DMO Sデバイス中の多重 ά ドープ層 1 0と基本的には同じである。 ただし、 本実施形態の多重 6 ド一ブ層 1 0は、 厚 みが 4 0 nmのアンドープ層 1 0 b (低濃度ドープ層） （不純物濃度が約 5 x 1 015 c m 3) と、 厚みが約 1 011111の11型ドープ層 1 0 & (高濃度ド一プ層） （ 不純物濃度が約 1 X 1 018c m 3) とを交互に 4層ずつ積層した後、 最上層に厚 みが 4 0 nmのアンドープ層 1 0 bを設けて構成されており、 トータル厚みが約 2 4 0 nmである。 The multi-layer (5 doped layer 10 (active region) is provided in the region of the surface portion of the epitaxial layer other than the portion where the n + S i C layer 5 is formed. The point that the MOS device functions as an ACCUFET (Accumulation Mode FET) is the same as the DMOS device of the first embodiment, and the structure of the multiplexed 6-doped layer 10 is the same as that of the first embodiment. It is basically the same as the multi-doped layer 10 in the DMOS device, except that the multi-doped layer 10 of the present embodiment has an undoped layer 10 b (low Concentration doped layer) (impurity concentration is about 5 × 10 15 cm 3 ) and 11-type doped layer with thickness of about 11011111 10 & (high concentration doped layer) (impurity concentration is about 1 × 10 18 cm 3 ) alternately, and then an undoped layer 10 b with a thickness of 40 nm is provided on the uppermost layer, for a total thickness of about 240 nm.
そして、 この半導体パワー素子において、 n+ S i C層 5がソース領域として 機能し、 多重 d ド一プ層 1 0がチャネル領域として機能し、 3 1 0基板2及び11 — S i C層 3がドレイン領域として機能する。 次に、 本実施形態の DMO Sデバイスの製造工程について、 図 7 (a) 〜 （d ) 及び図 8 (a) 〜 （d) を参照しながら説明する。 In this semiconductor power device, the n + SiC layer 5 functions as a source region, the multiple d-doped layer 10 functions as a channel region, and the 310 substrates 2 and 11—SiC layers 3 Functions as a drain region. Next, the manufacturing process of the DMOS device of the present embodiment will be described with reference to FIGS. 7 (a) to (d) and FIGS. 8 (a) to (d).
まず、 図 7 (a) に示す工程で、 主面が （ 0 0 0 1) 面 （C面） から数度ずれ た方位を有する n+ 型の S i C基板 2を準備する。 S i C基板 2の直径は 5 0 m mであり、 n型不純物の濃度は 1 X 1 018 c m— 3である。 流量 5 ( l/min.) の 酸素によってバブリングされた水蒸気雰囲気中で、 S i C基板 2を 1 1 0 0 で 3時間ほど熱酸化し、 表面に厚みが約 4 0 nmの熱酸化膜を形成した後、 バッフ ァ一ド弗酸 （弗酸 ： フッ化アンモニゥム水溶液 = 1 ： 7 ) により、 その熱酸化膜 を除去する。 その後、 C VD装置のチャンバ一内に S i C基板 2を設置し、 チヤ ンバ一内を 1 0— 6P a程度 （ 1 0 -8Torr) の真空度になるまで減圧する。 次に 、 チャンバ一内に希釈ガスとして流量 2 ( 1/min.) の水素ガスと流量 1 ( 1/ min.) のアルゴンガスとを供給し、 チヤンバ一内の圧力を 0. 0 9 3 3 MP aと して、 基板温度を約 1 6 0 0 °Cに制御する。 水素ガス及びアルゴンガスの流量は 上述の一定値に保持しながら、 原料ガスとして流量が 2 (m 1/min.) のプロパ ンガスと、 流量が 3 (m 1/min.) のシランガスとをチャンバ一内に導入する。 原料ガスは流量 5 0 (m l/min.) の水素ガスで希釈されている。 このとき、 ド 一ビングガス供給用のパルスバルブを開いて、 窒素を in- situ ドープすることに より、 S i C基板 2の主面の上に、 低濃度 ( 1 1 016 atoms · c m— 3程度） の 窒素を含む n型 S i C単結晶からなる厚み約 1 2〃1!1の 11ー 3 ;1 〇層 3を形成す る。 ' First, in the step shown in FIG. 7A, an n + -type SiC substrate 2 whose main surface has an orientation shifted from the (001) plane (C plane) by several degrees is prepared. The diameter of the SiC substrate 2 is 50 mm, and the concentration of the n-type impurity is 1 × 10 18 cm— 3 . In a steam atmosphere bubbled with oxygen at a flow rate of 5 (l / min.), The SiC substrate 2 was thermally oxidized at 110 for 3 hours to form a thermal oxide film having a thickness of about 40 nm on the surface. After the formation, the thermal oxide film is removed with buffered hydrofluoric acid (hydrofluoric acid: aqueous solution of ammonium fluoride = 1: 7). Thereafter, the SiC substrate 2 is set in the chamber of the CVD apparatus, and the pressure in the chamber is reduced to a degree of vacuum of about 10 to 6 Pa (10 to 8 Torr). Next, hydrogen gas at a flow rate of 2 (1 / min.) And argon gas at a flow rate of 1 (1 / min.) Are supplied as dilution gases into the chamber, and the pressure in the chamber is reduced to 0.093. The substrate temperature is controlled to about 160 ° C. as MPa. While maintaining the flow rates of hydrogen gas and argon gas at the above-mentioned constant values, a propane gas with a flow rate of 2 (m1 / min.) And a silane gas with a flow rate of 3 (m1 / min.) Introduce within one. The source gas is diluted with a hydrogen gas at a flow rate of 50 (ml / min.). At this time, by opening a pulse valve for supplying a driving gas and in-situ doping with nitrogen, a low concentration (110 16 atoms · cm— 3 11-3; 1〇 layer 3 composed of n-type S i C single crystal containing nitrogen (about 1). '
ただし、 特許出願 2 0 0 0— 5 8 9 6 4号の明細書及び図面に記載されている ように、 ドーピングガスとして窒素を約 1 0 %含む水素ガスを供給可能にするた めに、 ドーピングガスを高圧ボンベに収納しておいて、 高圧ボンベとドーピング ガス供給用配管との間にパルスバルブが設けられている。  However, as described in the specification and drawings of Patent Application No. 2000-58964, the doping is performed so that a hydrogen gas containing about 10% of nitrogen can be supplied as a doping gas. The gas is stored in a high-pressure cylinder, and a pulse valve is provided between the high-pressure cylinder and the doping gas supply pipe.
次に、 図 7 (b) に示す工程で、 n— S i C層 3の上に S i 02 からなる注入 マスク （図示せず） を形成した後、 S i C基板 2を 5 0 0 °C以上の高温に保ちつ つ、 注入マスクの上方から n— S i C層 3内に p型不純物であるアルミニウム （ A 1 ) のイオン注入を行なう。 その後、 表面の未注入領域を反応性イオンエッチ ング （R I E) によって除去したのち、 アルゴンガス雰囲気中， 温度 1 7 0 0 °C で活性化のためのァニ一ルを行なって、 逆ド一プ領域である P— S i C層 4を形 成する。 ここでは、 R I Eの後に活性化のためのァニールを行っているが、 活性 化のためのァニールを行なってから R I Eを行ってもよい。 ただし、 R I Eを行 なつてから活性化のためのァニールを行なうことにより、 ； I Eのイオン衝撃に よる欠陥が回復しやすく、 R I Eによって生じた表面の堆積物も除去することが できる。 Next, in the step shown in FIG. 7 (b), n- S i after forming an implantation mask consisting of S i 0 2 on the C layer 3 (not shown), S i C substrate 2 5 0 0 While maintaining a high temperature of not less than ° C, ions of aluminum (A 1), which is a p-type impurity, are implanted into the n-SiC layer 3 from above the implantation mask. After that, the non-implanted area on the surface is removed by reactive ion etching (RIE), and then in an argon gas atmosphere, at a temperature of 170 ° C. Then, annealing for activation is performed to form a P-SiC layer 4 which is a reverse doped region. Here, annealing for activation is performed after RIE, but RIE may be performed after annealing for activation. However, by performing annealing for activation after RIE, defects due to ion bombardment of IE can be easily recovered, and surface deposits generated by RIE can be removed.
その後、 図 7 ( c ) に示す工程で、 以下の手順により、 多重 ά ド一プ層 1 0を 形成する。  Thereafter, in the step shown in FIG. 7 (c), a multiplexed lead layer 10 is formed by the following procedure.
まず、 上記 n— S i C層 3を形成した際の原料ガスや希釈ガスの供給量， 温度 などの条件は代えずに、 パルスバルブを閉じることにより、 n— S i C層 3の上 に、 厚みが 4 0 nmのアンドープ層 1 0 b (不純物濃度が 5 x 1 015 c m 3程度 であることが確認されている） を形成する。 次に、 チャンバ一内への希釈ガス， 原料ガスの供給量， 温度などの条件は変えずに、 パルスバルブを開いて p型不純 物であるアルミニウムを含むガス (ドーピングガス） をパルス状に供給すること により、 アンド一プ層 1 0 bの上に、 厚み約 1 0 nmの n型ド一プ層 1 0 a (高 濃度ドープ層） （不純物濃度が約 1 X 1 01Bcm 3) を形成する。 First, the pulse valve is closed without changing the conditions such as the supply amount of the source gas and the dilution gas and the temperature when the n-SiC layer 3 is formed. An undoped layer 10b having a thickness of 40 nm (it has been confirmed that the impurity concentration is about 5 × 10 15 cm 3 ) is formed. Next, the pulse valve is opened and the gas (doping gas) containing aluminum, which is a p-type impurity, is supplied in a pulsed manner without changing the conditions such as the supply amount of diluent gas, source gas, and temperature in the chamber. As a result, an n-type doped layer 10a (highly doped layer) with a thickness of about 10 nm (impurity concentration of about 1 × 10 1 B cm 3 ) is formed on the AND layer 10b. Form.
このようにして、 原料ガス及び希釈ガスを供給しながら同時にパルスバルプを 開閉してドーピングガス （窒素） を導入することによる n型ドープ層 1 0 aの形 成と、 パルスバルブを閉じた状態にしてドーピングガスを供給しないで原料ガス 及び希釈ガスのみの供給によるアンド一プ層 1 0 bの形成とを各々 4回ずつ繰り 返す。 最後に、 最上層には、 厚みが 4 O nmのアンド一プ層 1 0 bを形成する。 これにより、 厚みが約 24 O nmの多重 5 ドープ層 1 0を形成する。  In this way, the n-type doped layer 10a is formed by simultaneously opening and closing the pulse valve and introducing the doping gas (nitrogen) while supplying the source gas and the diluent gas, and closing the pulse valve. The formation of the AND layer 10b by supplying only the source gas and the dilution gas without supplying the doping gas is repeated four times each. Finally, an AND layer 10b having a thickness of 4 O nm is formed on the uppermost layer. As a result, a multiple 5-doped layer 10 having a thickness of about 24 O nm is formed.
なお、 多重 (5 ドープ層 1 0の最上層を占めているアン ドープ層 10 bの厚みを 他のアンドープ層 1 0 bよりも 5 0 nm程度厚く してもよい。 ただし、 この場合 には、 DMO Sデバイスのしきい値電圧が高くなるので、 ゲート絶縁膜—多重 5 ドープ層の界面の界面準位の悪影響によるチャネル移動度としきい値電圧とを所 望の条件に調整するように、 最上部のアンドープ層 1 0 bの厚みを決めることが できる。  Note that the thickness of the undoped layer 10b occupying the uppermost layer of the multiple undoped layer 10 may be made about 50 nm thicker than the other undoped layers 10b. Since the threshold voltage of the DMOS device is increased, the channel mobility and the threshold voltage due to the adverse effect of the interface state at the interface between the gate insulating film and the multi-doped layer should be adjusted to the desired conditions. The thickness of the upper undoped layer 10b can be determined.
次に、 図 7 (d) に示す工程で、 基板上に S i 02 からなる注入マスク （図示 せず） を形成した後、 S i C基板 2を 5 0 0 °C以上の高温に保ちつつ、 注入マス クの上方から多重 5 ド一プ層 1 0内に n型不純物である高濃度の窒素 （N) のィ オン注入を、 注入深さが 3 0 0 nmになるように行なう。 その後、 注入マスクを 除去した後、 S i Cシャーレ中で 1 6 0 0 °Cで活性化のためのァニールを行なつ てソース領域となる n+ S i C層 5を形成する。 n+ S i C層 5は多重 5 ド一プ 層 1 0を貫通して、 その下端は p— S i C層 4と接している。 ソース領域である n+ S i C層 5は、 多重 δ ドープ層 1 0の全ての半導体層に接触していることが 好ましいので、 n+ S i C層 5の深さは、 多重 6 ドープ層 1 0の厚さよりも大き いことが好ましい。 Next, in the step shown in FIG. 7 (d), an implantation mask made of SiO 2 (shown in FIG. After forming), while maintaining the SiC substrate 2 at a temperature of 500 ° C. or higher, a high concentration of n-type impurity, which is an n-type impurity, is introduced into the multiple doped layers 10 from above the implantation mask. The ion implantation of nitrogen (N) is performed so that the implantation depth becomes 300 nm. Then, after removing the implantation mask, annealing for activation is performed at 160 ° C. in a SiC petri dish to form an n + SiC layer 5 serving as a source region. The n + SiC layer 5 penetrates the multi-doped layer 10 and its lower end is in contact with the pSiC layer 4. Since the n + S i C layer 5 as the source region preferably contacts all the semiconductor layers of the multiple δ-doped layer 10, the depth of the n + S i C layer 5 is It is preferable that the thickness is larger than the thickness.
次に、 図 8 (a) に示す工程で、 p— S i C層 4の表面を露出するために n + S i C層 5 (ソース領域） の一部を除去する。 その後、 基板上に、 アルミニウム 薄膜を蒸着によって堆積し、 フォ トリソグラフィ一及びドライエッチングにより 、 アルミニウム薄膜をパ夕一ニングしてエッチングマスク （図示せず） を形成す る。 このエッチングマスクを用いて、 CF4 と 02 との混合ガス （流量比 CF 4 ： 02 = 4 : 1 ) を用いた R I Eにより、 n+ S i C層 5を貫通して p— S i C層 4に達する深さ 3 5 0 nmの開口部 2 0を形成する。 これにより、 開口 2 0 の底面には p— S i C層 4の一部の表面が露出した状態となる。 このとき、 開口 部 2 0の深さは、 少なく とも n+ S i C層 5 (ソース領域） の深さよりも深いこ とが必要である。 Next, in the step shown in FIG. 8A, a part of the n + Sic layer 5 (source region) is removed to expose the surface of the p-SiC layer 4. Thereafter, an aluminum thin film is deposited on the substrate by vapor deposition, and the aluminum thin film is patterned by photolithography and dry etching to form an etching mask (not shown). Using this etching mask, RIE using a mixed gas of CF 4 and O 2 (flow ratio CF 4: 02 = 4: 1) penetrates the n + S i C layer 5 and the p—S i C layer An opening 20 with a depth of 350 nm reaching 4 is formed. As a result, a part of the surface of the p-SiC layer 4 is exposed at the bottom of the opening 20. At this time, the depth of the opening 20 needs to be at least deeper than the depth of the n + SiC layer 5 (source region).
このとき、 エッチングガスとして C F4 と 02 との混合ガスを用いた場合には 、 ェヅチレ一トは 6 7 nm/min.であり、 n + 層 5をエッチングするときと、 p 一 S i C層 4をエッチングするときとでエッチレートはほとんど変わらず、 ほぼ 一定とみなせる。 したがって、 開口部 2 0の深さは、 エッチング時間によって制 御することができる。 At this time, when a mixed gas of CF 4 and O 2 is used as an etching gas, the etch rate is 67 nm / min., And when etching the n + layer 5, p-SiC The etch rate is almost the same as when etching layer 4, and can be regarded as almost constant. Therefore, the depth of the opening 20 can be controlled by the etching time.
次に、 図 8 (b) に示す工程で、 基板上にゲート絶縁膜 6となる熱酸化膜を形 成した。 S i C基板 2上の各層の表面領域を、 流量 2. 5 ( 1/min.) の酸素に よってバブリングされた水蒸気雰囲気中で、 1 1 0 0 °Cで 3時間の間熱酸化する ことにより、 基板の表面上に厚みが約 4 0 nmの熱酸化膜を形成する。  Next, in the step shown in FIG. 8B, a thermal oxide film to be the gate insulating film 6 was formed on the substrate. The surface area of each layer on the SiC substrate 2 is thermally oxidized at 110 ° C for 3 hours in a steam atmosphere bubbled with oxygen at a flow rate of 2.5 (1 / min.). As a result, a thermal oxide film having a thickness of about 40 nm is formed on the surface of the substrate.
次に、 図 8 ( c ) に示す工程で、 ゲート絶縁膜 6となる熱酸化膜の上に、 開口 部 2 0及びその周辺部を開口したレジス トマスク （図示せず） を形成した後、 バ ヅファード弗酸によって、 熱酸化膜のうちレジス トマスクの開口部 2 0に位置す る領域を除去する。 これにより、 開口部 2 0及びその周辺部において、 p— S i C層 4および n+ S i C層 5 (ソース領域） の各一部の表面を露出させる。 その 後、 リフ トオフ法により、 露出している p— S i C層 4および n+ S i C層 5の 各一部の表面上にソース電極 7 bを形成する。 リフ トオフ法によるソース電極 7 bの形成は以下の手順で行なう。 まず、 電子ビーム蒸着法により、 基板上に厚み が約 2 0 0 nmのニッケル膜を堆積して、 基板全体を有機溶剤に浸漬することに より、 二ヅケル膜のうち， p— S i C層 4および n+ S i C層 5の各一部に接触 している部分のみを残して、 他の部分を基板から剥離させる。 Next, in the step shown in FIG. 8C, an opening is formed on the thermal oxide film serving as the gate insulating film 6. After forming a resist mask (not shown) having an opening in the portion 20 and its peripheral portion, a region of the thermal oxide film located in the opening portion 20 of the resist mask is removed by buffered hydrofluoric acid. As a result, the surface of each of the p-SiC layer 4 and the n + SiC layer 5 (source region) is exposed in the opening 20 and the periphery thereof. Thereafter, a source electrode 7b is formed on the surface of each of the exposed p-SiC layer 4 and n + SiC layer 5 by a lift-off method. The source electrode 7b is formed by the lift-off method in the following procedure. First, a nickel film with a thickness of about 200 nm is deposited on the substrate by electron beam evaporation, and the entire substrate is immersed in an organic solvent to form the p-SiC layer of the nickel film. Except for the part in contact with each part of 4 and n + SiC layer 5, the other part is peeled off from the substrate.
また、 S i C基板 2の裏面上に、 真空蒸着法により厚みが約 2 00 nmの N i 合金膜を堆積し、 からなる ドレイン電極 7 cを形成する。 さらに、 ソース， ドレ イン電極 7 b， 7 cと下地層とのォーミ ックコンタク トをとるために、 N2 ガス 中で温度 1 0 0 0 °C, 3分間の条件でァニールを行なう。 Further, a Ni alloy film having a thickness of about 200 nm is deposited on the rear surface of the SiC substrate 2 by a vacuum evaporation method, thereby forming a drain electrode 7c made of: Further, annealing is performed in N 2 gas at 100 ° C. for 3 minutes at a temperature of 100 ° C. in order to obtain an ohmic contact between the source and drain electrodes 7 b and 7 c and the underlying layer.
次に、 図 8 (d) に示す工程で、 電子ビーム蒸着法により、 基板上に厚みが約 2 0 0 nmのアルミニウム膜 (図示せず) を形成した後、 フォ トリソグラフィ一 及びドライェヅチングにより、 アルミニウム膜をパ夕一ニングして、 ゲート長約 1 0 /zmのゲ一ト電極 7 aを形成する。  Next, in a step shown in FIG. 8D, an aluminum film (not shown) having a thickness of about 200 nm is formed on the substrate by electron beam evaporation, and then photolithography and drying are performed. The aluminum film is patterned to form a gate electrode 7a having a gate length of about 10 / zm.
図 1 1は、 本実施形態の DMO Sデバイス （AC CUFE T) の電流 （ I ) — 電圧 （V) 特性を示す図である。 同図に示すように、 従来の DMO Sデバイスに 比べて、 飽和電流量がさらに増大している。  FIG. 11 is a diagram showing a current (I) -voltage (V) characteristic of the DMOS device (AC CUFET) of the present embodiment. As shown in the figure, the saturation current is further increased compared to the conventional DMOS device.
本実施形態の DMO Sデバイスによると、 第 1の実施形態の DMO Sデバイス と基本的には同じ作用効果を発揮することができる。  According to the DMOS device of the present embodiment, basically the same operational effects as the DMOS device of the first embodiment can be exerted.
加えて、 本実施形態の DMO Sデバイスにおいては、 ソース電極 7 bが n+ S i C層 5に形成された開口部 2 0の上に形成されているので、 高ドーズ量のィォ ン注入によつて表面が荒らされた領域や、 高ドーズ量のィオン注入による欠陥が 多く存在する領域を生じることなく、 P— S i C層 4と接している。 その結果、 多重 (5 ドープ層 1 0に逆電流が流れたときのソース電極 7 b下での抵抗が低く、 第 1の実施形態に比べて逆電流による抵抗損失が低いという利点がある。 また、 抵抗損失が小さいことから、 逆電流が流れたときの温度上昇も小さいので、 逆電 流に起因する D M 0 Sデバイスの破壊をさらに効果的に抑制することができる。 なお、 S i C基板 2として濃度 1 X 1 018c m_3前後の p型不純物を含む p + S i C基板を用いれば、 本実施形態と同様の製造方法によって I GB Tを試作す ることが可能である。 その場合、 ドレイン電極 7 cとして、 ニッケルに代えて、 p型 S i C層に対してォ一ミヅク特性の得られる金属膜 （例えばアルミニウム膜 、 アルミニウム膜とニッケル膜またはチタン膜との積層膜、 アルミニウムとニヅ ケルまたはチタンとの合金からなる合金膜など） を用いる。 この製造方法によつ て得られた I GB Tのオン抵抗はさらに低く 0. 7 πιΩ · c m2 であった。 In addition, in the DMOS device of the present embodiment, since the source electrode 7b is formed above the opening 20 formed in the n + SiC layer 5, it can be used for high dose ion implantation. Therefore, it is in contact with the P—SiC layer 4 without generating a region whose surface is roughened or a region where many defects exist due to high dose ion implantation. As a result, there is an advantage that the resistance under the source electrode 7b when the reverse current flows through the multiplexed (5-doped layer 10) is low, and the resistance loss due to the reverse current is lower than in the first embodiment. , Since the resistance loss is small, the temperature rise when the reverse current flows is also small, so that the destruction of the DMOS device due to the reverse current can be more effectively suppressed. Note that the use of the p + S i C substrate containing S i C as the substrate 2 concentration 1 X 1 0 18 c m_ 3 before and after the p-type impurity, we prototype I GB T by the method of manufacturing the same manner as in the present embodiment It is possible. In this case, instead of nickel, the drain electrode 7c may be replaced with nickel by a metal film (for example, an aluminum film, a laminated film of an aluminum film and a nickel film or a titanium film, Alloy film made of an alloy of aluminum and nickel or titanium). The ON resistance of the IGBT obtained by this manufacturing method was even lower, 0.7 πιΩ · cm 2 .
図 9 (a) ， （b) は、 順に、 DMO Sデバイス及び I GB Tに流れる電流を 比較して示す断面図である。 図 9 (a) に示すように、 n型 DMO Sデバイスで は、 S i C基板 2およびドリフ ト領域 （n— S i C層 3 ) が、 共に n型層である ために、 DMO Sデバイスのオン時には電子電流だけが流れる。 それに対し、 図 9 (b ) に示すように、 I GB Tでは、 S i C基板 2が p型層でドリフ ト領域 （ n— S i C層 3 ) が n型層であるために、 I GB Tのオン時には電子電流のみな らず p型の S i C基板 2から正孔が供給されて、 電子電流及び正孔電流の両方が 流れるのでオン抵抗がさらに低くなる。 ただし、 I GB Tの場合、 オフにしたと きに n型ェピタキシャル層に注入された正孔が p型基板に戻り、 逆電流が流れる ためにスイ ッチング速度は DMO Sデバイスに比べて遅い。 また、 I GB Tでは 、 S i C基板 2と n— S i C層 3との間に: P N接合が形成されるために、 数 Vの 電圧ロスが生じる。 そのために、 本実施形態の I GB Tは、 耐圧の設計値が数 k V程度の高耐圧型デバイスに適した構造といえる。  9 (a) and 9 (b) are cross-sectional views showing the currents flowing through the DMOS device and the IGBT in order. As shown in FIG. 9 (a), in the n-type DMOS device, since the SiC substrate 2 and the drift region (n—SiC layer 3) are both n-type layers, the DMOS device When is turned on, only electron current flows. On the other hand, as shown in FIG. 9 (b), in the IGBT, the SiC substrate 2 is a p-type layer and the drift region (n—SiC layer 3) is an n-type layer. When the GBT is on, not only the electron current but also the holes are supplied from the p-type SiC substrate 2, and both the electron current and the hole current flow, so that the on-resistance is further reduced. However, in the case of IGBT, when it is turned off, the holes injected into the n-type epitaxial layer return to the p-type substrate, and a reverse current flows, so that the switching speed is lower than that of the DMOS device. In the IGBT, a voltage loss of several volts occurs due to the formation of a PN junction between the SiC substrate 2 and the n-SiC layer 3. Therefore, the IGBT of the present embodiment can be said to be a structure suitable for a high withstand voltage type device having a withstand voltage design value of about several kV.
一平面形状に関する変形例一  Modification 1 regarding one plane shape
なお、 本実施形態では、 第 1の実施形態と同様に、 図 2のように正方形のセル を配置しているが、 本発明の AC CUF E Tのセルの平面的形状は必ずしも正方 形に限定されるものではなく、 各種の形状をとることができる。  In this embodiment, as in the first embodiment, square cells are arranged as shown in FIG. 2, but the planar shape of the AC CUFET cell of the present invention is not necessarily limited to a square. It can take various shapes.
図 1 0は、 AC CUF E T (又は I GB T) のセルの平面形状を六角形にした 本実施形態の変形例の平面図である。 各セルは等間隔に配置され、 ハニカム状の ゲート電極 Ί aが設けられている。 A C C U F E T (又は I GB T) は相隣接するセルから延びる空乏層が互いに つながるほうが絶縁破壊が生じにくい。 図 2に示すごとく正方形のセルを等間隔 に配置した場合、 相隣接するセルの辺同士の距離に比べ、 斜め方向に相隣接する 頂点同士の距離が大きくなる。 すなわち、 相隣接するセルの辺同士間で空乏層が つながっても、 相隣接する頂点同士の間でつながらない領域が残ることがある。 その結果、 絶縁破壊が生じやすくなる。 FIG. 10 is a plan view of a modification of the present embodiment in which the planar shape of the AC CUF ET (or I GB T) cell is hexagonal. Each cell is arranged at equal intervals, and a honeycomb-shaped gate electrode ゲ ー ト a is provided. ACCUFETs (or IGBTs) are less susceptible to dielectric breakdown when depletion layers extending from adjacent cells are connected to each other. When square cells are arranged at equal intervals as shown in Fig. 2, the distance between adjacent vertices in the diagonal direction is larger than the distance between sides of adjacent cells. That is, even if the depletion layer is connected between the sides of adjacent cells, a region that is not connected between the adjacent vertices may remain. As a result, dielectric breakdown is likely to occur.
それに対し、 図 1 0に示す六角形のセルの場合、 相隣接する辺同士の間で空乏 層がつながる場合には、 頂点同士の間でも空乏層がつながつている。 そのため、 六角形のセルの法が絶縁破壊が生じにくい。  On the other hand, in the case of the hexagonal cell shown in Fig. 10, when a depletion layer is connected between adjacent sides, the depletion layer is connected between the vertices. Therefore, the hexagonal cell method is less likely to cause dielectric breakdown.
また、 本発明の AC CUF E T (又は I GBT) のセルの平面的形状は必ずし も正方形や六角形に限定されるものではなく、 各種の形状をとることができる。 また、 上記第 2の実施形態においては、 ソース領域である n+ S i C層 5の形 成のためのイオン注入工程， 開口部 2 0の形成工程， ソース電極 7 bの形成工程 を行なった後に、 ゲート電極 7 aを形成したが、 先にゲート電極 7 aを形成する ことも可能である。 その場合、 まず、 ゲート絶縁膜 6となる熱酸化膜の上に、 n + S i C層 5を形成しょうとする領域を開口したアルミニウム膜 （この例では、 ゲート電極と一致する） を形成し、 このアルミニウム膜をマスクとして n型不純 物のイオン注入を行なう。 その後、 n+ S i C層 5を貫通して p— S i C層 4に 達する開口部の形成と、 ソース電極 7 bの形成とを行なう。 このような手順によ り、 ゲート電極 7 aと自己整合的にソース領域 （ n+ S i C層 5 ) を形成するこ とができるので、 微細な AC CUF E T又は I GB Tとして機能する半導体装置 が得られる。 ただし、 その場合には、 ゲート電極 7 aを構成する材料として、 ソ —ス電極形成時の高温処理工程によって特性が劣化しないものを用いることが好 ましい。  Further, the planar shape of the AC CUFET (or IGBT) cell of the present invention is not necessarily limited to a square or a hexagon, and may take various shapes. In the second embodiment, after performing the ion implantation step for forming the n + SiC layer 5 as the source region, the step of forming the opening 20 and the step of forming the source electrode 7b, Although the gate electrode 7a is formed, the gate electrode 7a can be formed first. In this case, first, an aluminum film (in this example, coincident with the gate electrode) is formed on the thermal oxide film serving as the gate insulating film 6 with an opening in a region where the n + S iC layer 5 is to be formed. Using this aluminum film as a mask, ion implantation of n-type impurities is performed. Thereafter, an opening is formed to reach the p-SiC layer 4 through the n + SiC layer 5, and a source electrode 7b is formed. By such a procedure, the source region (n + SiC layer 5) can be formed in a self-aligned manner with the gate electrode 7a, so that the semiconductor device functioning as a fine AC CUFET or IGBT. Is obtained. However, in such a case, it is preferable to use a material that does not deteriorate its characteristics due to a high-temperature treatment step at the time of forming the source electrode as a material constituting the gate electrode 7a.
本発明の半導体装置によると、 縦型構造の AC CUF E T又は I GB Tとして 機能する半導体装置において、 ゲート電極下方のチャネル領域として機能する部 分を、 第 1の半導体層と、 第 1の半導体層よりも高濃度のキャリア用不純物を含 み第 1の半導体層よりも膜厚が薄く量子効果による第 1の半導体層へのキヤリァ の浸みだしが可能な少なく とも第 2の半導体層とを互いに接するように設けて構 成した。 高濃度不純物層を含む第 1の半導体層からキャリアが供給され、 不純物 の少ない高品質の結晶性のよい第 2の半導体層をキヤリァが走行するので、 高い チャネル移動度と、 高い耐圧とを同時に実現することが可能になる。 産業上の利用分野 According to the semiconductor device of the present invention, in a semiconductor device functioning as an AC CUFET or IGBT having a vertical structure, a portion functioning as a channel region below a gate electrode is formed by a first semiconductor layer and a first semiconductor. The first semiconductor layer contains a carrier impurity at a higher concentration than the first semiconductor layer, is thinner than the first semiconductor layer, and is capable of exuding carriers into the first semiconductor layer by a quantum effect. To be in contact with Done. Carriers are supplied from the first semiconductor layer including the high-concentration impurity layer, and the carrier travels through the second semiconductor layer, which is low in impurities and has good crystallinity. It can be realized. Industrial applications
本発明の半導体装置は、 電子機器に搭載される AC CUF E T, 縦型 MO S F E T， D MO Sデバイス， I GB Tなどのデバイス、 特に、 高周波信号を扱うデ バイスや、 パワーデバイスに利用される。  INDUSTRIAL APPLICABILITY The semiconductor device of the present invention is used for devices such as an AC CUFET, a vertical MOS FET, a DMOS device, and an IGBT mounted on an electronic device, particularly, a device that handles a high-frequency signal and a power device. .

Claims

言青求の範囲 Scope of word blue
1 . 半導体基板と、  1. a semiconductor substrate;
上記半導体基板の主面上に設けられた化合物半導体層と、  A compound semiconductor layer provided on the main surface of the semiconductor substrate,
上記化合物半導体層の上に設けられたゲート絶縁膜と、  A gate insulating film provided on the compound semiconductor layer,
上記ゲート絶縁膜の上に設けられたゲート電極と、  A gate electrode provided on the gate insulating film;
上記化合物半導体層の上で上記ゲート電極の側方に設けられたソース電極と、 上記半導体基板の上記主面に対向する面に設けられたドレイン電極と、 上記化合物半導体層内で上記ソース電極の一部の下方から上記ゲート電極の端 部下方に直って設けられ第 1導電型不純物を含むソース領域と、  A source electrode provided on a side of the gate electrode on the compound semiconductor layer, a drain electrode provided on a surface of the semiconductor substrate facing the main surface, and a source electrode provided in the compound semiconductor layer. A source region including a first conductivity type impurity and provided directly below a part of the end of the gate electrode from below a part thereof;
上記化合物半導体層内で上記ゲ一ト電極の下方に設けられ第 1導電型不純物を 含むキヤリァ走行領域として機能する活性領域と、  An active region provided in the compound semiconductor layer below the gate electrode and functioning as a carrier traveling region containing a first conductivity type impurity;
上記化合物半導体層内で上記ゲート電極の下方に設けられ、 第 1導電型不純物 を含むドリフ ト領域と、  A drift region provided below the gate electrode in the compound semiconductor layer and containing a first conductivity type impurity;
上記化合物半導体層内で上記ドリフ ト領域と上記ソース領域との間に設けられ The semiconductor device is provided between the drift region and the source region in the compound semiconductor layer.
、 第 2導電型不純物を含む逆ドープ領域とを備え、 A reverse-doped region containing a second conductivity type impurity,
上記活性領域は、 少なくとも 1つの第 1の半導体層と、 上記第 1の半導体層よ りも高濃度のキヤリァ用不純物を含み上記第 1の半導体層よりも膜厚が薄く量子 効果による第 1の半導体層へのキヤリァの浸みだしが可能な少なくとも 1つの第 2の半導体層とを有していることを特徴とする半導体装置。  The active region includes at least one first semiconductor layer and a carrier impurity having a higher concentration than the first semiconductor layer, has a smaller thickness than the first semiconductor layer, and has a first effect due to a quantum effect. A semiconductor device comprising: at least one second semiconductor layer capable of exuding a carrier into a semiconductor layer.
2 . 請求項 1の半導体装置において、 2. The semiconductor device according to claim 1,
上記半導体基板は、 第 1導電型であることを特徴とする半導体装置。  The semiconductor device, wherein the semiconductor substrate is of a first conductivity type.
3 . 請求項 1の半導体装置において、 3. The semiconductor device according to claim 1,
上記半導体基板は、 第 2導電型であることを特徴とする半導体装置。  The semiconductor device, wherein the semiconductor substrate is of a second conductivity type.
4 . 請求項 1 ~ 3のうちいずれか 1つの半導体装置において、 4. The semiconductor device according to any one of claims 1 to 3,
上記活性領域は、 上記第 1の半導体層と第 2の半導体層とを各々複数個積層し て設けられていることを特徴とする半導体装置。 A semiconductor device, wherein the active region is provided by laminating a plurality of the first semiconductor layers and a plurality of the second semiconductor layers.
5 . 請求項 1〜 4のうちいずれか 1つの半導体装置において、 5. The semiconductor device according to any one of claims 1 to 4,
上記第 2の半導体層は、 炭化珪素からなり、  The second semiconductor layer is made of silicon carbide,
上記第 2の半導体層の厚みは、 1モノ レイヤ一以上で 2 0 n m未満であること を特徴とする半導体装置。  A semiconductor device, wherein the thickness of the second semiconductor layer is at least one monolayer and less than 20 nm.
6 . 請求項 1〜 5のうちいずれか 1つの半導体装置において、 6. The semiconductor device according to any one of claims 1 to 5,
上記第 1の半導体層は、 炭化珪素からなり、  The first semiconductor layer is made of silicon carbide,
上記第 1の半導体層の厚みは、 1 0 n m以上で 1 0 0 n m以下であることを特 徴とする半導体装置。  A semiconductor device, wherein the thickness of the first semiconductor layer is not less than 100 nm and not more than 100 nm.
7 . 請求項 1〜 6のうちいずれか 1つの半導体装置において、 7. The semiconductor device according to any one of claims 1 to 6,
上記ドリフ ト領域を横切って設けられ、 上記ドリフ ト領域よりも高濃度の第 1 導電型不純物を含む少なくとも 1つの高濃度ドープ層をさらに備えていることを 特徴とする半導体装置。  A semiconductor device further comprising at least one heavily doped layer provided across the drift region and containing a first conductivity type impurity at a higher concentration than the drift region.
8 . 請求項 1〜 7のうちいずれか 1つの半導体装置において、 8. The semiconductor device according to any one of claims 1 to 7,
上記ソース領域を貫通して上記逆ド一プ領域に達する開口部をさらに備え、 上記ソース電極は、 上記開口部の壁面上に設けられて、 上記ソース領域および 上記逆ドープ領域の各一部に直接接触していることを特徴とする半導体装置。  An opening that penetrates the source region and reaches the reverse doping region; the source electrode is provided on a wall surface of the opening; and a part of each of the source region and the reverse doping region is provided. A semiconductor device which is in direct contact.
9 . 半導体基板の主面上に、 第 1導電型の化合物半導体層を形成する工程 （a ) と、 9. A step (a) of forming a compound semiconductor layer of the first conductivity type on the main surface of the semiconductor substrate;
上記化合物半導体層の一部に第 2導電型不純物を導入して逆ド一プ領域を形成 する工程 （b ) と、  A step (b) of introducing an impurity of the second conductivity type into a part of the compound semiconductor layer to form a reverse doped region;
上記化合物半導体層及び上記逆ド一プ領域の上に、 少なく とも 1つの第 1の半 導体層と、 上記第 1の半導体層よりも高濃度のキヤリァ用不純物を含み上記第 1 の半導体層よりも膜厚が薄く量子効果による第 1の半導体層へのキヤリァの浸み だしが可能な少なくとも 1つの第 2の半導体層とを有する活性領域を形成するェ 程 （ C ) と、 On the compound semiconductor layer and the reverse dopant region, at least one first semiconductor layer, and a carrier impurity having a higher concentration than the first semiconductor layer and containing a carrier impurity. Forming an active region having at least one second semiconductor layer having a small thickness and capable of leaching the carrier into the first semiconductor layer by the quantum effect. About (C)
上記活性領域のうち少なくとも逆ド一プ領域の上方に位置する領域に第 1導電 型不純物を導入してソース領域を形成する工程 （d) と、  (D) introducing a first conductivity type impurity into at least a region of the active region located above the reverse doping region to form a source region;
上記活性領域のうち上記逆ドープ領域の上に位置する部分を除去して、 逆ド一 プ領域に達する開口部を形成する工程 （e) と、  Removing (e) removing a portion of the active region located above the reverse doped region to form an opening reaching the reverse doped region;
上記活性化領域の上にゲート絶縁膜を形成する工程 （f ) と、  Forming a gate insulating film on the activation region (f);
上記開口部内に露出するソース領域および上記逆ドープ領域の両方に接触する ソース電極を設ける工程 （g) と、  Providing a source electrode in contact with both the source region exposed in the opening and the counter-doped region (g);
上記ゲート絶縁膜上にゲート電極を形成する工程 （h) と  (H) forming a gate electrode on the gate insulating film;
を含む半導体装置の製造方法。 A method for manufacturing a semiconductor device including:
1 0. 請求項 9の半導体装置の製造方法において、 10. The method of manufacturing a semiconductor device according to claim 9,
上記工程 （a) では、 第 1導電型不純物の in- situ ド一ブを伴うェピ夕キシャ ル成長法により、 上記化合物半導体層を形成することを特徴とする半導体装置の 製造方法。  In the step (a), a compound semiconductor layer is formed by an epitaxial growth method involving an in-situ doping of a first conductivity type impurity.
1 1. 請求項 9又は 1 0の半導体装置の製造方法において、 1 1. The method for manufacturing a semiconductor device according to claim 9 or 10,
上記工程 （a) 及び （c) では、 上記化合物半導体層及び上記活性領域として 、 S i C層を形成することを特徴とする半導体装置の製造方法。  In the above steps (a) and (c), a method of manufacturing a semiconductor device, comprising forming a SiC layer as the compound semiconductor layer and the active region.
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