WO2001015213A1 - Procede d'attaque chimique - Google Patents
Procede d'attaque chimique Download PDFInfo
- Publication number
- WO2001015213A1 WO2001015213A1 PCT/JP2000/005623 JP0005623W WO0115213A1 WO 2001015213 A1 WO2001015213 A1 WO 2001015213A1 JP 0005623 W JP0005623 W JP 0005623W WO 0115213 A1 WO0115213 A1 WO 0115213A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- etching
- processing chamber
- gas
- etching method
- containing gas
- Prior art date
Links
- 238000005530 etching Methods 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000007789 gas Substances 0.000 claims abstract description 67
- 230000008569 process Effects 0.000 claims abstract description 17
- 125000004435 hydrogen atom Chemical group [H]* 0.000 claims abstract description 10
- 125000004433 nitrogen atom Chemical group N* 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 239000012044 organic layer Substances 0.000 claims description 5
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 239000011229 interlayer Substances 0.000 description 14
- 239000000463 material Substances 0.000 description 6
- 230000009977 dual effect Effects 0.000 description 5
- 239000011261 inert gas Substances 0.000 description 4
- 239000000956 alloy Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- VLKZOEOYAKHREP-UHFFFAOYSA-N n-Hexane Chemical compound CCCCCC VLKZOEOYAKHREP-UHFFFAOYSA-N 0.000 description 3
- 238000010792 warming Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
- H01L21/0212—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
Definitions
- TECHNICAL FIELD The present invention relates to an etching method.
- an A1 alloy is used for wiring of a semiconductor device, an A1 alloy is deposited on an interlayer insulating film by a sputtering method and then etched to form a wiring pattern.
- the pressure in the processing chamber is several mTorr or more!
- the pressure range of OO mTorr was common.
- Japanese Patent Application Laid-Open No. 60-170,2308 it is described that the etching rate can be maximized in a pressure range of 50 to: L00 mTorr.
- Cu wiring called the damascene process has recently been formed.
- the damascene process is a method in which a wiring pattern groove is formed in an interlayer insulating film and a wiring material is embedded in this groove.
- the specific resistance is reduced to about half and the speed is easily increased.
- CMP chemical mechanical polishing
- the damascene process has become easier to put into practical use.
- dual damascene means that It grooves opposite convex wiring and the via holes are formed are formed in the interlayer insulating film: is a technique for simultaneously forming the wiring and the via-hole by embedding a metal material for wiring in the groove.
- etch stopper has a high dielectric constant, another problem arises in that a capacitor is formed between wires.
- a first object of the present invention is to prevent micro-trenching without using an etch stopper. It is to provide a new and improved etching method. Further, a second object of the present invention is to improve the mask selectivity. It is to provide a new and improved etching method that can be performed.
- a processing gas is introduced into an airtight processing chamber, and an etching method for an organic layer film formed on an object to be processed arranged in the processing chamber is performed.
- An etching method is provided wherein the gas contains at least a gas containing nitrogen atoms and a gas containing hydrogen atoms, and the pressure in the vacuum processing chamber is substantially 500 mTorr or more.
- the organic film is preferably a low dielectric constant material having a relative dielectric constant of 3.5 or less. Further, it is preferable that the pressure in the vacuum processing chamber is substantially 50 OmTorr to 800 mTorr.
- the processing gas contains at least a nitrogen atom-containing gas and a hydrogen atom-containing gas, and the pressure in the vacuum processing chamber is substantially 500 mTorr or more, microtrenching can be prevented without using an etch stopper. Can be passed. Also, the mask selection ratio can be increased. Therefore, it is particularly effective in a process where it is necessary to stop the etching in the middle of the organic layer film, for example, a dual damascene process. Also, N 2 may be used as the gas containing nitrogen atoms, and H 2 may be used as the gas containing hydrogen atoms. If N 2 or H 2 is used as the composition of the processing gas, handling is easy and even if released into the atmosphere, it is unlikely to cause global warming. Furthermore, since N 2 or H 2 is inexpensive, the processing cost is prevented from increasing. If Ar is included in the processing gas, the etching conditions can be easily controlled, and the shape of the groove can be easily controlled.
- FIG. 1 is a schematic sectional view showing an etching apparatus to which the present invention can be applied.
- FIG. 2 is a schematic explanatory diagram for explaining Embodiment 1 of the present invention.
- FIG. 3 is a schematic explanatory diagram for explaining Embodiment 2 of the present invention.
- FIG. 4 is a schematic sectional view showing another etching apparatus to which the present invention can be applied.
- FIG. 5 is a schematic explanatory diagram for explaining Embodiment 3 of the present invention.
- BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of an etching method according to the present invention will be described below in detail with reference to the accompanying drawings.
- a processing chamber 104 is formed in a processing vessel 102 of the etching apparatus 100 shown in the same figure, and a lower electrode constituting a vertically movable susceptor is formed in the processing chamber 104.
- 106 are arranged. Above the lower electrode 106, an electrostatic chuck 110 connected to a high-voltage DC power supply 108 is provided.
- an object to be processed for example, a semiconductor wafer ( Hereinafter, it is referred to as “wafer”.) W is placed on the upper surface of the electrostatic chuck 110. Furthermore, an insulating focus ring 112 is arranged around the wafer W placed on the lower electrode 106.
- a high-frequency power supply 120 is connected to the lower electrode 106 via a matching device 118.
- An upper electrode 122 having a large number of gas discharge holes 122a is arranged on the ceiling of the processing chamber 104 facing the mounting surface of the lower electrode 106.
- An insulator 123 is provided between the upper electrode 122 and the processing vessel 102.
- the upper electrode 122 is connected to a high-frequency power supply 121 that outputs plasma-generating high-frequency power via a matching unit 119.
- a gas supply pipe 124 is connected to the gas discharge hole 122a, and the first to third branch pipes 126, 122 in the example shown in the figure are connected to the gas supply pipe 124. 8, 130 are connected.
- the first branch pipe 1 2 6, via an on-off valve 1 3 2 and the flow control valve 1 3 4, the gas supply source 1 3 6 is connected for supplying N 2.
- a gas supply source 148 for supplying Ar is connected to the third branch pipe 130 via an on-off valve 144 and a flow control valve 146.
- the inert gas added to the processing gas is not limited to the above Ar, but may be any inert gas (eg, He, K) capable of adjusting the plasma excited in the processing chamber 104. r etc.) can also be adopted.
- An exhaust pipe 150 communicating with a vacuum evacuation mechanism (not shown) is connected below the processing vessel 102, and the operation of the vacuum evacuation mechanism causes the inside of the processing chamber 104 to move to a predetermined position. It can be maintained in a reduced pressure atmosphere.
- the wafer W used in the present embodiment has an interlayer insulating film to be etched on the Cu film layer.
- the interlayer insulating film has a specific dielectric constant is very small Le ,, for example polyorganosiloxanes white hexane crosslinked benzocyclobutene resin (hereinafter, that referred to as "BCB".) Than conventional sio 2 and, manufactured by DowChemical Co. It is composed of organic low dielectric constant materials such as SiLK (trade name) and FLARE (trade name) having the following structure.
- An etching mask having a predetermined pattern is formed on the interlayer insulating film.
- the etching mask for example, a mask composed of a photo resist film layer or a mask composed of a SiO 2 film layer and a photo resist film layer can be adopted.
- an etching step in the case where a contact hole is formed in a wafer by the etching method according to the present embodiment using the above-described etching apparatus 100 will be described. First, the wafer W is placed on the lower electrode 106 that has been adjusted to a predetermined temperature in advance, and the temperature of the wafer W is maintained at about 20 ° C. to 60 ° C. according to the processing.
- the processing gas according to the present embodiment that is, the mixed gas of N 2 , H 2, and Ar is supplied to the gas supply pipes 124 by the flow control valves 134, 140, and 146.
- the gases are introduced into the processing chamber 104 while adjusting the flow rate of each gas.
- the processing chamber 10 is controlled so that the pressure atmosphere in the processing chamber 104 is substantially equal to or more than 500 mT orr, preferably substantially 500 to 800 mT orr. 4 ⁇ is evacuated.
- high-frequency power with a frequency of 2 MHz and a power of 600 W to 140 W, for example, is applied to the lower electrode 106.
- high-frequency power with a frequency of 60 MHz and a power of 600 W to 140 W, for example, is applied to the upper electrode 122.
- high-density plasma is generated in the processing chamber 102 1, and a contact hole having a predetermined shape is formed in the interlayer insulating layer made of the organic low-k material of the wafer W by the plasma.
- the present embodiment is configured as described above, and the processing gas contains at least a gas containing nitrogen atoms and a gas containing hydrogen atoms, and the pressure in the vacuum processing chamber is substantially 500 mTorr.
- micro-trenching can be prevented without using an etch stop.
- the use of the above processing gas can increase the mask selectivity.
- contact holes were formed in the interlayer insulating film of the wafer W using the etching apparatus 100 described in the above embodiment.
- Components having substantially the same functions and configurations as those of the wafer 100 and the wafer W are denoted by the same reference numerals, and redundant description is omitted.
- the etching process conditions are set substantially the same as in the above-described embodiment, unless otherwise specified.
- Example 1 (Change in pressure atmosphere in processing chamber) First, referring to FIG. 2, Examples 1 (a) to 1 (Example) in the case where the pressure atmosphere in processing chamber 104 was changed. c) will be described. In Examples 1 (a) to 1 (c), etching was performed under the conditions shown in the following table, and contact holes were formed in the above-described interlayer insulating film of the wafer W. In the tables and drawings, the center of the wafer W is described as the center, the edge of the wafer W is described as the edge, and the middle between the center and the edge of the wafer W is described as the middle.
- tapping refers to the ratio of the etching depth at the end of the contact hole to the etching depth at the approximate center of the contact hole, and the larger the value, the more adversely the shape of the contact hole is adversely affected.
- Microphone mouth Indicates that trenching is formed.
- Example 1 (b) and 1 (c) As a result, in Examples 1 (b) and 1 (c), as shown in Table 1 and Figs. 2 (b) and 2 (c), it was possible to form contact holes with good shapes without lowering the etching rate. did it. In contrast, in Example 1 (a), micro-trenching occurred in the contact hole as shown in Table 1 and Fig. 2 (a).
- Example 2 (Change in pressure atmosphere in processing chamber) Next, referring to FIG. 3, Example 2 (a) to Example 2 when the pressure atmosphere in processing chamber 104 was changed. (c) will be described.
- the width of the contact hole to be formed is changed under the same conditions as in the first embodiment.
- the etching treatment was performed under the conditions shown in the following table, and contact holes were formed in the interlayer insulating film of the wafer W described above.
- Example 2 (b) and (c) As a result, in Examples 2 (b) and (c), as shown in Table 2 and Figs. 3 (b) and (c), it was possible to form contact holes of good shape without lowering the etching rate. did it. In contrast, in Example 2 (a), micro-trenching occurred in the contact hole as shown in Table 2 and Fig. 3 (a).
- the results of this example show that if the pressure in the processing chamber is set to a predetermined pressure, a contact hole having a good shape can be formed even when the width of the contact hole is changed.
- Example 3 (Changes in flow rates of N 2 and H 2 )
- the flow rates of N 2 and H 2 constituting the processing gas were changed using an etching apparatus 200 described later.
- Example 3 in the case of this will be described.
- a processing chamber 204 is formed in a processing vessel 202 of the etching apparatus 200 shown in FIG.
- a lower electrode 206 constituting a susceptor that can move up and down is arranged.
- An electrostatic chuck 210 connected to a high-voltage DC power supply 208 is provided above the lower electrode 206, and a wafer W is placed on the upper surface of the electrostatic chuck 210.
- an insulating focus ring 212 is arranged around the wafer W placed on the lower electrode 206.
- the lower electrode 206 is connected to a high-frequency power supply 220 that outputs high-frequency power for plasma generation via a matching unit 220.
- an upper electrode 222 with many gas discharge holes 222a is arranged on the ceiling of the processing chamber 204 opposing the mounting surface of the lower electrode 206.
- the upper electrode 222 forms a part of the processing vessel 202.
- a gas supply pipe 224 is connected to the gas discharge hole 222 a in the same manner as in the etching apparatus 100, and the gas supply pipe 224 is connected to the first gas supply pipe in the illustrated example.
- the second branch pipes 224 and 228 are connected.
- a gas supply source 236 for supplying N 2 is connected to the first branch pipe 226 via an on-off valve 232 and a flow control valve 234.
- a third branch pipe may be provided so as to supply an inert gas such as Ar.
- an exhaust pipe 150 is connected below the processing vessel 202 in the same manner as the etching apparatus 100 described above.
- a magnet 238 is arranged outside the processing chamber 204 so as to surround the outer side wall of the processing vessel 202, and the upper electrode 222 and the lower electrode 222 are arranged by the magnet 238.
- the temperature of the wafer W is maintained at about 20 ° C to 80 ° C. Then, a high-frequency power having a frequency of 13.56 MHz and a power of 500 W to 1500 W is applied to the lower electrode 206.
- etching was performed based on the conditions shown in the following table, and contact holes were formed in the interlayer insulating film of the wafer W described above.
- a configuration in which a mixed gas of N 2 and H 2 or a mixed gas of N 2 , H 2 and Ar is used as a processing gas has been described as an example.
- the present invention is not limited to such a configuration.
- various gases such as further 0 2 and inert gas to a mixed gas of N 2 and H 2 and A r, it is possible to implement the present invention. That is, the present invention can be implemented as long as the processing gas contains at least a nitrogen atom-containing gas and a hydrogen atom-containing gas.
- the parallel plate type etching apparatus and the etching apparatus for forming a magnetic field in the processing chamber have been described as examples.
- the present invention is not limited to such a configuration.
- the present invention can also be applied to various plasma etching devices such as an inductively coupled etching device provided with an electrostatic shield and a microphone mouth-wave type etching device.
- plasma etching devices such as an inductively coupled etching device provided with an electrostatic shield and a microphone mouth-wave type etching device.
- the configuration in which the contact hole is formed in the interlayer insulating film made of the organic low dielectric constant material formed on the wafer has been described as an example, but the present invention is not limited to this configuration.
- the present invention can be applied to the case where any etching process is performed on the interlayer insulating film formed on the object to be processed. According to the present invention, micro-trenching can be prevented without using an etch stopper. Also, the mask selection ratio can be increased.
- the processing gas is easy to handle, and even if the processing gas is released into the atmosphere, it is unlikely to cause global warming. Furthermore, processing costs do not increase. Furthermore, according to the present invention, since the etching conditions can be easily controlled, the shape of the groove can be easily controlled.
- the present invention is applicable to an etching method.
- the present invention can be used for an etching process that requires micro-trenching and requires an improved mask selectivity.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- ing And Chemical Polishing (AREA)
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00954910A EP1225621B1 (en) | 1999-08-23 | 2000-08-23 | Method of etching |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11/235191 | 1999-08-23 | ||
JP23519199A JP3844413B2 (ja) | 1999-08-23 | 1999-08-23 | エッチング方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001015213A1 true WO2001015213A1 (fr) | 2001-03-01 |
Family
ID=16982437
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2000/005623 WO2001015213A1 (fr) | 1999-08-23 | 2000-08-23 | Procede d'attaque chimique |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1225621B1 (ja) |
JP (1) | JP3844413B2 (ja) |
KR (1) | KR100709817B1 (ja) |
TW (1) | TW469488B (ja) |
WO (1) | WO2001015213A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6793833B2 (en) * | 2001-09-20 | 2004-09-21 | Hitachi, Ltd. | Etching method of organic insulating film |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004214336A (ja) | 2002-12-27 | 2004-07-29 | Tokyo Electron Ltd | プラズマエッチング方法およびプラズマエッチング装置 |
JP2004342873A (ja) | 2003-05-16 | 2004-12-02 | Tokyo Electron Ltd | 半導体装置およびその製造方法 |
US7344993B2 (en) * | 2005-01-11 | 2008-03-18 | Tokyo Electron Limited, Inc. | Low-pressure removal of photoresist and etch residue |
CN101866846B (zh) * | 2009-04-14 | 2012-04-18 | 中芯国际集成电路制造(北京)有限公司 | 刻蚀沟槽的方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4529860A (en) * | 1982-08-02 | 1985-07-16 | Motorola, Inc. | Plasma etching of organic materials |
JPS60170238A (ja) * | 1984-02-15 | 1985-09-03 | Toyota Central Res & Dev Lab Inc | ドライエツチング方法 |
JPH10209118A (ja) * | 1997-01-28 | 1998-08-07 | Sony Corp | アッシング方法 |
JPH11150101A (ja) * | 1997-11-18 | 1999-06-02 | Nec Corp | 半導体装置の製造方法 |
JP2000036484A (ja) * | 1998-05-11 | 2000-02-02 | Tokyo Electron Ltd | プラズマ処理方法 |
JP2000294633A (ja) * | 1999-04-07 | 2000-10-20 | Sony Corp | 半導体装置およびその製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10150101A (ja) * | 1996-11-15 | 1998-06-02 | Nippon Steel Corp | 半導体装置及びその製造方法 |
WO1999026277A1 (en) * | 1997-11-17 | 1999-05-27 | Mattson Technology, Inc. | Systems and methods for plasma enhanced processing of semiconductor wafers |
US6080680A (en) * | 1997-12-19 | 2000-06-27 | Lam Research Corporation | Method and composition for dry etching in semiconductor fabrication |
FR2789804B1 (fr) * | 1999-02-17 | 2002-08-23 | France Telecom | Procede de gravure anisotrope par plasma gazeux d'un materiau polymere dielectrique organique et application a la microelectronique |
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1999
- 1999-08-23 JP JP23519199A patent/JP3844413B2/ja not_active Expired - Fee Related
-
2000
- 2000-08-22 TW TW089116981A patent/TW469488B/zh active
- 2000-08-23 WO PCT/JP2000/005623 patent/WO2001015213A1/ja active IP Right Grant
- 2000-08-23 EP EP00954910A patent/EP1225621B1/en not_active Expired - Lifetime
- 2000-08-23 KR KR1020027002261A patent/KR100709817B1/ko not_active IP Right Cessation
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US4529860A (en) * | 1982-08-02 | 1985-07-16 | Motorola, Inc. | Plasma etching of organic materials |
JPS60170238A (ja) * | 1984-02-15 | 1985-09-03 | Toyota Central Res & Dev Lab Inc | ドライエツチング方法 |
JPH10209118A (ja) * | 1997-01-28 | 1998-08-07 | Sony Corp | アッシング方法 |
JPH11150101A (ja) * | 1997-11-18 | 1999-06-02 | Nec Corp | 半導体装置の製造方法 |
JP2000036484A (ja) * | 1998-05-11 | 2000-02-02 | Tokyo Electron Ltd | プラズマ処理方法 |
JP2000294633A (ja) * | 1999-04-07 | 2000-10-20 | Sony Corp | 半導体装置およびその製造方法 |
Non-Patent Citations (1)
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6793833B2 (en) * | 2001-09-20 | 2004-09-21 | Hitachi, Ltd. | Etching method of organic insulating film |
Also Published As
Publication number | Publication date |
---|---|
KR100709817B1 (ko) | 2007-04-23 |
EP1225621A4 (en) | 2007-03-28 |
JP2001060582A (ja) | 2001-03-06 |
EP1225621A1 (en) | 2002-07-24 |
JP3844413B2 (ja) | 2006-11-15 |
KR20020027567A (ko) | 2002-04-13 |
EP1225621B1 (en) | 2011-07-13 |
TW469488B (en) | 2001-12-21 |
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